blob: da51f2d7f540d8878cb88e8cfe98e3ebc495c776 [file] [log] [blame]
Richard Henderson1b3b7692022-06-07 10:31:22 -07001/*
2 * Target-specific parts of semihosting/arm-compat-semi.c.
3 *
4 * Copyright (c) 2005, 2007 CodeSourcery.
5 * Copyright (c) 2019, 2022 Linaro
6 *
7 * SPDX-License-Identifier: GPL-2.0-or-later
8 */
9
10#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
11#define TARGET_ARM_COMMON_SEMI_TARGET_H
12
Peter Maydell30722e02023-09-25 12:22:19 +010013#include "target/arm/cpu-qom.h"
Richard Henderson1b3b7692022-06-07 10:31:22 -070014
15static inline target_ulong common_semi_arg(CPUState *cs, int argno)
16{
17 ARMCPU *cpu = ARM_CPU(cs);
18 CPUARMState *env = &cpu->env;
19 if (is_a64(env)) {
20 return env->xregs[argno];
21 } else {
22 return env->regs[argno];
23 }
24}
25
26static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
27{
28 ARMCPU *cpu = ARM_CPU(cs);
29 CPUARMState *env = &cpu->env;
30 if (is_a64(env)) {
31 env->xregs[0] = ret;
32 } else {
33 env->regs[0] = ret;
34 }
35}
36
37static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
38{
Richard Hendersonb77af262023-09-13 17:22:49 -070039 return nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cpu_env(cs));
Richard Henderson1b3b7692022-06-07 10:31:22 -070040}
41
42static inline bool is_64bit_semihosting(CPUArchState *env)
43{
44 return is_a64(env);
45}
46
47static inline target_ulong common_semi_stack_bottom(CPUState *cs)
48{
49 ARMCPU *cpu = ARM_CPU(cs);
50 CPUARMState *env = &cpu->env;
51 return is_a64(env) ? env->xregs[31] : env->regs[13];
52}
53
54static inline bool common_semi_has_synccache(CPUArchState *env)
55{
56 /* Ok for A64, invalid for A32/T32 */
57 return is_a64(env);
58}
59
60#endif