Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU model of the Milkymist UART block. |
| 3 | * |
| 4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | * |
| 20 | * Specification available at: |
Michael Walle | 6dbbe24 | 2016-06-20 17:08:41 +0100 | [diff] [blame] | 21 | * http://milkymist.walle.cc/socdoc/uart.pdf |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 22 | */ |
| 23 | |
Peter Maydell | ea99dde | 2016-01-26 18:16:57 +0000 | [diff] [blame] | 24 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 25 | #include "hw/hw.h" |
| 26 | #include "hw/sysbus.h" |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 27 | #include "trace.h" |
Paolo Bonzini | dccfcd0 | 2013-04-08 16:55:25 +0200 | [diff] [blame] | 28 | #include "sysemu/char.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 29 | #include "qemu/error-report.h" |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 30 | |
| 31 | enum { |
| 32 | R_RXTX = 0, |
| 33 | R_DIV, |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 34 | R_STAT, |
| 35 | R_CTRL, |
| 36 | R_DBG, |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 37 | R_MAX |
| 38 | }; |
| 39 | |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 40 | enum { |
| 41 | STAT_THRE = (1<<0), |
| 42 | STAT_RX_EVT = (1<<1), |
| 43 | STAT_TX_EVT = (1<<2), |
| 44 | }; |
| 45 | |
| 46 | enum { |
| 47 | CTRL_RX_IRQ_EN = (1<<0), |
| 48 | CTRL_TX_IRQ_EN = (1<<1), |
| 49 | CTRL_THRU_EN = (1<<2), |
| 50 | }; |
| 51 | |
| 52 | enum { |
| 53 | DBG_BREAK_EN = (1<<0), |
| 54 | }; |
| 55 | |
Andreas Färber | 79bbe8b | 2013-07-24 23:08:14 +0200 | [diff] [blame] | 56 | #define TYPE_MILKYMIST_UART "milkymist-uart" |
| 57 | #define MILKYMIST_UART(obj) \ |
| 58 | OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART) |
| 59 | |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 60 | struct MilkymistUartState { |
Andreas Färber | 79bbe8b | 2013-07-24 23:08:14 +0200 | [diff] [blame] | 61 | SysBusDevice parent_obj; |
| 62 | |
Michael Walle | 5adb30d | 2011-08-31 16:48:45 +0200 | [diff] [blame] | 63 | MemoryRegion regs_region; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 64 | CharDriverState *chr; |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 65 | qemu_irq irq; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 66 | |
| 67 | uint32_t regs[R_MAX]; |
| 68 | }; |
| 69 | typedef struct MilkymistUartState MilkymistUartState; |
| 70 | |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 71 | static void uart_update_irq(MilkymistUartState *s) |
| 72 | { |
| 73 | int rx_event = s->regs[R_STAT] & STAT_RX_EVT; |
| 74 | int tx_event = s->regs[R_STAT] & STAT_TX_EVT; |
| 75 | int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN; |
| 76 | int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN; |
| 77 | |
| 78 | if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) { |
| 79 | trace_milkymist_uart_raise_irq(); |
| 80 | qemu_irq_raise(s->irq); |
| 81 | } else { |
| 82 | trace_milkymist_uart_lower_irq(); |
| 83 | qemu_irq_lower(s->irq); |
| 84 | } |
| 85 | } |
| 86 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 87 | static uint64_t uart_read(void *opaque, hwaddr addr, |
Michael Walle | 5adb30d | 2011-08-31 16:48:45 +0200 | [diff] [blame] | 88 | unsigned size) |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 89 | { |
| 90 | MilkymistUartState *s = opaque; |
| 91 | uint32_t r = 0; |
| 92 | |
| 93 | addr >>= 2; |
| 94 | switch (addr) { |
| 95 | case R_RXTX: |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 96 | r = s->regs[addr]; |
| 97 | break; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 98 | case R_DIV: |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 99 | case R_STAT: |
| 100 | case R_CTRL: |
| 101 | case R_DBG: |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 102 | r = s->regs[addr]; |
| 103 | break; |
| 104 | |
| 105 | default: |
| 106 | error_report("milkymist_uart: read access to unknown register 0x" |
| 107 | TARGET_FMT_plx, addr << 2); |
| 108 | break; |
| 109 | } |
| 110 | |
| 111 | trace_milkymist_uart_memory_read(addr << 2, r); |
| 112 | |
| 113 | return r; |
| 114 | } |
| 115 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 116 | static void uart_write(void *opaque, hwaddr addr, uint64_t value, |
Michael Walle | 5adb30d | 2011-08-31 16:48:45 +0200 | [diff] [blame] | 117 | unsigned size) |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 118 | { |
| 119 | MilkymistUartState *s = opaque; |
| 120 | unsigned char ch = value; |
| 121 | |
| 122 | trace_milkymist_uart_memory_write(addr, value); |
| 123 | |
| 124 | addr >>= 2; |
| 125 | switch (addr) { |
| 126 | case R_RXTX: |
| 127 | if (s->chr) { |
Antony Pavlov | b2c623a | 2013-08-31 21:22:39 +0400 | [diff] [blame] | 128 | qemu_chr_fe_write_all(s->chr, &ch, 1); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 129 | } |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 130 | s->regs[R_STAT] |= STAT_TX_EVT; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 131 | break; |
| 132 | case R_DIV: |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 133 | case R_CTRL: |
| 134 | case R_DBG: |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 135 | s->regs[addr] = value; |
| 136 | break; |
| 137 | |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 138 | case R_STAT: |
| 139 | /* write one to clear bits */ |
| 140 | s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT)); |
Michael Walle | 44ac582 | 2012-07-31 00:04:57 +0200 | [diff] [blame] | 141 | qemu_chr_accept_input(s->chr); |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 142 | break; |
| 143 | |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 144 | default: |
| 145 | error_report("milkymist_uart: write access to unknown register 0x" |
| 146 | TARGET_FMT_plx, addr << 2); |
| 147 | break; |
| 148 | } |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 149 | |
| 150 | uart_update_irq(s); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 151 | } |
| 152 | |
Michael Walle | 5adb30d | 2011-08-31 16:48:45 +0200 | [diff] [blame] | 153 | static const MemoryRegionOps uart_mmio_ops = { |
| 154 | .read = uart_read, |
| 155 | .write = uart_write, |
| 156 | .valid = { |
| 157 | .min_access_size = 4, |
| 158 | .max_access_size = 4, |
| 159 | }, |
| 160 | .endianness = DEVICE_NATIVE_ENDIAN, |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 161 | }; |
| 162 | |
| 163 | static void uart_rx(void *opaque, const uint8_t *buf, int size) |
| 164 | { |
| 165 | MilkymistUartState *s = opaque; |
| 166 | |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 167 | assert(!(s->regs[R_STAT] & STAT_RX_EVT)); |
| 168 | |
| 169 | s->regs[R_STAT] |= STAT_RX_EVT; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 170 | s->regs[R_RXTX] = *buf; |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 171 | |
| 172 | uart_update_irq(s); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static int uart_can_rx(void *opaque) |
| 176 | { |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 177 | MilkymistUartState *s = opaque; |
| 178 | |
| 179 | return !(s->regs[R_STAT] & STAT_RX_EVT); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 180 | } |
| 181 | |
| 182 | static void uart_event(void *opaque, int event) |
| 183 | { |
| 184 | } |
| 185 | |
| 186 | static void milkymist_uart_reset(DeviceState *d) |
| 187 | { |
Andreas Färber | 79bbe8b | 2013-07-24 23:08:14 +0200 | [diff] [blame] | 188 | MilkymistUartState *s = MILKYMIST_UART(d); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 189 | int i; |
| 190 | |
| 191 | for (i = 0; i < R_MAX; i++) { |
| 192 | s->regs[i] = 0; |
| 193 | } |
Michael Walle | fcfa339 | 2011-08-11 00:13:23 +0200 | [diff] [blame] | 194 | |
| 195 | /* THRE is always set */ |
| 196 | s->regs[R_STAT] = STAT_THRE; |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 197 | } |
| 198 | |
Antony Pavlov | c77dd5f | 2013-08-31 21:22:40 +0400 | [diff] [blame] | 199 | static void milkymist_uart_realize(DeviceState *dev, Error **errp) |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 200 | { |
Andreas Färber | 79bbe8b | 2013-07-24 23:08:14 +0200 | [diff] [blame] | 201 | MilkymistUartState *s = MILKYMIST_UART(dev); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 202 | |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 203 | if (s->chr) { |
| 204 | qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); |
| 205 | } |
Antony Pavlov | c77dd5f | 2013-08-31 21:22:40 +0400 | [diff] [blame] | 206 | } |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 207 | |
Antony Pavlov | c77dd5f | 2013-08-31 21:22:40 +0400 | [diff] [blame] | 208 | static void milkymist_uart_init(Object *obj) |
| 209 | { |
| 210 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 211 | MilkymistUartState *s = MILKYMIST_UART(obj); |
| 212 | |
| 213 | sysbus_init_irq(sbd, &s->irq); |
| 214 | |
| 215 | memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s, |
| 216 | "milkymist-uart", R_MAX * 4); |
| 217 | sysbus_init_mmio(sbd, &s->regs_region); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | static const VMStateDescription vmstate_milkymist_uart = { |
| 221 | .name = "milkymist-uart", |
| 222 | .version_id = 1, |
| 223 | .minimum_version_id = 1, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 224 | .fields = (VMStateField[]) { |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 225 | VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX), |
| 226 | VMSTATE_END_OF_LIST() |
| 227 | } |
| 228 | }; |
| 229 | |
xiaoqiang zhao | e269fbe | 2016-05-25 14:39:04 +0800 | [diff] [blame] | 230 | static Property milkymist_uart_properties[] = { |
| 231 | DEFINE_PROP_CHR("chardev", MilkymistUartState, chr), |
| 232 | DEFINE_PROP_END_OF_LIST(), |
| 233 | }; |
| 234 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 235 | static void milkymist_uart_class_init(ObjectClass *klass, void *data) |
| 236 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 237 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 238 | |
Antony Pavlov | c77dd5f | 2013-08-31 21:22:40 +0400 | [diff] [blame] | 239 | dc->realize = milkymist_uart_realize; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 240 | dc->reset = milkymist_uart_reset; |
| 241 | dc->vmsd = &vmstate_milkymist_uart; |
xiaoqiang zhao | e269fbe | 2016-05-25 14:39:04 +0800 | [diff] [blame] | 242 | dc->props = milkymist_uart_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 243 | } |
| 244 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 245 | static const TypeInfo milkymist_uart_info = { |
Andreas Färber | 79bbe8b | 2013-07-24 23:08:14 +0200 | [diff] [blame] | 246 | .name = TYPE_MILKYMIST_UART, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 247 | .parent = TYPE_SYS_BUS_DEVICE, |
| 248 | .instance_size = sizeof(MilkymistUartState), |
Antony Pavlov | c77dd5f | 2013-08-31 21:22:40 +0400 | [diff] [blame] | 249 | .instance_init = milkymist_uart_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 250 | .class_init = milkymist_uart_class_init, |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 251 | }; |
| 252 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 253 | static void milkymist_uart_register_types(void) |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 254 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 255 | type_register_static(&milkymist_uart_info); |
Michael Walle | 883de16 | 2011-03-07 23:32:41 +0100 | [diff] [blame] | 256 | } |
| 257 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 258 | type_init(milkymist_uart_register_types) |