Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 1 | #ifndef QEMU_ARCH_INIT_H |
| 2 | #define QEMU_ARCH_INIT_H |
| 3 | |
Anthony Liguori | 76b64a7 | 2012-08-14 22:17:36 -0500 | [diff] [blame] | 4 | |
Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 5 | enum { |
| 6 | QEMU_ARCH_ALL = -1, |
Bastian Koppelmann | 7e3d523 | 2014-09-21 12:07:21 +0100 | [diff] [blame] | 7 | QEMU_ARCH_ALPHA = (1 << 0), |
| 8 | QEMU_ARCH_ARM = (1 << 1), |
| 9 | QEMU_ARCH_CRIS = (1 << 2), |
| 10 | QEMU_ARCH_I386 = (1 << 3), |
| 11 | QEMU_ARCH_M68K = (1 << 4), |
Bastian Koppelmann | 7e3d523 | 2014-09-21 12:07:21 +0100 | [diff] [blame] | 12 | QEMU_ARCH_MICROBLAZE = (1 << 6), |
| 13 | QEMU_ARCH_MIPS = (1 << 7), |
| 14 | QEMU_ARCH_PPC = (1 << 8), |
| 15 | QEMU_ARCH_S390X = (1 << 9), |
| 16 | QEMU_ARCH_SH4 = (1 << 10), |
| 17 | QEMU_ARCH_SPARC = (1 << 11), |
| 18 | QEMU_ARCH_XTENSA = (1 << 12), |
| 19 | QEMU_ARCH_OPENRISC = (1 << 13), |
Bastian Koppelmann | 7e3d523 | 2014-09-21 12:07:21 +0100 | [diff] [blame] | 20 | QEMU_ARCH_TRICORE = (1 << 16), |
Marek Vasut | e671711 | 2017-01-18 23:01:46 +0100 | [diff] [blame] | 21 | QEMU_ARCH_NIOS2 = (1 << 17), |
Helge Deller | 813dff1 | 2017-10-01 22:11:45 +0200 | [diff] [blame] | 22 | QEMU_ARCH_HPPA = (1 << 18), |
Michael Clark | 25fa194 | 2018-03-03 01:32:59 +1300 | [diff] [blame] | 23 | QEMU_ARCH_RISCV = (1 << 19), |
Yoshinori Sato | c8c35e5 | 2019-01-21 05:18:59 -0800 | [diff] [blame] | 24 | QEMU_ARCH_RX = (1 << 20), |
Michael Rolnik | 42f3ff0 | 2020-01-24 01:51:21 +0100 | [diff] [blame] | 25 | QEMU_ARCH_AVR = (1 << 21), |
Kevin Wolf | 5964ed5 | 2020-02-24 15:29:50 +0100 | [diff] [blame] | 26 | |
| 27 | QEMU_ARCH_NONE = (1 << 31), |
Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | extern const uint32_t arch_type; |
| 31 | |
Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 32 | int kvm_available(void); |
Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 33 | |
Laurent Vivier | 203adb4 | 2021-03-23 16:53:02 +0000 | [diff] [blame] | 34 | /* default virtio transport per architecture */ |
| 35 | #define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \ |
| 36 | QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \ |
| 37 | QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \ |
| 38 | QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \ |
| 39 | QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA) |
| 40 | #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X) |
Laurent Vivier | 4c5806a | 2021-03-23 16:53:03 +0000 | [diff] [blame] | 41 | #define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K) |
Laurent Vivier | 203adb4 | 2021-03-23 16:53:02 +0000 | [diff] [blame] | 42 | |
Blue Swirl | ad96090 | 2010-03-29 19:23:52 +0000 | [diff] [blame] | 43 | #endif |