blob: 871a70a316e71af6ed2b981fe0f782d0ecbd79a0 [file] [log] [blame]
Michael Clarkf798f1e2018-03-03 01:31:10 +13001/*
2 * RISC-V FPU Emulation Helpers for QEMU.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "qemu/osdep.h"
Michael Clarkf798f1e2018-03-03 01:31:10 +130020#include "cpu.h"
21#include "qemu/host-utils.h"
22#include "exec/exec-all.h"
23#include "exec/helper-proto.h"
Alex Bennée135b03c2019-08-08 17:29:41 +010024#include "fpu/softfloat.h"
LIU Zhiwei121ddbb2020-07-01 23:25:28 +080025#include "internals.h"
Michael Clarkf798f1e2018-03-03 01:31:10 +130026
Michael Clarkfb738832019-01-14 23:58:23 +000027target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
Michael Clarkf798f1e2018-03-03 01:31:10 +130028{
29 int soft = get_float_exception_flags(&env->fp_status);
30 target_ulong hard = 0;
31
32 hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
33 hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
34 hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
35 hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
36 hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
37
38 return hard;
39}
40
Michael Clarkfb738832019-01-14 23:58:23 +000041void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
Michael Clarkf798f1e2018-03-03 01:31:10 +130042{
43 int soft = 0;
44
45 soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
46 soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
47 soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
48 soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
49 soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
50
51 set_float_exception_flags(soft, &env->fp_status);
52}
53
54void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
55{
56 int softrm;
57
Frank Chang986c8952021-12-10 15:56:46 +080058 if (rm == RISCV_FRM_DYN) {
Michael Clarkf798f1e2018-03-03 01:31:10 +130059 rm = env->frm;
60 }
61 switch (rm) {
Frank Chang986c8952021-12-10 15:56:46 +080062 case RISCV_FRM_RNE:
Michael Clarkf798f1e2018-03-03 01:31:10 +130063 softrm = float_round_nearest_even;
64 break;
Frank Chang986c8952021-12-10 15:56:46 +080065 case RISCV_FRM_RTZ:
Michael Clarkf798f1e2018-03-03 01:31:10 +130066 softrm = float_round_to_zero;
67 break;
Frank Chang986c8952021-12-10 15:56:46 +080068 case RISCV_FRM_RDN:
Michael Clarkf798f1e2018-03-03 01:31:10 +130069 softrm = float_round_down;
70 break;
Frank Chang986c8952021-12-10 15:56:46 +080071 case RISCV_FRM_RUP:
Michael Clarkf798f1e2018-03-03 01:31:10 +130072 softrm = float_round_up;
73 break;
Frank Chang986c8952021-12-10 15:56:46 +080074 case RISCV_FRM_RMM:
Michael Clarkf798f1e2018-03-03 01:31:10 +130075 softrm = float_round_ties_away;
76 break;
77 default:
Michael Clarkfb738832019-01-14 23:58:23 +000078 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
Michael Clarkf798f1e2018-03-03 01:31:10 +130079 }
80
81 set_float_rounding_mode(softrm, &env->fp_status);
82}
83
Richard Henderson3ceeb192023-01-15 06:06:56 -100084void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
85{
86 int softrm;
87
88 /* Always validate frm, even if rm != DYN. */
89 if (unlikely(env->frm >= 5)) {
90 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
91 }
92 if (rm == RISCV_FRM_DYN) {
93 rm = env->frm;
94 }
95 switch (rm) {
96 case RISCV_FRM_RNE:
97 softrm = float_round_nearest_even;
98 break;
99 case RISCV_FRM_RTZ:
100 softrm = float_round_to_zero;
101 break;
102 case RISCV_FRM_RDN:
103 softrm = float_round_down;
104 break;
105 case RISCV_FRM_RUP:
106 softrm = float_round_up;
107 break;
108 case RISCV_FRM_RMM:
109 softrm = float_round_ties_away;
110 break;
111 case RISCV_FRM_ROD:
112 softrm = float_round_to_odd;
113 break;
114 default:
115 g_assert_not_reached();
116 }
117
118 set_float_rounding_mode(softrm, &env->fp_status);
119}
120
Kito Cheng00c18992021-12-10 15:43:21 +0800121static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
122 uint64_t rs3, int flags)
123{
Weiwei Lia2464a42022-02-11 12:39:19 +0800124 float16 frs1 = check_nanbox_h(env, rs1);
125 float16 frs2 = check_nanbox_h(env, rs2);
126 float16 frs3 = check_nanbox_h(env, rs3);
127 return nanbox_h(env, float16_muladd(frs1, frs2, frs3, flags,
128 &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800129}
130
Richard Henderson00e925c2020-07-23 17:28:04 -0700131static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
132 uint64_t rs3, int flags)
Richard Henderson9921e3d2020-07-23 17:28:01 -0700133{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800134 float32 frs1 = check_nanbox_s(env, rs1);
135 float32 frs2 = check_nanbox_s(env, rs2);
136 float32 frs3 = check_nanbox_s(env, rs3);
137 return nanbox_s(env, float32_muladd(frs1, frs2, frs3, flags,
138 &env->fp_status));
Richard Henderson9921e3d2020-07-23 17:28:01 -0700139}
140
Michael Clarkf798f1e2018-03-03 01:31:10 +1300141uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
142 uint64_t frs3)
143{
Richard Henderson9921e3d2020-07-23 17:28:01 -0700144 return do_fmadd_s(env, frs1, frs2, frs3, 0);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300145}
146
147uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
148 uint64_t frs3)
149{
150 return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status);
151}
152
Kito Cheng00c18992021-12-10 15:43:21 +0800153uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
154 uint64_t frs3)
155{
156 return do_fmadd_h(env, frs1, frs2, frs3, 0);
157}
158
Michael Clarkf798f1e2018-03-03 01:31:10 +1300159uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
160 uint64_t frs3)
161{
Richard Henderson9921e3d2020-07-23 17:28:01 -0700162 return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300163}
164
165uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
166 uint64_t frs3)
167{
168 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c,
169 &env->fp_status);
170}
171
Kito Cheng00c18992021-12-10 15:43:21 +0800172uint64_t helper_fmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
173 uint64_t frs3)
174{
175 return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_c);
176}
177
Michael Clarkf798f1e2018-03-03 01:31:10 +1300178uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
179 uint64_t frs3)
180{
Richard Henderson9921e3d2020-07-23 17:28:01 -0700181 return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300182}
183
184uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
185 uint64_t frs3)
186{
187 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product,
188 &env->fp_status);
189}
190
Kito Cheng00c18992021-12-10 15:43:21 +0800191uint64_t helper_fnmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
192 uint64_t frs3)
193{
194 return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_product);
195}
196
Michael Clarkf798f1e2018-03-03 01:31:10 +1300197uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
198 uint64_t frs3)
199{
Richard Henderson9921e3d2020-07-23 17:28:01 -0700200 return do_fmadd_s(env, frs1, frs2, frs3,
201 float_muladd_negate_c | float_muladd_negate_product);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300202}
203
204uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
205 uint64_t frs3)
206{
207 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c |
208 float_muladd_negate_product, &env->fp_status);
209}
210
Kito Cheng00c18992021-12-10 15:43:21 +0800211uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
212 uint64_t frs3)
213{
214 return do_fmadd_h(env, frs1, frs2, frs3,
215 float_muladd_negate_c | float_muladd_negate_product);
216}
217
Richard Henderson00e925c2020-07-23 17:28:04 -0700218uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300219{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800220 float32 frs1 = check_nanbox_s(env, rs1);
221 float32 frs2 = check_nanbox_s(env, rs2);
222 return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300223}
224
Richard Henderson00e925c2020-07-23 17:28:04 -0700225uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300226{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800227 float32 frs1 = check_nanbox_s(env, rs1);
228 float32 frs2 = check_nanbox_s(env, rs2);
229 return nanbox_s(env, float32_sub(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300230}
231
Richard Henderson00e925c2020-07-23 17:28:04 -0700232uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300233{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800234 float32 frs1 = check_nanbox_s(env, rs1);
235 float32 frs2 = check_nanbox_s(env, rs2);
236 return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300237}
238
Richard Henderson00e925c2020-07-23 17:28:04 -0700239uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300240{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800241 float32 frs1 = check_nanbox_s(env, rs1);
242 float32 frs2 = check_nanbox_s(env, rs2);
243 return nanbox_s(env, float32_div(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300244}
245
Richard Henderson00e925c2020-07-23 17:28:04 -0700246uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300247{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800248 float32 frs1 = check_nanbox_s(env, rs1);
249 float32 frs2 = check_nanbox_s(env, rs2);
250 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800251 float32_minnum(frs1, frs2, &env->fp_status) :
252 float32_minimum_number(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300253}
254
Christoph Müllnera47842d2023-07-10 09:12:43 +0200255uint64_t helper_fminm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
256{
257 float32 frs1 = check_nanbox_s(env, rs1);
258 float32 frs2 = check_nanbox_s(env, rs2);
259 float32 ret = float32_min(frs1, frs2, &env->fp_status);
260 return nanbox_s(env, ret);
261}
262
Richard Henderson00e925c2020-07-23 17:28:04 -0700263uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300264{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800265 float32 frs1 = check_nanbox_s(env, rs1);
266 float32 frs2 = check_nanbox_s(env, rs2);
267 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800268 float32_maxnum(frs1, frs2, &env->fp_status) :
269 float32_maximum_number(frs1, frs2, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300270}
271
Christoph Müllnera47842d2023-07-10 09:12:43 +0200272uint64_t helper_fmaxm_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
273{
274 float32 frs1 = check_nanbox_s(env, rs1);
275 float32 frs2 = check_nanbox_s(env, rs2);
276 float32 ret = float32_max(frs1, frs2, &env->fp_status);
277 return nanbox_s(env, ret);
278}
279
Richard Henderson00e925c2020-07-23 17:28:04 -0700280uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300281{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800282 float32 frs1 = check_nanbox_s(env, rs1);
283 return nanbox_s(env, float32_sqrt(frs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300284}
285
Richard Henderson00e925c2020-07-23 17:28:04 -0700286target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300287{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800288 float32 frs1 = check_nanbox_s(env, rs1);
289 float32 frs2 = check_nanbox_s(env, rs2);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300290 return float32_le(frs1, frs2, &env->fp_status);
291}
292
Christoph Müllnera47842d2023-07-10 09:12:43 +0200293target_ulong helper_fleq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
294{
295 float32 frs1 = check_nanbox_s(env, rs1);
296 float32 frs2 = check_nanbox_s(env, rs2);
297 return float32_le_quiet(frs1, frs2, &env->fp_status);
298}
299
Richard Henderson00e925c2020-07-23 17:28:04 -0700300target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300301{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800302 float32 frs1 = check_nanbox_s(env, rs1);
303 float32 frs2 = check_nanbox_s(env, rs2);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300304 return float32_lt(frs1, frs2, &env->fp_status);
305}
306
Christoph Müllnera47842d2023-07-10 09:12:43 +0200307target_ulong helper_fltq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
308{
309 float32 frs1 = check_nanbox_s(env, rs1);
310 float32 frs2 = check_nanbox_s(env, rs2);
311 return float32_lt_quiet(frs1, frs2, &env->fp_status);
312}
313
Richard Henderson00e925c2020-07-23 17:28:04 -0700314target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300315{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800316 float32 frs1 = check_nanbox_s(env, rs1);
317 float32 frs2 = check_nanbox_s(env, rs2);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300318 return float32_eq_quiet(frs1, frs2, &env->fp_status);
319}
320
Richard Henderson00e925c2020-07-23 17:28:04 -0700321target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300322{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800323 float32 frs1 = check_nanbox_s(env, rs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300324 return float32_to_int32(frs1, &env->fp_status);
325}
326
Richard Henderson00e925c2020-07-23 17:28:04 -0700327target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300328{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800329 float32 frs1 = check_nanbox_s(env, rs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300330 return (int32_t)float32_to_uint32(frs1, &env->fp_status);
331}
332
Alistair Francisdaf866b2021-04-24 13:34:12 +1000333target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300334{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800335 float32 frs1 = check_nanbox_s(env, rs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300336 return float32_to_int64(frs1, &env->fp_status);
337}
338
Alistair Francisdaf866b2021-04-24 13:34:12 +1000339target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300340{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800341 float32 frs1 = check_nanbox_s(env, rs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300342 return float32_to_uint64(frs1, &env->fp_status);
343}
Michael Clarkf798f1e2018-03-03 01:31:10 +1300344
345uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
346{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800347 return nanbox_s(env, int32_to_float32((int32_t)rs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300348}
349
350uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
351{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800352 return nanbox_s(env, uint32_to_float32((uint32_t)rs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300353}
354
Alistair Francisdaf866b2021-04-24 13:34:12 +1000355uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300356{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800357 return nanbox_s(env, int64_to_float32(rs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300358}
359
Alistair Francisdaf866b2021-04-24 13:34:12 +1000360uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300361{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800362 return nanbox_s(env, uint64_to_float32(rs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300363}
Michael Clarkf798f1e2018-03-03 01:31:10 +1300364
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800365target_ulong helper_fclass_s(CPURISCVState *env, uint64_t rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300366{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800367 float32 frs1 = check_nanbox_s(env, rs1);
LIU Zhiwei121ddbb2020-07-01 23:25:28 +0800368 return fclass_s(frs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300369}
370
Christoph Müllnera47842d2023-07-10 09:12:43 +0200371uint64_t helper_fround_s(CPURISCVState *env, uint64_t rs1)
372{
373 float_status *fs = &env->fp_status;
374 uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact;
375 float32 frs1 = check_nanbox_s(env, rs1);
376
377 frs1 = float32_round_to_int(frs1, fs);
378
379 /* Restore the original NX flag. */
380 uint16_t flags = get_float_exception_flags(fs);
381 flags &= ~float_flag_inexact;
382 flags |= nx_old;
383 set_float_exception_flags(flags, fs);
384
385 return nanbox_s(env, frs1);
386}
387
388uint64_t helper_froundnx_s(CPURISCVState *env, uint64_t rs1)
389{
390 float32 frs1 = check_nanbox_s(env, rs1);
391 frs1 = float32_round_to_int(frs1, &env->fp_status);
392 return nanbox_s(env, frs1);
393}
394
Michael Clarkf798f1e2018-03-03 01:31:10 +1300395uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
396{
397 return float64_add(frs1, frs2, &env->fp_status);
398}
399
400uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
401{
402 return float64_sub(frs1, frs2, &env->fp_status);
403}
404
405uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
406{
407 return float64_mul(frs1, frs2, &env->fp_status);
408}
409
410uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
411{
412 return float64_div(frs1, frs2, &env->fp_status);
413}
414
415uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
416{
Chih-Min Chao15161e42021-10-22 00:08:46 +0800417 return env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800418 float64_minnum(frs1, frs2, &env->fp_status) :
419 float64_minimum_number(frs1, frs2, &env->fp_status);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300420}
421
Christoph Müllnera47842d2023-07-10 09:12:43 +0200422uint64_t helper_fminm_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
423{
424 return float64_min(frs1, frs2, &env->fp_status);
425}
426
Michael Clarkf798f1e2018-03-03 01:31:10 +1300427uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
428{
Chih-Min Chao15161e42021-10-22 00:08:46 +0800429 return env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800430 float64_maxnum(frs1, frs2, &env->fp_status) :
431 float64_maximum_number(frs1, frs2, &env->fp_status);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300432}
433
Christoph Müllnera47842d2023-07-10 09:12:43 +0200434uint64_t helper_fmaxm_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
435{
436 return float64_max(frs1, frs2, &env->fp_status);
437}
438
Michael Clarkf798f1e2018-03-03 01:31:10 +1300439uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
440{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800441 return nanbox_s(env, float64_to_float32(rs1, &env->fp_status));
Michael Clarkf798f1e2018-03-03 01:31:10 +1300442}
443
444uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
445{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800446 float32 frs1 = check_nanbox_s(env, rs1);
Richard Henderson00e925c2020-07-23 17:28:04 -0700447 return float32_to_float64(frs1, &env->fp_status);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300448}
449
450uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
451{
452 return float64_sqrt(frs1, &env->fp_status);
453}
454
455target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
456{
457 return float64_le(frs1, frs2, &env->fp_status);
458}
459
Christoph Müllnera47842d2023-07-10 09:12:43 +0200460target_ulong helper_fleq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
461{
462 return float64_le_quiet(frs1, frs2, &env->fp_status);
463}
464
Michael Clarkf798f1e2018-03-03 01:31:10 +1300465target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
466{
467 return float64_lt(frs1, frs2, &env->fp_status);
468}
469
Christoph Müllnera47842d2023-07-10 09:12:43 +0200470target_ulong helper_fltq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
471{
472 return float64_lt_quiet(frs1, frs2, &env->fp_status);
473}
474
Michael Clarkf798f1e2018-03-03 01:31:10 +1300475target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
476{
477 return float64_eq_quiet(frs1, frs2, &env->fp_status);
478}
479
480target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1)
481{
482 return float64_to_int32(frs1, &env->fp_status);
483}
484
Christoph Müllnera47842d2023-07-10 09:12:43 +0200485uint64_t helper_fcvtmod_w_d(CPURISCVState *env, uint64_t value)
486{
487 return float64_to_int32_modulo(value, float_round_to_zero, &env->fp_status);
488}
489
Michael Clarkf798f1e2018-03-03 01:31:10 +1300490target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
491{
492 return (int32_t)float64_to_uint32(frs1, &env->fp_status);
493}
494
Alistair Francisdaf866b2021-04-24 13:34:12 +1000495target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300496{
497 return float64_to_int64(frs1, &env->fp_status);
498}
499
Alistair Francisdaf866b2021-04-24 13:34:12 +1000500target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300501{
502 return float64_to_uint64(frs1, &env->fp_status);
503}
Michael Clarkf798f1e2018-03-03 01:31:10 +1300504
505uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
506{
507 return int32_to_float64((int32_t)rs1, &env->fp_status);
508}
509
510uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
511{
512 return uint32_to_float64((uint32_t)rs1, &env->fp_status);
513}
514
Alistair Francisdaf866b2021-04-24 13:34:12 +1000515uint64_t helper_fcvt_d_l(CPURISCVState *env, target_ulong rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300516{
517 return int64_to_float64(rs1, &env->fp_status);
518}
519
Alistair Francisdaf866b2021-04-24 13:34:12 +1000520uint64_t helper_fcvt_d_lu(CPURISCVState *env, target_ulong rs1)
Michael Clarkf798f1e2018-03-03 01:31:10 +1300521{
522 return uint64_to_float64(rs1, &env->fp_status);
523}
Michael Clarkf798f1e2018-03-03 01:31:10 +1300524
525target_ulong helper_fclass_d(uint64_t frs1)
526{
LIU Zhiwei121ddbb2020-07-01 23:25:28 +0800527 return fclass_d(frs1);
Michael Clarkf798f1e2018-03-03 01:31:10 +1300528}
Kito Cheng00c18992021-12-10 15:43:21 +0800529
Christoph Müllnera47842d2023-07-10 09:12:43 +0200530uint64_t helper_fround_d(CPURISCVState *env, uint64_t frs1)
531{
532 float_status *fs = &env->fp_status;
533 uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact;
534
535 frs1 = float64_round_to_int(frs1, fs);
536
537 /* Restore the original NX flag. */
538 uint16_t flags = get_float_exception_flags(fs);
539 flags &= ~float_flag_inexact;
540 flags |= nx_old;
541 set_float_exception_flags(flags, fs);
542
543 return frs1;
544}
545
546uint64_t helper_froundnx_d(CPURISCVState *env, uint64_t frs1)
547{
548 return float64_round_to_int(frs1, &env->fp_status);
549}
550
Kito Cheng00c18992021-12-10 15:43:21 +0800551uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
552{
Weiwei Lia2464a42022-02-11 12:39:19 +0800553 float16 frs1 = check_nanbox_h(env, rs1);
554 float16 frs2 = check_nanbox_h(env, rs2);
555 return nanbox_h(env, float16_add(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800556}
557
558uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
559{
Weiwei Lia2464a42022-02-11 12:39:19 +0800560 float16 frs1 = check_nanbox_h(env, rs1);
561 float16 frs2 = check_nanbox_h(env, rs2);
562 return nanbox_h(env, float16_sub(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800563}
564
565uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
566{
Weiwei Lia2464a42022-02-11 12:39:19 +0800567 float16 frs1 = check_nanbox_h(env, rs1);
568 float16 frs2 = check_nanbox_h(env, rs2);
569 return nanbox_h(env, float16_mul(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800570}
571
572uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
573{
Weiwei Lia2464a42022-02-11 12:39:19 +0800574 float16 frs1 = check_nanbox_h(env, rs1);
575 float16 frs2 = check_nanbox_h(env, rs2);
576 return nanbox_h(env, float16_div(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800577}
578
579uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
580{
Weiwei Lia2464a42022-02-11 12:39:19 +0800581 float16 frs1 = check_nanbox_h(env, rs1);
582 float16 frs2 = check_nanbox_h(env, rs2);
583 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800584 float16_minnum(frs1, frs2, &env->fp_status) :
585 float16_minimum_number(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800586}
587
Christoph Müllnera47842d2023-07-10 09:12:43 +0200588uint64_t helper_fminm_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
589{
590 float16 frs1 = check_nanbox_h(env, rs1);
591 float16 frs2 = check_nanbox_h(env, rs2);
592 float16 ret = float16_min(frs1, frs2, &env->fp_status);
593 return nanbox_h(env, ret);
594}
595
Kito Cheng00c18992021-12-10 15:43:21 +0800596uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
597{
Weiwei Lia2464a42022-02-11 12:39:19 +0800598 float16 frs1 = check_nanbox_h(env, rs1);
599 float16 frs2 = check_nanbox_h(env, rs2);
600 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ?
Weiwei Lic45eff32023-04-05 16:58:11 +0800601 float16_maxnum(frs1, frs2, &env->fp_status) :
602 float16_maximum_number(frs1, frs2, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800603}
604
Christoph Müllnera47842d2023-07-10 09:12:43 +0200605uint64_t helper_fmaxm_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
606{
607 float16 frs1 = check_nanbox_h(env, rs1);
608 float16 frs2 = check_nanbox_h(env, rs2);
609 float16 ret = float16_max(frs1, frs2, &env->fp_status);
610 return nanbox_h(env, ret);
611}
612
Kito Cheng00c18992021-12-10 15:43:21 +0800613uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
614{
Weiwei Lia2464a42022-02-11 12:39:19 +0800615 float16 frs1 = check_nanbox_h(env, rs1);
616 return nanbox_h(env, float16_sqrt(frs1, &env->fp_status));
Kito Cheng00c18992021-12-10 15:43:21 +0800617}
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800618
Kito Cheng11f9c452021-12-10 15:43:23 +0800619target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
620{
Weiwei Lia2464a42022-02-11 12:39:19 +0800621 float16 frs1 = check_nanbox_h(env, rs1);
622 float16 frs2 = check_nanbox_h(env, rs2);
Kito Cheng11f9c452021-12-10 15:43:23 +0800623 return float16_le(frs1, frs2, &env->fp_status);
624}
625
Christoph Müllnera47842d2023-07-10 09:12:43 +0200626target_ulong helper_fleq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
627{
628 float16 frs1 = check_nanbox_h(env, rs1);
629 float16 frs2 = check_nanbox_h(env, rs2);
630 return float16_le_quiet(frs1, frs2, &env->fp_status);
631}
632
Kito Cheng11f9c452021-12-10 15:43:23 +0800633target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
634{
Weiwei Lia2464a42022-02-11 12:39:19 +0800635 float16 frs1 = check_nanbox_h(env, rs1);
636 float16 frs2 = check_nanbox_h(env, rs2);
Kito Cheng11f9c452021-12-10 15:43:23 +0800637 return float16_lt(frs1, frs2, &env->fp_status);
638}
639
Christoph Müllnera47842d2023-07-10 09:12:43 +0200640target_ulong helper_fltq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
641{
642 float16 frs1 = check_nanbox_h(env, rs1);
643 float16 frs2 = check_nanbox_h(env, rs2);
644 return float16_lt_quiet(frs1, frs2, &env->fp_status);
645}
646
Kito Cheng11f9c452021-12-10 15:43:23 +0800647target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
648{
Weiwei Lia2464a42022-02-11 12:39:19 +0800649 float16 frs1 = check_nanbox_h(env, rs1);
650 float16 frs2 = check_nanbox_h(env, rs2);
Kito Cheng11f9c452021-12-10 15:43:23 +0800651 return float16_eq_quiet(frs1, frs2, &env->fp_status);
652}
653
Weiwei Lia2464a42022-02-11 12:39:19 +0800654target_ulong helper_fclass_h(CPURISCVState *env, uint64_t rs1)
Kito Cheng6bc6fc92021-12-10 15:43:24 +0800655{
Weiwei Lia2464a42022-02-11 12:39:19 +0800656 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng6bc6fc92021-12-10 15:43:24 +0800657 return fclass_h(frs1);
658}
659
Christoph Müllnera47842d2023-07-10 09:12:43 +0200660uint64_t helper_fround_h(CPURISCVState *env, uint64_t rs1)
661{
662 float_status *fs = &env->fp_status;
663 uint16_t nx_old = get_float_exception_flags(fs) & float_flag_inexact;
664 float16 frs1 = check_nanbox_h(env, rs1);
665
666 frs1 = float16_round_to_int(frs1, fs);
667
668 /* Restore the original NX flag. */
669 uint16_t flags = get_float_exception_flags(fs);
670 flags &= ~float_flag_inexact;
671 flags |= nx_old;
672 set_float_exception_flags(flags, fs);
673
674 return nanbox_h(env, frs1);
675}
676
677uint64_t helper_froundnx_h(CPURISCVState *env, uint64_t rs1)
678{
679 float16 frs1 = check_nanbox_s(env, rs1);
680 frs1 = float16_round_to_int(frs1, &env->fp_status);
681 return nanbox_h(env, frs1);
682}
683
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800684target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
685{
Weiwei Lia2464a42022-02-11 12:39:19 +0800686 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800687 return float16_to_int32(frs1, &env->fp_status);
688}
689
690target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1)
691{
Weiwei Lia2464a42022-02-11 12:39:19 +0800692 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800693 return (int32_t)float16_to_uint32(frs1, &env->fp_status);
694}
695
696target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1)
697{
Weiwei Lia2464a42022-02-11 12:39:19 +0800698 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800699 return float16_to_int64(frs1, &env->fp_status);
700}
701
702target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1)
703{
Weiwei Lia2464a42022-02-11 12:39:19 +0800704 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800705 return float16_to_uint64(frs1, &env->fp_status);
706}
707
708uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1)
709{
Weiwei Lia2464a42022-02-11 12:39:19 +0800710 return nanbox_h(env, int32_to_float16((int32_t)rs1, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800711}
712
713uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1)
714{
Weiwei Lia2464a42022-02-11 12:39:19 +0800715 return nanbox_h(env, uint32_to_float16((uint32_t)rs1, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800716}
717
718uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1)
719{
Weiwei Lia2464a42022-02-11 12:39:19 +0800720 return nanbox_h(env, int64_to_float16(rs1, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800721}
722
723uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1)
724{
Weiwei Lia2464a42022-02-11 12:39:19 +0800725 return nanbox_h(env, uint64_to_float16(rs1, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800726}
727
728uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1)
729{
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800730 float32 frs1 = check_nanbox_s(env, rs1);
Weiwei Lia2464a42022-02-11 12:39:19 +0800731 return nanbox_h(env, float32_to_float16(frs1, true, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800732}
733
734uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1)
735{
Weiwei Lia2464a42022-02-11 12:39:19 +0800736 float16 frs1 = check_nanbox_h(env, rs1);
Weiwei Lie1a29bb2022-02-11 12:39:17 +0800737 return nanbox_s(env, float16_to_float32(frs1, true, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800738}
739
740uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1)
741{
Weiwei Lia2464a42022-02-11 12:39:19 +0800742 return nanbox_h(env, float64_to_float16(rs1, true, &env->fp_status));
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800743}
744
745uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1)
746{
Weiwei Lia2464a42022-02-11 12:39:19 +0800747 float16 frs1 = check_nanbox_h(env, rs1);
Kito Cheng7b03c8e2021-12-10 15:43:22 +0800748 return float16_to_float64(frs1, true, &env->fp_status);
749}
Weiwei Li5d1270c2023-06-15 14:32:58 +0800750
751uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1)
752{
753 float32 frs1 = check_nanbox_s(env, rs1);
754 return nanbox_h(env, float32_to_bfloat16(frs1, &env->fp_status));
755}
756
757uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1)
758{
759 float16 frs1 = check_nanbox_h(env, rs1);
760 return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status));
761}