balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Intel XScale PXA255/270 OS Timers. |
| 3 | * |
| 4 | * Copyright (c) 2006 Openedhand Ltd. |
| 5 | * Copyright (c) 2006 Thorsten Zitterell |
| 6 | * |
Matthew Fernandez | 8e31bf3 | 2011-06-26 12:21:35 +1000 | [diff] [blame] | 7 | * This code is licensed under the GPL. |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 10 | #include "hw/hw.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 11 | #include "qemu/timer.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 12 | #include "sysemu/sysemu.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 13 | #include "hw/arm/pxa.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 14 | #include "hw/sysbus.h" |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 15 | |
| 16 | #define OSMR0 0x00 |
| 17 | #define OSMR1 0x04 |
| 18 | #define OSMR2 0x08 |
| 19 | #define OSMR3 0x0c |
| 20 | #define OSMR4 0x80 |
| 21 | #define OSMR5 0x84 |
| 22 | #define OSMR6 0x88 |
| 23 | #define OSMR7 0x8c |
| 24 | #define OSMR8 0x90 |
| 25 | #define OSMR9 0x94 |
| 26 | #define OSMR10 0x98 |
| 27 | #define OSMR11 0x9c |
| 28 | #define OSCR 0x10 /* OS Timer Count */ |
| 29 | #define OSCR4 0x40 |
| 30 | #define OSCR5 0x44 |
| 31 | #define OSCR6 0x48 |
| 32 | #define OSCR7 0x4c |
| 33 | #define OSCR8 0x50 |
| 34 | #define OSCR9 0x54 |
| 35 | #define OSCR10 0x58 |
| 36 | #define OSCR11 0x5c |
| 37 | #define OSSR 0x14 /* Timer status register */ |
| 38 | #define OWER 0x18 |
| 39 | #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
| 40 | #define OMCR4 0xc0 /* OS Match Control registers */ |
| 41 | #define OMCR5 0xc4 |
| 42 | #define OMCR6 0xc8 |
| 43 | #define OMCR7 0xcc |
| 44 | #define OMCR8 0xd0 |
| 45 | #define OMCR9 0xd4 |
| 46 | #define OMCR10 0xd8 |
| 47 | #define OMCR11 0xdc |
| 48 | #define OSNR 0x20 |
| 49 | |
| 50 | #define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
| 51 | #define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
| 52 | |
| 53 | static int pxa2xx_timer4_freq[8] = { |
| 54 | [0] = 0, |
| 55 | [1] = 32768, |
| 56 | [2] = 1000, |
| 57 | [3] = 1, |
| 58 | [4] = 1000000, |
| 59 | /* [5] is the "Externally supplied clock". Assign if necessary. */ |
| 60 | [5 ... 7] = 0, |
| 61 | }; |
| 62 | |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 63 | #define TYPE_PXA2XX_TIMER "pxa2xx-timer" |
| 64 | #define PXA2XX_TIMER(obj) \ |
| 65 | OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER) |
| 66 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 67 | typedef struct PXA2xxTimerInfo PXA2xxTimerInfo; |
| 68 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 69 | typedef struct { |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 70 | uint32_t value; |
Andrzej Zaborowski | 5251d19 | 2011-03-03 14:24:25 +0100 | [diff] [blame] | 71 | qemu_irq irq; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 72 | QEMUTimer *qtimer; |
| 73 | int num; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 74 | PXA2xxTimerInfo *info; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 75 | } PXA2xxTimer0; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 76 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 77 | typedef struct { |
| 78 | PXA2xxTimer0 tm; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 79 | int32_t oldclock; |
| 80 | int32_t clock; |
| 81 | uint64_t lastload; |
| 82 | uint32_t freq; |
| 83 | uint32_t control; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 84 | } PXA2xxTimer4; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 85 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 86 | struct PXA2xxTimerInfo { |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 87 | SysBusDevice parent_obj; |
| 88 | |
Benoît Canet | b755bde | 2011-10-30 14:50:16 +0100 | [diff] [blame] | 89 | MemoryRegion iomem; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 90 | uint32_t flags; |
| 91 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 92 | int32_t clock; |
| 93 | int32_t oldclock; |
| 94 | uint64_t lastload; |
| 95 | uint32_t freq; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 96 | PXA2xxTimer0 timer[4]; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 97 | uint32_t events; |
| 98 | uint32_t irq_enabled; |
| 99 | uint32_t reset3; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 100 | uint32_t snapshot; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 101 | |
Dmitry Eremin-Solenikov | 4ff927c | 2011-03-04 03:40:59 +0300 | [diff] [blame] | 102 | qemu_irq irq4; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 103 | PXA2xxTimer4 tm4[8]; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | #define PXA2XX_TIMER_HAVE_TM4 0 |
| 107 | |
| 108 | static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s) |
| 109 | { |
| 110 | return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4); |
| 111 | } |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 112 | |
| 113 | static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
| 114 | { |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 115 | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 116 | int i; |
| 117 | uint32_t now_vm; |
| 118 | uint64_t new_qemu; |
| 119 | |
| 120 | now_vm = s->clock + |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 121 | muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec()); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 122 | |
| 123 | for (i = 0; i < 4; i ++) { |
| 124 | new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 125 | get_ticks_per_sec(), s->freq); |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 126 | timer_mod(s->timer[i].qtimer, new_qemu); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 127 | } |
| 128 | } |
| 129 | |
| 130 | static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
| 131 | { |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 132 | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 133 | uint32_t now_vm; |
| 134 | uint64_t new_qemu; |
| 135 | static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
| 136 | int counter; |
| 137 | |
| 138 | if (s->tm4[n].control & (1 << 7)) |
| 139 | counter = n; |
| 140 | else |
| 141 | counter = counters[n]; |
| 142 | |
| 143 | if (!s->tm4[counter].freq) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 144 | timer_del(s->tm4[n].tm.qtimer); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 145 | return; |
| 146 | } |
| 147 | |
| 148 | now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
| 149 | s->tm4[counter].lastload, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 150 | s->tm4[counter].freq, get_ticks_per_sec()); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 151 | |
balrog | 3bdd58a | 2007-05-08 22:51:00 +0000 | [diff] [blame] | 152 | new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 153 | get_ticks_per_sec(), s->tm4[counter].freq); |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 154 | timer_mod(s->tm4[n].tm.qtimer, new_qemu); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 155 | } |
| 156 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 157 | static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, |
Benoît Canet | b755bde | 2011-10-30 14:50:16 +0100 | [diff] [blame] | 158 | unsigned size) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 159 | { |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 160 | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 161 | int tm = 0; |
| 162 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 163 | switch (offset) { |
| 164 | case OSMR3: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 165 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 166 | case OSMR2: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 167 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 168 | case OSMR1: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 169 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 170 | case OSMR0: |
| 171 | return s->timer[tm].value; |
| 172 | case OSMR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 173 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 174 | case OSMR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 175 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 176 | case OSMR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 177 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 178 | case OSMR8: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 179 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 180 | case OSMR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 181 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 182 | case OSMR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 183 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 184 | case OSMR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 185 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 186 | case OSMR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 187 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 188 | goto badreg; |
balrog | 3bdd58a | 2007-05-08 22:51:00 +0000 | [diff] [blame] | 189 | return s->tm4[tm].tm.value; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 190 | case OSCR: |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 191 | return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 192 | s->lastload, s->freq, get_ticks_per_sec()); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 193 | case OSCR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 194 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 195 | case OSCR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 196 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 197 | case OSCR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 198 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 199 | case OSCR8: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 200 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 201 | case OSCR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 202 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 203 | case OSCR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 204 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 205 | case OSCR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 206 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 207 | case OSCR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 208 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 209 | goto badreg; |
| 210 | |
| 211 | if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
| 212 | if (s->tm4[tm - 1].freq) |
| 213 | s->snapshot = s->tm4[tm - 1].clock + muldiv64( |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 214 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 215 | s->tm4[tm - 1].lastload, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 216 | s->tm4[tm - 1].freq, get_ticks_per_sec()); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 217 | else |
| 218 | s->snapshot = s->tm4[tm - 1].clock; |
| 219 | } |
| 220 | |
| 221 | if (!s->tm4[tm].freq) |
| 222 | return s->tm4[tm].clock; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 223 | return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 224 | s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 225 | case OIER: |
| 226 | return s->irq_enabled; |
| 227 | case OSSR: /* Status register */ |
| 228 | return s->events; |
| 229 | case OWER: |
| 230 | return s->reset3; |
| 231 | case OMCR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 232 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 233 | case OMCR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 234 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 235 | case OMCR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 236 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 237 | case OMCR8: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 238 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 239 | case OMCR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 240 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 241 | case OMCR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 242 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 243 | case OMCR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 244 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 245 | case OMCR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 246 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 247 | goto badreg; |
| 248 | return s->tm4[tm].control; |
| 249 | case OSNR: |
| 250 | return s->snapshot; |
| 251 | default: |
| 252 | badreg: |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 253 | hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 259 | static void pxa2xx_timer_write(void *opaque, hwaddr offset, |
Benoît Canet | b755bde | 2011-10-30 14:50:16 +0100 | [diff] [blame] | 260 | uint64_t value, unsigned size) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 261 | { |
| 262 | int i, tm = 0; |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 263 | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 264 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 265 | switch (offset) { |
| 266 | case OSMR3: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 267 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 268 | case OSMR2: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 269 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 270 | case OSMR1: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 271 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 272 | case OSMR0: |
| 273 | s->timer[tm].value = value; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 274 | pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 275 | break; |
| 276 | case OSMR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 277 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 278 | case OSMR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 279 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 280 | case OSMR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 281 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 282 | case OSMR8: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 283 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 284 | case OSMR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 285 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 286 | case OSMR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 287 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 288 | case OSMR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 289 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 290 | case OSMR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 291 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 292 | goto badreg; |
balrog | 3bdd58a | 2007-05-08 22:51:00 +0000 | [diff] [blame] | 293 | s->tm4[tm].tm.value = value; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 294 | pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 295 | break; |
| 296 | case OSCR: |
| 297 | s->oldclock = s->clock; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 298 | s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 299 | s->clock = value; |
| 300 | pxa2xx_timer_update(s, s->lastload); |
| 301 | break; |
| 302 | case OSCR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 303 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 304 | case OSCR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 305 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 306 | case OSCR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 307 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 308 | case OSCR8: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 309 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 310 | case OSCR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 311 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 312 | case OSCR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 313 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 314 | case OSCR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 315 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 316 | case OSCR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 317 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 318 | goto badreg; |
| 319 | s->tm4[tm].oldclock = s->tm4[tm].clock; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 320 | s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 321 | s->tm4[tm].clock = value; |
| 322 | pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
| 323 | break; |
| 324 | case OIER: |
| 325 | s->irq_enabled = value & 0xfff; |
| 326 | break; |
| 327 | case OSSR: /* Status register */ |
Andrzej Zaborowski | 8034ce7 | 2011-03-10 03:31:02 +0100 | [diff] [blame] | 328 | value &= s->events; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 329 | s->events &= ~value; |
Andrzej Zaborowski | 8034ce7 | 2011-03-10 03:31:02 +0100 | [diff] [blame] | 330 | for (i = 0; i < 4; i ++, value >>= 1) |
| 331 | if (value & 1) |
Andrzej Zaborowski | 5251d19 | 2011-03-03 14:24:25 +0100 | [diff] [blame] | 332 | qemu_irq_lower(s->timer[i].irq); |
Andrzej Zaborowski | 8034ce7 | 2011-03-10 03:31:02 +0100 | [diff] [blame] | 333 | if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value) |
| 334 | qemu_irq_lower(s->irq4); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 335 | break; |
| 336 | case OWER: /* XXX: Reset on OSMR3 match? */ |
| 337 | s->reset3 = value; |
| 338 | break; |
| 339 | case OMCR7: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 340 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 341 | case OMCR6: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 342 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 343 | case OMCR5: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 344 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 345 | case OMCR4: |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 346 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 347 | goto badreg; |
| 348 | s->tm4[tm].control = value & 0x0ff; |
| 349 | /* XXX Stop if running (shouldn't happen) */ |
| 350 | if ((value & (1 << 7)) || tm == 0) |
| 351 | s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7]; |
| 352 | else { |
| 353 | s->tm4[tm].freq = 0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 354 | pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 355 | } |
| 356 | break; |
| 357 | case OMCR11: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 358 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 359 | case OMCR10: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 360 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 361 | case OMCR9: tm ++; |
Peter Maydell | de16017 | 2013-01-21 12:50:56 +0000 | [diff] [blame] | 362 | /* fall through */ |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 363 | case OMCR8: tm += 4; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 364 | if (!pxa2xx_timer_has_tm4(s)) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 365 | goto badreg; |
| 366 | s->tm4[tm].control = value & 0x3ff; |
| 367 | /* XXX Stop if running (shouldn't happen) */ |
| 368 | if ((value & (1 << 7)) || !(tm & 1)) |
| 369 | s->tm4[tm].freq = |
| 370 | pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
| 371 | else { |
| 372 | s->tm4[tm].freq = 0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 373 | pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 374 | } |
| 375 | break; |
| 376 | default: |
| 377 | badreg: |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 378 | hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 379 | } |
| 380 | } |
| 381 | |
Benoît Canet | b755bde | 2011-10-30 14:50:16 +0100 | [diff] [blame] | 382 | static const MemoryRegionOps pxa2xx_timer_ops = { |
| 383 | .read = pxa2xx_timer_read, |
| 384 | .write = pxa2xx_timer_write, |
| 385 | .endianness = DEVICE_NATIVE_ENDIAN, |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 386 | }; |
| 387 | |
| 388 | static void pxa2xx_timer_tick(void *opaque) |
| 389 | { |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 390 | PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 391 | PXA2xxTimerInfo *i = t->info; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 392 | |
| 393 | if (i->irq_enabled & (1 << t->num)) { |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 394 | i->events |= 1 << t->num; |
Andrzej Zaborowski | 5251d19 | 2011-03-03 14:24:25 +0100 | [diff] [blame] | 395 | qemu_irq_raise(t->irq); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 396 | } |
| 397 | |
| 398 | if (t->num == 3) |
| 399 | if (i->reset3 & 1) { |
| 400 | i->reset3 = 0; |
balrog | 3f58226 | 2007-05-23 21:47:51 +0000 | [diff] [blame] | 401 | qemu_system_reset_request(); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 402 | } |
| 403 | } |
| 404 | |
| 405 | static void pxa2xx_timer_tick4(void *opaque) |
| 406 | { |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 407 | PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 408 | PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 409 | |
balrog | 3bdd58a | 2007-05-08 22:51:00 +0000 | [diff] [blame] | 410 | pxa2xx_timer_tick(&t->tm); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 411 | if (t->control & (1 << 3)) |
| 412 | t->clock = 0; |
| 413 | if (t->control & (1 << 6)) |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 414 | pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4); |
Dmitry Eremin-Solenikov | 4ff927c | 2011-03-04 03:40:59 +0300 | [diff] [blame] | 415 | if (i->events & 0xff0) |
| 416 | qemu_irq_raise(i->irq4); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 417 | } |
| 418 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 419 | static int pxa25x_timer_post_load(void *opaque, int version_id) |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 420 | { |
Dmitry Eremin-Solenikov | d353eb4 | 2011-02-20 16:50:33 +0300 | [diff] [blame] | 421 | PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque; |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 422 | int64_t now; |
| 423 | int i; |
| 424 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 425 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 426 | pxa2xx_timer_update(s, now); |
| 427 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 428 | if (pxa2xx_timer_has_tm4(s)) |
| 429 | for (i = 0; i < 8; i ++) |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 430 | pxa2xx_timer_update4(s, now, i); |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 431 | |
| 432 | return 0; |
| 433 | } |
| 434 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 435 | static int pxa2xx_timer_init(SysBusDevice *dev) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 436 | { |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 437 | PXA2xxTimerInfo *s = PXA2XX_TIMER(dev); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 438 | int i; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 439 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 440 | s->irq_enabled = 0; |
| 441 | s->oldclock = 0; |
| 442 | s->clock = 0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 443 | s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 444 | s->reset3 = 0; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 445 | |
| 446 | for (i = 0; i < 4; i ++) { |
| 447 | s->timer[i].value = 0; |
Andrzej Zaborowski | 5251d19 | 2011-03-03 14:24:25 +0100 | [diff] [blame] | 448 | sysbus_init_irq(dev, &s->timer[i].irq); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 449 | s->timer[i].info = s; |
| 450 | s->timer[i].num = i; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 451 | s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 452 | pxa2xx_timer_tick, &s->timer[i]); |
| 453 | } |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 454 | if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { |
Dmitry Eremin-Solenikov | 4ff927c | 2011-03-04 03:40:59 +0300 | [diff] [blame] | 455 | sysbus_init_irq(dev, &s->irq4); |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 456 | |
| 457 | for (i = 0; i < 8; i ++) { |
| 458 | s->tm4[i].tm.value = 0; |
| 459 | s->tm4[i].tm.info = s; |
| 460 | s->tm4[i].tm.num = i + 4; |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 461 | s->tm4[i].freq = 0; |
| 462 | s->tm4[i].control = 0x0; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 463 | s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 464 | pxa2xx_timer_tick4, &s->tm4[i]); |
| 465 | } |
| 466 | } |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 467 | |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 468 | memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_timer_ops, s, |
Benoît Canet | b755bde | 2011-10-30 14:50:16 +0100 | [diff] [blame] | 469 | "pxa2xx-timer", 0x00001000); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 470 | sysbus_init_mmio(dev, &s->iomem); |
balrog | aa941b9 | 2007-05-24 18:50:09 +0000 | [diff] [blame] | 471 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 472 | return 0; |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 473 | } |
| 474 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 475 | static const VMStateDescription vmstate_pxa2xx_timer0_regs = { |
| 476 | .name = "pxa2xx_timer0", |
Andrzej Zaborowski | 8034ce7 | 2011-03-10 03:31:02 +0100 | [diff] [blame] | 477 | .version_id = 2, |
| 478 | .minimum_version_id = 2, |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 479 | .fields = (VMStateField[]) { |
| 480 | VMSTATE_UINT32(value, PXA2xxTimer0), |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 481 | VMSTATE_END_OF_LIST(), |
| 482 | }, |
| 483 | }; |
| 484 | |
| 485 | static const VMStateDescription vmstate_pxa2xx_timer4_regs = { |
| 486 | .name = "pxa2xx_timer4", |
| 487 | .version_id = 1, |
| 488 | .minimum_version_id = 1, |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 489 | .fields = (VMStateField[]) { |
| 490 | VMSTATE_STRUCT(tm, PXA2xxTimer4, 1, |
| 491 | vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
| 492 | VMSTATE_INT32(oldclock, PXA2xxTimer4), |
| 493 | VMSTATE_INT32(clock, PXA2xxTimer4), |
| 494 | VMSTATE_UINT64(lastload, PXA2xxTimer4), |
| 495 | VMSTATE_UINT32(freq, PXA2xxTimer4), |
| 496 | VMSTATE_UINT32(control, PXA2xxTimer4), |
| 497 | VMSTATE_END_OF_LIST(), |
| 498 | }, |
| 499 | }; |
| 500 | |
| 501 | static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id) |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 502 | { |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 503 | return pxa2xx_timer_has_tm4(opaque); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 504 | } |
| 505 | |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 506 | static const VMStateDescription vmstate_pxa2xx_timer_regs = { |
| 507 | .name = "pxa2xx_timer", |
| 508 | .version_id = 1, |
| 509 | .minimum_version_id = 1, |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 510 | .post_load = pxa25x_timer_post_load, |
| 511 | .fields = (VMStateField[]) { |
| 512 | VMSTATE_INT32(clock, PXA2xxTimerInfo), |
| 513 | VMSTATE_INT32(oldclock, PXA2xxTimerInfo), |
| 514 | VMSTATE_UINT64(lastload, PXA2xxTimerInfo), |
| 515 | VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1, |
| 516 | vmstate_pxa2xx_timer0_regs, PXA2xxTimer0), |
| 517 | VMSTATE_UINT32(events, PXA2xxTimerInfo), |
| 518 | VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo), |
| 519 | VMSTATE_UINT32(reset3, PXA2xxTimerInfo), |
| 520 | VMSTATE_UINT32(snapshot, PXA2xxTimerInfo), |
| 521 | VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8, |
| 522 | pxa2xx_timer_has_tm4_test, 0, |
| 523 | vmstate_pxa2xx_timer4_regs, PXA2xxTimer4), |
| 524 | VMSTATE_END_OF_LIST(), |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 525 | } |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 526 | }; |
| 527 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 528 | static Property pxa25x_timer_dev_properties[] = { |
| 529 | DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ), |
| 530 | DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags, |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 531 | PXA2XX_TIMER_HAVE_TM4, false), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 532 | DEFINE_PROP_END_OF_LIST(), |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 533 | }; |
| 534 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 535 | static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data) |
| 536 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 537 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 538 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 539 | dc->desc = "PXA25x timer"; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 540 | dc->props = pxa25x_timer_dev_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 541 | } |
| 542 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 543 | static const TypeInfo pxa25x_timer_dev_info = { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 544 | .name = "pxa25x-timer", |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 545 | .parent = TYPE_PXA2XX_TIMER, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 546 | .instance_size = sizeof(PXA2xxTimerInfo), |
| 547 | .class_init = pxa25x_timer_dev_class_init, |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 548 | }; |
| 549 | |
| 550 | static Property pxa27x_timer_dev_properties[] = { |
| 551 | DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ), |
| 552 | DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags, |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 553 | PXA2XX_TIMER_HAVE_TM4, true), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 554 | DEFINE_PROP_END_OF_LIST(), |
| 555 | }; |
| 556 | |
| 557 | static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data) |
| 558 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 559 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 560 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 561 | dc->desc = "PXA27x timer"; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 562 | dc->props = pxa27x_timer_dev_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 563 | } |
| 564 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 565 | static const TypeInfo pxa27x_timer_dev_info = { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 566 | .name = "pxa27x-timer", |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 567 | .parent = TYPE_PXA2XX_TIMER, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 568 | .instance_size = sizeof(PXA2xxTimerInfo), |
| 569 | .class_init = pxa27x_timer_dev_class_init, |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 570 | }; |
| 571 | |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 572 | static void pxa2xx_timer_class_init(ObjectClass *oc, void *data) |
| 573 | { |
| 574 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 575 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc); |
| 576 | |
| 577 | sdc->init = pxa2xx_timer_init; |
| 578 | dc->vmsd = &vmstate_pxa2xx_timer_regs; |
| 579 | } |
| 580 | |
| 581 | static const TypeInfo pxa2xx_timer_type_info = { |
| 582 | .name = TYPE_PXA2XX_TIMER, |
| 583 | .parent = TYPE_SYS_BUS_DEVICE, |
| 584 | .instance_size = sizeof(PXA2xxTimerInfo), |
| 585 | .abstract = true, |
| 586 | .class_init = pxa2xx_timer_class_init, |
| 587 | }; |
| 588 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 589 | static void pxa2xx_timer_register_types(void) |
Dmitry Eremin-Solenikov | 797e954 | 2011-03-03 14:14:44 +0100 | [diff] [blame] | 590 | { |
Andreas Färber | feea436 | 2013-07-27 15:20:20 +0200 | [diff] [blame] | 591 | type_register_static(&pxa2xx_timer_type_info); |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 592 | type_register_static(&pxa25x_timer_dev_info); |
| 593 | type_register_static(&pxa27x_timer_dev_info); |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | type_init(pxa2xx_timer_register_types) |