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Joel Stanleye1acf582022-02-18 09:18:10 +01001/*
2 * ASPEED Secure Boot Controller
3 *
4 * Copyright (C) 2021-2022 IBM Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9#ifndef ASPEED_SBC_H
10#define ASPEED_SBC_H
11
12#include "hw/sysbus.h"
13
14#define TYPE_ASPEED_SBC "aspeed.sbc"
15#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
16OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
17
18#define ASPEED_SBC_NR_REGS (0x93c >> 2)
19
Joel Stanley54ee5642022-07-14 16:24:38 +020020#define QSR_AES BIT(27)
21#define QSR_RSA1024 (0x0 << 12)
22#define QSR_RSA2048 (0x1 << 12)
23#define QSR_RSA3072 (0x2 << 12)
24#define QSR_RSA4096 (0x3 << 12)
25#define QSR_SHA224 (0x0 << 10)
26#define QSR_SHA256 (0x1 << 10)
27#define QSR_SHA384 (0x2 << 10)
28#define QSR_SHA512 (0x3 << 10)
29
Joel Stanleye1acf582022-02-18 09:18:10 +010030struct AspeedSBCState {
31 SysBusDevice parent;
32
Joel Stanley54ee5642022-07-14 16:24:38 +020033 bool emmc_abr;
34 uint32_t signing_settings;
35
Joel Stanleye1acf582022-02-18 09:18:10 +010036 MemoryRegion iomem;
37
38 uint32_t regs[ASPEED_SBC_NR_REGS];
39};
40
41struct AspeedSBCClass {
42 SysBusDeviceClass parent_class;
43};
44
Markus Armbrusterea9cea92022-05-06 15:49:11 +020045#endif /* ASPEED_SBC_H */