Andreas Färber | 9c219b7 | 2013-08-19 01:33:59 +0200 | [diff] [blame] | 1 | /* |
| 2 | * RealView ARM11MPCore internal peripheral emulation |
| 3 | * |
| 4 | * Copyright (c) 2006-2007 CodeSourcery. |
| 5 | * Copyright (c) 2013 SUSE LINUX Products GmbH |
| 6 | * Written by Paul Brook and Andreas Färber |
| 7 | * |
| 8 | * This code is licensed under the GPL. |
| 9 | */ |
| 10 | |
Peter Maydell | 17b7f2d | 2016-01-26 18:17:28 +0000 | [diff] [blame] | 11 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 12 | #include "qapi/error.h" |
Andreas Färber | 9c219b7 | 2013-08-19 01:33:59 +0200 | [diff] [blame] | 13 | #include "hw/cpu/arm11mpcore.h" |
| 14 | #include "hw/intc/realview_gic.h" |
| 15 | |
| 16 | #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" |
| 17 | #define REALVIEW_MPCORE_RIRQ(obj) \ |
| 18 | OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) |
| 19 | |
| 20 | /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ |
| 21 | controllers. The output of these, plus some of the raw input lines |
| 22 | are fed into a single SMP-aware interrupt controller on the CPU. */ |
| 23 | typedef struct { |
| 24 | SysBusDevice parent_obj; |
| 25 | |
| 26 | qemu_irq cpuic[32]; |
| 27 | qemu_irq rvic[4][64]; |
| 28 | uint32_t num_cpu; |
| 29 | |
| 30 | ARM11MPCorePriveState priv; |
| 31 | RealViewGICState gic[4]; |
| 32 | } mpcore_rirq_state; |
| 33 | |
| 34 | /* Map baseboard IRQs onto CPU IRQ lines. */ |
| 35 | static const int mpcore_irq_map[32] = { |
| 36 | -1, -1, -1, -1, 1, 2, -1, -1, |
| 37 | -1, -1, 6, -1, 4, 5, -1, -1, |
| 38 | -1, 14, 15, 0, 7, 8, -1, -1, |
| 39 | -1, -1, -1, -1, 9, 3, -1, -1, |
| 40 | }; |
| 41 | |
| 42 | static void mpcore_rirq_set_irq(void *opaque, int irq, int level) |
| 43 | { |
| 44 | mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; |
| 45 | int i; |
| 46 | |
| 47 | for (i = 0; i < 4; i++) { |
| 48 | qemu_set_irq(s->rvic[i][irq], level); |
| 49 | } |
| 50 | if (irq < 32) { |
| 51 | irq = mpcore_irq_map[irq]; |
| 52 | if (irq >= 0) { |
| 53 | qemu_set_irq(s->cpuic[irq], level); |
| 54 | } |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | static void realview_mpcore_realize(DeviceState *dev, Error **errp) |
| 59 | { |
| 60 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 61 | mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); |
| 62 | DeviceState *priv = DEVICE(&s->priv); |
| 63 | DeviceState *gic; |
| 64 | SysBusDevice *gicbusdev; |
| 65 | Error *err = NULL; |
| 66 | int n; |
| 67 | int i; |
| 68 | |
| 69 | qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); |
| 70 | object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); |
| 71 | if (err != NULL) { |
| 72 | error_propagate(errp, err); |
| 73 | return; |
| 74 | } |
| 75 | sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); |
| 76 | for (i = 0; i < 32; i++) { |
| 77 | s->cpuic[i] = qdev_get_gpio_in(priv, i); |
| 78 | } |
| 79 | /* ??? IRQ routing is hardcoded to "normal" mode. */ |
| 80 | for (n = 0; n < 4; n++) { |
| 81 | object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err); |
| 82 | if (err != NULL) { |
| 83 | error_propagate(errp, err); |
| 84 | return; |
| 85 | } |
| 86 | gic = DEVICE(&s->gic[n]); |
| 87 | gicbusdev = SYS_BUS_DEVICE(&s->gic[n]); |
| 88 | sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); |
| 89 | sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); |
| 90 | for (i = 0; i < 64; i++) { |
| 91 | s->rvic[n][i] = qdev_get_gpio_in(gic, i); |
| 92 | } |
| 93 | } |
| 94 | qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); |
| 95 | } |
| 96 | |
| 97 | static void mpcore_rirq_init(Object *obj) |
| 98 | { |
| 99 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
| 100 | mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj); |
| 101 | SysBusDevice *privbusdev; |
| 102 | int i; |
| 103 | |
| 104 | object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV); |
| 105 | qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default()); |
| 106 | privbusdev = SYS_BUS_DEVICE(&s->priv); |
| 107 | sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); |
| 108 | |
| 109 | for (i = 0; i < 4; i++) { |
| 110 | object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_GIC); |
| 111 | qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default()); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | static Property mpcore_rirq_properties[] = { |
| 116 | DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
| 117 | DEFINE_PROP_END_OF_LIST(), |
| 118 | }; |
| 119 | |
| 120 | static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
| 121 | { |
| 122 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 123 | |
| 124 | dc->realize = realview_mpcore_realize; |
| 125 | dc->props = mpcore_rirq_properties; |
| 126 | } |
| 127 | |
| 128 | static const TypeInfo mpcore_rirq_info = { |
| 129 | .name = TYPE_REALVIEW_MPCORE_RIRQ, |
| 130 | .parent = TYPE_SYS_BUS_DEVICE, |
| 131 | .instance_size = sizeof(mpcore_rirq_state), |
| 132 | .instance_init = mpcore_rirq_init, |
| 133 | .class_init = mpcore_rirq_class_init, |
| 134 | }; |
| 135 | |
| 136 | static void realview_mpcore_register_types(void) |
| 137 | { |
| 138 | type_register_static(&mpcore_rirq_info); |
| 139 | } |
| 140 | |
| 141 | type_init(realview_mpcore_register_types) |