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bellard5a9fdfe2003-06-15 20:02:25 +00001/*
2 * defines common to all virtual CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_ALL_H
21#define CPU_ALL_H
22
bellard0ac4bd52004-01-04 15:44:17 +000023#if defined(__arm__) || defined(__sparc__)
24#define WORDS_ALIGNED
25#endif
26
27/* some important defines:
28 *
29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
30 * memory accesses.
31 *
32 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
33 * otherwise little endian.
34 *
35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
36 *
37 * TARGET_WORDS_BIGENDIAN : same for target cpu
38 */
39
bellardf193c792004-03-21 17:06:25 +000040#include "bswap.h"
41
42#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
43#define BSWAP_NEEDED
44#endif
45
46#ifdef BSWAP_NEEDED
47
48static inline uint16_t tswap16(uint16_t s)
49{
50 return bswap16(s);
51}
52
53static inline uint32_t tswap32(uint32_t s)
54{
55 return bswap32(s);
56}
57
58static inline uint64_t tswap64(uint64_t s)
59{
60 return bswap64(s);
61}
62
63static inline void tswap16s(uint16_t *s)
64{
65 *s = bswap16(*s);
66}
67
68static inline void tswap32s(uint32_t *s)
69{
70 *s = bswap32(*s);
71}
72
73static inline void tswap64s(uint64_t *s)
74{
75 *s = bswap64(*s);
76}
77
78#else
79
80static inline uint16_t tswap16(uint16_t s)
81{
82 return s;
83}
84
85static inline uint32_t tswap32(uint32_t s)
86{
87 return s;
88}
89
90static inline uint64_t tswap64(uint64_t s)
91{
92 return s;
93}
94
95static inline void tswap16s(uint16_t *s)
96{
97}
98
99static inline void tswap32s(uint32_t *s)
100{
101}
102
103static inline void tswap64s(uint64_t *s)
104{
105}
106
107#endif
108
109#if TARGET_LONG_SIZE == 4
110#define tswapl(s) tswap32(s)
111#define tswapls(s) tswap32s((uint32_t *)(s))
bellard0a962c02005-02-10 22:00:27 +0000112#define bswaptls(s) bswap32s(s)
bellardf193c792004-03-21 17:06:25 +0000113#else
114#define tswapl(s) tswap64(s)
115#define tswapls(s) tswap64s((uint64_t *)(s))
bellard0a962c02005-02-10 22:00:27 +0000116#define bswaptls(s) bswap64s(s)
bellardf193c792004-03-21 17:06:25 +0000117#endif
118
bellard832ed0f2005-02-07 12:35:16 +0000119/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
120 endian ! */
bellard0ac4bd52004-01-04 15:44:17 +0000121typedef union {
bellard53cd6632005-03-13 18:50:23 +0000122 float64 d;
bellard9d60cac2005-04-07 19:55:52 +0000123#if defined(WORDS_BIGENDIAN) \
124 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
bellard0ac4bd52004-01-04 15:44:17 +0000125 struct {
bellard0ac4bd52004-01-04 15:44:17 +0000126 uint32_t upper;
bellard832ed0f2005-02-07 12:35:16 +0000127 uint32_t lower;
bellard0ac4bd52004-01-04 15:44:17 +0000128 } l;
129#else
130 struct {
bellard0ac4bd52004-01-04 15:44:17 +0000131 uint32_t lower;
bellard832ed0f2005-02-07 12:35:16 +0000132 uint32_t upper;
bellard0ac4bd52004-01-04 15:44:17 +0000133 } l;
134#endif
135 uint64_t ll;
136} CPU_DoubleU;
137
bellard61382a52003-10-27 21:22:23 +0000138/* CPU memory access without any memory or io remapping */
139
bellard83d73962004-02-22 11:53:50 +0000140/*
141 * the generic syntax for the memory accesses is:
142 *
143 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
144 *
145 * store: st{type}{size}{endian}_{access_type}(ptr, val)
146 *
147 * type is:
148 * (empty): integer access
149 * f : float access
150 *
151 * sign is:
152 * (empty): for floats or 32 bit size
153 * u : unsigned
154 * s : signed
155 *
156 * size is:
157 * b: 8 bits
158 * w: 16 bits
159 * l: 32 bits
160 * q: 64 bits
161 *
162 * endian is:
163 * (empty): target cpu endianness or 8 bit access
164 * r : reversed target cpu endianness (not implemented yet)
165 * be : big endian (not implemented yet)
166 * le : little endian (not implemented yet)
167 *
168 * access_type is:
169 * raw : host memory access
170 * user : user mode access using soft MMU
171 * kernel : kernel mode access using soft MMU
172 */
bellardc27004e2005-01-03 23:35:10 +0000173static inline int ldub_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000174{
175 return *(uint8_t *)ptr;
176}
177
bellardc27004e2005-01-03 23:35:10 +0000178static inline int ldsb_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000179{
180 return *(int8_t *)ptr;
181}
182
bellardc27004e2005-01-03 23:35:10 +0000183static inline void stb_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000184{
185 *(uint8_t *)ptr = v;
186}
187
188/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
189 kernel handles unaligned load/stores may give better results, but
190 it is a system wide setting : bad */
bellard2df3b952005-11-19 17:47:39 +0000191#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
bellard5a9fdfe2003-06-15 20:02:25 +0000192
193/* conservative code for little endian unaligned accesses */
bellard2df3b952005-11-19 17:47:39 +0000194static inline int lduw_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000195{
196#ifdef __powerpc__
197 int val;
198 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
199 return val;
200#else
201 uint8_t *p = ptr;
202 return p[0] | (p[1] << 8);
203#endif
204}
205
bellard2df3b952005-11-19 17:47:39 +0000206static inline int ldsw_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000207{
208#ifdef __powerpc__
209 int val;
210 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
211 return (int16_t)val;
212#else
213 uint8_t *p = ptr;
214 return (int16_t)(p[0] | (p[1] << 8));
215#endif
216}
217
bellard2df3b952005-11-19 17:47:39 +0000218static inline int ldl_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000219{
220#ifdef __powerpc__
221 int val;
222 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
223 return val;
224#else
225 uint8_t *p = ptr;
226 return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
227#endif
228}
229
bellard2df3b952005-11-19 17:47:39 +0000230static inline uint64_t ldq_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000231{
232 uint8_t *p = ptr;
233 uint32_t v1, v2;
bellardf0aca822005-11-21 23:22:06 +0000234 v1 = ldl_le_p(p);
235 v2 = ldl_le_p(p + 4);
bellard5a9fdfe2003-06-15 20:02:25 +0000236 return v1 | ((uint64_t)v2 << 32);
237}
238
bellard2df3b952005-11-19 17:47:39 +0000239static inline void stw_le_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000240{
241#ifdef __powerpc__
242 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
243#else
244 uint8_t *p = ptr;
245 p[0] = v;
246 p[1] = v >> 8;
247#endif
248}
249
bellard2df3b952005-11-19 17:47:39 +0000250static inline void stl_le_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000251{
252#ifdef __powerpc__
253 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
254#else
255 uint8_t *p = ptr;
256 p[0] = v;
257 p[1] = v >> 8;
258 p[2] = v >> 16;
259 p[3] = v >> 24;
260#endif
261}
262
bellard2df3b952005-11-19 17:47:39 +0000263static inline void stq_le_p(void *ptr, uint64_t v)
bellard5a9fdfe2003-06-15 20:02:25 +0000264{
265 uint8_t *p = ptr;
bellardf0aca822005-11-21 23:22:06 +0000266 stl_le_p(p, (uint32_t)v);
267 stl_le_p(p + 4, v >> 32);
bellard5a9fdfe2003-06-15 20:02:25 +0000268}
269
270/* float access */
271
bellard2df3b952005-11-19 17:47:39 +0000272static inline float32 ldfl_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000273{
274 union {
bellard53cd6632005-03-13 18:50:23 +0000275 float32 f;
bellard5a9fdfe2003-06-15 20:02:25 +0000276 uint32_t i;
277 } u;
bellard2df3b952005-11-19 17:47:39 +0000278 u.i = ldl_le_p(ptr);
bellard5a9fdfe2003-06-15 20:02:25 +0000279 return u.f;
280}
281
bellard2df3b952005-11-19 17:47:39 +0000282static inline void stfl_le_p(void *ptr, float32 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000283{
284 union {
bellard53cd6632005-03-13 18:50:23 +0000285 float32 f;
bellard5a9fdfe2003-06-15 20:02:25 +0000286 uint32_t i;
287 } u;
288 u.f = v;
bellard2df3b952005-11-19 17:47:39 +0000289 stl_le_p(ptr, u.i);
bellard5a9fdfe2003-06-15 20:02:25 +0000290}
291
bellard2df3b952005-11-19 17:47:39 +0000292static inline float64 ldfq_le_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000293{
bellard0ac4bd52004-01-04 15:44:17 +0000294 CPU_DoubleU u;
bellard2df3b952005-11-19 17:47:39 +0000295 u.l.lower = ldl_le_p(ptr);
296 u.l.upper = ldl_le_p(ptr + 4);
bellard5a9fdfe2003-06-15 20:02:25 +0000297 return u.d;
298}
299
bellard2df3b952005-11-19 17:47:39 +0000300static inline void stfq_le_p(void *ptr, float64 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000301{
bellard0ac4bd52004-01-04 15:44:17 +0000302 CPU_DoubleU u;
bellard5a9fdfe2003-06-15 20:02:25 +0000303 u.d = v;
bellard2df3b952005-11-19 17:47:39 +0000304 stl_le_p(ptr, u.l.lower);
305 stl_le_p(ptr + 4, u.l.upper);
bellard5a9fdfe2003-06-15 20:02:25 +0000306}
307
bellard2df3b952005-11-19 17:47:39 +0000308#else
bellard93ac68b2003-09-30 20:57:29 +0000309
bellard2df3b952005-11-19 17:47:39 +0000310static inline int lduw_le_p(void *ptr)
311{
312 return *(uint16_t *)ptr;
313}
314
315static inline int ldsw_le_p(void *ptr)
316{
317 return *(int16_t *)ptr;
318}
319
320static inline int ldl_le_p(void *ptr)
321{
322 return *(uint32_t *)ptr;
323}
324
325static inline uint64_t ldq_le_p(void *ptr)
326{
327 return *(uint64_t *)ptr;
328}
329
330static inline void stw_le_p(void *ptr, int v)
331{
332 *(uint16_t *)ptr = v;
333}
334
335static inline void stl_le_p(void *ptr, int v)
336{
337 *(uint32_t *)ptr = v;
338}
339
340static inline void stq_le_p(void *ptr, uint64_t v)
341{
342 *(uint64_t *)ptr = v;
343}
344
345/* float access */
346
347static inline float32 ldfl_le_p(void *ptr)
348{
349 return *(float32 *)ptr;
350}
351
352static inline float64 ldfq_le_p(void *ptr)
353{
354 return *(float64 *)ptr;
355}
356
357static inline void stfl_le_p(void *ptr, float32 v)
358{
359 *(float32 *)ptr = v;
360}
361
362static inline void stfq_le_p(void *ptr, float64 v)
363{
364 *(float64 *)ptr = v;
365}
366#endif
367
368#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
369
370static inline int lduw_be_p(void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000371{
bellard83d73962004-02-22 11:53:50 +0000372#if defined(__i386__)
373 int val;
374 asm volatile ("movzwl %1, %0\n"
375 "xchgb %b0, %h0\n"
376 : "=q" (val)
377 : "m" (*(uint16_t *)ptr));
378 return val;
379#else
bellard93ac68b2003-09-30 20:57:29 +0000380 uint8_t *b = (uint8_t *) ptr;
bellard83d73962004-02-22 11:53:50 +0000381 return ((b[0] << 8) | b[1]);
382#endif
bellard93ac68b2003-09-30 20:57:29 +0000383}
384
bellard2df3b952005-11-19 17:47:39 +0000385static inline int ldsw_be_p(void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000386{
bellard83d73962004-02-22 11:53:50 +0000387#if defined(__i386__)
388 int val;
389 asm volatile ("movzwl %1, %0\n"
390 "xchgb %b0, %h0\n"
391 : "=q" (val)
392 : "m" (*(uint16_t *)ptr));
393 return (int16_t)val;
394#else
395 uint8_t *b = (uint8_t *) ptr;
396 return (int16_t)((b[0] << 8) | b[1]);
397#endif
bellard93ac68b2003-09-30 20:57:29 +0000398}
399
bellard2df3b952005-11-19 17:47:39 +0000400static inline int ldl_be_p(void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000401{
bellard4f2ac232004-04-26 19:44:02 +0000402#if defined(__i386__) || defined(__x86_64__)
bellard83d73962004-02-22 11:53:50 +0000403 int val;
404 asm volatile ("movl %1, %0\n"
405 "bswap %0\n"
406 : "=r" (val)
407 : "m" (*(uint32_t *)ptr));
408 return val;
409#else
bellard93ac68b2003-09-30 20:57:29 +0000410 uint8_t *b = (uint8_t *) ptr;
bellard83d73962004-02-22 11:53:50 +0000411 return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
412#endif
bellard93ac68b2003-09-30 20:57:29 +0000413}
414
bellard2df3b952005-11-19 17:47:39 +0000415static inline uint64_t ldq_be_p(void *ptr)
bellard93ac68b2003-09-30 20:57:29 +0000416{
417 uint32_t a,b;
bellard2df3b952005-11-19 17:47:39 +0000418 a = ldl_be_p(ptr);
419 b = ldl_be_p(ptr+4);
bellard93ac68b2003-09-30 20:57:29 +0000420 return (((uint64_t)a<<32)|b);
421}
422
bellard2df3b952005-11-19 17:47:39 +0000423static inline void stw_be_p(void *ptr, int v)
bellard93ac68b2003-09-30 20:57:29 +0000424{
bellard83d73962004-02-22 11:53:50 +0000425#if defined(__i386__)
426 asm volatile ("xchgb %b0, %h0\n"
427 "movw %w0, %1\n"
428 : "=q" (v)
429 : "m" (*(uint16_t *)ptr), "0" (v));
430#else
bellard93ac68b2003-09-30 20:57:29 +0000431 uint8_t *d = (uint8_t *) ptr;
432 d[0] = v >> 8;
433 d[1] = v;
bellard83d73962004-02-22 11:53:50 +0000434#endif
bellard93ac68b2003-09-30 20:57:29 +0000435}
436
bellard2df3b952005-11-19 17:47:39 +0000437static inline void stl_be_p(void *ptr, int v)
bellard93ac68b2003-09-30 20:57:29 +0000438{
bellard4f2ac232004-04-26 19:44:02 +0000439#if defined(__i386__) || defined(__x86_64__)
bellard83d73962004-02-22 11:53:50 +0000440 asm volatile ("bswap %0\n"
441 "movl %0, %1\n"
442 : "=r" (v)
443 : "m" (*(uint32_t *)ptr), "0" (v));
444#else
bellard93ac68b2003-09-30 20:57:29 +0000445 uint8_t *d = (uint8_t *) ptr;
446 d[0] = v >> 24;
447 d[1] = v >> 16;
448 d[2] = v >> 8;
449 d[3] = v;
bellard83d73962004-02-22 11:53:50 +0000450#endif
bellard93ac68b2003-09-30 20:57:29 +0000451}
452
bellard2df3b952005-11-19 17:47:39 +0000453static inline void stq_be_p(void *ptr, uint64_t v)
bellard93ac68b2003-09-30 20:57:29 +0000454{
bellard2df3b952005-11-19 17:47:39 +0000455 stl_be_p(ptr, v >> 32);
456 stl_be_p(ptr + 4, v);
bellard0ac4bd52004-01-04 15:44:17 +0000457}
458
459/* float access */
460
bellard2df3b952005-11-19 17:47:39 +0000461static inline float32 ldfl_be_p(void *ptr)
bellard0ac4bd52004-01-04 15:44:17 +0000462{
463 union {
bellard53cd6632005-03-13 18:50:23 +0000464 float32 f;
bellard0ac4bd52004-01-04 15:44:17 +0000465 uint32_t i;
466 } u;
bellard2df3b952005-11-19 17:47:39 +0000467 u.i = ldl_be_p(ptr);
bellard0ac4bd52004-01-04 15:44:17 +0000468 return u.f;
469}
470
bellard2df3b952005-11-19 17:47:39 +0000471static inline void stfl_be_p(void *ptr, float32 v)
bellard0ac4bd52004-01-04 15:44:17 +0000472{
473 union {
bellard53cd6632005-03-13 18:50:23 +0000474 float32 f;
bellard0ac4bd52004-01-04 15:44:17 +0000475 uint32_t i;
476 } u;
477 u.f = v;
bellard2df3b952005-11-19 17:47:39 +0000478 stl_be_p(ptr, u.i);
bellard0ac4bd52004-01-04 15:44:17 +0000479}
480
bellard2df3b952005-11-19 17:47:39 +0000481static inline float64 ldfq_be_p(void *ptr)
bellard0ac4bd52004-01-04 15:44:17 +0000482{
483 CPU_DoubleU u;
bellard2df3b952005-11-19 17:47:39 +0000484 u.l.upper = ldl_be_p(ptr);
485 u.l.lower = ldl_be_p(ptr + 4);
bellard0ac4bd52004-01-04 15:44:17 +0000486 return u.d;
487}
488
bellard2df3b952005-11-19 17:47:39 +0000489static inline void stfq_be_p(void *ptr, float64 v)
bellard0ac4bd52004-01-04 15:44:17 +0000490{
491 CPU_DoubleU u;
492 u.d = v;
bellard2df3b952005-11-19 17:47:39 +0000493 stl_be_p(ptr, u.l.upper);
494 stl_be_p(ptr + 4, u.l.lower);
bellard93ac68b2003-09-30 20:57:29 +0000495}
496
bellard5a9fdfe2003-06-15 20:02:25 +0000497#else
498
bellard2df3b952005-11-19 17:47:39 +0000499static inline int lduw_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000500{
501 return *(uint16_t *)ptr;
502}
503
bellard2df3b952005-11-19 17:47:39 +0000504static inline int ldsw_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000505{
506 return *(int16_t *)ptr;
507}
508
bellard2df3b952005-11-19 17:47:39 +0000509static inline int ldl_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000510{
511 return *(uint32_t *)ptr;
512}
513
bellard2df3b952005-11-19 17:47:39 +0000514static inline uint64_t ldq_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000515{
516 return *(uint64_t *)ptr;
517}
518
bellard2df3b952005-11-19 17:47:39 +0000519static inline void stw_be_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000520{
521 *(uint16_t *)ptr = v;
522}
523
bellard2df3b952005-11-19 17:47:39 +0000524static inline void stl_be_p(void *ptr, int v)
bellard5a9fdfe2003-06-15 20:02:25 +0000525{
526 *(uint32_t *)ptr = v;
527}
528
bellard2df3b952005-11-19 17:47:39 +0000529static inline void stq_be_p(void *ptr, uint64_t v)
bellard5a9fdfe2003-06-15 20:02:25 +0000530{
531 *(uint64_t *)ptr = v;
532}
533
534/* float access */
535
bellard2df3b952005-11-19 17:47:39 +0000536static inline float32 ldfl_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000537{
bellard53cd6632005-03-13 18:50:23 +0000538 return *(float32 *)ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000539}
540
bellard2df3b952005-11-19 17:47:39 +0000541static inline float64 ldfq_be_p(void *ptr)
bellard5a9fdfe2003-06-15 20:02:25 +0000542{
bellard53cd6632005-03-13 18:50:23 +0000543 return *(float64 *)ptr;
bellard5a9fdfe2003-06-15 20:02:25 +0000544}
545
bellard2df3b952005-11-19 17:47:39 +0000546static inline void stfl_be_p(void *ptr, float32 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000547{
bellard53cd6632005-03-13 18:50:23 +0000548 *(float32 *)ptr = v;
bellard5a9fdfe2003-06-15 20:02:25 +0000549}
550
bellard2df3b952005-11-19 17:47:39 +0000551static inline void stfq_be_p(void *ptr, float64 v)
bellard5a9fdfe2003-06-15 20:02:25 +0000552{
bellard53cd6632005-03-13 18:50:23 +0000553 *(float64 *)ptr = v;
bellard5a9fdfe2003-06-15 20:02:25 +0000554}
bellard2df3b952005-11-19 17:47:39 +0000555
556#endif
557
558/* target CPU memory access functions */
559#if defined(TARGET_WORDS_BIGENDIAN)
560#define lduw_p(p) lduw_be_p(p)
561#define ldsw_p(p) ldsw_be_p(p)
562#define ldl_p(p) ldl_be_p(p)
563#define ldq_p(p) ldq_be_p(p)
564#define ldfl_p(p) ldfl_be_p(p)
565#define ldfq_p(p) ldfq_be_p(p)
566#define stw_p(p, v) stw_be_p(p, v)
567#define stl_p(p, v) stl_be_p(p, v)
568#define stq_p(p, v) stq_be_p(p, v)
569#define stfl_p(p, v) stfl_be_p(p, v)
570#define stfq_p(p, v) stfq_be_p(p, v)
571#else
572#define lduw_p(p) lduw_le_p(p)
573#define ldsw_p(p) ldsw_le_p(p)
574#define ldl_p(p) ldl_le_p(p)
575#define ldq_p(p) ldq_le_p(p)
576#define ldfl_p(p) ldfl_le_p(p)
577#define ldfq_p(p) ldfq_le_p(p)
578#define stw_p(p, v) stw_le_p(p, v)
579#define stl_p(p, v) stl_le_p(p, v)
580#define stq_p(p, v) stq_le_p(p, v)
581#define stfl_p(p, v) stfl_le_p(p, v)
582#define stfq_p(p, v) stfq_le_p(p, v)
bellard5a9fdfe2003-06-15 20:02:25 +0000583#endif
584
bellard61382a52003-10-27 21:22:23 +0000585/* MMU memory access macros */
586
pbrook53a59602006-03-25 19:31:22 +0000587#if defined(CONFIG_USER_ONLY)
588/* On some host systems the guest address space is reserved on the host.
589 * This allows the guest address space to be offset to a convenient location.
590 */
591//#define GUEST_BASE 0x20000000
592#define GUEST_BASE 0
593
594/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
595#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
596#define h2g(x) ((target_ulong)(x - GUEST_BASE))
597
598#define saddr(x) g2h(x)
599#define laddr(x) g2h(x)
600
601#else /* !CONFIG_USER_ONLY */
bellardc27004e2005-01-03 23:35:10 +0000602/* NOTE: we use double casts if pointers and target_ulong have
603 different sizes */
pbrook53a59602006-03-25 19:31:22 +0000604#define saddr(x) (uint8_t *)(long)(x)
605#define laddr(x) (uint8_t *)(long)(x)
606#endif
607
608#define ldub_raw(p) ldub_p(laddr((p)))
609#define ldsb_raw(p) ldsb_p(laddr((p)))
610#define lduw_raw(p) lduw_p(laddr((p)))
611#define ldsw_raw(p) ldsw_p(laddr((p)))
612#define ldl_raw(p) ldl_p(laddr((p)))
613#define ldq_raw(p) ldq_p(laddr((p)))
614#define ldfl_raw(p) ldfl_p(laddr((p)))
615#define ldfq_raw(p) ldfq_p(laddr((p)))
616#define stb_raw(p, v) stb_p(saddr((p)), v)
617#define stw_raw(p, v) stw_p(saddr((p)), v)
618#define stl_raw(p, v) stl_p(saddr((p)), v)
619#define stq_raw(p, v) stq_p(saddr((p)), v)
620#define stfl_raw(p, v) stfl_p(saddr((p)), v)
621#define stfq_raw(p, v) stfq_p(saddr((p)), v)
bellardc27004e2005-01-03 23:35:10 +0000622
623
bellard61382a52003-10-27 21:22:23 +0000624#if defined(CONFIG_USER_ONLY)
625
626/* if user mode, no other memory access functions */
627#define ldub(p) ldub_raw(p)
628#define ldsb(p) ldsb_raw(p)
629#define lduw(p) lduw_raw(p)
630#define ldsw(p) ldsw_raw(p)
631#define ldl(p) ldl_raw(p)
632#define ldq(p) ldq_raw(p)
633#define ldfl(p) ldfl_raw(p)
634#define ldfq(p) ldfq_raw(p)
635#define stb(p, v) stb_raw(p, v)
636#define stw(p, v) stw_raw(p, v)
637#define stl(p, v) stl_raw(p, v)
638#define stq(p, v) stq_raw(p, v)
639#define stfl(p, v) stfl_raw(p, v)
640#define stfq(p, v) stfq_raw(p, v)
641
642#define ldub_code(p) ldub_raw(p)
643#define ldsb_code(p) ldsb_raw(p)
644#define lduw_code(p) lduw_raw(p)
645#define ldsw_code(p) ldsw_raw(p)
646#define ldl_code(p) ldl_raw(p)
647
648#define ldub_kernel(p) ldub_raw(p)
649#define ldsb_kernel(p) ldsb_raw(p)
650#define lduw_kernel(p) lduw_raw(p)
651#define ldsw_kernel(p) ldsw_raw(p)
652#define ldl_kernel(p) ldl_raw(p)
bellard0ac4bd52004-01-04 15:44:17 +0000653#define ldfl_kernel(p) ldfl_raw(p)
654#define ldfq_kernel(p) ldfq_raw(p)
bellard61382a52003-10-27 21:22:23 +0000655#define stb_kernel(p, v) stb_raw(p, v)
656#define stw_kernel(p, v) stw_raw(p, v)
657#define stl_kernel(p, v) stl_raw(p, v)
658#define stq_kernel(p, v) stq_raw(p, v)
bellard0ac4bd52004-01-04 15:44:17 +0000659#define stfl_kernel(p, v) stfl_raw(p, v)
660#define stfq_kernel(p, vt) stfq_raw(p, v)
bellard61382a52003-10-27 21:22:23 +0000661
662#endif /* defined(CONFIG_USER_ONLY) */
663
bellard5a9fdfe2003-06-15 20:02:25 +0000664/* page related stuff */
665
666#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
667#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
668#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
669
pbrook53a59602006-03-25 19:31:22 +0000670/* ??? These should be the larger of unsigned long and target_ulong. */
bellard83fb7ad2004-07-05 21:25:26 +0000671extern unsigned long qemu_real_host_page_size;
672extern unsigned long qemu_host_page_bits;
673extern unsigned long qemu_host_page_size;
674extern unsigned long qemu_host_page_mask;
bellard5a9fdfe2003-06-15 20:02:25 +0000675
bellard83fb7ad2004-07-05 21:25:26 +0000676#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
bellard5a9fdfe2003-06-15 20:02:25 +0000677
678/* same as PROT_xxx */
679#define PAGE_READ 0x0001
680#define PAGE_WRITE 0x0002
681#define PAGE_EXEC 0x0004
682#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
683#define PAGE_VALID 0x0008
684/* original state of the write flag (used when tracking self-modifying
685 code */
686#define PAGE_WRITE_ORG 0x0010
687
688void page_dump(FILE *f);
pbrook53a59602006-03-25 19:31:22 +0000689int page_get_flags(target_ulong address);
690void page_set_flags(target_ulong start, target_ulong end, int flags);
691void page_unprotect_range(target_ulong data, target_ulong data_size);
bellard5a9fdfe2003-06-15 20:02:25 +0000692
693#define SINGLE_CPU_DEFINES
694#ifdef SINGLE_CPU_DEFINES
695
696#if defined(TARGET_I386)
697
698#define CPUState CPUX86State
699#define cpu_init cpu_x86_init
700#define cpu_exec cpu_x86_exec
701#define cpu_gen_code cpu_x86_gen_code
bellard5a9fdfe2003-06-15 20:02:25 +0000702#define cpu_signal_handler cpu_x86_signal_handler
703
704#elif defined(TARGET_ARM)
705
706#define CPUState CPUARMState
707#define cpu_init cpu_arm_init
708#define cpu_exec cpu_arm_exec
709#define cpu_gen_code cpu_arm_gen_code
bellard5a9fdfe2003-06-15 20:02:25 +0000710#define cpu_signal_handler cpu_arm_signal_handler
711
bellard93ac68b2003-09-30 20:57:29 +0000712#elif defined(TARGET_SPARC)
713
714#define CPUState CPUSPARCState
715#define cpu_init cpu_sparc_init
716#define cpu_exec cpu_sparc_exec
717#define cpu_gen_code cpu_sparc_gen_code
bellard93ac68b2003-09-30 20:57:29 +0000718#define cpu_signal_handler cpu_sparc_signal_handler
719
bellard67867302003-11-23 17:05:30 +0000720#elif defined(TARGET_PPC)
721
722#define CPUState CPUPPCState
723#define cpu_init cpu_ppc_init
724#define cpu_exec cpu_ppc_exec
725#define cpu_gen_code cpu_ppc_gen_code
bellard67867302003-11-23 17:05:30 +0000726#define cpu_signal_handler cpu_ppc_signal_handler
727
pbrooke6e59062006-10-22 00:18:54 +0000728#elif defined(TARGET_M68K)
729#define CPUState CPUM68KState
730#define cpu_init cpu_m68k_init
731#define cpu_exec cpu_m68k_exec
732#define cpu_gen_code cpu_m68k_gen_code
733#define cpu_signal_handler cpu_m68k_signal_handler
734
bellard6af0bf92005-07-02 14:58:51 +0000735#elif defined(TARGET_MIPS)
736#define CPUState CPUMIPSState
737#define cpu_init cpu_mips_init
738#define cpu_exec cpu_mips_exec
739#define cpu_gen_code cpu_mips_gen_code
740#define cpu_signal_handler cpu_mips_signal_handler
741
bellardfdf9b3e2006-04-27 21:07:38 +0000742#elif defined(TARGET_SH4)
743#define CPUState CPUSH4State
744#define cpu_init cpu_sh4_init
745#define cpu_exec cpu_sh4_exec
746#define cpu_gen_code cpu_sh4_gen_code
747#define cpu_signal_handler cpu_sh4_signal_handler
748
bellard5a9fdfe2003-06-15 20:02:25 +0000749#else
750
751#error unsupported target CPU
752
753#endif
754
bellard972ddf72003-06-21 13:08:39 +0000755#endif /* SINGLE_CPU_DEFINES */
756
thsc5be9f02007-02-28 20:20:53 +0000757CPUState *cpu_copy(CPUState *env);
758
bellard7fe48482004-10-09 18:08:01 +0000759void cpu_dump_state(CPUState *env, FILE *f,
760 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
761 int flags);
j_mayer76a66252007-03-07 08:32:30 +0000762void cpu_dump_statistics (CPUState *env, FILE *f,
763 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
764 int flags);
bellard7fe48482004-10-09 18:08:01 +0000765
bellard972ddf72003-06-21 13:08:39 +0000766void cpu_abort(CPUState *env, const char *fmt, ...);
bellardf0aca822005-11-21 23:22:06 +0000767extern CPUState *first_cpu;
bellarde2f22892003-06-25 16:09:48 +0000768extern CPUState *cpu_single_env;
bellard9acbed02004-02-16 21:57:02 +0000769extern int code_copy_enabled;
bellard5a9fdfe2003-06-15 20:02:25 +0000770
bellard9acbed02004-02-16 21:57:02 +0000771#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
772#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
773#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
bellardef792f92004-05-17 20:19:32 +0000774#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
bellard98699962005-11-26 10:29:22 +0000775#define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */
bellardba3c64f2005-12-05 20:31:52 +0000776#define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */
bellard3b21e032006-09-24 18:41:56 +0000777#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */
pbrook6658ffb2007-03-16 23:58:11 +0000778#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */
bellard98699962005-11-26 10:29:22 +0000779
bellard46907642003-07-07 12:17:46 +0000780void cpu_interrupt(CPUState *s, int mask);
bellardb54ad042004-05-20 13:42:52 +0000781void cpu_reset_interrupt(CPUState *env, int mask);
bellard68a79312003-06-30 13:12:32 +0000782
pbrook6658ffb2007-03-16 23:58:11 +0000783int cpu_watchpoint_insert(CPUState *env, target_ulong addr);
784int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
bellard2e126692004-04-25 21:28:44 +0000785int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
786int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
bellardc33a3462003-07-29 20:50:33 +0000787void cpu_single_step(CPUState *env, int enabled);
bellardd95dc322004-06-20 12:35:26 +0000788void cpu_reset(CPUState *s);
bellard4c3a88a2003-07-26 12:06:08 +0000789
bellard13eb76e2004-01-24 15:23:36 +0000790/* Return the physical page corresponding to a virtual one. Use it
791 only for debugging because no protection checks are done. Return -1
792 if no page found. */
793target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
794
bellard9fddaa02004-05-21 12:59:32 +0000795#define CPU_LOG_TB_OUT_ASM (1 << 0)
796#define CPU_LOG_TB_IN_ASM (1 << 1)
bellardf193c792004-03-21 17:06:25 +0000797#define CPU_LOG_TB_OP (1 << 2)
798#define CPU_LOG_TB_OP_OPT (1 << 3)
799#define CPU_LOG_INT (1 << 4)
800#define CPU_LOG_EXEC (1 << 5)
801#define CPU_LOG_PCALL (1 << 6)
bellardfd872592004-05-12 19:11:15 +0000802#define CPU_LOG_IOPORT (1 << 7)
bellard9fddaa02004-05-21 12:59:32 +0000803#define CPU_LOG_TB_CPU (1 << 8)
bellardf193c792004-03-21 17:06:25 +0000804
805/* define log items */
806typedef struct CPULogItem {
807 int mask;
808 const char *name;
809 const char *help;
810} CPULogItem;
811
812extern CPULogItem cpu_log_items[];
813
bellard34865132003-10-05 14:28:56 +0000814void cpu_set_log(int log_flags);
815void cpu_set_log_filename(const char *filename);
bellardf193c792004-03-21 17:06:25 +0000816int cpu_str_to_log_mask(const char *str);
bellard34865132003-10-05 14:28:56 +0000817
bellard09683d32004-01-04 23:49:41 +0000818/* IO ports API */
819
820/* NOTE: as these functions may be even used when there is an isa
821 brige on non x86 targets, we always defined them */
822#ifndef NO_CPU_IO_DEFS
823void cpu_outb(CPUState *env, int addr, int val);
824void cpu_outw(CPUState *env, int addr, int val);
825void cpu_outl(CPUState *env, int addr, int val);
826int cpu_inb(CPUState *env, int addr);
827int cpu_inw(CPUState *env, int addr);
828int cpu_inl(CPUState *env, int addr);
829#endif
830
bellard33417e72003-08-10 21:47:01 +0000831/* memory API */
832
bellardedf75d52004-01-04 17:43:30 +0000833extern int phys_ram_size;
834extern int phys_ram_fd;
835extern uint8_t *phys_ram_base;
bellard1ccde1c2004-02-06 19:46:14 +0000836extern uint8_t *phys_ram_dirty;
bellardedf75d52004-01-04 17:43:30 +0000837
838/* physical memory access */
bellardedf75d52004-01-04 17:43:30 +0000839#define TLB_INVALID_MASK (1 << 3)
840#define IO_MEM_SHIFT 4
bellard98699962005-11-26 10:29:22 +0000841#define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
bellardedf75d52004-01-04 17:43:30 +0000842
843#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
844#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
845#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
bellard1ccde1c2004-02-06 19:46:14 +0000846#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
bellard2a4188a2006-06-25 21:54:59 +0000847/* acts like a ROM when read and like a device when written. As an
848 exception, the write memory callback gets the ram offset instead of
849 the physical address */
850#define IO_MEM_ROMD (1)
bellardedf75d52004-01-04 17:43:30 +0000851
bellard77279942004-06-03 14:08:36 +0000852typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
853typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
bellard33417e72003-08-10 21:47:01 +0000854
bellard2e126692004-04-25 21:28:44 +0000855void cpu_register_physical_memory(target_phys_addr_t start_addr,
856 unsigned long size,
857 unsigned long phys_offset);
bellard3b21e032006-09-24 18:41:56 +0000858uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
bellarde9a1ab12007-02-08 23:08:38 +0000859ram_addr_t qemu_ram_alloc(unsigned int size);
860void qemu_ram_free(ram_addr_t addr);
bellard33417e72003-08-10 21:47:01 +0000861int cpu_register_io_memory(int io_index,
862 CPUReadMemoryFunc **mem_read,
bellard77279942004-06-03 14:08:36 +0000863 CPUWriteMemoryFunc **mem_write,
864 void *opaque);
bellard8926b512004-10-10 15:14:20 +0000865CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
866CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
bellard33417e72003-08-10 21:47:01 +0000867
bellard2e126692004-04-25 21:28:44 +0000868void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
bellard13eb76e2004-01-24 15:23:36 +0000869 int len, int is_write);
bellard2e126692004-04-25 21:28:44 +0000870static inline void cpu_physical_memory_read(target_phys_addr_t addr,
871 uint8_t *buf, int len)
bellard8b1f24b2004-02-25 23:24:38 +0000872{
873 cpu_physical_memory_rw(addr, buf, len, 0);
874}
bellard2e126692004-04-25 21:28:44 +0000875static inline void cpu_physical_memory_write(target_phys_addr_t addr,
876 const uint8_t *buf, int len)
bellard8b1f24b2004-02-25 23:24:38 +0000877{
878 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
879}
bellardaab33092005-10-30 20:48:42 +0000880uint32_t ldub_phys(target_phys_addr_t addr);
881uint32_t lduw_phys(target_phys_addr_t addr);
bellard8df1cd02005-01-28 22:37:22 +0000882uint32_t ldl_phys(target_phys_addr_t addr);
bellardaab33092005-10-30 20:48:42 +0000883uint64_t ldq_phys(target_phys_addr_t addr);
bellard8df1cd02005-01-28 22:37:22 +0000884void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
bellardaab33092005-10-30 20:48:42 +0000885void stb_phys(target_phys_addr_t addr, uint32_t val);
886void stw_phys(target_phys_addr_t addr, uint32_t val);
bellard8df1cd02005-01-28 22:37:22 +0000887void stl_phys(target_phys_addr_t addr, uint32_t val);
bellardaab33092005-10-30 20:48:42 +0000888void stq_phys(target_phys_addr_t addr, uint64_t val);
bellard8b1f24b2004-02-25 23:24:38 +0000889
bellardd0ecd2a2006-04-23 17:14:48 +0000890void cpu_physical_memory_write_rom(target_phys_addr_t addr,
891 const uint8_t *buf, int len);
bellard8b1f24b2004-02-25 23:24:38 +0000892int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
893 uint8_t *buf, int len, int is_write);
bellard13eb76e2004-01-24 15:23:36 +0000894
bellard04c504c2005-08-21 09:24:50 +0000895#define VGA_DIRTY_FLAG 0x01
896#define CODE_DIRTY_FLAG 0x02
bellard0a962c02005-02-10 22:00:27 +0000897
bellard1ccde1c2004-02-06 19:46:14 +0000898/* read dirty bit (return 0 or 1) */
bellard04c504c2005-08-21 09:24:50 +0000899static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
bellard1ccde1c2004-02-06 19:46:14 +0000900{
bellard0a962c02005-02-10 22:00:27 +0000901 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
902}
903
bellard04c504c2005-08-21 09:24:50 +0000904static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
bellard0a962c02005-02-10 22:00:27 +0000905 int dirty_flags)
906{
907 return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
bellard1ccde1c2004-02-06 19:46:14 +0000908}
909
bellard04c504c2005-08-21 09:24:50 +0000910static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
bellard1ccde1c2004-02-06 19:46:14 +0000911{
bellard0a962c02005-02-10 22:00:27 +0000912 phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
bellard1ccde1c2004-02-06 19:46:14 +0000913}
914
bellard04c504c2005-08-21 09:24:50 +0000915void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard0a962c02005-02-10 22:00:27 +0000916 int dirty_flags);
bellard04c504c2005-08-21 09:24:50 +0000917void cpu_tlb_update_dirty(CPUState *env);
bellard1ccde1c2004-02-06 19:46:14 +0000918
bellarde3db7222005-01-26 22:00:47 +0000919void dump_exec_info(FILE *f,
920 int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
921
bellardeffedbc2006-07-13 23:00:40 +0000922/*******************************************/
923/* host CPU ticks (if available) */
924
925#if defined(__powerpc__)
926
927static inline uint32_t get_tbl(void)
928{
929 uint32_t tbl;
930 asm volatile("mftb %0" : "=r" (tbl));
931 return tbl;
932}
933
934static inline uint32_t get_tbu(void)
935{
936 uint32_t tbl;
937 asm volatile("mftbu %0" : "=r" (tbl));
938 return tbl;
939}
940
941static inline int64_t cpu_get_real_ticks(void)
942{
943 uint32_t l, h, h1;
944 /* NOTE: we test if wrapping has occurred */
945 do {
946 h = get_tbu();
947 l = get_tbl();
948 h1 = get_tbu();
949 } while (h != h1);
950 return ((int64_t)h << 32) | l;
951}
952
953#elif defined(__i386__)
954
955static inline int64_t cpu_get_real_ticks(void)
bellard5f1ce942006-02-08 22:40:15 +0000956{
957 int64_t val;
958 asm volatile ("rdtsc" : "=A" (val));
959 return val;
960}
961
bellardeffedbc2006-07-13 23:00:40 +0000962#elif defined(__x86_64__)
963
964static inline int64_t cpu_get_real_ticks(void)
965{
966 uint32_t low,high;
967 int64_t val;
968 asm volatile("rdtsc" : "=a" (low), "=d" (high));
969 val = high;
970 val <<= 32;
971 val |= low;
972 return val;
973}
974
975#elif defined(__ia64)
976
977static inline int64_t cpu_get_real_ticks(void)
978{
979 int64_t val;
980 asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
981 return val;
982}
983
984#elif defined(__s390__)
985
986static inline int64_t cpu_get_real_ticks(void)
987{
988 int64_t val;
989 asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
990 return val;
991}
992
bellard74ccb342006-07-18 21:23:34 +0000993#elif defined(__sparc_v9__)
bellardeffedbc2006-07-13 23:00:40 +0000994
995static inline int64_t cpu_get_real_ticks (void)
996{
997#if defined(_LP64)
998 uint64_t rval;
999 asm volatile("rd %%tick,%0" : "=r"(rval));
1000 return rval;
1001#else
1002 union {
1003 uint64_t i64;
1004 struct {
1005 uint32_t high;
1006 uint32_t low;
1007 } i32;
1008 } rval;
1009 asm volatile("rd %%tick,%1; srlx %1,32,%0"
1010 : "=r"(rval.i32.high), "=r"(rval.i32.low));
1011 return rval.i64;
1012#endif
1013}
pbrook46152182006-07-30 19:16:29 +00001014#else
1015/* The host CPU doesn't have an easily accessible cycle counter.
1016 Just return a monotonically increasing vlue. This will be totally wrong,
1017 but hopefully better than nothing. */
1018static inline int64_t cpu_get_real_ticks (void)
1019{
1020 static int64_t ticks = 0;
1021 return ticks++;
1022}
bellardeffedbc2006-07-13 23:00:40 +00001023#endif
1024
1025/* profiling */
1026#ifdef CONFIG_PROFILER
1027static inline int64_t profile_getclock(void)
1028{
1029 return cpu_get_real_ticks();
1030}
1031
bellard5f1ce942006-02-08 22:40:15 +00001032extern int64_t kqemu_time, kqemu_time_start;
1033extern int64_t qemu_time, qemu_time_start;
1034extern int64_t tlb_flush_time;
1035extern int64_t kqemu_exec_count;
1036extern int64_t dev_time;
1037extern int64_t kqemu_ret_int_count;
1038extern int64_t kqemu_ret_excp_count;
1039extern int64_t kqemu_ret_intr_count;
1040
1041#endif
1042
bellard5a9fdfe2003-06-15 20:02:25 +00001043#endif /* CPU_ALL_H */