bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * defines common to all virtual CPUs |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #ifndef CPU_ALL_H |
| 21 | #define CPU_ALL_H |
| 22 | |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 23 | #if defined(__arm__) || defined(__sparc__) |
| 24 | #define WORDS_ALIGNED |
| 25 | #endif |
| 26 | |
| 27 | /* some important defines: |
| 28 | * |
| 29 | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned |
| 30 | * memory accesses. |
| 31 | * |
| 32 | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and |
| 33 | * otherwise little endian. |
| 34 | * |
| 35 | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) |
| 36 | * |
| 37 | * TARGET_WORDS_BIGENDIAN : same for target cpu |
| 38 | */ |
| 39 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 40 | #include "bswap.h" |
| 41 | |
| 42 | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) |
| 43 | #define BSWAP_NEEDED |
| 44 | #endif |
| 45 | |
| 46 | #ifdef BSWAP_NEEDED |
| 47 | |
| 48 | static inline uint16_t tswap16(uint16_t s) |
| 49 | { |
| 50 | return bswap16(s); |
| 51 | } |
| 52 | |
| 53 | static inline uint32_t tswap32(uint32_t s) |
| 54 | { |
| 55 | return bswap32(s); |
| 56 | } |
| 57 | |
| 58 | static inline uint64_t tswap64(uint64_t s) |
| 59 | { |
| 60 | return bswap64(s); |
| 61 | } |
| 62 | |
| 63 | static inline void tswap16s(uint16_t *s) |
| 64 | { |
| 65 | *s = bswap16(*s); |
| 66 | } |
| 67 | |
| 68 | static inline void tswap32s(uint32_t *s) |
| 69 | { |
| 70 | *s = bswap32(*s); |
| 71 | } |
| 72 | |
| 73 | static inline void tswap64s(uint64_t *s) |
| 74 | { |
| 75 | *s = bswap64(*s); |
| 76 | } |
| 77 | |
| 78 | #else |
| 79 | |
| 80 | static inline uint16_t tswap16(uint16_t s) |
| 81 | { |
| 82 | return s; |
| 83 | } |
| 84 | |
| 85 | static inline uint32_t tswap32(uint32_t s) |
| 86 | { |
| 87 | return s; |
| 88 | } |
| 89 | |
| 90 | static inline uint64_t tswap64(uint64_t s) |
| 91 | { |
| 92 | return s; |
| 93 | } |
| 94 | |
| 95 | static inline void tswap16s(uint16_t *s) |
| 96 | { |
| 97 | } |
| 98 | |
| 99 | static inline void tswap32s(uint32_t *s) |
| 100 | { |
| 101 | } |
| 102 | |
| 103 | static inline void tswap64s(uint64_t *s) |
| 104 | { |
| 105 | } |
| 106 | |
| 107 | #endif |
| 108 | |
| 109 | #if TARGET_LONG_SIZE == 4 |
| 110 | #define tswapl(s) tswap32(s) |
| 111 | #define tswapls(s) tswap32s((uint32_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 112 | #define bswaptls(s) bswap32s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 113 | #else |
| 114 | #define tswapl(s) tswap64(s) |
| 115 | #define tswapls(s) tswap64s((uint64_t *)(s)) |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 116 | #define bswaptls(s) bswap64s(s) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 117 | #endif |
| 118 | |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 119 | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big |
| 120 | endian ! */ |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 121 | typedef union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 122 | float64 d; |
bellard | 9d60cac | 2005-04-07 19:55:52 +0000 | [diff] [blame] | 123 | #if defined(WORDS_BIGENDIAN) \ |
| 124 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 125 | struct { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 126 | uint32_t upper; |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 127 | uint32_t lower; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 128 | } l; |
| 129 | #else |
| 130 | struct { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 131 | uint32_t lower; |
bellard | 832ed0f | 2005-02-07 12:35:16 +0000 | [diff] [blame] | 132 | uint32_t upper; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 133 | } l; |
| 134 | #endif |
| 135 | uint64_t ll; |
| 136 | } CPU_DoubleU; |
| 137 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 138 | /* CPU memory access without any memory or io remapping */ |
| 139 | |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 140 | /* |
| 141 | * the generic syntax for the memory accesses is: |
| 142 | * |
| 143 | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) |
| 144 | * |
| 145 | * store: st{type}{size}{endian}_{access_type}(ptr, val) |
| 146 | * |
| 147 | * type is: |
| 148 | * (empty): integer access |
| 149 | * f : float access |
| 150 | * |
| 151 | * sign is: |
| 152 | * (empty): for floats or 32 bit size |
| 153 | * u : unsigned |
| 154 | * s : signed |
| 155 | * |
| 156 | * size is: |
| 157 | * b: 8 bits |
| 158 | * w: 16 bits |
| 159 | * l: 32 bits |
| 160 | * q: 64 bits |
| 161 | * |
| 162 | * endian is: |
| 163 | * (empty): target cpu endianness or 8 bit access |
| 164 | * r : reversed target cpu endianness (not implemented yet) |
| 165 | * be : big endian (not implemented yet) |
| 166 | * le : little endian (not implemented yet) |
| 167 | * |
| 168 | * access_type is: |
| 169 | * raw : host memory access |
| 170 | * user : user mode access using soft MMU |
| 171 | * kernel : kernel mode access using soft MMU |
| 172 | */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 173 | static inline int ldub_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 174 | { |
| 175 | return *(uint8_t *)ptr; |
| 176 | } |
| 177 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 178 | static inline int ldsb_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 179 | { |
| 180 | return *(int8_t *)ptr; |
| 181 | } |
| 182 | |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 183 | static inline void stb_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 184 | { |
| 185 | *(uint8_t *)ptr = v; |
| 186 | } |
| 187 | |
| 188 | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the |
| 189 | kernel handles unaligned load/stores may give better results, but |
| 190 | it is a system wide setting : bad */ |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 191 | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 192 | |
| 193 | /* conservative code for little endian unaligned accesses */ |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 194 | static inline int lduw_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 195 | { |
| 196 | #ifdef __powerpc__ |
| 197 | int val; |
| 198 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 199 | return val; |
| 200 | #else |
| 201 | uint8_t *p = ptr; |
| 202 | return p[0] | (p[1] << 8); |
| 203 | #endif |
| 204 | } |
| 205 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 206 | static inline int ldsw_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 207 | { |
| 208 | #ifdef __powerpc__ |
| 209 | int val; |
| 210 | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 211 | return (int16_t)val; |
| 212 | #else |
| 213 | uint8_t *p = ptr; |
| 214 | return (int16_t)(p[0] | (p[1] << 8)); |
| 215 | #endif |
| 216 | } |
| 217 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 218 | static inline int ldl_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 219 | { |
| 220 | #ifdef __powerpc__ |
| 221 | int val; |
| 222 | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
| 223 | return val; |
| 224 | #else |
| 225 | uint8_t *p = ptr; |
| 226 | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
| 227 | #endif |
| 228 | } |
| 229 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 230 | static inline uint64_t ldq_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 231 | { |
| 232 | uint8_t *p = ptr; |
| 233 | uint32_t v1, v2; |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 234 | v1 = ldl_le_p(p); |
| 235 | v2 = ldl_le_p(p + 4); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 236 | return v1 | ((uint64_t)v2 << 32); |
| 237 | } |
| 238 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 239 | static inline void stw_le_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 240 | { |
| 241 | #ifdef __powerpc__ |
| 242 | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
| 243 | #else |
| 244 | uint8_t *p = ptr; |
| 245 | p[0] = v; |
| 246 | p[1] = v >> 8; |
| 247 | #endif |
| 248 | } |
| 249 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 250 | static inline void stl_le_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 251 | { |
| 252 | #ifdef __powerpc__ |
| 253 | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
| 254 | #else |
| 255 | uint8_t *p = ptr; |
| 256 | p[0] = v; |
| 257 | p[1] = v >> 8; |
| 258 | p[2] = v >> 16; |
| 259 | p[3] = v >> 24; |
| 260 | #endif |
| 261 | } |
| 262 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 263 | static inline void stq_le_p(void *ptr, uint64_t v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 264 | { |
| 265 | uint8_t *p = ptr; |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 266 | stl_le_p(p, (uint32_t)v); |
| 267 | stl_le_p(p + 4, v >> 32); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | /* float access */ |
| 271 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 272 | static inline float32 ldfl_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 273 | { |
| 274 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 275 | float32 f; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 276 | uint32_t i; |
| 277 | } u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 278 | u.i = ldl_le_p(ptr); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 279 | return u.f; |
| 280 | } |
| 281 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 282 | static inline void stfl_le_p(void *ptr, float32 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 283 | { |
| 284 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 285 | float32 f; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 286 | uint32_t i; |
| 287 | } u; |
| 288 | u.f = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 289 | stl_le_p(ptr, u.i); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 290 | } |
| 291 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 292 | static inline float64 ldfq_le_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 293 | { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 294 | CPU_DoubleU u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 295 | u.l.lower = ldl_le_p(ptr); |
| 296 | u.l.upper = ldl_le_p(ptr + 4); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 297 | return u.d; |
| 298 | } |
| 299 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 300 | static inline void stfq_le_p(void *ptr, float64 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 301 | { |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 302 | CPU_DoubleU u; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 303 | u.d = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 304 | stl_le_p(ptr, u.l.lower); |
| 305 | stl_le_p(ptr + 4, u.l.upper); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 306 | } |
| 307 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 308 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 309 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 310 | static inline int lduw_le_p(void *ptr) |
| 311 | { |
| 312 | return *(uint16_t *)ptr; |
| 313 | } |
| 314 | |
| 315 | static inline int ldsw_le_p(void *ptr) |
| 316 | { |
| 317 | return *(int16_t *)ptr; |
| 318 | } |
| 319 | |
| 320 | static inline int ldl_le_p(void *ptr) |
| 321 | { |
| 322 | return *(uint32_t *)ptr; |
| 323 | } |
| 324 | |
| 325 | static inline uint64_t ldq_le_p(void *ptr) |
| 326 | { |
| 327 | return *(uint64_t *)ptr; |
| 328 | } |
| 329 | |
| 330 | static inline void stw_le_p(void *ptr, int v) |
| 331 | { |
| 332 | *(uint16_t *)ptr = v; |
| 333 | } |
| 334 | |
| 335 | static inline void stl_le_p(void *ptr, int v) |
| 336 | { |
| 337 | *(uint32_t *)ptr = v; |
| 338 | } |
| 339 | |
| 340 | static inline void stq_le_p(void *ptr, uint64_t v) |
| 341 | { |
| 342 | *(uint64_t *)ptr = v; |
| 343 | } |
| 344 | |
| 345 | /* float access */ |
| 346 | |
| 347 | static inline float32 ldfl_le_p(void *ptr) |
| 348 | { |
| 349 | return *(float32 *)ptr; |
| 350 | } |
| 351 | |
| 352 | static inline float64 ldfq_le_p(void *ptr) |
| 353 | { |
| 354 | return *(float64 *)ptr; |
| 355 | } |
| 356 | |
| 357 | static inline void stfl_le_p(void *ptr, float32 v) |
| 358 | { |
| 359 | *(float32 *)ptr = v; |
| 360 | } |
| 361 | |
| 362 | static inline void stfq_le_p(void *ptr, float64 v) |
| 363 | { |
| 364 | *(float64 *)ptr = v; |
| 365 | } |
| 366 | #endif |
| 367 | |
| 368 | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED) |
| 369 | |
| 370 | static inline int lduw_be_p(void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 371 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 372 | #if defined(__i386__) |
| 373 | int val; |
| 374 | asm volatile ("movzwl %1, %0\n" |
| 375 | "xchgb %b0, %h0\n" |
| 376 | : "=q" (val) |
| 377 | : "m" (*(uint16_t *)ptr)); |
| 378 | return val; |
| 379 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 380 | uint8_t *b = (uint8_t *) ptr; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 381 | return ((b[0] << 8) | b[1]); |
| 382 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 383 | } |
| 384 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 385 | static inline int ldsw_be_p(void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 386 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 387 | #if defined(__i386__) |
| 388 | int val; |
| 389 | asm volatile ("movzwl %1, %0\n" |
| 390 | "xchgb %b0, %h0\n" |
| 391 | : "=q" (val) |
| 392 | : "m" (*(uint16_t *)ptr)); |
| 393 | return (int16_t)val; |
| 394 | #else |
| 395 | uint8_t *b = (uint8_t *) ptr; |
| 396 | return (int16_t)((b[0] << 8) | b[1]); |
| 397 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 398 | } |
| 399 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 400 | static inline int ldl_be_p(void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 401 | { |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 402 | #if defined(__i386__) || defined(__x86_64__) |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 403 | int val; |
| 404 | asm volatile ("movl %1, %0\n" |
| 405 | "bswap %0\n" |
| 406 | : "=r" (val) |
| 407 | : "m" (*(uint32_t *)ptr)); |
| 408 | return val; |
| 409 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 410 | uint8_t *b = (uint8_t *) ptr; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 411 | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
| 412 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 413 | } |
| 414 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 415 | static inline uint64_t ldq_be_p(void *ptr) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 416 | { |
| 417 | uint32_t a,b; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 418 | a = ldl_be_p(ptr); |
| 419 | b = ldl_be_p(ptr+4); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 420 | return (((uint64_t)a<<32)|b); |
| 421 | } |
| 422 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 423 | static inline void stw_be_p(void *ptr, int v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 424 | { |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 425 | #if defined(__i386__) |
| 426 | asm volatile ("xchgb %b0, %h0\n" |
| 427 | "movw %w0, %1\n" |
| 428 | : "=q" (v) |
| 429 | : "m" (*(uint16_t *)ptr), "0" (v)); |
| 430 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 431 | uint8_t *d = (uint8_t *) ptr; |
| 432 | d[0] = v >> 8; |
| 433 | d[1] = v; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 434 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 435 | } |
| 436 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 437 | static inline void stl_be_p(void *ptr, int v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 438 | { |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 439 | #if defined(__i386__) || defined(__x86_64__) |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 440 | asm volatile ("bswap %0\n" |
| 441 | "movl %0, %1\n" |
| 442 | : "=r" (v) |
| 443 | : "m" (*(uint32_t *)ptr), "0" (v)); |
| 444 | #else |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 445 | uint8_t *d = (uint8_t *) ptr; |
| 446 | d[0] = v >> 24; |
| 447 | d[1] = v >> 16; |
| 448 | d[2] = v >> 8; |
| 449 | d[3] = v; |
bellard | 83d7396 | 2004-02-22 11:53:50 +0000 | [diff] [blame] | 450 | #endif |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 451 | } |
| 452 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 453 | static inline void stq_be_p(void *ptr, uint64_t v) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 454 | { |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 455 | stl_be_p(ptr, v >> 32); |
| 456 | stl_be_p(ptr + 4, v); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 457 | } |
| 458 | |
| 459 | /* float access */ |
| 460 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 461 | static inline float32 ldfl_be_p(void *ptr) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 462 | { |
| 463 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 464 | float32 f; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 465 | uint32_t i; |
| 466 | } u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 467 | u.i = ldl_be_p(ptr); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 468 | return u.f; |
| 469 | } |
| 470 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 471 | static inline void stfl_be_p(void *ptr, float32 v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 472 | { |
| 473 | union { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 474 | float32 f; |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 475 | uint32_t i; |
| 476 | } u; |
| 477 | u.f = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 478 | stl_be_p(ptr, u.i); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 479 | } |
| 480 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 481 | static inline float64 ldfq_be_p(void *ptr) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 482 | { |
| 483 | CPU_DoubleU u; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 484 | u.l.upper = ldl_be_p(ptr); |
| 485 | u.l.lower = ldl_be_p(ptr + 4); |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 486 | return u.d; |
| 487 | } |
| 488 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 489 | static inline void stfq_be_p(void *ptr, float64 v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 490 | { |
| 491 | CPU_DoubleU u; |
| 492 | u.d = v; |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 493 | stl_be_p(ptr, u.l.upper); |
| 494 | stl_be_p(ptr + 4, u.l.lower); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 495 | } |
| 496 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 497 | #else |
| 498 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 499 | static inline int lduw_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 500 | { |
| 501 | return *(uint16_t *)ptr; |
| 502 | } |
| 503 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 504 | static inline int ldsw_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 505 | { |
| 506 | return *(int16_t *)ptr; |
| 507 | } |
| 508 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 509 | static inline int ldl_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 510 | { |
| 511 | return *(uint32_t *)ptr; |
| 512 | } |
| 513 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 514 | static inline uint64_t ldq_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 515 | { |
| 516 | return *(uint64_t *)ptr; |
| 517 | } |
| 518 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 519 | static inline void stw_be_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 520 | { |
| 521 | *(uint16_t *)ptr = v; |
| 522 | } |
| 523 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 524 | static inline void stl_be_p(void *ptr, int v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 525 | { |
| 526 | *(uint32_t *)ptr = v; |
| 527 | } |
| 528 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 529 | static inline void stq_be_p(void *ptr, uint64_t v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 530 | { |
| 531 | *(uint64_t *)ptr = v; |
| 532 | } |
| 533 | |
| 534 | /* float access */ |
| 535 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 536 | static inline float32 ldfl_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 537 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 538 | return *(float32 *)ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 539 | } |
| 540 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 541 | static inline float64 ldfq_be_p(void *ptr) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 542 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 543 | return *(float64 *)ptr; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 544 | } |
| 545 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 546 | static inline void stfl_be_p(void *ptr, float32 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 547 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 548 | *(float32 *)ptr = v; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 549 | } |
| 550 | |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 551 | static inline void stfq_be_p(void *ptr, float64 v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 552 | { |
bellard | 53cd663 | 2005-03-13 18:50:23 +0000 | [diff] [blame] | 553 | *(float64 *)ptr = v; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 554 | } |
bellard | 2df3b95 | 2005-11-19 17:47:39 +0000 | [diff] [blame] | 555 | |
| 556 | #endif |
| 557 | |
| 558 | /* target CPU memory access functions */ |
| 559 | #if defined(TARGET_WORDS_BIGENDIAN) |
| 560 | #define lduw_p(p) lduw_be_p(p) |
| 561 | #define ldsw_p(p) ldsw_be_p(p) |
| 562 | #define ldl_p(p) ldl_be_p(p) |
| 563 | #define ldq_p(p) ldq_be_p(p) |
| 564 | #define ldfl_p(p) ldfl_be_p(p) |
| 565 | #define ldfq_p(p) ldfq_be_p(p) |
| 566 | #define stw_p(p, v) stw_be_p(p, v) |
| 567 | #define stl_p(p, v) stl_be_p(p, v) |
| 568 | #define stq_p(p, v) stq_be_p(p, v) |
| 569 | #define stfl_p(p, v) stfl_be_p(p, v) |
| 570 | #define stfq_p(p, v) stfq_be_p(p, v) |
| 571 | #else |
| 572 | #define lduw_p(p) lduw_le_p(p) |
| 573 | #define ldsw_p(p) ldsw_le_p(p) |
| 574 | #define ldl_p(p) ldl_le_p(p) |
| 575 | #define ldq_p(p) ldq_le_p(p) |
| 576 | #define ldfl_p(p) ldfl_le_p(p) |
| 577 | #define ldfq_p(p) ldfq_le_p(p) |
| 578 | #define stw_p(p, v) stw_le_p(p, v) |
| 579 | #define stl_p(p, v) stl_le_p(p, v) |
| 580 | #define stq_p(p, v) stq_le_p(p, v) |
| 581 | #define stfl_p(p, v) stfl_le_p(p, v) |
| 582 | #define stfq_p(p, v) stfq_le_p(p, v) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 583 | #endif |
| 584 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 585 | /* MMU memory access macros */ |
| 586 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 587 | #if defined(CONFIG_USER_ONLY) |
| 588 | /* On some host systems the guest address space is reserved on the host. |
| 589 | * This allows the guest address space to be offset to a convenient location. |
| 590 | */ |
| 591 | //#define GUEST_BASE 0x20000000 |
| 592 | #define GUEST_BASE 0 |
| 593 | |
| 594 | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ |
| 595 | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
| 596 | #define h2g(x) ((target_ulong)(x - GUEST_BASE)) |
| 597 | |
| 598 | #define saddr(x) g2h(x) |
| 599 | #define laddr(x) g2h(x) |
| 600 | |
| 601 | #else /* !CONFIG_USER_ONLY */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 602 | /* NOTE: we use double casts if pointers and target_ulong have |
| 603 | different sizes */ |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 604 | #define saddr(x) (uint8_t *)(long)(x) |
| 605 | #define laddr(x) (uint8_t *)(long)(x) |
| 606 | #endif |
| 607 | |
| 608 | #define ldub_raw(p) ldub_p(laddr((p))) |
| 609 | #define ldsb_raw(p) ldsb_p(laddr((p))) |
| 610 | #define lduw_raw(p) lduw_p(laddr((p))) |
| 611 | #define ldsw_raw(p) ldsw_p(laddr((p))) |
| 612 | #define ldl_raw(p) ldl_p(laddr((p))) |
| 613 | #define ldq_raw(p) ldq_p(laddr((p))) |
| 614 | #define ldfl_raw(p) ldfl_p(laddr((p))) |
| 615 | #define ldfq_raw(p) ldfq_p(laddr((p))) |
| 616 | #define stb_raw(p, v) stb_p(saddr((p)), v) |
| 617 | #define stw_raw(p, v) stw_p(saddr((p)), v) |
| 618 | #define stl_raw(p, v) stl_p(saddr((p)), v) |
| 619 | #define stq_raw(p, v) stq_p(saddr((p)), v) |
| 620 | #define stfl_raw(p, v) stfl_p(saddr((p)), v) |
| 621 | #define stfq_raw(p, v) stfq_p(saddr((p)), v) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 622 | |
| 623 | |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 624 | #if defined(CONFIG_USER_ONLY) |
| 625 | |
| 626 | /* if user mode, no other memory access functions */ |
| 627 | #define ldub(p) ldub_raw(p) |
| 628 | #define ldsb(p) ldsb_raw(p) |
| 629 | #define lduw(p) lduw_raw(p) |
| 630 | #define ldsw(p) ldsw_raw(p) |
| 631 | #define ldl(p) ldl_raw(p) |
| 632 | #define ldq(p) ldq_raw(p) |
| 633 | #define ldfl(p) ldfl_raw(p) |
| 634 | #define ldfq(p) ldfq_raw(p) |
| 635 | #define stb(p, v) stb_raw(p, v) |
| 636 | #define stw(p, v) stw_raw(p, v) |
| 637 | #define stl(p, v) stl_raw(p, v) |
| 638 | #define stq(p, v) stq_raw(p, v) |
| 639 | #define stfl(p, v) stfl_raw(p, v) |
| 640 | #define stfq(p, v) stfq_raw(p, v) |
| 641 | |
| 642 | #define ldub_code(p) ldub_raw(p) |
| 643 | #define ldsb_code(p) ldsb_raw(p) |
| 644 | #define lduw_code(p) lduw_raw(p) |
| 645 | #define ldsw_code(p) ldsw_raw(p) |
| 646 | #define ldl_code(p) ldl_raw(p) |
| 647 | |
| 648 | #define ldub_kernel(p) ldub_raw(p) |
| 649 | #define ldsb_kernel(p) ldsb_raw(p) |
| 650 | #define lduw_kernel(p) lduw_raw(p) |
| 651 | #define ldsw_kernel(p) ldsw_raw(p) |
| 652 | #define ldl_kernel(p) ldl_raw(p) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 653 | #define ldfl_kernel(p) ldfl_raw(p) |
| 654 | #define ldfq_kernel(p) ldfq_raw(p) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 655 | #define stb_kernel(p, v) stb_raw(p, v) |
| 656 | #define stw_kernel(p, v) stw_raw(p, v) |
| 657 | #define stl_kernel(p, v) stl_raw(p, v) |
| 658 | #define stq_kernel(p, v) stq_raw(p, v) |
bellard | 0ac4bd5 | 2004-01-04 15:44:17 +0000 | [diff] [blame] | 659 | #define stfl_kernel(p, v) stfl_raw(p, v) |
| 660 | #define stfq_kernel(p, vt) stfq_raw(p, v) |
bellard | 61382a5 | 2003-10-27 21:22:23 +0000 | [diff] [blame] | 661 | |
| 662 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 663 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 664 | /* page related stuff */ |
| 665 | |
| 666 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
| 667 | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
| 668 | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
| 669 | |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 670 | /* ??? These should be the larger of unsigned long and target_ulong. */ |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 671 | extern unsigned long qemu_real_host_page_size; |
| 672 | extern unsigned long qemu_host_page_bits; |
| 673 | extern unsigned long qemu_host_page_size; |
| 674 | extern unsigned long qemu_host_page_mask; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 675 | |
bellard | 83fb7ad | 2004-07-05 21:25:26 +0000 | [diff] [blame] | 676 | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 677 | |
| 678 | /* same as PROT_xxx */ |
| 679 | #define PAGE_READ 0x0001 |
| 680 | #define PAGE_WRITE 0x0002 |
| 681 | #define PAGE_EXEC 0x0004 |
| 682 | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) |
| 683 | #define PAGE_VALID 0x0008 |
| 684 | /* original state of the write flag (used when tracking self-modifying |
| 685 | code */ |
| 686 | #define PAGE_WRITE_ORG 0x0010 |
| 687 | |
| 688 | void page_dump(FILE *f); |
pbrook | 53a5960 | 2006-03-25 19:31:22 +0000 | [diff] [blame] | 689 | int page_get_flags(target_ulong address); |
| 690 | void page_set_flags(target_ulong start, target_ulong end, int flags); |
| 691 | void page_unprotect_range(target_ulong data, target_ulong data_size); |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 692 | |
| 693 | #define SINGLE_CPU_DEFINES |
| 694 | #ifdef SINGLE_CPU_DEFINES |
| 695 | |
| 696 | #if defined(TARGET_I386) |
| 697 | |
| 698 | #define CPUState CPUX86State |
| 699 | #define cpu_init cpu_x86_init |
| 700 | #define cpu_exec cpu_x86_exec |
| 701 | #define cpu_gen_code cpu_x86_gen_code |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 702 | #define cpu_signal_handler cpu_x86_signal_handler |
| 703 | |
| 704 | #elif defined(TARGET_ARM) |
| 705 | |
| 706 | #define CPUState CPUARMState |
| 707 | #define cpu_init cpu_arm_init |
| 708 | #define cpu_exec cpu_arm_exec |
| 709 | #define cpu_gen_code cpu_arm_gen_code |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 710 | #define cpu_signal_handler cpu_arm_signal_handler |
| 711 | |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 712 | #elif defined(TARGET_SPARC) |
| 713 | |
| 714 | #define CPUState CPUSPARCState |
| 715 | #define cpu_init cpu_sparc_init |
| 716 | #define cpu_exec cpu_sparc_exec |
| 717 | #define cpu_gen_code cpu_sparc_gen_code |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 718 | #define cpu_signal_handler cpu_sparc_signal_handler |
| 719 | |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 720 | #elif defined(TARGET_PPC) |
| 721 | |
| 722 | #define CPUState CPUPPCState |
| 723 | #define cpu_init cpu_ppc_init |
| 724 | #define cpu_exec cpu_ppc_exec |
| 725 | #define cpu_gen_code cpu_ppc_gen_code |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 726 | #define cpu_signal_handler cpu_ppc_signal_handler |
| 727 | |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 728 | #elif defined(TARGET_M68K) |
| 729 | #define CPUState CPUM68KState |
| 730 | #define cpu_init cpu_m68k_init |
| 731 | #define cpu_exec cpu_m68k_exec |
| 732 | #define cpu_gen_code cpu_m68k_gen_code |
| 733 | #define cpu_signal_handler cpu_m68k_signal_handler |
| 734 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 735 | #elif defined(TARGET_MIPS) |
| 736 | #define CPUState CPUMIPSState |
| 737 | #define cpu_init cpu_mips_init |
| 738 | #define cpu_exec cpu_mips_exec |
| 739 | #define cpu_gen_code cpu_mips_gen_code |
| 740 | #define cpu_signal_handler cpu_mips_signal_handler |
| 741 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 742 | #elif defined(TARGET_SH4) |
| 743 | #define CPUState CPUSH4State |
| 744 | #define cpu_init cpu_sh4_init |
| 745 | #define cpu_exec cpu_sh4_exec |
| 746 | #define cpu_gen_code cpu_sh4_gen_code |
| 747 | #define cpu_signal_handler cpu_sh4_signal_handler |
| 748 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 749 | #else |
| 750 | |
| 751 | #error unsupported target CPU |
| 752 | |
| 753 | #endif |
| 754 | |
bellard | 972ddf7 | 2003-06-21 13:08:39 +0000 | [diff] [blame] | 755 | #endif /* SINGLE_CPU_DEFINES */ |
| 756 | |
ths | c5be9f0 | 2007-02-28 20:20:53 +0000 | [diff] [blame] | 757 | CPUState *cpu_copy(CPUState *env); |
| 758 | |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 759 | void cpu_dump_state(CPUState *env, FILE *f, |
| 760 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 761 | int flags); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 762 | void cpu_dump_statistics (CPUState *env, FILE *f, |
| 763 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 764 | int flags); |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 765 | |
bellard | 972ddf7 | 2003-06-21 13:08:39 +0000 | [diff] [blame] | 766 | void cpu_abort(CPUState *env, const char *fmt, ...); |
bellard | f0aca82 | 2005-11-21 23:22:06 +0000 | [diff] [blame] | 767 | extern CPUState *first_cpu; |
bellard | e2f2289 | 2003-06-25 16:09:48 +0000 | [diff] [blame] | 768 | extern CPUState *cpu_single_env; |
bellard | 9acbed0 | 2004-02-16 21:57:02 +0000 | [diff] [blame] | 769 | extern int code_copy_enabled; |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 770 | |
bellard | 9acbed0 | 2004-02-16 21:57:02 +0000 | [diff] [blame] | 771 | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
| 772 | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
| 773 | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
bellard | ef792f9 | 2004-05-17 20:19:32 +0000 | [diff] [blame] | 774 | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 775 | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 776 | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 777 | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 778 | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 779 | |
bellard | 4690764 | 2003-07-07 12:17:46 +0000 | [diff] [blame] | 780 | void cpu_interrupt(CPUState *s, int mask); |
bellard | b54ad04 | 2004-05-20 13:42:52 +0000 | [diff] [blame] | 781 | void cpu_reset_interrupt(CPUState *env, int mask); |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 782 | |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 783 | int cpu_watchpoint_insert(CPUState *env, target_ulong addr); |
| 784 | int cpu_watchpoint_remove(CPUState *env, target_ulong addr); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 785 | int cpu_breakpoint_insert(CPUState *env, target_ulong pc); |
| 786 | int cpu_breakpoint_remove(CPUState *env, target_ulong pc); |
bellard | c33a346 | 2003-07-29 20:50:33 +0000 | [diff] [blame] | 787 | void cpu_single_step(CPUState *env, int enabled); |
bellard | d95dc32 | 2004-06-20 12:35:26 +0000 | [diff] [blame] | 788 | void cpu_reset(CPUState *s); |
bellard | 4c3a88a | 2003-07-26 12:06:08 +0000 | [diff] [blame] | 789 | |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 790 | /* Return the physical page corresponding to a virtual one. Use it |
| 791 | only for debugging because no protection checks are done. Return -1 |
| 792 | if no page found. */ |
| 793 | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
| 794 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 795 | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
| 796 | #define CPU_LOG_TB_IN_ASM (1 << 1) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 797 | #define CPU_LOG_TB_OP (1 << 2) |
| 798 | #define CPU_LOG_TB_OP_OPT (1 << 3) |
| 799 | #define CPU_LOG_INT (1 << 4) |
| 800 | #define CPU_LOG_EXEC (1 << 5) |
| 801 | #define CPU_LOG_PCALL (1 << 6) |
bellard | fd87259 | 2004-05-12 19:11:15 +0000 | [diff] [blame] | 802 | #define CPU_LOG_IOPORT (1 << 7) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 803 | #define CPU_LOG_TB_CPU (1 << 8) |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 804 | |
| 805 | /* define log items */ |
| 806 | typedef struct CPULogItem { |
| 807 | int mask; |
| 808 | const char *name; |
| 809 | const char *help; |
| 810 | } CPULogItem; |
| 811 | |
| 812 | extern CPULogItem cpu_log_items[]; |
| 813 | |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 814 | void cpu_set_log(int log_flags); |
| 815 | void cpu_set_log_filename(const char *filename); |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 816 | int cpu_str_to_log_mask(const char *str); |
bellard | 3486513 | 2003-10-05 14:28:56 +0000 | [diff] [blame] | 817 | |
bellard | 09683d3 | 2004-01-04 23:49:41 +0000 | [diff] [blame] | 818 | /* IO ports API */ |
| 819 | |
| 820 | /* NOTE: as these functions may be even used when there is an isa |
| 821 | brige on non x86 targets, we always defined them */ |
| 822 | #ifndef NO_CPU_IO_DEFS |
| 823 | void cpu_outb(CPUState *env, int addr, int val); |
| 824 | void cpu_outw(CPUState *env, int addr, int val); |
| 825 | void cpu_outl(CPUState *env, int addr, int val); |
| 826 | int cpu_inb(CPUState *env, int addr); |
| 827 | int cpu_inw(CPUState *env, int addr); |
| 828 | int cpu_inl(CPUState *env, int addr); |
| 829 | #endif |
| 830 | |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 831 | /* memory API */ |
| 832 | |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 833 | extern int phys_ram_size; |
| 834 | extern int phys_ram_fd; |
| 835 | extern uint8_t *phys_ram_base; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 836 | extern uint8_t *phys_ram_dirty; |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 837 | |
| 838 | /* physical memory access */ |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 839 | #define TLB_INVALID_MASK (1 << 3) |
| 840 | #define IO_MEM_SHIFT 4 |
bellard | 9869996 | 2005-11-26 10:29:22 +0000 | [diff] [blame] | 841 | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 842 | |
| 843 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
| 844 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
| 845 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 846 | #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ |
bellard | 2a4188a | 2006-06-25 21:54:59 +0000 | [diff] [blame] | 847 | /* acts like a ROM when read and like a device when written. As an |
| 848 | exception, the write memory callback gets the ram offset instead of |
| 849 | the physical address */ |
| 850 | #define IO_MEM_ROMD (1) |
bellard | edf75d5 | 2004-01-04 17:43:30 +0000 | [diff] [blame] | 851 | |
bellard | 7727994 | 2004-06-03 14:08:36 +0000 | [diff] [blame] | 852 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
| 853 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 854 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 855 | void cpu_register_physical_memory(target_phys_addr_t start_addr, |
| 856 | unsigned long size, |
| 857 | unsigned long phys_offset); |
bellard | 3b21e03 | 2006-09-24 18:41:56 +0000 | [diff] [blame] | 858 | uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
bellard | e9a1ab1 | 2007-02-08 23:08:38 +0000 | [diff] [blame] | 859 | ram_addr_t qemu_ram_alloc(unsigned int size); |
| 860 | void qemu_ram_free(ram_addr_t addr); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 861 | int cpu_register_io_memory(int io_index, |
| 862 | CPUReadMemoryFunc **mem_read, |
bellard | 7727994 | 2004-06-03 14:08:36 +0000 | [diff] [blame] | 863 | CPUWriteMemoryFunc **mem_write, |
| 864 | void *opaque); |
bellard | 8926b51 | 2004-10-10 15:14:20 +0000 | [diff] [blame] | 865 | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index); |
| 866 | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index); |
bellard | 33417e7 | 2003-08-10 21:47:01 +0000 | [diff] [blame] | 867 | |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 868 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 869 | int len, int is_write); |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 870 | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
| 871 | uint8_t *buf, int len) |
bellard | 8b1f24b | 2004-02-25 23:24:38 +0000 | [diff] [blame] | 872 | { |
| 873 | cpu_physical_memory_rw(addr, buf, len, 0); |
| 874 | } |
bellard | 2e12669 | 2004-04-25 21:28:44 +0000 | [diff] [blame] | 875 | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
| 876 | const uint8_t *buf, int len) |
bellard | 8b1f24b | 2004-02-25 23:24:38 +0000 | [diff] [blame] | 877 | { |
| 878 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); |
| 879 | } |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 880 | uint32_t ldub_phys(target_phys_addr_t addr); |
| 881 | uint32_t lduw_phys(target_phys_addr_t addr); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 882 | uint32_t ldl_phys(target_phys_addr_t addr); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 883 | uint64_t ldq_phys(target_phys_addr_t addr); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 884 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 885 | void stb_phys(target_phys_addr_t addr, uint32_t val); |
| 886 | void stw_phys(target_phys_addr_t addr, uint32_t val); |
bellard | 8df1cd0 | 2005-01-28 22:37:22 +0000 | [diff] [blame] | 887 | void stl_phys(target_phys_addr_t addr, uint32_t val); |
bellard | aab3309 | 2005-10-30 20:48:42 +0000 | [diff] [blame] | 888 | void stq_phys(target_phys_addr_t addr, uint64_t val); |
bellard | 8b1f24b | 2004-02-25 23:24:38 +0000 | [diff] [blame] | 889 | |
bellard | d0ecd2a | 2006-04-23 17:14:48 +0000 | [diff] [blame] | 890 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, |
| 891 | const uint8_t *buf, int len); |
bellard | 8b1f24b | 2004-02-25 23:24:38 +0000 | [diff] [blame] | 892 | int cpu_memory_rw_debug(CPUState *env, target_ulong addr, |
| 893 | uint8_t *buf, int len, int is_write); |
bellard | 13eb76e | 2004-01-24 15:23:36 +0000 | [diff] [blame] | 894 | |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 895 | #define VGA_DIRTY_FLAG 0x01 |
| 896 | #define CODE_DIRTY_FLAG 0x02 |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 897 | |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 898 | /* read dirty bit (return 0 or 1) */ |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 899 | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 900 | { |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 901 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
| 902 | } |
| 903 | |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 904 | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 905 | int dirty_flags) |
| 906 | { |
| 907 | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 908 | } |
| 909 | |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 910 | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 911 | { |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 912 | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 913 | } |
| 914 | |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 915 | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 916 | int dirty_flags); |
bellard | 04c504c | 2005-08-21 09:24:50 +0000 | [diff] [blame] | 917 | void cpu_tlb_update_dirty(CPUState *env); |
bellard | 1ccde1c | 2004-02-06 19:46:14 +0000 | [diff] [blame] | 918 | |
bellard | e3db722 | 2005-01-26 22:00:47 +0000 | [diff] [blame] | 919 | void dump_exec_info(FILE *f, |
| 920 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 921 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 922 | /*******************************************/ |
| 923 | /* host CPU ticks (if available) */ |
| 924 | |
| 925 | #if defined(__powerpc__) |
| 926 | |
| 927 | static inline uint32_t get_tbl(void) |
| 928 | { |
| 929 | uint32_t tbl; |
| 930 | asm volatile("mftb %0" : "=r" (tbl)); |
| 931 | return tbl; |
| 932 | } |
| 933 | |
| 934 | static inline uint32_t get_tbu(void) |
| 935 | { |
| 936 | uint32_t tbl; |
| 937 | asm volatile("mftbu %0" : "=r" (tbl)); |
| 938 | return tbl; |
| 939 | } |
| 940 | |
| 941 | static inline int64_t cpu_get_real_ticks(void) |
| 942 | { |
| 943 | uint32_t l, h, h1; |
| 944 | /* NOTE: we test if wrapping has occurred */ |
| 945 | do { |
| 946 | h = get_tbu(); |
| 947 | l = get_tbl(); |
| 948 | h1 = get_tbu(); |
| 949 | } while (h != h1); |
| 950 | return ((int64_t)h << 32) | l; |
| 951 | } |
| 952 | |
| 953 | #elif defined(__i386__) |
| 954 | |
| 955 | static inline int64_t cpu_get_real_ticks(void) |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 956 | { |
| 957 | int64_t val; |
| 958 | asm volatile ("rdtsc" : "=A" (val)); |
| 959 | return val; |
| 960 | } |
| 961 | |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 962 | #elif defined(__x86_64__) |
| 963 | |
| 964 | static inline int64_t cpu_get_real_ticks(void) |
| 965 | { |
| 966 | uint32_t low,high; |
| 967 | int64_t val; |
| 968 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
| 969 | val = high; |
| 970 | val <<= 32; |
| 971 | val |= low; |
| 972 | return val; |
| 973 | } |
| 974 | |
| 975 | #elif defined(__ia64) |
| 976 | |
| 977 | static inline int64_t cpu_get_real_ticks(void) |
| 978 | { |
| 979 | int64_t val; |
| 980 | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
| 981 | return val; |
| 982 | } |
| 983 | |
| 984 | #elif defined(__s390__) |
| 985 | |
| 986 | static inline int64_t cpu_get_real_ticks(void) |
| 987 | { |
| 988 | int64_t val; |
| 989 | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
| 990 | return val; |
| 991 | } |
| 992 | |
bellard | 74ccb34 | 2006-07-18 21:23:34 +0000 | [diff] [blame] | 993 | #elif defined(__sparc_v9__) |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 994 | |
| 995 | static inline int64_t cpu_get_real_ticks (void) |
| 996 | { |
| 997 | #if defined(_LP64) |
| 998 | uint64_t rval; |
| 999 | asm volatile("rd %%tick,%0" : "=r"(rval)); |
| 1000 | return rval; |
| 1001 | #else |
| 1002 | union { |
| 1003 | uint64_t i64; |
| 1004 | struct { |
| 1005 | uint32_t high; |
| 1006 | uint32_t low; |
| 1007 | } i32; |
| 1008 | } rval; |
| 1009 | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
| 1010 | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
| 1011 | return rval.i64; |
| 1012 | #endif |
| 1013 | } |
pbrook | 4615218 | 2006-07-30 19:16:29 +0000 | [diff] [blame] | 1014 | #else |
| 1015 | /* The host CPU doesn't have an easily accessible cycle counter. |
| 1016 | Just return a monotonically increasing vlue. This will be totally wrong, |
| 1017 | but hopefully better than nothing. */ |
| 1018 | static inline int64_t cpu_get_real_ticks (void) |
| 1019 | { |
| 1020 | static int64_t ticks = 0; |
| 1021 | return ticks++; |
| 1022 | } |
bellard | effedbc | 2006-07-13 23:00:40 +0000 | [diff] [blame] | 1023 | #endif |
| 1024 | |
| 1025 | /* profiling */ |
| 1026 | #ifdef CONFIG_PROFILER |
| 1027 | static inline int64_t profile_getclock(void) |
| 1028 | { |
| 1029 | return cpu_get_real_ticks(); |
| 1030 | } |
| 1031 | |
bellard | 5f1ce94 | 2006-02-08 22:40:15 +0000 | [diff] [blame] | 1032 | extern int64_t kqemu_time, kqemu_time_start; |
| 1033 | extern int64_t qemu_time, qemu_time_start; |
| 1034 | extern int64_t tlb_flush_time; |
| 1035 | extern int64_t kqemu_exec_count; |
| 1036 | extern int64_t dev_time; |
| 1037 | extern int64_t kqemu_ret_int_count; |
| 1038 | extern int64_t kqemu_ret_excp_count; |
| 1039 | extern int64_t kqemu_ret_intr_count; |
| 1040 | |
| 1041 | #endif |
| 1042 | |
bellard | 5a9fdfe | 2003-06-15 20:02:25 +0000 | [diff] [blame] | 1043 | #endif /* CPU_ALL_H */ |