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qemu / qemu / 5e78c98b7cc98619d2740c7c5030aa56fb22e79f / . / hw / meson.build
blob: b3366c888ef61b3093091c260d23926c0524ca6e [file] [log] [blame]
Marc-André Lureaub2c00bc2019-08-17 12:04:43 +0400[diff] [blame]1subdir('9pfs')
Marc-André Lureau36b34c32019-08-17 11:40:51 +0400[diff] [blame]2subdir('acpi')
Marc-André Lureaub53d5552019-08-17 11:34:47 +0400[diff] [blame]3subdir('adc')
Marc-André Lureaua9d48252019-08-17 11:33:44 +0400[diff] [blame]4subdir('audio')
Marc-André Lureau6bcb5d92019-08-17 11:30:59 +0400[diff] [blame]5subdir('block')
Marc-André Lureaua518e032019-08-17 11:25:08 +0400[diff] [blame]6subdir('char')
Marc-André Lureauc92a3092019-08-15 15:24:58 +0400[diff] [blame]7subdir('core')
Marc-André Lureaucff3c5d2019-08-17 11:21:13 +0400[diff] [blame]8subdir('cpu')
Marc-André Lureaub4c8eec2019-08-17 11:03:19 +0400[diff] [blame]9subdir('display')
Marc-André Lureau7d744252019-08-16 19:06:19 +0400[diff] [blame]10subdir('dma')
Marc-André Lureaua7b057d2019-08-16 19:03:55 +0400[diff] [blame]11subdir('gpio')
Marc-André Lureaucc4d76a2019-08-16 19:02:41 +0400[diff] [blame]12subdir('hyperv')
Marc-André Lureauc8d93332019-08-16 19:00:37 +0400[diff] [blame]13subdir('i2c')
Marc-André Lureau5b8c4d22019-08-16 18:56:47 +0400[diff] [blame]14subdir('ide')
Marc-André Lureau6a18fd02019-08-16 18:39:54 +0400[diff] [blame]15subdir('input')
Marc-André Lureaubff065a2019-08-16 18:36:51 +0400[diff] [blame]16subdir('intc')
Marc-André Lureauae36d232019-08-16 18:23:55 +0400[diff] [blame]17subdir('ipack')
Marc-André Lureaua7b9b7d2019-08-16 18:22:36 +0400[diff] [blame]18subdir('ipmi')
Marc-André Lureaua74fb392019-08-16 18:20:39 +0400[diff] [blame]19subdir('isa')
Marc-André Lureau97813b92019-08-15 15:45:58 +0400[diff] [blame]20subdir('mem')
Marc-André Lureau721cdca2019-08-16 18:15:00 +0400[diff] [blame]21subdir('misc')
Marc-André Lureaub1419fa2019-08-16 17:48:00 +0400[diff] [blame]22subdir('net')
Paolo Bonzinib908c372020-01-24 12:50:57 +0100[diff] [blame]23subdir('nubus')
Klaus Jensen88eea452021-04-14 22:14:30 +0200[diff] [blame]24subdir('nvme')
Marc-André Lureau9f6ede22019-08-16 17:35:29 +0400[diff] [blame]25subdir('nvram')
Marc-André Lureau4a328442019-08-16 17:32:24 +0400[diff] [blame]26subdir('pci')
Marc-André Lureauea7e9b52019-08-16 17:26:17 +0400[diff] [blame]27subdir('pci-bridge')
Marc-André Lureau9235a822019-08-16 17:23:03 +0400[diff] [blame]28subdir('pci-host')
Marc-André Lureau00953fa2019-08-16 17:19:34 +0400[diff] [blame]29subdir('pcmcia')
Marc-André Lureau19233c92019-08-16 17:47:43 +0400[diff] [blame]30subdir('rdma')
Paolo Bonziniee802372020-01-24 12:35:13 +0100[diff] [blame]31subdir('rtc')
Marc-André Lureau7633d842019-08-16 17:16:48 +0400[diff] [blame]32subdir('scsi')
Marc-André Lureau092795f2019-08-16 17:04:35 +0400[diff] [blame]33subdir('sd')
Corey Minyard5e9ae4b2021-05-18 16:08:03 -0500[diff] [blame]34subdir('sensor')
Marc-André Lureaud6c9b1f2019-08-15 15:39:54 +0400[diff] [blame]35subdir('smbios')
Marc-André Lureaub1bc8172019-08-16 17:02:22 +0400[diff] [blame]36subdir('ssi')
Paolo Bonzinibeeb0562020-01-24 12:35:13 +0100[diff] [blame]37subdir('timer')
Paolo Bonzini70c2cfe2020-08-04 14:03:59 +0200[diff] [blame]38subdir('tpm')
Paolo Bonzini06677ce2020-08-06 13:07:39 +0200[diff] [blame]39subdir('usb')
Marc-André Lureau4f780d52019-08-15 17:31:07 +0400[diff] [blame]40subdir('vfio')
Marc-André Lureaube786d22019-08-15 17:23:36 +0400[diff] [blame]41subdir('virtio')
Marc-André Lureaue4fea7d2019-08-15 15:50:11 +0400[diff] [blame]42subdir('watchdog')
Marc-André Lureau582ea952019-08-15 15:15:32 +0400[diff] [blame]43subdir('xen')
Marc-André Lureau2c442202019-08-17 13:55:58 +0400[diff] [blame]44subdir('xenpv')
45
46subdir('alpha')
47subdir('arm')
48subdir('avr')
49subdir('cris')
50subdir('hppa')
51subdir('i386')
Marc-André Lureau2c442202019-08-17 13:55:58 +0400[diff] [blame]52subdir('m68k')
53subdir('microblaze')
54subdir('mips')
Marc-André Lureau2c442202019-08-17 13:55:58 +0400[diff] [blame]55subdir('nios2')
56subdir('openrisc')
57subdir('ppc')
Jagannathan Raman3f0e7e52021-01-29 11:46:07 -0500[diff] [blame]58subdir('remote')
Marc-André Lureau2c442202019-08-17 13:55:58 +0400[diff] [blame]59subdir('riscv')
60subdir('rx')
61subdir('s390x')
62subdir('sh4')
63subdir('sparc')
64subdir('sparc64')
65subdir('tricore')
Marc-André Lureau2c442202019-08-17 13:55:58 +0400[diff] [blame]66subdir('xtensa')