blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
Richard Henderson | 3cf246f | 2013-10-03 14:04:46 -0500 | [diff] [blame] | 25 | #include "tcg-be-null.h" |
| 26 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 27 | #ifndef NDEBUG |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 28 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
| 29 | "%g0", |
| 30 | "%g1", |
| 31 | "%g2", |
| 32 | "%g3", |
| 33 | "%g4", |
| 34 | "%g5", |
| 35 | "%g6", |
| 36 | "%g7", |
| 37 | "%o0", |
| 38 | "%o1", |
| 39 | "%o2", |
| 40 | "%o3", |
| 41 | "%o4", |
| 42 | "%o5", |
| 43 | "%o6", |
| 44 | "%o7", |
| 45 | "%l0", |
| 46 | "%l1", |
| 47 | "%l2", |
| 48 | "%l3", |
| 49 | "%l4", |
| 50 | "%l5", |
| 51 | "%l6", |
| 52 | "%l7", |
| 53 | "%i0", |
| 54 | "%i1", |
| 55 | "%i2", |
| 56 | "%i3", |
| 57 | "%i4", |
| 58 | "%i5", |
| 59 | "%i6", |
| 60 | "%i7", |
| 61 | }; |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 62 | #endif |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 63 | |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 64 | /* Define some temporary registers. T2 is used for constant generation. */ |
| 65 | #define TCG_REG_T1 TCG_REG_G1 |
| 66 | #define TCG_REG_T2 TCG_REG_O7 |
| 67 | |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 68 | #ifdef CONFIG_USE_GUEST_BASE |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 69 | # define TCG_GUEST_BASE_REG TCG_REG_I5 |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 70 | #else |
| 71 | # define TCG_GUEST_BASE_REG TCG_REG_G0 |
| 72 | #endif |
Blue Swirl | e141ab5 | 2011-09-18 14:55:46 +0000 | [diff] [blame] | 73 | |
blueswir1 | 0954d0d | 2008-03-11 21:01:02 +0000 | [diff] [blame] | 74 | static const int tcg_target_reg_alloc_order[] = { |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 75 | TCG_REG_L0, |
| 76 | TCG_REG_L1, |
| 77 | TCG_REG_L2, |
| 78 | TCG_REG_L3, |
| 79 | TCG_REG_L4, |
| 80 | TCG_REG_L5, |
| 81 | TCG_REG_L6, |
| 82 | TCG_REG_L7, |
Richard Henderson | 26adfb7 | 2012-03-25 22:43:17 +0200 | [diff] [blame] | 83 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 84 | TCG_REG_I0, |
| 85 | TCG_REG_I1, |
| 86 | TCG_REG_I2, |
| 87 | TCG_REG_I3, |
| 88 | TCG_REG_I4, |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 89 | TCG_REG_I5, |
Richard Henderson | 26adfb7 | 2012-03-25 22:43:17 +0200 | [diff] [blame] | 90 | |
| 91 | TCG_REG_G2, |
| 92 | TCG_REG_G3, |
| 93 | TCG_REG_G4, |
| 94 | TCG_REG_G5, |
| 95 | |
| 96 | TCG_REG_O0, |
| 97 | TCG_REG_O1, |
| 98 | TCG_REG_O2, |
| 99 | TCG_REG_O3, |
| 100 | TCG_REG_O4, |
| 101 | TCG_REG_O5, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 102 | }; |
| 103 | |
| 104 | static const int tcg_target_call_iarg_regs[6] = { |
| 105 | TCG_REG_O0, |
| 106 | TCG_REG_O1, |
| 107 | TCG_REG_O2, |
| 108 | TCG_REG_O3, |
| 109 | TCG_REG_O4, |
| 110 | TCG_REG_O5, |
| 111 | }; |
| 112 | |
Stefan Weil | 26a74ae | 2011-09-05 11:07:01 +0200 | [diff] [blame] | 113 | static const int tcg_target_call_oarg_regs[] = { |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 114 | TCG_REG_O0, |
Blue Swirl | e141ab5 | 2011-09-18 14:55:46 +0000 | [diff] [blame] | 115 | TCG_REG_O1, |
| 116 | TCG_REG_O2, |
| 117 | TCG_REG_O3, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 118 | }; |
| 119 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 120 | #define INSN_OP(x) ((x) << 30) |
| 121 | #define INSN_OP2(x) ((x) << 22) |
| 122 | #define INSN_OP3(x) ((x) << 19) |
| 123 | #define INSN_OPF(x) ((x) << 5) |
| 124 | #define INSN_RD(x) ((x) << 25) |
| 125 | #define INSN_RS1(x) ((x) << 14) |
| 126 | #define INSN_RS2(x) (x) |
blueswir1 | 8384dd6 | 2008-05-25 11:19:24 +0000 | [diff] [blame] | 127 | #define INSN_ASI(x) ((x) << 5) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 128 | |
Richard Henderson | 203342d | 2012-10-10 09:02:47 -0700 | [diff] [blame] | 129 | #define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff)) |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 130 | #define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 131 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 132 | #define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20)) |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 133 | #define INSN_OFF19(x) (((x) >> 2) & 0x07ffff) |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 134 | #define INSN_COND(x) ((x) << 25) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 135 | |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 136 | #define COND_N 0x0 |
| 137 | #define COND_E 0x1 |
| 138 | #define COND_LE 0x2 |
| 139 | #define COND_L 0x3 |
| 140 | #define COND_LEU 0x4 |
| 141 | #define COND_CS 0x5 |
| 142 | #define COND_NEG 0x6 |
| 143 | #define COND_VS 0x7 |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 144 | #define COND_A 0x8 |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 145 | #define COND_NE 0x9 |
| 146 | #define COND_G 0xa |
| 147 | #define COND_GE 0xb |
| 148 | #define COND_GU 0xc |
| 149 | #define COND_CC 0xd |
| 150 | #define COND_POS 0xe |
| 151 | #define COND_VC 0xf |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 152 | #define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 153 | |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 154 | #define RCOND_Z 1 |
| 155 | #define RCOND_LEZ 2 |
| 156 | #define RCOND_LZ 3 |
| 157 | #define RCOND_NZ 5 |
| 158 | #define RCOND_GZ 6 |
| 159 | #define RCOND_GEZ 7 |
| 160 | |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 161 | #define MOVCC_ICC (1 << 18) |
| 162 | #define MOVCC_XCC (1 << 18 | 1 << 12) |
| 163 | |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 164 | #define BPCC_ICC 0 |
| 165 | #define BPCC_XCC (2 << 20) |
| 166 | #define BPCC_PT (1 << 19) |
| 167 | #define BPCC_PN 0 |
| 168 | #define BPCC_A (1 << 29) |
| 169 | |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 170 | #define BPR_PT BPCC_PT |
| 171 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 172 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 173 | #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 174 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
Richard Henderson | dc69960 | 2010-02-16 14:21:19 -0800 | [diff] [blame] | 175 | #define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 176 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
blueswir1 | 9a7f322 | 2008-05-17 09:41:14 +0000 | [diff] [blame] | 177 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
Richard Henderson | be6551b | 2010-02-16 14:02:04 -0800 | [diff] [blame] | 178 | #define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 179 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 180 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
| 181 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
Richard Henderson | a221ae3 | 2012-03-23 23:57:12 +0100 | [diff] [blame] | 182 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x08)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 183 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
| 184 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
| 185 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
| 186 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
| 187 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
| 188 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
| 189 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 190 | #define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c)) |
Richard Henderson | 203342d | 2012-10-10 09:02:47 -0700 | [diff] [blame] | 191 | #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 192 | |
| 193 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
| 194 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
| 195 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
| 196 | |
| 197 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
| 198 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
| 199 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
| 200 | |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 201 | #define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0)) |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 202 | #define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 203 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
| 204 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
| 205 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
| 206 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
| 207 | #define CALL INSN_OP(1) |
| 208 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
| 209 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
| 210 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
| 211 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
| 212 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
| 213 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
| 214 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
| 215 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
| 216 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
| 217 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
| 218 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
blueswir1 | 8384dd6 | 2008-05-25 11:19:24 +0000 | [diff] [blame] | 219 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
| 220 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
| 221 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
| 222 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
| 223 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
| 224 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
| 225 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
| 226 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
| 227 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
| 228 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
| 229 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
| 230 | |
| 231 | #ifndef ASI_PRIMARY_LITTLE |
| 232 | #define ASI_PRIMARY_LITTLE 0x88 |
| 233 | #endif |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 234 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 235 | #define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 236 | #define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 237 | #define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 238 | #define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 239 | #define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 240 | |
| 241 | #define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 242 | #define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 243 | #define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE)) |
| 244 | |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 245 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
| 246 | { |
| 247 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
| 248 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
| 249 | } |
| 250 | |
| 251 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
| 252 | { |
| 253 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
| 254 | } |
| 255 | |
| 256 | static void patch_reloc(uint8_t *code_ptr, int type, |
Richard Henderson | 2ba7fae2 | 2013-08-20 15:30:10 -0700 | [diff] [blame] | 257 | intptr_t value, intptr_t addend) |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 258 | { |
| 259 | uint32_t insn; |
| 260 | value += addend; |
| 261 | switch (type) { |
| 262 | case R_SPARC_32: |
| 263 | if (value != (uint32_t)value) { |
| 264 | tcg_abort(); |
| 265 | } |
| 266 | *(uint32_t *)code_ptr = value; |
| 267 | break; |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 268 | case R_SPARC_WDISP16: |
Richard Henderson | 2ba7fae2 | 2013-08-20 15:30:10 -0700 | [diff] [blame] | 269 | value -= (intptr_t)code_ptr; |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 270 | if (!check_fit_tl(value >> 2, 16)) { |
| 271 | tcg_abort(); |
| 272 | } |
| 273 | insn = *(uint32_t *)code_ptr; |
| 274 | insn &= ~INSN_OFF16(-1); |
| 275 | insn |= INSN_OFF16(value); |
| 276 | *(uint32_t *)code_ptr = insn; |
| 277 | break; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 278 | case R_SPARC_WDISP19: |
Richard Henderson | 2ba7fae2 | 2013-08-20 15:30:10 -0700 | [diff] [blame] | 279 | value -= (intptr_t)code_ptr; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 280 | if (!check_fit_tl(value >> 2, 19)) { |
| 281 | tcg_abort(); |
| 282 | } |
| 283 | insn = *(uint32_t *)code_ptr; |
| 284 | insn &= ~INSN_OFF19(-1); |
| 285 | insn |= INSN_OFF19(value); |
| 286 | *(uint32_t *)code_ptr = insn; |
| 287 | break; |
| 288 | default: |
| 289 | tcg_abort(); |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* parse target specific constraints */ |
| 294 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
| 295 | { |
| 296 | const char *ct_str; |
| 297 | |
| 298 | ct_str = *pct_str; |
| 299 | switch (ct_str[0]) { |
| 300 | case 'r': |
| 301 | ct->ct |= TCG_CT_REG; |
| 302 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
| 303 | break; |
| 304 | case 'L': /* qemu_ld/st constraint */ |
| 305 | ct->ct |= TCG_CT_REG; |
| 306 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
| 307 | // Helper args |
| 308 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); |
| 309 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); |
| 310 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); |
| 311 | break; |
| 312 | case 'I': |
| 313 | ct->ct |= TCG_CT_CONST_S11; |
| 314 | break; |
| 315 | case 'J': |
| 316 | ct->ct |= TCG_CT_CONST_S13; |
| 317 | break; |
| 318 | case 'Z': |
| 319 | ct->ct |= TCG_CT_CONST_ZERO; |
| 320 | break; |
| 321 | default: |
| 322 | return -1; |
| 323 | } |
| 324 | ct_str++; |
| 325 | *pct_str = ct_str; |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | /* test if a constant matches the constraint */ |
| 330 | static inline int tcg_target_const_match(tcg_target_long val, |
| 331 | const TCGArgConstraint *arg_ct) |
| 332 | { |
| 333 | int ct = arg_ct->ct; |
| 334 | |
| 335 | if (ct & TCG_CT_CONST) { |
| 336 | return 1; |
| 337 | } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { |
| 338 | return 1; |
| 339 | } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) { |
| 340 | return 1; |
| 341 | } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { |
| 342 | return 1; |
| 343 | } else { |
| 344 | return 0; |
| 345 | } |
| 346 | } |
| 347 | |
blueswir1 | 26cc915 | 2008-05-24 18:06:35 +0000 | [diff] [blame] | 348 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
| 349 | int op) |
| 350 | { |
| 351 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
| 352 | INSN_RS2(rs2)); |
| 353 | } |
| 354 | |
blueswir1 | 6f41b77 | 2008-08-17 20:14:16 +0000 | [diff] [blame] | 355 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, |
| 356 | uint32_t offset, int op) |
blueswir1 | 26cc915 | 2008-05-24 18:06:35 +0000 | [diff] [blame] | 357 | { |
| 358 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
| 359 | INSN_IMM13(offset)); |
| 360 | } |
| 361 | |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 362 | static void tcg_out_arithc(TCGContext *s, int rd, int rs1, |
| 363 | int val2, int val2const, int op) |
| 364 | { |
| 365 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
| 366 | | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); |
| 367 | } |
| 368 | |
Richard Henderson | 2a534af | 2011-11-09 08:03:34 +0000 | [diff] [blame] | 369 | static inline void tcg_out_mov(TCGContext *s, TCGType type, |
| 370 | TCGReg ret, TCGReg arg) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 371 | { |
Richard Henderson | dda73c7 | 2012-10-10 09:02:38 -0700 | [diff] [blame] | 372 | if (ret != arg) { |
| 373 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
| 374 | } |
blueswir1 | 26cc915 | 2008-05-24 18:06:35 +0000 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
| 378 | { |
| 379 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 380 | } |
| 381 | |
blueswir1 | b101234 | 2008-05-24 18:09:50 +0000 | [diff] [blame] | 382 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
| 383 | { |
| 384 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
| 385 | } |
| 386 | |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 387 | static void tcg_out_movi(TCGContext *s, TCGType type, |
| 388 | TCGReg ret, tcg_target_long arg) |
blueswir1 | b101234 | 2008-05-24 18:09:50 +0000 | [diff] [blame] | 389 | { |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 390 | tcg_target_long hi, lo; |
blueswir1 | b101234 | 2008-05-24 18:09:50 +0000 | [diff] [blame] | 391 | |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 392 | /* A 13-bit constant sign-extended to 64-bits. */ |
| 393 | if (check_fit_tl(arg, 13)) { |
| 394 | tcg_out_movi_imm13(s, ret, arg); |
| 395 | return; |
| 396 | } |
| 397 | |
| 398 | /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ |
Richard Henderson | 4317220 | 2009-12-19 19:45:27 -0800 | [diff] [blame] | 399 | if (TCG_TARGET_REG_BITS == 32 |
| 400 | || type == TCG_TYPE_I32 |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 401 | || (arg & ~0xffffffffu) == 0) { |
| 402 | tcg_out_sethi(s, ret, arg); |
| 403 | if (arg & 0x3ff) { |
| 404 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); |
| 405 | } |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | /* A 32-bit constant sign-extended to 64-bits. */ |
| 410 | if (check_fit_tl(arg, 32)) { |
Richard Henderson | 4317220 | 2009-12-19 19:45:27 -0800 | [diff] [blame] | 411 | tcg_out_sethi(s, ret, ~arg); |
| 412 | tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 413 | return; |
| 414 | } |
| 415 | |
| 416 | /* A 64-bit constant decomposed into 2 32-bit pieces. */ |
| 417 | lo = (int32_t)arg; |
| 418 | if (check_fit_tl(lo, 13)) { |
| 419 | hi = (arg - lo) >> 31 >> 1; |
| 420 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 421 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
Richard Henderson | a9c7d27 | 2013-09-09 21:07:09 -0700 | [diff] [blame] | 422 | tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); |
| 423 | } else { |
| 424 | hi = arg >> 31 >> 1; |
| 425 | tcg_out_movi(s, TCG_TYPE_I32, ret, hi); |
| 426 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo); |
| 427 | tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 428 | tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR); |
blueswir1 | 6f41b77 | 2008-08-17 20:14:16 +0000 | [diff] [blame] | 429 | } |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 430 | } |
| 431 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 432 | static inline void tcg_out_ldst_rr(TCGContext *s, int data, int a1, |
| 433 | int a2, int op) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 434 | { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 435 | tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2)); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 436 | } |
| 437 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 438 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, |
| 439 | int offset, int op) |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 440 | { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 441 | if (check_fit_tl(offset, 13)) { |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 442 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
| 443 | INSN_IMM13(offset)); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 444 | } else { |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 445 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset); |
| 446 | tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op); |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 447 | } |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 448 | } |
| 449 | |
Richard Henderson | 2a534af | 2011-11-09 08:03:34 +0000 | [diff] [blame] | 450 | static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, |
Richard Henderson | a05b5b9 | 2013-08-20 17:07:26 -0700 | [diff] [blame] | 451 | TCGReg arg1, intptr_t arg2) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 452 | { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 453 | tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX)); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 454 | } |
| 455 | |
Richard Henderson | 2a534af | 2011-11-09 08:03:34 +0000 | [diff] [blame] | 456 | static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, |
Richard Henderson | a05b5b9 | 2013-08-20 17:07:26 -0700 | [diff] [blame] | 457 | TCGReg arg1, intptr_t arg2) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 458 | { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 459 | tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX)); |
| 460 | } |
| 461 | |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 462 | static inline void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 463 | { |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 464 | TCGReg base = TCG_REG_G0; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 465 | if (!check_fit_tl(arg, 10)) { |
| 466 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 467 | base = ret; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 468 | } |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 469 | tcg_out_ld(s, TCG_TYPE_PTR, ret, base, arg & 0x3ff); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 470 | } |
| 471 | |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 472 | static inline void tcg_out_sety(TCGContext *s, int rs) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 473 | { |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 474 | tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs)); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 475 | } |
| 476 | |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 477 | static inline void tcg_out_rdy(TCGContext *s, int rd) |
| 478 | { |
| 479 | tcg_out32(s, RDY | INSN_RD(rd)); |
| 480 | } |
| 481 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 482 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
| 483 | { |
| 484 | if (val != 0) { |
blueswir1 | 57e49b4 | 2008-05-18 08:11:14 +0000 | [diff] [blame] | 485 | if (check_fit_tl(val, 13)) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 486 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 487 | else { |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 488 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, val); |
| 489 | tcg_out_arith(s, reg, reg, TCG_REG_T1, ARITH_ADD); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 490 | } |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 491 | } |
| 492 | } |
| 493 | |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 494 | static void tcg_out_div32(TCGContext *s, int rd, int rs1, |
| 495 | int val2, int val2const, int uns) |
| 496 | { |
| 497 | /* Load Y with the sign/zero extension of RS1 to 64-bits. */ |
| 498 | if (uns) { |
| 499 | tcg_out_sety(s, TCG_REG_G0); |
| 500 | } else { |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 501 | tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA); |
| 502 | tcg_out_sety(s, TCG_REG_T1); |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | tcg_out_arithc(s, rd, rs1, val2, val2const, |
| 506 | uns ? ARITH_UDIV : ARITH_SDIV); |
| 507 | } |
| 508 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 509 | static inline void tcg_out_nop(TCGContext *s) |
| 510 | { |
blueswir1 | 26cc915 | 2008-05-24 18:06:35 +0000 | [diff] [blame] | 511 | tcg_out_sethi(s, TCG_REG_G0, 0); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 512 | } |
| 513 | |
Richard Henderson | 0aed257 | 2012-09-24 14:21:40 -0700 | [diff] [blame] | 514 | static const uint8_t tcg_cond_to_bcond[] = { |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 515 | [TCG_COND_EQ] = COND_E, |
| 516 | [TCG_COND_NE] = COND_NE, |
| 517 | [TCG_COND_LT] = COND_L, |
| 518 | [TCG_COND_GE] = COND_GE, |
| 519 | [TCG_COND_LE] = COND_LE, |
| 520 | [TCG_COND_GT] = COND_G, |
| 521 | [TCG_COND_LTU] = COND_CS, |
| 522 | [TCG_COND_GEU] = COND_CC, |
| 523 | [TCG_COND_LEU] = COND_LEU, |
| 524 | [TCG_COND_GTU] = COND_GU, |
| 525 | }; |
| 526 | |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 527 | static const uint8_t tcg_cond_to_rcond[] = { |
| 528 | [TCG_COND_EQ] = RCOND_Z, |
| 529 | [TCG_COND_NE] = RCOND_NZ, |
| 530 | [TCG_COND_LT] = RCOND_LZ, |
| 531 | [TCG_COND_GT] = RCOND_GZ, |
| 532 | [TCG_COND_LE] = RCOND_LEZ, |
| 533 | [TCG_COND_GE] = RCOND_GEZ |
| 534 | }; |
| 535 | |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 536 | static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19) |
| 537 | { |
| 538 | tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19); |
| 539 | } |
| 540 | |
| 541 | static void tcg_out_bpcc(TCGContext *s, int scond, int flags, int label) |
| 542 | { |
| 543 | TCGLabel *l = &s->labels[label]; |
| 544 | int off19; |
| 545 | |
| 546 | if (l->has_value) { |
| 547 | off19 = INSN_OFF19(l->u.value - (unsigned long)s->code_ptr); |
| 548 | } else { |
| 549 | /* Make sure to preserve destinations during retranslation. */ |
| 550 | off19 = *(uint32_t *)s->code_ptr & INSN_OFF19(-1); |
| 551 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label, 0); |
| 552 | } |
| 553 | tcg_out_bpcc0(s, scond, flags, off19); |
| 554 | } |
| 555 | |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 556 | static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const) |
| 557 | { |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 558 | tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 559 | } |
| 560 | |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 561 | static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGArg arg1, |
| 562 | TCGArg arg2, int const_arg2, int label) |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 563 | { |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 564 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 565 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, label); |
blueswir1 | cf7c2ca | 2008-05-15 19:44:09 +0000 | [diff] [blame] | 566 | tcg_out_nop(s); |
| 567 | } |
| 568 | |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 569 | static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret, |
| 570 | TCGArg v1, int v1const) |
| 571 | { |
| 572 | tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) |
| 573 | | INSN_RS1(tcg_cond_to_bcond[cond]) |
| 574 | | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); |
| 575 | } |
| 576 | |
| 577 | static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, |
| 578 | TCGArg c1, TCGArg c2, int c2const, |
| 579 | TCGArg v1, int v1const) |
| 580 | { |
| 581 | tcg_out_cmp(s, c1, c2, c2const); |
| 582 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); |
| 583 | } |
| 584 | |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 585 | #if TCG_TARGET_REG_BITS == 64 |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 586 | static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1, |
| 587 | TCGArg arg2, int const_arg2, int label) |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 588 | { |
Richard Henderson | ab1339b | 2012-10-10 09:02:46 -0700 | [diff] [blame] | 589 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. */ |
| 590 | if (arg2 == 0 && !is_unsigned_cond(cond)) { |
| 591 | TCGLabel *l = &s->labels[label]; |
| 592 | int off16; |
| 593 | |
| 594 | if (l->has_value) { |
| 595 | off16 = INSN_OFF16(l->u.value - (unsigned long)s->code_ptr); |
| 596 | } else { |
| 597 | /* Make sure to preserve destinations during retranslation. */ |
| 598 | off16 = *(uint32_t *)s->code_ptr & INSN_OFF16(-1); |
| 599 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, label, 0); |
| 600 | } |
| 601 | tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1) |
| 602 | | INSN_COND(tcg_cond_to_rcond[cond]) | off16); |
| 603 | } else { |
| 604 | tcg_out_cmp(s, arg1, arg2, const_arg2); |
| 605 | tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, label); |
| 606 | } |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 607 | tcg_out_nop(s); |
| 608 | } |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 609 | |
Richard Henderson | 203342d | 2012-10-10 09:02:47 -0700 | [diff] [blame] | 610 | static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGArg ret, TCGArg c1, |
| 611 | TCGArg v1, int v1const) |
| 612 | { |
| 613 | tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1) |
| 614 | | (tcg_cond_to_rcond[cond] << 10) |
| 615 | | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1))); |
| 616 | } |
| 617 | |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 618 | static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, |
| 619 | TCGArg c1, TCGArg c2, int c2const, |
| 620 | TCGArg v1, int v1const) |
| 621 | { |
Richard Henderson | 203342d | 2012-10-10 09:02:47 -0700 | [diff] [blame] | 622 | /* For 64-bit signed comparisons vs zero, we can avoid the compare. |
| 623 | Note that the immediate range is one bit smaller, so we must check |
| 624 | for that as well. */ |
| 625 | if (c2 == 0 && !is_unsigned_cond(cond) |
| 626 | && (!v1const || check_fit_tl(v1, 10))) { |
| 627 | tcg_out_movr(s, cond, ret, c1, v1, v1const); |
| 628 | } else { |
| 629 | tcg_out_cmp(s, c1, c2, c2const); |
| 630 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); |
| 631 | } |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 632 | } |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 633 | #else |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 634 | static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond, |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 635 | TCGArg al, TCGArg ah, |
| 636 | TCGArg bl, int blconst, |
| 637 | TCGArg bh, int bhconst, int label_dest) |
| 638 | { |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 639 | int scond, label_next = gen_new_label(); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 640 | |
| 641 | tcg_out_cmp(s, ah, bh, bhconst); |
| 642 | |
| 643 | /* Note that we fill one of the delay slots with the second compare. */ |
| 644 | switch (cond) { |
| 645 | case TCG_COND_EQ: |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 646 | tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 647 | tcg_out_cmp(s, al, bl, blconst); |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 648 | tcg_out_bpcc(s, COND_E, BPCC_ICC | BPCC_PT, label_dest); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 649 | break; |
| 650 | |
| 651 | case TCG_COND_NE: |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 652 | tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 653 | tcg_out_cmp(s, al, bl, blconst); |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 654 | tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_dest); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 655 | break; |
| 656 | |
| 657 | default: |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 658 | scond = tcg_cond_to_bcond[tcg_high_cond(cond)]; |
| 659 | tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 660 | tcg_out_nop(s); |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 661 | tcg_out_bpcc(s, COND_NE, BPCC_ICC | BPCC_PT, label_next); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 662 | tcg_out_cmp(s, al, bl, blconst); |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 663 | scond = tcg_cond_to_bcond[tcg_unsigned_cond(cond)]; |
| 664 | tcg_out_bpcc(s, scond, BPCC_ICC | BPCC_PT, label_dest); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 665 | break; |
| 666 | } |
| 667 | tcg_out_nop(s); |
| 668 | |
Stefan Weil | 9d6fca7 | 2012-03-10 19:59:04 +0100 | [diff] [blame] | 669 | tcg_out_label(s, label_next, s->code_ptr); |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 670 | } |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 671 | #endif |
| 672 | |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 673 | static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 674 | TCGArg c1, TCGArg c2, int c2const) |
| 675 | { |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 676 | /* For 32-bit comparisons, we can play games with ADDX/SUBX. */ |
| 677 | switch (cond) { |
Richard Henderson | 7d458a7 | 2012-10-10 09:02:40 -0700 | [diff] [blame] | 678 | case TCG_COND_LTU: |
| 679 | case TCG_COND_GEU: |
| 680 | /* The result of the comparison is in the carry bit. */ |
| 681 | break; |
| 682 | |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 683 | case TCG_COND_EQ: |
| 684 | case TCG_COND_NE: |
Richard Henderson | 7d458a7 | 2012-10-10 09:02:40 -0700 | [diff] [blame] | 685 | /* For equality, we can transform to inequality vs zero. */ |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 686 | if (c2 != 0) { |
| 687 | tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR); |
| 688 | } |
| 689 | c1 = TCG_REG_G0, c2 = ret, c2const = 0; |
Richard Henderson | 7d458a7 | 2012-10-10 09:02:40 -0700 | [diff] [blame] | 690 | cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 691 | break; |
| 692 | |
| 693 | case TCG_COND_GTU: |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 694 | case TCG_COND_LEU: |
Richard Henderson | 7d458a7 | 2012-10-10 09:02:40 -0700 | [diff] [blame] | 695 | /* If we don't need to load a constant into a register, we can |
| 696 | swap the operands on GTU/LEU. There's no benefit to loading |
| 697 | the constant into a temporary register. */ |
| 698 | if (!c2const || c2 == 0) { |
| 699 | TCGArg t = c1; |
| 700 | c1 = c2; |
| 701 | c2 = t; |
| 702 | c2const = 0; |
| 703 | cond = tcg_swap_cond(cond); |
| 704 | break; |
| 705 | } |
| 706 | /* FALLTHRU */ |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 707 | |
| 708 | default: |
| 709 | tcg_out_cmp(s, c1, c2, c2const); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 710 | tcg_out_movi_imm13(s, ret, 0); |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 711 | tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 712 | return; |
| 713 | } |
| 714 | |
| 715 | tcg_out_cmp(s, c1, c2, c2const); |
| 716 | if (cond == TCG_COND_LTU) { |
| 717 | tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX); |
| 718 | } else { |
| 719 | tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | #if TCG_TARGET_REG_BITS == 64 |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 724 | static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 725 | TCGArg c1, TCGArg c2, int c2const) |
| 726 | { |
Richard Henderson | 203342d | 2012-10-10 09:02:47 -0700 | [diff] [blame] | 727 | /* For 64-bit signed comparisons vs zero, we can avoid the compare |
| 728 | if the input does not overlap the output. */ |
| 729 | if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { |
| 730 | tcg_out_movi_imm13(s, ret, 0); |
| 731 | tcg_out_movr(s, cond, ret, c1, 1, 1); |
| 732 | } else { |
| 733 | tcg_out_cmp(s, c1, c2, c2const); |
| 734 | tcg_out_movi_imm13(s, ret, 0); |
| 735 | tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); |
| 736 | } |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 737 | } |
| 738 | #else |
Richard Henderson | 8a56e84 | 2010-03-19 11:26:05 -0700 | [diff] [blame] | 739 | static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret, |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 740 | TCGArg al, TCGArg ah, |
| 741 | TCGArg bl, int blconst, |
| 742 | TCGArg bh, int bhconst) |
| 743 | { |
Richard Henderson | dda73c7 | 2012-10-10 09:02:38 -0700 | [diff] [blame] | 744 | int tmp = TCG_REG_T1; |
| 745 | |
| 746 | /* Note that the low parts are fully consumed before tmp is set. */ |
| 747 | if (ret != ah && (bhconst || ret != bh)) { |
| 748 | tmp = ret; |
| 749 | } |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 750 | |
| 751 | switch (cond) { |
| 752 | case TCG_COND_EQ: |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 753 | case TCG_COND_NE: |
Richard Henderson | fd84ea2 | 2012-10-10 09:02:43 -0700 | [diff] [blame] | 754 | if (bl == 0 && bh == 0) { |
| 755 | if (cond == TCG_COND_EQ) { |
| 756 | tcg_out_arith(s, TCG_REG_G0, al, ah, ARITH_ORCC); |
| 757 | tcg_out_movi(s, TCG_TYPE_I32, ret, 1); |
| 758 | } else { |
| 759 | tcg_out_arith(s, ret, al, ah, ARITH_ORCC); |
| 760 | } |
| 761 | } else { |
| 762 | tcg_out_setcond_i32(s, cond, tmp, al, bl, blconst); |
| 763 | tcg_out_cmp(s, ah, bh, bhconst); |
| 764 | tcg_out_mov(s, TCG_TYPE_I32, ret, tmp); |
| 765 | } |
Richard Henderson | dda73c7 | 2012-10-10 09:02:38 -0700 | [diff] [blame] | 766 | tcg_out_movcc(s, TCG_COND_NE, MOVCC_ICC, ret, cond == TCG_COND_NE, 1); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 767 | break; |
| 768 | |
| 769 | default: |
Richard Henderson | dda73c7 | 2012-10-10 09:02:38 -0700 | [diff] [blame] | 770 | /* <= : ah < bh | (ah == bh && al <= bl) */ |
| 771 | tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), tmp, al, bl, blconst); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 772 | tcg_out_cmp(s, ah, bh, bhconst); |
Richard Henderson | dda73c7 | 2012-10-10 09:02:38 -0700 | [diff] [blame] | 773 | tcg_out_mov(s, TCG_TYPE_I32, ret, tmp); |
| 774 | tcg_out_movcc(s, TCG_COND_NE, MOVCC_ICC, ret, 0, 1); |
| 775 | tcg_out_movcc(s, tcg_high_cond(cond), MOVCC_ICC, ret, 1, 1); |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 776 | break; |
| 777 | } |
| 778 | } |
Blue Swirl | 07ca08b | 2013-02-27 16:09:38 +0000 | [diff] [blame] | 779 | #endif |
Richard Henderson | 4ec28e2 | 2012-10-10 09:02:41 -0700 | [diff] [blame] | 780 | |
| 781 | static void tcg_out_addsub2(TCGContext *s, TCGArg rl, TCGArg rh, |
| 782 | TCGArg al, TCGArg ah, TCGArg bl, int blconst, |
| 783 | TCGArg bh, int bhconst, int opl, int oph) |
| 784 | { |
| 785 | TCGArg tmp = TCG_REG_T1; |
| 786 | |
| 787 | /* Note that the low parts are fully consumed before tmp is set. */ |
| 788 | if (rl != ah && (bhconst || rl != bh)) { |
| 789 | tmp = rl; |
| 790 | } |
| 791 | |
| 792 | tcg_out_arithc(s, tmp, al, bl, blconst, opl); |
| 793 | tcg_out_arithc(s, rh, ah, bh, bhconst, oph); |
| 794 | tcg_out_mov(s, TCG_TYPE_I32, rl, tmp); |
| 795 | } |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 796 | |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 797 | static inline void tcg_out_calli(TCGContext *s, uintptr_t dest) |
| 798 | { |
| 799 | intptr_t disp = dest - (uintptr_t)s->code_ptr; |
| 800 | |
| 801 | if (disp == (int32_t)disp) { |
| 802 | tcg_out32(s, CALL | (uint32_t)disp >> 2); |
| 803 | } else { |
| 804 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, dest & ~0xfff); |
| 805 | tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, dest & 0xfff, JMPL); |
| 806 | } |
| 807 | } |
| 808 | |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 809 | #ifdef CONFIG_SOFTMMU |
| 810 | static uintptr_t qemu_ld_trampoline[16]; |
| 811 | static uintptr_t qemu_st_trampoline[16]; |
| 812 | |
| 813 | static void build_trampolines(TCGContext *s) |
| 814 | { |
| 815 | static uintptr_t const qemu_ld_helpers[16] = { |
| 816 | [MO_UB] = (uintptr_t)helper_ret_ldub_mmu, |
| 817 | [MO_SB] = (uintptr_t)helper_ret_ldsb_mmu, |
| 818 | [MO_LEUW] = (uintptr_t)helper_le_lduw_mmu, |
| 819 | [MO_LESW] = (uintptr_t)helper_le_ldsw_mmu, |
| 820 | [MO_LEUL] = (uintptr_t)helper_le_ldul_mmu, |
| 821 | [MO_LEQ] = (uintptr_t)helper_le_ldq_mmu, |
| 822 | [MO_BEUW] = (uintptr_t)helper_be_lduw_mmu, |
| 823 | [MO_BESW] = (uintptr_t)helper_be_ldsw_mmu, |
| 824 | [MO_BEUL] = (uintptr_t)helper_be_ldul_mmu, |
| 825 | [MO_BEQ] = (uintptr_t)helper_be_ldq_mmu, |
| 826 | }; |
| 827 | static uintptr_t const qemu_st_helpers[16] = { |
| 828 | [MO_UB] = (uintptr_t)helper_ret_stb_mmu, |
| 829 | [MO_LEUW] = (uintptr_t)helper_le_stw_mmu, |
| 830 | [MO_LEUL] = (uintptr_t)helper_le_stl_mmu, |
| 831 | [MO_LEQ] = (uintptr_t)helper_le_stq_mmu, |
| 832 | [MO_BEUW] = (uintptr_t)helper_be_stw_mmu, |
| 833 | [MO_BEUL] = (uintptr_t)helper_be_stl_mmu, |
| 834 | [MO_BEQ] = (uintptr_t)helper_be_stq_mmu, |
| 835 | }; |
| 836 | |
| 837 | int i; |
| 838 | TCGReg ra; |
| 839 | uintptr_t tramp; |
| 840 | |
| 841 | for (i = 0; i < 16; ++i) { |
| 842 | if (qemu_ld_helpers[i] == 0) { |
| 843 | continue; |
| 844 | } |
| 845 | |
| 846 | /* May as well align the trampoline. */ |
| 847 | tramp = (uintptr_t)s->code_ptr; |
| 848 | while (tramp & 15) { |
| 849 | tcg_out_nop(s); |
| 850 | tramp += 4; |
| 851 | } |
| 852 | qemu_ld_trampoline[i] = tramp; |
| 853 | |
| 854 | /* Find the retaddr argument register. */ |
| 855 | ra = TCG_REG_O3 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS); |
| 856 | |
| 857 | /* Set the retaddr operand. */ |
| 858 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); |
| 859 | /* Set the env operand. */ |
| 860 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); |
| 861 | /* Tail call. */ |
| 862 | tcg_out_calli(s, qemu_ld_helpers[i]); |
| 863 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
| 864 | } |
| 865 | |
| 866 | for (i = 0; i < 16; ++i) { |
| 867 | if (qemu_st_helpers[i] == 0) { |
| 868 | continue; |
| 869 | } |
| 870 | |
| 871 | /* May as well align the trampoline. */ |
| 872 | tramp = (uintptr_t)s->code_ptr; |
| 873 | while (tramp & 15) { |
| 874 | tcg_out_nop(s); |
| 875 | tramp += 4; |
| 876 | } |
| 877 | qemu_st_trampoline[i] = tramp; |
| 878 | |
| 879 | /* Find the retaddr argument. For 32-bit, this may be past the |
| 880 | last argument register, and need passing on the stack. */ |
| 881 | ra = (TCG_REG_O4 |
| 882 | + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) |
| 883 | + (TCG_TARGET_REG_BITS == 32 && (i & MO_SIZE) == MO_64)); |
| 884 | |
| 885 | /* Set the retaddr operand. */ |
| 886 | if (ra >= TCG_REG_O6) { |
| 887 | tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK, |
| 888 | TCG_TARGET_CALL_STACK_OFFSET); |
| 889 | ra = TCG_REG_G1; |
| 890 | } |
| 891 | tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7); |
| 892 | /* Set the env operand. */ |
| 893 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); |
| 894 | /* Tail call. */ |
| 895 | tcg_out_calli(s, qemu_st_helpers[i]); |
| 896 | tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); |
| 897 | } |
| 898 | } |
| 899 | #endif |
| 900 | |
blueswir1 | 7d55170 | 2008-05-14 19:22:05 +0000 | [diff] [blame] | 901 | /* Generate global QEMU prologue and epilogue code */ |
Richard Henderson | e4d58b4 | 2010-06-02 17:26:56 -0700 | [diff] [blame] | 902 | static void tcg_target_qemu_prologue(TCGContext *s) |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 903 | { |
Richard Henderson | 4c3204c | 2012-03-25 21:21:46 +0200 | [diff] [blame] | 904 | int tmp_buf_size, frame_size; |
| 905 | |
| 906 | /* The TCG temp buffer is at the top of the frame, immediately |
| 907 | below the frame pointer. */ |
| 908 | tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long); |
| 909 | tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size, |
| 910 | tmp_buf_size); |
| 911 | |
| 912 | /* TCG_TARGET_CALL_STACK_OFFSET includes the stack bias, but is |
| 913 | otherwise the minimal frame usable by callees. */ |
| 914 | frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS; |
| 915 | frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size; |
| 916 | frame_size += TCG_TARGET_STACK_ALIGN - 1; |
| 917 | frame_size &= -TCG_TARGET_STACK_ALIGN; |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 918 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
Richard Henderson | 4c3204c | 2012-03-25 21:21:46 +0200 | [diff] [blame] | 919 | INSN_IMM13(-frame_size)); |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 920 | |
| 921 | #ifdef CONFIG_USE_GUEST_BASE |
| 922 | if (GUEST_BASE != 0) { |
| 923 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE); |
| 924 | tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); |
| 925 | } |
| 926 | #endif |
| 927 | |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 928 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); |
Richard Henderson | 0c55416 | 2012-03-25 19:52:11 +0200 | [diff] [blame] | 929 | /* delay slot */ |
| 930 | tcg_out_nop(s); |
Richard Henderson | 4c3204c | 2012-03-25 21:21:46 +0200 | [diff] [blame] | 931 | |
| 932 | /* No epilogue required. We issue ret + restore directly in the TB. */ |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 933 | |
| 934 | #ifdef CONFIG_SOFTMMU |
| 935 | build_trampolines(s); |
| 936 | #endif |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 937 | } |
| 938 | |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 939 | #if defined(CONFIG_SOFTMMU) |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 940 | /* Perform the TLB load and compare. |
blueswir1 | bffe143 | 2008-08-17 14:34:27 +0000 | [diff] [blame] | 941 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 942 | Inputs: |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 943 | ADDRLO and ADDRHI contain the possible two parts of the address. |
blueswir1 | 9d0efc8 | 2008-09-13 20:07:53 +0000 | [diff] [blame] | 944 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 945 | MEM_INDEX and S_BITS are the memory context and log2 size of the load. |
blueswir1 | bffe143 | 2008-08-17 14:34:27 +0000 | [diff] [blame] | 946 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 947 | WHICH is the offset into the CPUTLBEntry structure of the slot to read. |
| 948 | This should be offsetof addr_read or addr_write. |
| 949 | |
| 950 | The result of the TLB comparison is in %[ix]cc. The sanitized address |
| 951 | is in the returned register, maybe %o0. The TLB addend is in %o1. */ |
| 952 | |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 953 | static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, |
| 954 | int mem_index, TCGMemOp s_bits, int which) |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 955 | { |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 956 | const TCGReg r0 = TCG_REG_O0; |
| 957 | const TCGReg r1 = TCG_REG_O1; |
| 958 | const TCGReg r2 = TCG_REG_O2; |
| 959 | TCGReg addr = addrlo; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 960 | int tlb_ofs; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 961 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 962 | if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) { |
| 963 | /* Assemble the 64-bit address in R0. */ |
| 964 | tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL); |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 965 | tcg_out_arithi(s, r1, addrhi, 32, SHIFT_SLLX); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 966 | tcg_out_arith(s, r0, r0, r1, ARITH_OR); |
Richard Henderson | d801a8f | 2013-09-06 17:19:12 -0700 | [diff] [blame] | 967 | addr = r0; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 968 | } |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 969 | |
Richard Henderson | d801a8f | 2013-09-06 17:19:12 -0700 | [diff] [blame] | 970 | /* Shift the page number down. */ |
| 971 | tcg_out_arithi(s, r1, addrlo, TARGET_PAGE_BITS, SHIFT_SRL); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 972 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 973 | /* Mask out the page offset, except for the required alignment. */ |
Richard Henderson | d801a8f | 2013-09-06 17:19:12 -0700 | [diff] [blame] | 974 | tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1, |
| 975 | TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 976 | |
Richard Henderson | d801a8f | 2013-09-06 17:19:12 -0700 | [diff] [blame] | 977 | /* Mask the tlb index. */ |
| 978 | tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND); |
| 979 | |
| 980 | /* Mask page, part 2. */ |
| 981 | tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND); |
| 982 | |
| 983 | /* Shift the tlb index into place. */ |
| 984 | tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 985 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 986 | /* Relative to the current ENV. */ |
| 987 | tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 988 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 989 | /* Find a base address that can load both tlb comparator and addend. */ |
| 990 | tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]); |
| 991 | if (!check_fit_tl(tlb_ofs + sizeof(CPUTLBEntry), 13)) { |
Richard Henderson | d801a8f | 2013-09-06 17:19:12 -0700 | [diff] [blame] | 992 | tcg_out_addi(s, r1, tlb_ofs & ~0x3ff); |
| 993 | tlb_ofs &= 0x3ff; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 994 | } |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 995 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 996 | /* Load the tlb comparator and the addend. */ |
| 997 | tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which); |
| 998 | tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend)); |
blueswir1 | 53c3748 | 2008-08-15 18:14:44 +0000 | [diff] [blame] | 999 | |
blueswir1 | 56fc64d | 2008-08-16 19:54:01 +0000 | [diff] [blame] | 1000 | /* subcc arg0, arg2, %g0 */ |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1001 | tcg_out_cmp(s, r0, r2, 0); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1002 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1003 | /* If the guest address must be zero-extended, do so now. */ |
| 1004 | if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { |
| 1005 | tcg_out_arithi(s, r0, addrlo, 0, SHIFT_SRL); |
| 1006 | return r0; |
| 1007 | } |
| 1008 | return addrlo; |
| 1009 | } |
| 1010 | #endif /* CONFIG_SOFTMMU */ |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1011 | |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1012 | static const int qemu_ld_opc[16] = { |
| 1013 | [MO_UB] = LDUB, |
| 1014 | [MO_SB] = LDSB, |
| 1015 | |
| 1016 | [MO_BEUW] = LDUH, |
| 1017 | [MO_BESW] = LDSH, |
| 1018 | [MO_BEUL] = LDUW, |
| 1019 | [MO_BESL] = LDSW, |
| 1020 | [MO_BEQ] = LDX, |
| 1021 | |
| 1022 | [MO_LEUW] = LDUH_LE, |
| 1023 | [MO_LESW] = LDSH_LE, |
| 1024 | [MO_LEUL] = LDUW_LE, |
| 1025 | [MO_LESL] = LDSW_LE, |
| 1026 | [MO_LEQ] = LDX_LE, |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1027 | }; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1028 | |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1029 | static const int qemu_st_opc[16] = { |
| 1030 | [MO_UB] = STB, |
| 1031 | |
| 1032 | [MO_BEUW] = STH, |
| 1033 | [MO_BEUL] = STW, |
| 1034 | [MO_BEQ] = STX, |
| 1035 | |
| 1036 | [MO_LEUW] = STH_LE, |
| 1037 | [MO_LEUL] = STW_LE, |
| 1038 | [MO_LEQ] = STX_LE, |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1039 | }; |
blueswir1 | bffe143 | 2008-08-17 14:34:27 +0000 | [diff] [blame] | 1040 | |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1041 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1042 | { |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1043 | TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); |
| 1044 | TCGMemOp memop, s_bits; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1045 | #if defined(CONFIG_SOFTMMU) |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1046 | TCGReg addrz, param; |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1047 | uintptr_t func; |
| 1048 | int memi; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1049 | uint32_t *label_ptr[2]; |
| 1050 | #endif |
| 1051 | |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 1052 | datalo = *args++; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1053 | datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); |
| 1054 | addrlo = *args++; |
| 1055 | addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); |
| 1056 | memop = *args++; |
| 1057 | s_bits = memop & MO_SIZE; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1058 | |
| 1059 | #if defined(CONFIG_SOFTMMU) |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 1060 | memi = *args++; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1061 | addrz = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits, |
| 1062 | offsetof(CPUTLBEntry, addr_read)); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1063 | |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1064 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1065 | int reg64; |
| 1066 | |
| 1067 | /* bne,pn %[xi]cc, label0 */ |
| 1068 | label_ptr[0] = (uint32_t *)s->code_ptr; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 1069 | tcg_out_bpcc0(s, COND_NE, BPCC_PN |
| 1070 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); |
Richard Henderson | e7bc900 | 2013-09-06 14:20:00 -0700 | [diff] [blame] | 1071 | tcg_out_nop(s); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1072 | |
| 1073 | /* TLB Hit. */ |
| 1074 | /* Load all 64-bits into an O/G register. */ |
| 1075 | reg64 = (datalo < 16 ? datalo : TCG_REG_O0); |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1076 | tcg_out_ldst_rr(s, reg64, addrz, TCG_REG_O1, qemu_ld_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1077 | |
| 1078 | /* Move the two 32-bit pieces into the destination registers. */ |
| 1079 | tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX); |
| 1080 | if (reg64 != datalo) { |
| 1081 | tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64); |
| 1082 | } |
| 1083 | |
| 1084 | /* b,a,pt label1 */ |
| 1085 | label_ptr[1] = (uint32_t *)s->code_ptr; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 1086 | tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1087 | } else { |
| 1088 | /* The fast path is exactly one insn. Thus we can perform the |
| 1089 | entire TLB Hit in the (annulled) delay slot of the branch |
| 1090 | over the TLB Miss case. */ |
| 1091 | |
| 1092 | /* beq,a,pt %[xi]cc, label0 */ |
| 1093 | label_ptr[0] = NULL; |
| 1094 | label_ptr[1] = (uint32_t *)s->code_ptr; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 1095 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
| 1096 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1097 | /* delay slot */ |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1098 | tcg_out_ldst_rr(s, datalo, addrz, TCG_REG_O1, qemu_ld_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | /* TLB Miss. */ |
| 1102 | |
| 1103 | if (label_ptr[0]) { |
| 1104 | *label_ptr[0] |= INSN_OFF19((unsigned long)s->code_ptr - |
| 1105 | (unsigned long)label_ptr[0]); |
| 1106 | } |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1107 | |
| 1108 | param = TCG_REG_O1; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1109 | if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1110 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrhi); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1111 | } |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1112 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrlo); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1113 | |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1114 | /* We use the helpers to extend SB and SW data, leaving the case |
| 1115 | of SL needing explicit extending below. */ |
| 1116 | if ((memop & ~MO_BSWAP) == MO_SL) { |
| 1117 | func = qemu_ld_trampoline[memop & ~MO_SIGN]; |
| 1118 | } else { |
| 1119 | func = qemu_ld_trampoline[memop]; |
| 1120 | } |
| 1121 | assert(func != 0); |
| 1122 | tcg_out_calli(s, func); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1123 | /* delay slot */ |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1124 | tcg_out_movi(s, TCG_TYPE_I32, param, memi); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1125 | |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1126 | switch (memop & ~MO_BSWAP) { |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1127 | case MO_SL: |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1128 | tcg_out_arithi(s, datalo, TCG_REG_O0, 0, SHIFT_SRA); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1129 | break; |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1130 | case MO_Q: |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1131 | if (TCG_TARGET_REG_BITS == 32) { |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1132 | tcg_out_mov(s, TCG_TYPE_REG, datahi, TCG_REG_O0); |
| 1133 | tcg_out_mov(s, TCG_TYPE_REG, datalo, TCG_REG_O1); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1134 | break; |
| 1135 | } |
| 1136 | /* FALLTHRU */ |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1137 | default: |
| 1138 | /* mov */ |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1139 | tcg_out_mov(s, TCG_TYPE_REG, datalo, TCG_REG_O0); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1140 | break; |
| 1141 | } |
| 1142 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1143 | *label_ptr[1] |= INSN_OFF19((unsigned long)s->code_ptr - |
| 1144 | (unsigned long)label_ptr[1]); |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 1145 | #else |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1146 | if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1147 | tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL); |
| 1148 | addrlo = TCG_REG_T1; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1149 | } |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1150 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1151 | int reg64 = (datalo < 16 ? datalo : TCG_REG_O0); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1152 | |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1153 | tcg_out_ldst_rr(s, reg64, addrlo, |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 1154 | (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1155 | qemu_ld_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1156 | |
| 1157 | tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX); |
| 1158 | if (reg64 != datalo) { |
| 1159 | tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64); |
| 1160 | } |
| 1161 | } else { |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1162 | tcg_out_ldst_rr(s, datalo, addrlo, |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 1163 | (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1164 | qemu_ld_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1165 | } |
| 1166 | #endif /* CONFIG_SOFTMMU */ |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1167 | } |
| 1168 | |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1169 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1170 | { |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1171 | TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); |
| 1172 | TCGMemOp memop, s_bits; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1173 | #if defined(CONFIG_SOFTMMU) |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1174 | TCGReg addrz, datafull, param; |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1175 | uintptr_t func; |
| 1176 | int memi; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1177 | uint32_t *label_ptr; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1178 | #endif |
| 1179 | |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 1180 | datalo = *args++; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1181 | datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0); |
| 1182 | addrlo = *args++; |
| 1183 | addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); |
| 1184 | memop = *args++; |
| 1185 | s_bits = memop & MO_SIZE; |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1186 | |
| 1187 | #if defined(CONFIG_SOFTMMU) |
Richard Henderson | a8b12c1 | 2013-09-06 15:01:14 -0700 | [diff] [blame] | 1188 | memi = *args++; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1189 | addrz = tcg_out_tlb_load(s, addrlo, addrhi, memi, s_bits, |
| 1190 | offsetof(CPUTLBEntry, addr_write)); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1191 | |
Richard Henderson | a7a4984 | 2012-10-10 09:02:39 -0700 | [diff] [blame] | 1192 | datafull = datalo; |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1193 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1194 | /* Reconstruct the full 64-bit value. */ |
| 1195 | tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1196 | tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1197 | tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR); |
Richard Henderson | a7a4984 | 2012-10-10 09:02:39 -0700 | [diff] [blame] | 1198 | datafull = TCG_REG_O2; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | /* The fast path is exactly one insn. Thus we can perform the entire |
| 1202 | TLB Hit in the (annulled) delay slot of the branch over TLB Miss. */ |
| 1203 | /* beq,a,pt %[xi]cc, label0 */ |
| 1204 | label_ptr = (uint32_t *)s->code_ptr; |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 1205 | tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT |
| 1206 | | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1207 | /* delay slot */ |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1208 | tcg_out_ldst_rr(s, datafull, addrz, TCG_REG_O1, qemu_st_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1209 | |
| 1210 | /* TLB Miss. */ |
| 1211 | |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1212 | param = TCG_REG_O1; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1213 | if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1214 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrhi); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1215 | } |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1216 | tcg_out_mov(s, TCG_TYPE_REG, param++, addrlo); |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1217 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1218 | tcg_out_mov(s, TCG_TYPE_REG, param++, datahi); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1219 | } |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1220 | tcg_out_mov(s, TCG_TYPE_REG, param++, datalo); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1221 | |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1222 | func = qemu_st_trampoline[memop]; |
| 1223 | assert(func != 0); |
| 1224 | tcg_out_calli(s, func); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1225 | /* delay slot */ |
Richard Henderson | 7ea5d72 | 2014-03-05 09:42:08 -0800 | [diff] [blame] | 1226 | tcg_out_movi(s, TCG_TYPE_REG, param, memi); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1227 | |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1228 | *label_ptr |= INSN_OFF19((unsigned long)s->code_ptr - |
| 1229 | (unsigned long)label_ptr); |
| 1230 | #else |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1231 | if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 32) { |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1232 | tcg_out_arithi(s, TCG_REG_T1, addrlo, 0, SHIFT_SRL); |
| 1233 | addrlo = TCG_REG_T1; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1234 | } |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1235 | if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1236 | tcg_out_arithi(s, TCG_REG_T1, datalo, 0, SHIFT_SRL); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1237 | tcg_out_arithi(s, TCG_REG_O2, datahi, 32, SHIFT_SLLX); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1238 | tcg_out_arith(s, TCG_REG_O2, TCG_REG_T1, TCG_REG_O2, ARITH_OR); |
| 1239 | datalo = TCG_REG_O2; |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1240 | } |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1241 | tcg_out_ldst_rr(s, datalo, addrlo, |
Richard Henderson | c6f7e4f | 2012-03-24 22:11:25 +0100 | [diff] [blame] | 1242 | (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), |
Richard Henderson | eef0d9e | 2013-09-03 20:12:01 -0700 | [diff] [blame] | 1243 | qemu_st_opc[memop]); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1244 | #endif /* CONFIG_SOFTMMU */ |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1245 | } |
| 1246 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 1247 | static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1248 | const int *const_args) |
| 1249 | { |
| 1250 | int c; |
| 1251 | |
| 1252 | switch (opc) { |
| 1253 | case INDEX_op_exit_tb: |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 1254 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]); |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 1255 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, JMPL); |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 1256 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
| 1257 | INSN_RS2(TCG_REG_G0)); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1258 | break; |
| 1259 | case INDEX_op_goto_tb: |
| 1260 | if (s->tb_jmp_offset) { |
| 1261 | /* direct jump method */ |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1262 | uint32_t old_insn = *(uint32_t *)s->code_ptr; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1263 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1264 | /* Make sure to preserve links during retranslation. */ |
| 1265 | tcg_out32(s, CALL | (old_insn & ~INSN_OP(-1))); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1266 | } else { |
| 1267 | /* indirect jump method */ |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 1268 | tcg_out_ld_ptr(s, TCG_REG_T1, (uintptr_t)(s->tb_next + args[0])); |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 1269 | tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1270 | } |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1271 | tcg_out_nop(s); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1272 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; |
| 1273 | break; |
| 1274 | case INDEX_op_call: |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1275 | if (const_args[0]) { |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 1276 | tcg_out_calli(s, args[0]); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1277 | } else { |
Richard Henderson | aad2f06 | 2013-08-20 18:25:38 -0700 | [diff] [blame] | 1278 | tcg_out_arithi(s, TCG_REG_O7, args[0], 0, JMPL); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1279 | } |
Richard Henderson | 4c3204c | 2012-03-25 21:21:46 +0200 | [diff] [blame] | 1280 | /* delay slot */ |
| 1281 | tcg_out_nop(s); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1282 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1283 | case INDEX_op_br: |
Richard Henderson | a115f3e | 2012-10-10 09:02:44 -0700 | [diff] [blame] | 1284 | tcg_out_bpcc(s, COND_A, BPCC_PT, args[0]); |
blueswir1 | f5ef6aa | 2008-05-16 20:15:58 +0000 | [diff] [blame] | 1285 | tcg_out_nop(s); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1286 | break; |
| 1287 | case INDEX_op_movi_i32: |
| 1288 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
| 1289 | break; |
| 1290 | |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1291 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1292 | #define OP_32_64(x) \ |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1293 | glue(glue(case INDEX_op_, x), _i32): \ |
| 1294 | glue(glue(case INDEX_op_, x), _i64) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1295 | #else |
| 1296 | #define OP_32_64(x) \ |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1297 | glue(glue(case INDEX_op_, x), _i32) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1298 | #endif |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1299 | OP_32_64(ld8u): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1300 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
| 1301 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1302 | OP_32_64(ld8s): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1303 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
| 1304 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1305 | OP_32_64(ld16u): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1306 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
| 1307 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1308 | OP_32_64(ld16s): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1309 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
| 1310 | break; |
| 1311 | case INDEX_op_ld_i32: |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1312 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1313 | case INDEX_op_ld32u_i64: |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1314 | #endif |
| 1315 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
| 1316 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1317 | OP_32_64(st8): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1318 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
| 1319 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1320 | OP_32_64(st16): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1321 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
| 1322 | break; |
| 1323 | case INDEX_op_st_i32: |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1324 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1325 | case INDEX_op_st32_i64: |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1326 | #endif |
| 1327 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
| 1328 | break; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1329 | OP_32_64(add): |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1330 | c = ARITH_ADD; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1331 | goto gen_arith; |
| 1332 | OP_32_64(sub): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1333 | c = ARITH_SUB; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1334 | goto gen_arith; |
| 1335 | OP_32_64(and): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1336 | c = ARITH_AND; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1337 | goto gen_arith; |
Richard Henderson | dc69960 | 2010-02-16 14:21:19 -0800 | [diff] [blame] | 1338 | OP_32_64(andc): |
| 1339 | c = ARITH_ANDN; |
| 1340 | goto gen_arith; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1341 | OP_32_64(or): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1342 | c = ARITH_OR; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1343 | goto gen_arith; |
Richard Henderson | 18c8f7a | 2010-02-16 14:23:39 -0800 | [diff] [blame] | 1344 | OP_32_64(orc): |
| 1345 | c = ARITH_ORN; |
| 1346 | goto gen_arith; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1347 | OP_32_64(xor): |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1348 | c = ARITH_XOR; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1349 | goto gen_arith; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1350 | case INDEX_op_shl_i32: |
| 1351 | c = SHIFT_SLL; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1352 | do_shift32: |
| 1353 | /* Limit immediate shift count lest we create an illegal insn. */ |
| 1354 | tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); |
| 1355 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1356 | case INDEX_op_shr_i32: |
| 1357 | c = SHIFT_SRL; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1358 | goto do_shift32; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1359 | case INDEX_op_sar_i32: |
| 1360 | c = SHIFT_SRA; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1361 | goto do_shift32; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1362 | case INDEX_op_mul_i32: |
| 1363 | c = ARITH_UMUL; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1364 | goto gen_arith; |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 1365 | |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1366 | OP_32_64(neg): |
| 1367 | c = ARITH_SUB; |
| 1368 | goto gen_arith1; |
Richard Henderson | be6551b | 2010-02-16 14:02:04 -0800 | [diff] [blame] | 1369 | OP_32_64(not): |
| 1370 | c = ARITH_ORN; |
| 1371 | goto gen_arith1; |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1372 | |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 1373 | case INDEX_op_div_i32: |
| 1374 | tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0); |
| 1375 | break; |
| 1376 | case INDEX_op_divu_i32: |
| 1377 | tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1); |
| 1378 | break; |
| 1379 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1380 | case INDEX_op_brcond_i32: |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 1381 | tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], |
| 1382 | args[3]); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1383 | break; |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 1384 | case INDEX_op_setcond_i32: |
| 1385 | tcg_out_setcond_i32(s, args[3], args[0], args[1], |
| 1386 | args[2], const_args[2]); |
| 1387 | break; |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 1388 | case INDEX_op_movcond_i32: |
| 1389 | tcg_out_movcond_i32(s, args[5], args[0], args[1], |
| 1390 | args[2], const_args[2], args[3], const_args[3]); |
| 1391 | break; |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 1392 | |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 1393 | #if TCG_TARGET_REG_BITS == 32 |
| 1394 | case INDEX_op_brcond2_i32: |
| 1395 | tcg_out_brcond2_i32(s, args[4], args[0], args[1], |
| 1396 | args[2], const_args[2], |
| 1397 | args[3], const_args[3], args[5]); |
| 1398 | break; |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 1399 | case INDEX_op_setcond2_i32: |
| 1400 | tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2], |
| 1401 | args[3], const_args[3], |
| 1402 | args[4], const_args[4]); |
| 1403 | break; |
Richard Henderson | 803d805 | 2013-02-19 23:51:51 -0800 | [diff] [blame] | 1404 | #endif |
| 1405 | |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 1406 | case INDEX_op_add2_i32: |
Richard Henderson | 4ec28e2 | 2012-10-10 09:02:41 -0700 | [diff] [blame] | 1407 | tcg_out_addsub2(s, args[0], args[1], args[2], args[3], |
| 1408 | args[4], const_args[4], args[5], const_args[5], |
| 1409 | ARITH_ADDCC, ARITH_ADDX); |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 1410 | break; |
| 1411 | case INDEX_op_sub2_i32: |
Richard Henderson | 4ec28e2 | 2012-10-10 09:02:41 -0700 | [diff] [blame] | 1412 | tcg_out_addsub2(s, args[0], args[1], args[2], args[3], |
| 1413 | args[4], const_args[4], args[5], const_args[5], |
| 1414 | ARITH_SUBCC, ARITH_SUBX); |
Richard Henderson | 7a3766f | 2010-01-12 19:59:31 +0000 | [diff] [blame] | 1415 | break; |
| 1416 | case INDEX_op_mulu2_i32: |
| 1417 | tcg_out_arithc(s, args[0], args[2], args[3], const_args[3], |
| 1418 | ARITH_UMUL); |
| 1419 | tcg_out_rdy(s, args[1]); |
| 1420 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1421 | |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1422 | case INDEX_op_qemu_ld_i32: |
| 1423 | tcg_out_qemu_ld(s, args, 0); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1424 | break; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1425 | case INDEX_op_qemu_ld_i64: |
| 1426 | tcg_out_qemu_ld(s, args, 1); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1427 | break; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1428 | case INDEX_op_qemu_st_i32: |
| 1429 | tcg_out_qemu_st(s, args, 0); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1430 | break; |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1431 | case INDEX_op_qemu_st_i64: |
| 1432 | tcg_out_qemu_st(s, args, 1); |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1433 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1434 | |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1435 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1436 | case INDEX_op_movi_i64: |
| 1437 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 1438 | break; |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1439 | case INDEX_op_ld32s_i64: |
| 1440 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
| 1441 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1442 | case INDEX_op_ld_i64: |
| 1443 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
| 1444 | break; |
| 1445 | case INDEX_op_st_i64: |
| 1446 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
| 1447 | break; |
| 1448 | case INDEX_op_shl_i64: |
| 1449 | c = SHIFT_SLLX; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1450 | do_shift64: |
| 1451 | /* Limit immediate shift count lest we create an illegal insn. */ |
| 1452 | tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); |
| 1453 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1454 | case INDEX_op_shr_i64: |
| 1455 | c = SHIFT_SRLX; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1456 | goto do_shift64; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1457 | case INDEX_op_sar_i64: |
| 1458 | c = SHIFT_SRAX; |
Richard Henderson | 1fd9594 | 2012-03-25 21:36:28 +0200 | [diff] [blame] | 1459 | goto do_shift64; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1460 | case INDEX_op_mul_i64: |
| 1461 | c = ARITH_MULX; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1462 | goto gen_arith; |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 1463 | case INDEX_op_div_i64: |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1464 | c = ARITH_SDIVX; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1465 | goto gen_arith; |
Richard Henderson | 583d121 | 2010-01-12 19:59:33 +0000 | [diff] [blame] | 1466 | case INDEX_op_divu_i64: |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1467 | c = ARITH_UDIVX; |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1468 | goto gen_arith; |
Richard Henderson | cc6dfec | 2010-01-12 19:59:34 +0000 | [diff] [blame] | 1469 | case INDEX_op_ext32s_i64: |
Richard Henderson | 1d0a606 | 2014-03-04 15:24:04 -0800 | [diff] [blame] | 1470 | tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA); |
Richard Henderson | cc6dfec | 2010-01-12 19:59:34 +0000 | [diff] [blame] | 1471 | break; |
| 1472 | case INDEX_op_ext32u_i64: |
Richard Henderson | 1d0a606 | 2014-03-04 15:24:04 -0800 | [diff] [blame] | 1473 | tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL); |
Richard Henderson | cc6dfec | 2010-01-12 19:59:34 +0000 | [diff] [blame] | 1474 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1475 | |
| 1476 | case INDEX_op_brcond_i64: |
blueswir1 | 1da92db | 2009-04-04 19:10:26 +0000 | [diff] [blame] | 1477 | tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1], |
| 1478 | args[3]); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1479 | break; |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 1480 | case INDEX_op_setcond_i64: |
| 1481 | tcg_out_setcond_i64(s, args[3], args[0], args[1], |
| 1482 | args[2], const_args[2]); |
| 1483 | break; |
Richard Henderson | ded37f0 | 2012-10-10 09:02:37 -0700 | [diff] [blame] | 1484 | case INDEX_op_movcond_i64: |
| 1485 | tcg_out_movcond_i64(s, args[5], args[0], args[1], |
| 1486 | args[2], const_args[2], args[3], const_args[3]); |
| 1487 | break; |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1488 | #endif |
Richard Henderson | ba22519 | 2010-01-12 19:59:29 +0000 | [diff] [blame] | 1489 | gen_arith: |
| 1490 | tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c); |
blueswir1 | 53cd927 | 2008-03-07 18:21:39 +0000 | [diff] [blame] | 1491 | break; |
| 1492 | |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1493 | gen_arith1: |
| 1494 | tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c); |
| 1495 | break; |
| 1496 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1497 | default: |
| 1498 | fprintf(stderr, "unknown opcode 0x%x\n", opc); |
| 1499 | tcg_abort(); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | static const TCGTargetOpDef sparc_op_defs[] = { |
| 1504 | { INDEX_op_exit_tb, { } }, |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 1505 | { INDEX_op_goto_tb, { } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1506 | { INDEX_op_call, { "ri" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1507 | { INDEX_op_br, { } }, |
| 1508 | |
| 1509 | { INDEX_op_mov_i32, { "r", "r" } }, |
| 1510 | { INDEX_op_movi_i32, { "r" } }, |
| 1511 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
| 1512 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
| 1513 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
| 1514 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
| 1515 | { INDEX_op_ld_i32, { "r", "r" } }, |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1516 | { INDEX_op_st8_i32, { "rZ", "r" } }, |
| 1517 | { INDEX_op_st16_i32, { "rZ", "r" } }, |
| 1518 | { INDEX_op_st_i32, { "rZ", "r" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1519 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1520 | { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, |
| 1521 | { INDEX_op_mul_i32, { "r", "rZ", "rJ" } }, |
| 1522 | { INDEX_op_div_i32, { "r", "rZ", "rJ" } }, |
| 1523 | { INDEX_op_divu_i32, { "r", "rZ", "rJ" } }, |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1524 | { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, |
| 1525 | { INDEX_op_and_i32, { "r", "rZ", "rJ" } }, |
| 1526 | { INDEX_op_andc_i32, { "r", "rZ", "rJ" } }, |
| 1527 | { INDEX_op_or_i32, { "r", "rZ", "rJ" } }, |
| 1528 | { INDEX_op_orc_i32, { "r", "rZ", "rJ" } }, |
| 1529 | { INDEX_op_xor_i32, { "r", "rZ", "rJ" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1530 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1531 | { INDEX_op_shl_i32, { "r", "rZ", "rJ" } }, |
| 1532 | { INDEX_op_shr_i32, { "r", "rZ", "rJ" } }, |
| 1533 | { INDEX_op_sar_i32, { "r", "rZ", "rJ" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1534 | |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1535 | { INDEX_op_neg_i32, { "r", "rJ" } }, |
Richard Henderson | be6551b | 2010-02-16 14:02:04 -0800 | [diff] [blame] | 1536 | { INDEX_op_not_i32, { "r", "rJ" } }, |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1537 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1538 | { INDEX_op_brcond_i32, { "rZ", "rJ" } }, |
| 1539 | { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } }, |
| 1540 | { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } }, |
Richard Henderson | dbfe80e | 2010-02-15 21:22:59 -0800 | [diff] [blame] | 1541 | |
Richard Henderson | 56f4927 | 2009-12-19 20:23:19 -0800 | [diff] [blame] | 1542 | #if TCG_TARGET_REG_BITS == 32 |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1543 | { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } }, |
| 1544 | { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rJ", "rJ" } }, |
Richard Henderson | 803d805 | 2013-02-19 23:51:51 -0800 | [diff] [blame] | 1545 | #endif |
| 1546 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1547 | { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, |
| 1548 | { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, |
| 1549 | { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1550 | |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1551 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1552 | { INDEX_op_mov_i64, { "r", "r" } }, |
| 1553 | { INDEX_op_movi_i64, { "r" } }, |
| 1554 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
| 1555 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
| 1556 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
| 1557 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
| 1558 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
| 1559 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
| 1560 | { INDEX_op_ld_i64, { "r", "r" } }, |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1561 | { INDEX_op_st8_i64, { "rZ", "r" } }, |
| 1562 | { INDEX_op_st16_i64, { "rZ", "r" } }, |
| 1563 | { INDEX_op_st32_i64, { "rZ", "r" } }, |
| 1564 | { INDEX_op_st_i64, { "rZ", "r" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1565 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1566 | { INDEX_op_add_i64, { "r", "rZ", "rJ" } }, |
| 1567 | { INDEX_op_mul_i64, { "r", "rZ", "rJ" } }, |
| 1568 | { INDEX_op_div_i64, { "r", "rZ", "rJ" } }, |
| 1569 | { INDEX_op_divu_i64, { "r", "rZ", "rJ" } }, |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1570 | { INDEX_op_sub_i64, { "r", "rZ", "rJ" } }, |
| 1571 | { INDEX_op_and_i64, { "r", "rZ", "rJ" } }, |
| 1572 | { INDEX_op_andc_i64, { "r", "rZ", "rJ" } }, |
| 1573 | { INDEX_op_or_i64, { "r", "rZ", "rJ" } }, |
| 1574 | { INDEX_op_orc_i64, { "r", "rZ", "rJ" } }, |
| 1575 | { INDEX_op_xor_i64, { "r", "rZ", "rJ" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1576 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1577 | { INDEX_op_shl_i64, { "r", "rZ", "rJ" } }, |
| 1578 | { INDEX_op_shr_i64, { "r", "rZ", "rJ" } }, |
| 1579 | { INDEX_op_sar_i64, { "r", "rZ", "rJ" } }, |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1580 | |
| 1581 | { INDEX_op_neg_i64, { "r", "rJ" } }, |
Richard Henderson | be6551b | 2010-02-16 14:02:04 -0800 | [diff] [blame] | 1582 | { INDEX_op_not_i64, { "r", "rJ" } }, |
Richard Henderson | 4b5a85c | 2010-02-16 13:55:15 -0800 | [diff] [blame] | 1583 | |
Richard Henderson | 1d0a606 | 2014-03-04 15:24:04 -0800 | [diff] [blame] | 1584 | { INDEX_op_ext32s_i64, { "r", "r" } }, |
| 1585 | { INDEX_op_ext32u_i64, { "r", "r" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1586 | |
Richard Henderson | 89269f6 | 2012-10-10 09:02:42 -0700 | [diff] [blame] | 1587 | { INDEX_op_brcond_i64, { "rZ", "rJ" } }, |
| 1588 | { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } }, |
| 1589 | { INDEX_op_movcond_i64, { "r", "rZ", "rJ", "rI", "0" } }, |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1590 | #endif |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1591 | |
| 1592 | #if TCG_TARGET_REG_BITS == 64 |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1593 | { INDEX_op_qemu_ld_i32, { "r", "L" } }, |
| 1594 | { INDEX_op_qemu_ld_i64, { "r", "L" } }, |
| 1595 | { INDEX_op_qemu_st_i32, { "L", "L" } }, |
| 1596 | { INDEX_op_qemu_st_i64, { "L", "L" } }, |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1597 | #elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1598 | { INDEX_op_qemu_ld_i32, { "r", "L" } }, |
| 1599 | { INDEX_op_qemu_ld_i64, { "r", "r", "L" } }, |
| 1600 | { INDEX_op_qemu_st_i32, { "L", "L" } }, |
| 1601 | { INDEX_op_qemu_st_i64, { "L", "L", "L" } }, |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1602 | #else |
Richard Henderson | cab0a7e | 2013-09-09 19:51:21 -0700 | [diff] [blame] | 1603 | { INDEX_op_qemu_ld_i32, { "r", "L", "L" } }, |
| 1604 | { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } }, |
| 1605 | { INDEX_op_qemu_st_i32, { "L", "L", "L" } }, |
| 1606 | { INDEX_op_qemu_st_i64, { "L", "L", "L", "L" } }, |
Richard Henderson | a0ce341 | 2012-03-23 23:27:39 +0100 | [diff] [blame] | 1607 | #endif |
| 1608 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1609 | { -1 }, |
| 1610 | }; |
| 1611 | |
Richard Henderson | e4d58b4 | 2010-06-02 17:26:56 -0700 | [diff] [blame] | 1612 | static void tcg_target_init(TCGContext *s) |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1613 | { |
| 1614 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
Richard Henderson | a212ea7 | 2009-12-17 23:47:54 -0800 | [diff] [blame] | 1615 | #if TCG_TARGET_REG_BITS == 64 |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1616 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
| 1617 | #endif |
| 1618 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
blueswir1 | b3db875 | 2008-03-08 13:33:42 +0000 | [diff] [blame] | 1619 | (1 << TCG_REG_G1) | |
| 1620 | (1 << TCG_REG_G2) | |
| 1621 | (1 << TCG_REG_G3) | |
| 1622 | (1 << TCG_REG_G4) | |
| 1623 | (1 << TCG_REG_G5) | |
| 1624 | (1 << TCG_REG_G6) | |
| 1625 | (1 << TCG_REG_G7) | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1626 | (1 << TCG_REG_O0) | |
| 1627 | (1 << TCG_REG_O1) | |
| 1628 | (1 << TCG_REG_O2) | |
| 1629 | (1 << TCG_REG_O3) | |
| 1630 | (1 << TCG_REG_O4) | |
| 1631 | (1 << TCG_REG_O5) | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1632 | (1 << TCG_REG_O7)); |
| 1633 | |
| 1634 | tcg_regset_clear(s->reserved_regs); |
Richard Henderson | 375816f | 2012-03-25 22:04:59 +0200 | [diff] [blame] | 1635 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ |
| 1636 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ |
| 1637 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ |
| 1638 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); /* frame pointer */ |
| 1639 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); /* return address */ |
| 1640 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ |
| 1641 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ |
| 1642 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ |
| 1643 | |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1644 | tcg_add_target_add_op_defs(sparc_op_defs); |
blueswir1 | 8289b27 | 2008-02-27 17:53:27 +0000 | [diff] [blame] | 1645 | } |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1646 | |
| 1647 | #if TCG_TARGET_REG_BITS == 64 |
| 1648 | # define ELF_HOST_MACHINE EM_SPARCV9 |
Richard Henderson | 9b9c37c | 2012-09-21 10:34:21 -0700 | [diff] [blame] | 1649 | #else |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1650 | # define ELF_HOST_MACHINE EM_SPARC32PLUS |
| 1651 | # define ELF_HOST_FLAGS EF_SPARC_32PLUS |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1652 | #endif |
| 1653 | |
| 1654 | typedef struct { |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1655 | DebugFrameCIE cie; |
Richard Henderson | 497a22e | 2013-06-05 07:39:57 -0700 | [diff] [blame] | 1656 | DebugFrameFDEHeader fde; |
| 1657 | uint8_t fde_def_cfa[TCG_TARGET_REG_BITS == 64 ? 4 : 2]; |
| 1658 | uint8_t fde_win_save; |
| 1659 | uint8_t fde_ret_save[3]; |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1660 | } DebugFrame; |
| 1661 | |
| 1662 | static DebugFrame debug_frame = { |
| 1663 | .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ |
| 1664 | .cie.id = -1, |
| 1665 | .cie.version = 1, |
| 1666 | .cie.code_align = 1, |
| 1667 | .cie.data_align = -sizeof(void *) & 0x7f, |
| 1668 | .cie.return_column = 15, /* o7 */ |
| 1669 | |
Richard Henderson | 497a22e | 2013-06-05 07:39:57 -0700 | [diff] [blame] | 1670 | /* Total FDE size does not include the "len" member. */ |
| 1671 | .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), |
| 1672 | |
| 1673 | .fde_def_cfa = { |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1674 | #if TCG_TARGET_REG_BITS == 64 |
| 1675 | 12, 30, /* DW_CFA_def_cfa i6, 2047 */ |
| 1676 | (2047 & 0x7f) | 0x80, (2047 >> 7) |
| 1677 | #else |
| 1678 | 13, 30 /* DW_CFA_def_cfa_register i6 */ |
| 1679 | #endif |
| 1680 | }, |
Richard Henderson | 497a22e | 2013-06-05 07:39:57 -0700 | [diff] [blame] | 1681 | .fde_win_save = 0x2d, /* DW_CFA_GNU_window_save */ |
| 1682 | .fde_ret_save = { 9, 15, 31 }, /* DW_CFA_register o7, i7 */ |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1683 | }; |
| 1684 | |
| 1685 | void tcg_register_jit(void *buf, size_t buf_size) |
| 1686 | { |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 1687 | debug_frame.fde.func_start = (uintptr_t)buf; |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 1688 | debug_frame.fde.func_len = buf_size; |
| 1689 | |
| 1690 | tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); |
| 1691 | } |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1692 | |
| 1693 | void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) |
| 1694 | { |
| 1695 | uint32_t *ptr = (uint32_t *)jmp_addr; |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 1696 | uintptr_t disp = addr - jmp_addr; |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1697 | |
| 1698 | /* We can reach the entire address space for 32-bit. For 64-bit |
| 1699 | the code_gen_buffer can't be larger than 2GB. */ |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 1700 | assert(disp == (int32_t)disp); |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1701 | |
Richard Henderson | c8fc56c | 2013-08-20 18:31:45 -0700 | [diff] [blame] | 1702 | *ptr = CALL | (uint32_t)disp >> 2; |
Richard Henderson | 5bbd2ca | 2012-09-21 10:48:51 -0700 | [diff] [blame] | 1703 | flush_icache_range(jmp_addr, jmp_addr + 4); |
| 1704 | } |