bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1 | /* Disassemble SH instructions. |
| 2 | Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the Free Software |
aurel32 | fad6cb1 | 2009-01-04 22:05:52 +0000 | [diff] [blame] | 17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| 18 | MA 02110-1301, USA. */ |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 19 | |
| 20 | #include <stdio.h> |
| 21 | #include "dis-asm.h" |
| 22 | |
| 23 | #define DEFINE_TABLE |
| 24 | |
| 25 | typedef enum |
| 26 | { |
| 27 | HEX_0, |
| 28 | HEX_1, |
| 29 | HEX_2, |
| 30 | HEX_3, |
| 31 | HEX_4, |
| 32 | HEX_5, |
| 33 | HEX_6, |
| 34 | HEX_7, |
| 35 | HEX_8, |
| 36 | HEX_9, |
| 37 | HEX_A, |
| 38 | HEX_B, |
| 39 | HEX_C, |
| 40 | HEX_D, |
| 41 | HEX_E, |
| 42 | HEX_F, |
| 43 | HEX_XX00, |
| 44 | HEX_00YY, |
| 45 | REG_N, |
| 46 | REG_N_D, /* nnn0 */ |
| 47 | REG_N_B01, /* nn01 */ |
| 48 | REG_M, |
| 49 | SDT_REG_N, |
| 50 | REG_NM, |
| 51 | REG_B, |
| 52 | BRANCH_12, |
| 53 | BRANCH_8, |
| 54 | IMM0_4, |
| 55 | IMM0_4BY2, |
| 56 | IMM0_4BY4, |
| 57 | IMM1_4, |
| 58 | IMM1_4BY2, |
| 59 | IMM1_4BY4, |
| 60 | PCRELIMM_8BY2, |
| 61 | PCRELIMM_8BY4, |
| 62 | IMM0_8, |
| 63 | IMM0_8BY2, |
| 64 | IMM0_8BY4, |
| 65 | IMM1_8, |
| 66 | IMM1_8BY2, |
| 67 | IMM1_8BY4, |
| 68 | PPI, |
| 69 | NOPX, |
| 70 | NOPY, |
| 71 | MOVX, |
| 72 | MOVY, |
| 73 | MOVX_NOPY, |
| 74 | MOVY_NOPX, |
| 75 | PSH, |
| 76 | PMUL, |
| 77 | PPI3, |
| 78 | PPI3NC, |
| 79 | PDC, |
| 80 | PPIC, |
| 81 | REPEAT, |
| 82 | IMM0_3c, /* xxxx 0iii */ |
| 83 | IMM0_3s, /* xxxx 1iii */ |
| 84 | IMM0_3Uc, /* 0iii xxxx */ |
| 85 | IMM0_3Us, /* 1iii xxxx */ |
| 86 | IMM0_20_4, |
| 87 | IMM0_20, /* follows IMM0_20_4 */ |
| 88 | IMM0_20BY8, /* follows IMM0_20_4 */ |
| 89 | DISP0_12, |
| 90 | DISP0_12BY2, |
| 91 | DISP0_12BY4, |
| 92 | DISP0_12BY8, |
| 93 | DISP1_12, |
| 94 | DISP1_12BY2, |
| 95 | DISP1_12BY4, |
| 96 | DISP1_12BY8 |
| 97 | } |
| 98 | sh_nibble_type; |
| 99 | |
| 100 | typedef enum |
| 101 | { |
| 102 | A_END, |
| 103 | A_BDISP12, |
| 104 | A_BDISP8, |
| 105 | A_DEC_M, |
| 106 | A_DEC_N, |
| 107 | A_DISP_GBR, |
| 108 | A_PC, |
| 109 | A_DISP_PC, |
| 110 | A_DISP_PC_ABS, |
| 111 | A_DISP_REG_M, |
| 112 | A_DISP_REG_N, |
| 113 | A_GBR, |
| 114 | A_IMM, |
| 115 | A_INC_M, |
| 116 | A_INC_N, |
| 117 | A_IND_M, |
| 118 | A_IND_N, |
| 119 | A_IND_R0_REG_M, |
| 120 | A_IND_R0_REG_N, |
| 121 | A_MACH, |
| 122 | A_MACL, |
| 123 | A_PR, |
| 124 | A_R0, |
| 125 | A_R0_GBR, |
| 126 | A_REG_M, |
| 127 | A_REG_N, |
| 128 | A_REG_B, |
| 129 | A_SR, |
| 130 | A_VBR, |
| 131 | A_TBR, |
| 132 | A_DISP_TBR, |
| 133 | A_DISP2_TBR, |
| 134 | A_DEC_R15, |
| 135 | A_INC_R15, |
| 136 | A_MOD, |
| 137 | A_RE, |
| 138 | A_RS, |
| 139 | A_DSR, |
| 140 | DSP_REG_M, |
| 141 | DSP_REG_N, |
| 142 | DSP_REG_X, |
| 143 | DSP_REG_Y, |
| 144 | DSP_REG_E, |
| 145 | DSP_REG_F, |
| 146 | DSP_REG_G, |
| 147 | DSP_REG_A_M, |
| 148 | DSP_REG_AX, |
| 149 | DSP_REG_XY, |
| 150 | DSP_REG_AY, |
| 151 | DSP_REG_YX, |
| 152 | AX_INC_N, |
| 153 | AY_INC_N, |
| 154 | AXY_INC_N, |
| 155 | AYX_INC_N, |
| 156 | AX_IND_N, |
| 157 | AY_IND_N, |
| 158 | AXY_IND_N, |
| 159 | AYX_IND_N, |
| 160 | AX_PMOD_N, |
| 161 | AXY_PMOD_N, |
| 162 | AY_PMOD_N, |
| 163 | AYX_PMOD_N, |
| 164 | AS_DEC_N, |
| 165 | AS_INC_N, |
| 166 | AS_IND_N, |
| 167 | AS_PMOD_N, |
| 168 | A_A0, |
| 169 | A_X0, |
| 170 | A_X1, |
| 171 | A_Y0, |
| 172 | A_Y1, |
| 173 | A_SSR, |
| 174 | A_SPC, |
| 175 | A_SGR, |
| 176 | A_DBR, |
| 177 | F_REG_N, |
| 178 | F_REG_M, |
| 179 | D_REG_N, |
| 180 | D_REG_M, |
| 181 | X_REG_N, /* Only used for argument parsing. */ |
| 182 | X_REG_M, /* Only used for argument parsing. */ |
| 183 | DX_REG_N, |
| 184 | DX_REG_M, |
| 185 | V_REG_N, |
| 186 | V_REG_M, |
| 187 | XMTRX_M4, |
| 188 | F_FR0, |
| 189 | FPUL_N, |
| 190 | FPUL_M, |
| 191 | FPSCR_N, |
| 192 | FPSCR_M |
| 193 | } |
| 194 | sh_arg_type; |
| 195 | |
| 196 | typedef enum |
| 197 | { |
| 198 | A_A1_NUM = 5, |
| 199 | A_A0_NUM = 7, |
| 200 | A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, |
| 201 | A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM |
| 202 | } |
| 203 | sh_dsp_reg_nums; |
| 204 | |
| 205 | #define arch_sh1_base 0x0001 |
| 206 | #define arch_sh2_base 0x0002 |
| 207 | #define arch_sh3_base 0x0004 |
| 208 | #define arch_sh4_base 0x0008 |
| 209 | #define arch_sh4a_base 0x0010 |
| 210 | #define arch_sh2a_base 0x0020 |
| 211 | |
| 212 | /* This is an annotation on instruction types, but we abuse the arch |
| 213 | field in instructions to denote it. */ |
| 214 | #define arch_op32 0x00100000 /* This is a 32-bit opcode. */ |
| 215 | |
| 216 | #define arch_sh_no_mmu 0x04000000 |
| 217 | #define arch_sh_has_mmu 0x08000000 |
| 218 | #define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */ |
| 219 | #define arch_sh_sp_fpu 0x20000000 /* single precision FPU */ |
| 220 | #define arch_sh_dp_fpu 0x40000000 /* double precision FPU */ |
| 221 | #define arch_sh_has_dsp 0x80000000 |
| 222 | |
| 223 | |
| 224 | #define arch_sh_base_mask 0x0000003f |
| 225 | #define arch_opann_mask 0x00100000 |
| 226 | #define arch_sh_mmu_mask 0x0c000000 |
| 227 | #define arch_sh_co_mask 0xf0000000 |
| 228 | |
| 229 | |
| 230 | #define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co) |
| 231 | #define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co) |
| 232 | #define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu) |
| 233 | #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co) |
| 234 | #define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu) |
| 235 | #define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp) |
| 236 | #define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co) |
| 237 | #define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co) |
| 238 | #define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu) |
| 239 | #define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp) |
| 240 | #define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu) |
| 241 | #define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu) |
| 242 | #define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp) |
| 243 | #define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co) |
| 244 | #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co) |
| 245 | #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co) |
| 246 | |
| 247 | #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) |
| 248 | #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) |
| 249 | #define SH_VALID_MMU_ARCH_SET(SET) (((SET) & arch_sh_mmu_mask) != 0) |
| 250 | #define SH_VALID_CO_ARCH_SET(SET) (((SET) & arch_sh_co_mask) != 0) |
| 251 | #define SH_VALID_ARCH_SET(SET) \ |
| 252 | (SH_VALID_BASE_ARCH_SET (SET) \ |
| 253 | && SH_VALID_MMU_ARCH_SET (SET) \ |
| 254 | && SH_VALID_CO_ARCH_SET (SET)) |
| 255 | #define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \ |
| 256 | SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2)) |
| 257 | |
| 258 | #define SH_ARCH_SET_HAS_FPU(SET) \ |
| 259 | (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0) |
| 260 | #define SH_ARCH_SET_HAS_DSP(SET) \ |
| 261 | (((SET) & arch_sh_has_dsp) != 0) |
| 262 | |
| 263 | /* This is returned from the functions below when an error occurs |
| 264 | (in addition to a call to BFD_FAIL). The value should allow |
| 265 | the tools to continue to function in most cases - there may |
| 266 | be some confusion between DSP and FPU etc. */ |
| 267 | #define SH_ARCH_UNKNOWN_ARCH 0xffffffff |
| 268 | |
| 269 | /* These are defined in bfd/cpu-sh.c . */ |
| 270 | unsigned int sh_get_arch_from_bfd_mach (unsigned long mach); |
| 271 | unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach); |
| 272 | unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set); |
| 273 | /* bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); */ |
| 274 | |
| 275 | /* Below are the 'architecture sets'. |
| 276 | They describe the following inheritance graph: |
| 277 | |
| 278 | SH1 |
| 279 | | |
| 280 | SH2 |
| 281 | .------------'|`--------------------. |
| 282 | / | \ |
| 283 | SH-DSP SH3-nommu SH2E |
| 284 | | |`--------. | |
| 285 | | | \ | |
| 286 | | SH3 SH4-nommu-nofpu | |
| 287 | | | | | |
| 288 | | .------------'|`----------+---------. | |
| 289 | |/ / \| |
| 290 | | | .-------' | |
| 291 | | |/ | |
| 292 | SH3-dsp SH4-nofpu SH3E |
| 293 | | |`--------------------. | |
| 294 | | | \| |
| 295 | | SH4A-nofpu SH4 |
| 296 | | .------------' `--------------------. | |
| 297 | |/ \| |
| 298 | SH4AL-dsp SH4A |
| 299 | |
| 300 | */ |
| 301 | |
| 302 | /* Central branches */ |
| 303 | #define arch_sh1_up (arch_sh1 | arch_sh2_up) |
| 304 | #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up) |
| 305 | #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up) |
| 306 | #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up) |
| 307 | #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) |
| 308 | #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) |
| 309 | #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) |
| 310 | |
| 311 | /* Right branch */ |
| 312 | #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up) |
| 313 | #define arch_sh3e_up (arch_sh3e | arch_sh4_up) |
| 314 | #define arch_sh4_up (arch_sh4 | arch_sh4a_up) |
| 315 | #define arch_sh4a_up (arch_sh4a) |
| 316 | |
| 317 | /* Left branch */ |
| 318 | #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) |
| 319 | #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) |
| 320 | #define arch_sh4al_dsp_up (arch_sh4al_dsp) |
| 321 | |
| 322 | /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a. */ |
| 323 | #define arch_sh2a_up (arch_sh2a) |
| 324 | #define arch_sh2a_nofpu_up (arch_sh2a_nofpu | arch_sh2a_up) |
| 325 | |
| 326 | |
| 327 | typedef struct |
| 328 | { |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 329 | const char *name; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 330 | sh_arg_type arg[4]; |
| 331 | sh_nibble_type nibbles[9]; |
| 332 | unsigned int arch; |
| 333 | } sh_opcode_info; |
| 334 | |
| 335 | #ifdef DEFINE_TABLE |
| 336 | |
| 337 | const sh_opcode_info sh_table[] = |
| 338 | { |
| 339 | /* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up}, |
| 340 | |
| 341 | /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
| 342 | |
| 343 | /* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
| 344 | |
| 345 | /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
| 346 | |
| 347 | /* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up}, |
| 348 | |
| 349 | /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, |
| 350 | |
| 351 | /* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up}, |
| 352 | |
| 353 | /* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, |
| 354 | |
| 355 | /* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, |
| 356 | |
| 357 | /* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, |
| 358 | |
| 359 | /* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, |
| 360 | |
| 361 | /* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, |
| 362 | |
| 363 | /* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, |
| 364 | |
| 365 | /* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, |
| 366 | |
| 367 | /* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, |
| 368 | |
| 369 | /* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}, |
| 370 | |
| 371 | /* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, |
| 372 | |
| 373 | /* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, |
| 374 | |
| 375 | /* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, |
| 376 | |
| 377 | /* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up}, |
| 378 | |
| 379 | /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
| 380 | |
| 381 | /* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, |
| 382 | |
| 383 | /* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
| 384 | |
| 385 | /* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
| 386 | |
| 387 | /* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
| 388 | |
| 389 | /* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, |
| 390 | |
| 391 | /* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, |
| 392 | |
| 393 | /* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
| 394 | |
| 395 | /* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
| 396 | |
| 397 | /* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, |
| 398 | |
| 399 | /* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
| 400 | |
| 401 | /* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
| 402 | |
| 403 | /* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
| 404 | |
| 405 | /* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
| 406 | |
| 407 | /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
| 408 | |
| 409 | /* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up}, |
| 410 | |
| 411 | /* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, |
| 412 | |
| 413 | /* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, |
| 414 | |
| 415 | /* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, |
| 416 | |
| 417 | /* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, |
| 418 | |
| 419 | /* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, |
| 420 | |
| 421 | /* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, |
| 422 | |
| 423 | /* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, |
| 424 | |
| 425 | /* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, |
| 426 | |
| 427 | /* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, |
| 428 | |
| 429 | /* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, |
| 430 | |
| 431 | /* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}, |
| 432 | |
| 433 | /* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}, |
| 434 | |
| 435 | /* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, |
| 436 | |
| 437 | /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}, |
| 438 | |
| 439 | /* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, |
| 440 | |
| 441 | /* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, |
| 442 | |
| 443 | /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, |
| 444 | |
| 445 | /* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}, |
| 446 | |
| 447 | /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, |
| 448 | |
| 449 | /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, |
| 450 | |
| 451 | /* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, |
| 452 | |
| 453 | /* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}, |
| 454 | |
| 455 | /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}, |
| 456 | |
| 457 | /* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}, |
| 458 | |
| 459 | /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}, |
| 460 | |
| 461 | /* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, |
| 462 | /* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, |
| 463 | |
| 464 | /* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, |
| 465 | |
| 466 | /* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, |
| 467 | |
| 468 | /* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, |
| 469 | |
| 470 | /* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, |
| 471 | |
| 472 | /* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, |
| 473 | |
| 474 | /* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, |
| 475 | |
| 476 | /* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, |
| 477 | |
| 478 | /* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, |
| 479 | |
| 480 | /* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, |
| 481 | |
| 482 | /* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, |
| 483 | |
| 484 | /* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, |
| 485 | |
| 486 | /* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 487 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 488 | /* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, |
| 489 | |
| 490 | /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, |
| 491 | |
| 492 | /* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, |
| 493 | |
| 494 | /* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, |
| 495 | |
| 496 | /* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, |
| 497 | |
| 498 | /* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, |
| 499 | |
| 500 | /* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, |
| 501 | |
| 502 | /* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, |
| 503 | |
| 504 | /* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, |
| 505 | |
| 506 | /* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, |
| 507 | |
| 508 | /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 509 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 510 | /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, |
| 511 | |
| 512 | /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, |
| 513 | |
| 514 | /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
| 515 | |
| 516 | /* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up}, |
| 517 | |
| 518 | /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, |
| 519 | |
| 520 | /* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
| 521 | |
| 522 | /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
| 523 | |
| 524 | /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
| 525 | |
| 526 | /* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up}, |
| 527 | |
| 528 | /* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up}, |
| 529 | |
| 530 | /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, |
| 531 | |
| 532 | /* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, |
| 533 | |
| 534 | /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, |
| 535 | |
| 536 | /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up}, |
| 537 | |
| 538 | /* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up}, |
| 539 | |
| 540 | /* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}, |
| 541 | /* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}, |
| 542 | /* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ |
| 543 | {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 544 | /* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ |
| 545 | {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 546 | /* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up}, |
| 547 | |
| 548 | /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
| 549 | |
| 550 | /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
| 551 | |
| 552 | /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
| 553 | |
| 554 | /* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up}, |
| 555 | |
| 556 | /* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up}, |
| 557 | |
| 558 | /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, |
| 559 | |
| 560 | /* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
| 561 | |
| 562 | /* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, |
| 563 | |
| 564 | /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, |
| 565 | |
| 566 | /* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up}, |
| 567 | |
| 568 | /* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}, |
| 569 | /* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}, |
| 570 | /* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ |
| 571 | {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}, |
| 572 | /* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ |
| 573 | {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}, |
| 574 | /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
| 575 | |
| 576 | /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
| 577 | |
| 578 | /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, |
| 579 | |
| 580 | /* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up}, |
| 581 | |
| 582 | /* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up}, |
| 583 | |
| 584 | /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, |
| 585 | |
| 586 | /* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
| 587 | |
| 588 | /* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, |
| 589 | |
| 590 | /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, |
| 591 | |
| 592 | /* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up}, |
| 593 | |
| 594 | /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, |
| 595 | |
| 596 | /* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}, |
| 597 | /* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}, |
| 598 | /* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ |
| 599 | {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}, |
| 600 | /* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ |
| 601 | {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, |
| 602 | /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, |
| 603 | /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}, |
| 604 | |
| 605 | /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, |
| 606 | /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, |
| 607 | |
| 608 | /* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, |
| 609 | |
| 610 | /* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up}, |
| 611 | /* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up}, |
| 612 | |
| 613 | /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
| 614 | /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, |
| 615 | |
| 616 | /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, |
| 617 | |
| 618 | /* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
| 619 | /* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, |
| 620 | |
| 621 | /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
| 622 | |
| 623 | /* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
| 624 | |
| 625 | /* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, |
| 626 | |
| 627 | /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
| 628 | /* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}, |
| 629 | |
| 630 | /* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}, |
| 631 | |
| 632 | /* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, |
| 633 | |
| 634 | |
| 635 | /* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, |
| 636 | |
| 637 | /* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
| 638 | |
| 639 | /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, |
| 640 | |
| 641 | /* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up}, |
| 642 | |
| 643 | /* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, |
| 644 | |
| 645 | /* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, |
| 646 | |
| 647 | /* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, |
| 648 | |
| 649 | /* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, |
| 650 | |
| 651 | /* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, |
| 652 | |
| 653 | /* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, |
| 654 | |
| 655 | /* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, |
| 656 | |
| 657 | /* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, |
| 658 | /* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, |
| 659 | |
| 660 | /* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, |
| 661 | /* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, |
| 662 | |
| 663 | /* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, |
| 664 | |
| 665 | /* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, |
| 666 | |
| 667 | /* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, |
| 668 | |
| 669 | /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, |
| 670 | |
| 671 | /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, |
| 672 | |
| 673 | /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up}, |
| 674 | |
| 675 | /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, |
| 676 | |
| 677 | /* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, |
| 678 | |
| 679 | /* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, |
| 680 | |
| 681 | /* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, |
| 682 | |
| 683 | /* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, |
| 684 | |
| 685 | /* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, |
| 686 | |
| 687 | /* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, |
| 688 | |
| 689 | /* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, |
| 690 | |
| 691 | /* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, |
| 692 | |
| 693 | /* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, |
| 694 | |
| 695 | /* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, |
| 696 | |
| 697 | /* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, |
| 698 | |
| 699 | /* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, |
| 700 | |
| 701 | /* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, |
| 702 | |
| 703 | /* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, |
| 704 | |
| 705 | /* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, |
| 706 | |
| 707 | /* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, |
| 708 | |
| 709 | /* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}, |
| 710 | |
| 711 | /* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}, |
| 712 | |
| 713 | /* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, |
| 714 | |
| 715 | /* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, |
| 716 | |
| 717 | /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}, |
| 718 | |
| 719 | /* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}, |
| 720 | |
| 721 | /* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, |
| 722 | |
| 723 | /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, |
| 724 | |
| 725 | /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, |
| 726 | |
| 727 | /* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, |
| 728 | |
| 729 | /* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, |
| 730 | |
| 731 | /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}, |
| 732 | |
| 733 | /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}, |
| 734 | |
| 735 | /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, |
| 736 | |
| 737 | /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}, |
| 738 | |
| 739 | /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}, |
| 740 | |
| 741 | /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}, |
| 742 | |
| 743 | /* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, |
| 744 | |
| 745 | /* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, |
| 746 | |
| 747 | /* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, |
| 748 | |
| 749 | /* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, |
| 750 | |
| 751 | /* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, |
| 752 | |
| 753 | /* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, |
| 754 | |
| 755 | /* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, |
| 756 | |
| 757 | /* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, |
| 758 | |
| 759 | /* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, |
| 760 | |
| 761 | /* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 762 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 763 | /* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, |
| 764 | |
| 765 | /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, |
| 766 | |
| 767 | /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, |
| 768 | |
| 769 | /* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, |
| 770 | |
| 771 | /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, |
| 772 | |
| 773 | /* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, |
| 774 | |
| 775 | /* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, |
| 776 | |
| 777 | /* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, |
| 778 | |
| 779 | /* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, |
| 780 | |
| 781 | /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, |
| 782 | |
| 783 | /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 784 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 785 | /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, |
| 786 | |
| 787 | /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
| 788 | |
| 789 | /* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
| 790 | |
| 791 | /* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, |
| 792 | |
| 793 | /* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
| 794 | |
| 795 | /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, |
| 796 | |
| 797 | /* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up}, |
| 798 | |
| 799 | /* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, |
| 800 | |
| 801 | /* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up}, |
| 802 | |
| 803 | /* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up}, |
| 804 | |
| 805 | /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, |
| 806 | |
| 807 | /* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up}, |
| 808 | |
| 809 | /* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up}, |
| 810 | |
| 811 | /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, |
| 812 | |
| 813 | /* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up}, |
| 814 | |
| 815 | /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, |
| 816 | |
| 817 | /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, |
| 818 | |
| 819 | /* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, |
| 820 | |
| 821 | /* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, |
| 822 | |
| 823 | /* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, |
| 824 | |
| 825 | /* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, |
| 826 | |
| 827 | /* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, |
| 828 | |
| 829 | /* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, |
| 830 | |
| 831 | /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, |
| 832 | |
| 833 | /* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, |
| 834 | |
| 835 | /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, |
| 836 | |
| 837 | /* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, |
| 838 | |
| 839 | /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, |
| 840 | |
| 841 | /* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, |
| 842 | |
| 843 | /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, |
| 844 | |
| 845 | /* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, |
| 846 | |
| 847 | /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, |
| 848 | |
| 849 | /* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, |
| 850 | |
| 851 | /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, |
| 852 | |
| 853 | /* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, |
| 854 | |
| 855 | /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, |
| 856 | |
| 857 | /* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, |
| 858 | |
| 859 | /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, |
| 860 | |
| 861 | /* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, |
| 862 | |
| 863 | /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, |
| 864 | /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, |
| 865 | /* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, |
| 866 | /* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, |
| 867 | /* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, |
| 868 | /* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, |
| 869 | /* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, |
| 870 | /* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, |
| 871 | |
| 872 | /* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}, |
| 873 | /* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}, |
| 874 | /* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}, |
| 875 | /* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}, |
| 876 | /* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}, |
| 877 | /* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}, |
| 878 | |
| 879 | /* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}, |
| 880 | /* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}, |
| 881 | /* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}, |
| 882 | /* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}, |
| 883 | /* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}, |
| 884 | /* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}, |
| 885 | |
| 886 | /* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, |
| 887 | /* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, |
| 888 | /* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, |
| 889 | /* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, |
| 890 | /* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, |
| 891 | /* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, |
| 892 | |
| 893 | /* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}, |
| 894 | /* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}, |
| 895 | /* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}, |
| 896 | /* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}, |
| 897 | /* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}, |
| 898 | /* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}, |
| 899 | |
| 900 | /* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}, |
| 901 | /* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}, |
| 902 | /* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}, |
| 903 | /* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}, |
| 904 | /* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}, |
| 905 | /* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}, |
| 906 | |
| 907 | /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, |
| 908 | /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 909 | {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, |
| 910 | /* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 911 | {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, |
| 912 | /* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ |
| 913 | {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, |
| 914 | /* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 915 | {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, |
| 916 | /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 917 | {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, |
| 918 | /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ |
| 919 | {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}, |
| 920 | /* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ |
| 921 | {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}, |
| 922 | /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ |
| 923 | {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}, |
| 924 | /* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ |
| 925 | {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}, |
| 926 | /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ |
| 927 | {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}, |
| 928 | /* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ |
| 929 | {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}, |
| 930 | /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ |
| 931 | {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}, |
| 932 | /* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ |
| 933 | {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}, |
| 934 | |
| 935 | {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, |
| 936 | {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, |
| 937 | |
| 938 | /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 939 | {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, |
| 940 | /* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, |
| 941 | /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 942 | {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, |
| 943 | /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, |
| 944 | /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 945 | {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, |
| 946 | /* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ |
| 947 | {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}, |
| 948 | /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 949 | {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, |
| 950 | /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 951 | {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, |
| 952 | /* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 953 | {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, |
| 954 | /* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ |
| 955 | {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, |
| 956 | /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ |
| 957 | {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, |
| 958 | /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ |
| 959 | {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, |
| 960 | /* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ |
| 961 | {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}, |
| 962 | /* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ |
| 963 | {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}, |
| 964 | /* 10001101xxyynnnn pclr <DSP_REG_N> */ |
| 965 | {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, |
| 966 | /* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ |
| 967 | {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}, |
| 968 | /* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ |
| 969 | {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}, |
| 970 | /* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ |
| 971 | {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, |
| 972 | /* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ |
| 973 | {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, |
| 974 | /* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ |
| 975 | {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, |
| 976 | /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ |
| 977 | {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, |
| 978 | /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ |
| 979 | {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, |
| 980 | /* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ |
| 981 | {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, |
| 982 | /* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ |
| 983 | {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, |
| 984 | /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ |
| 985 | {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, |
| 986 | /* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ |
| 987 | {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}, |
| 988 | /* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ |
| 989 | {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, |
| 990 | |
| 991 | /* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, |
| 992 | /* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 993 | |
| 994 | /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, |
| 995 | /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up}, |
| 996 | |
| 997 | /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, |
| 998 | /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up}, |
| 999 | |
| 1000 | /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, |
| 1001 | /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up}, |
| 1002 | |
| 1003 | /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1004 | |
| 1005 | /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1006 | |
| 1007 | /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, |
| 1008 | /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up}, |
| 1009 | |
| 1010 | /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, |
| 1011 | |
| 1012 | /* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}, |
| 1013 | |
| 1014 | /* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}, |
| 1015 | |
| 1016 | /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, |
| 1017 | |
| 1018 | /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, |
| 1019 | /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1020 | |
| 1021 | /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, |
| 1022 | |
| 1023 | /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, |
| 1024 | /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up}, |
| 1025 | |
| 1026 | /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, |
| 1027 | /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, |
| 1028 | |
| 1029 | /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, |
| 1030 | /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, |
| 1031 | |
| 1032 | /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, |
| 1033 | /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, |
| 1034 | |
| 1035 | /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, |
| 1036 | /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, |
| 1037 | |
| 1038 | /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, |
| 1039 | /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, |
| 1040 | |
| 1041 | /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, |
| 1042 | /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, |
| 1043 | |
| 1044 | /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up}, |
| 1045 | |
| 1046 | /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up}, |
| 1047 | |
| 1048 | /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up}, |
| 1049 | |
| 1050 | /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up}, |
| 1051 | |
| 1052 | /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up}, |
| 1053 | |
| 1054 | /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up}, |
| 1055 | /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */ |
| 1056 | {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}, |
| 1057 | /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */ |
| 1058 | {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}, |
| 1059 | |
| 1060 | /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, |
| 1061 | |
| 1062 | /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, |
| 1063 | |
| 1064 | /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, |
| 1065 | |
| 1066 | /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, |
| 1067 | |
| 1068 | /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, |
| 1069 | |
| 1070 | /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, |
| 1071 | /* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ |
| 1072 | {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}, |
| 1073 | /* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),F_REG_N */ |
| 1074 | {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}, |
| 1075 | |
| 1076 | /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, |
| 1077 | /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up}, |
| 1078 | |
| 1079 | /* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, |
| 1080 | /* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1081 | |
| 1082 | /* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, |
| 1083 | |
| 1084 | /* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, |
| 1085 | |
| 1086 | /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, |
| 1087 | |
| 1088 | /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1089 | |
| 1090 | /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up}, |
| 1091 | /* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1092 | |
| 1093 | /* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, |
| 1094 | |
| 1095 | /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, |
| 1096 | |
| 1097 | /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, |
| 1098 | /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up}, |
| 1099 | |
| 1100 | /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, |
| 1101 | /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up}, |
| 1102 | |
| 1103 | /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, |
| 1104 | |
| 1105 | /* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, |
| 1106 | /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1107 | {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1108 | /* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, |
| 1109 | /* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1110 | {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1111 | /* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}, |
| 1112 | /* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1113 | {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1114 | /* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}, |
| 1115 | /* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1116 | {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1117 | /* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}, |
| 1118 | /* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}, |
| 1119 | /* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}, |
| 1120 | /* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}, |
| 1121 | /* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}, |
| 1122 | /* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}, |
| 1123 | /* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}, |
| 1124 | /* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}, |
| 1125 | /* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}, |
| 1126 | /* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}, |
| 1127 | /* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}, |
| 1128 | /* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}, |
| 1129 | /* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}, |
| 1130 | /* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}, |
| 1131 | /* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}, |
| 1132 | /* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}, |
| 1133 | /* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}, |
| 1134 | /* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}, |
| 1135 | /* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}, |
| 1136 | /* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}, |
| 1137 | |
| 1138 | /* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1139 | {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1140 | /* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1141 | {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1142 | /* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1143 | {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1144 | /* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1145 | {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1146 | /* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1147 | {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1148 | /* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ |
| 1149 | {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1150 | /* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ |
| 1151 | {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}, |
| 1152 | /* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ |
| 1153 | {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}, |
| 1154 | /* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ |
| 1155 | {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, |
| 1156 | /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ |
| 1157 | {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, |
| 1158 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1159 | { 0, {0}, {0}, 0 } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1160 | }; |
| 1161 | |
| 1162 | #endif |
| 1163 | |
| 1164 | #ifdef ARCH_all |
| 1165 | #define INCLUDE_SHMEDIA |
| 1166 | #endif |
| 1167 | |
| 1168 | static void print_movxy |
| 1169 | PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *)); |
| 1170 | static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); |
| 1171 | static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); |
| 1172 | static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); |
| 1173 | |
| 1174 | static void |
| 1175 | print_movxy (op, rn, rm, fprintf_fn, stream) |
| 1176 | const sh_opcode_info *op; |
| 1177 | int rn, rm; |
| 1178 | fprintf_ftype fprintf_fn; |
| 1179 | void *stream; |
| 1180 | { |
| 1181 | int n; |
| 1182 | |
| 1183 | fprintf_fn (stream, "%s\t", op->name); |
| 1184 | for (n = 0; n < 2; n++) |
| 1185 | { |
| 1186 | switch (op->arg[n]) |
| 1187 | { |
| 1188 | case A_IND_N: |
| 1189 | case AX_IND_N: |
| 1190 | case AXY_IND_N: |
| 1191 | case AY_IND_N: |
| 1192 | case AYX_IND_N: |
| 1193 | fprintf_fn (stream, "@r%d", rn); |
| 1194 | break; |
| 1195 | case A_INC_N: |
| 1196 | case AX_INC_N: |
| 1197 | case AXY_INC_N: |
| 1198 | case AY_INC_N: |
| 1199 | case AYX_INC_N: |
| 1200 | fprintf_fn (stream, "@r%d+", rn); |
| 1201 | break; |
| 1202 | case AX_PMOD_N: |
| 1203 | case AXY_PMOD_N: |
| 1204 | fprintf_fn (stream, "@r%d+r8", rn); |
| 1205 | break; |
| 1206 | case AY_PMOD_N: |
| 1207 | case AYX_PMOD_N: |
| 1208 | fprintf_fn (stream, "@r%d+r9", rn); |
| 1209 | break; |
| 1210 | case DSP_REG_A_M: |
| 1211 | fprintf_fn (stream, "a%c", '0' + rm); |
| 1212 | break; |
| 1213 | case DSP_REG_X: |
| 1214 | fprintf_fn (stream, "x%c", '0' + rm); |
| 1215 | break; |
| 1216 | case DSP_REG_Y: |
| 1217 | fprintf_fn (stream, "y%c", '0' + rm); |
| 1218 | break; |
| 1219 | case DSP_REG_AX: |
| 1220 | fprintf_fn (stream, "%c%c", |
| 1221 | (rm & 1) ? 'x' : 'a', |
| 1222 | (rm & 2) ? '1' : '0'); |
| 1223 | break; |
| 1224 | case DSP_REG_XY: |
| 1225 | fprintf_fn (stream, "%c%c", |
| 1226 | (rm & 1) ? 'y' : 'x', |
| 1227 | (rm & 2) ? '1' : '0'); |
| 1228 | break; |
| 1229 | case DSP_REG_AY: |
| 1230 | fprintf_fn (stream, "%c%c", |
| 1231 | (rm & 2) ? 'y' : 'a', |
| 1232 | (rm & 1) ? '1' : '0'); |
| 1233 | break; |
| 1234 | case DSP_REG_YX: |
| 1235 | fprintf_fn (stream, "%c%c", |
| 1236 | (rm & 2) ? 'x' : 'y', |
| 1237 | (rm & 1) ? '1' : '0'); |
| 1238 | break; |
| 1239 | default: |
| 1240 | abort (); |
| 1241 | } |
| 1242 | if (n == 0) |
| 1243 | fprintf_fn (stream, ","); |
| 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | /* Print a double data transfer insn. INSN is just the lower three |
| 1248 | nibbles of the insn, i.e. field a and the bit that indicates if |
| 1249 | a parallel processing insn follows. |
| 1250 | Return nonzero if a field b of a parallel processing insns follows. */ |
| 1251 | |
| 1252 | static void |
| 1253 | print_insn_ddt (insn, info) |
| 1254 | int insn; |
| 1255 | struct disassemble_info *info; |
| 1256 | { |
| 1257 | fprintf_ftype fprintf_fn = info->fprintf_func; |
| 1258 | void *stream = info->stream; |
| 1259 | |
| 1260 | /* If this is just a nop, make sure to emit something. */ |
| 1261 | if (insn == 0x000) |
| 1262 | fprintf_fn (stream, "nopx\tnopy"); |
| 1263 | |
| 1264 | /* If a parallel processing insn was printed before, |
| 1265 | and we got a non-nop, emit a tab. */ |
| 1266 | if ((insn & 0x800) && (insn & 0x3ff)) |
| 1267 | fprintf_fn (stream, "\t"); |
| 1268 | |
| 1269 | /* Check if either the x or y part is invalid. */ |
| 1270 | if (((insn & 0xc) == 0 && (insn & 0x2a0)) |
| 1271 | || ((insn & 3) == 0 && (insn & 0x150))) |
| 1272 | if (info->mach != bfd_mach_sh_dsp |
| 1273 | && info->mach != bfd_mach_sh3_dsp) |
| 1274 | { |
| 1275 | static const sh_opcode_info *first_movx, *first_movy; |
| 1276 | const sh_opcode_info *op; |
| 1277 | int is_movy; |
| 1278 | |
| 1279 | if (! first_movx) |
| 1280 | { |
| 1281 | for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) |
| 1282 | first_movx++; |
| 1283 | for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) |
| 1284 | first_movy++; |
| 1285 | } |
| 1286 | |
| 1287 | is_movy = ((insn & 3) != 0); |
| 1288 | |
| 1289 | if (is_movy) |
| 1290 | op = first_movy; |
| 1291 | else |
| 1292 | op = first_movx; |
| 1293 | |
| 1294 | while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) |
| 1295 | || op->nibbles[3] != (unsigned) (insn & 0xf)) |
| 1296 | op++; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1297 | |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1298 | print_movxy (op, |
| 1299 | (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0) |
| 1300 | + 2 * is_movy |
| 1301 | + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)), |
| 1302 | (insn >> 6) & 3, |
| 1303 | fprintf_fn, stream); |
| 1304 | } |
| 1305 | else |
| 1306 | fprintf_fn (stream, ".word 0x%x", insn); |
| 1307 | else |
| 1308 | { |
| 1309 | static const sh_opcode_info *first_movx, *first_movy; |
| 1310 | const sh_opcode_info *opx, *opy; |
| 1311 | unsigned int insn_x, insn_y; |
| 1312 | |
| 1313 | if (! first_movx) |
| 1314 | { |
| 1315 | for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) |
| 1316 | first_movx++; |
| 1317 | for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) |
| 1318 | first_movy++; |
| 1319 | } |
| 1320 | insn_x = (insn >> 2) & 0xb; |
| 1321 | if (insn_x) |
| 1322 | { |
| 1323 | for (opx = first_movx; opx->nibbles[2] != insn_x;) |
| 1324 | opx++; |
| 1325 | print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, |
| 1326 | fprintf_fn, stream); |
| 1327 | } |
| 1328 | insn_y = (insn & 3) | ((insn >> 1) & 8); |
| 1329 | if (insn_y) |
| 1330 | { |
| 1331 | if (insn_x) |
| 1332 | fprintf_fn (stream, "\t"); |
| 1333 | for (opy = first_movy; opy->nibbles[2] != insn_y;) |
| 1334 | opy++; |
| 1335 | print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, |
| 1336 | fprintf_fn, stream); |
| 1337 | } |
| 1338 | } |
| 1339 | } |
| 1340 | |
| 1341 | static void |
| 1342 | print_dsp_reg (rm, fprintf_fn, stream) |
| 1343 | int rm; |
| 1344 | fprintf_ftype fprintf_fn; |
| 1345 | void *stream; |
| 1346 | { |
| 1347 | switch (rm) |
| 1348 | { |
| 1349 | case A_A1_NUM: |
| 1350 | fprintf_fn (stream, "a1"); |
| 1351 | break; |
| 1352 | case A_A0_NUM: |
| 1353 | fprintf_fn (stream, "a0"); |
| 1354 | break; |
| 1355 | case A_X0_NUM: |
| 1356 | fprintf_fn (stream, "x0"); |
| 1357 | break; |
| 1358 | case A_X1_NUM: |
| 1359 | fprintf_fn (stream, "x1"); |
| 1360 | break; |
| 1361 | case A_Y0_NUM: |
| 1362 | fprintf_fn (stream, "y0"); |
| 1363 | break; |
| 1364 | case A_Y1_NUM: |
| 1365 | fprintf_fn (stream, "y1"); |
| 1366 | break; |
| 1367 | case A_M0_NUM: |
| 1368 | fprintf_fn (stream, "m0"); |
| 1369 | break; |
| 1370 | case A_A1G_NUM: |
| 1371 | fprintf_fn (stream, "a1g"); |
| 1372 | break; |
| 1373 | case A_M1_NUM: |
| 1374 | fprintf_fn (stream, "m1"); |
| 1375 | break; |
| 1376 | case A_A0G_NUM: |
| 1377 | fprintf_fn (stream, "a0g"); |
| 1378 | break; |
| 1379 | default: |
| 1380 | fprintf_fn (stream, "0x%x", rm); |
| 1381 | break; |
| 1382 | } |
| 1383 | } |
| 1384 | |
| 1385 | static void |
| 1386 | print_insn_ppi (field_b, info) |
| 1387 | int field_b; |
| 1388 | struct disassemble_info *info; |
| 1389 | { |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 1390 | static const char *sx_tab[] = { "x0", "x1", "a0", "a1" }; |
| 1391 | static const char *sy_tab[] = { "y0", "y1", "m0", "m1" }; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1392 | fprintf_ftype fprintf_fn = info->fprintf_func; |
| 1393 | void *stream = info->stream; |
| 1394 | unsigned int nib1, nib2, nib3; |
| 1395 | unsigned int altnib1, nib4; |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 1396 | const char *dc = NULL; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1397 | const sh_opcode_info *op; |
| 1398 | |
| 1399 | if ((field_b & 0xe800) == 0) |
| 1400 | { |
| 1401 | fprintf_fn (stream, "psh%c\t#%d,", |
| 1402 | field_b & 0x1000 ? 'a' : 'l', |
| 1403 | (field_b >> 4) & 127); |
| 1404 | print_dsp_reg (field_b & 0xf, fprintf_fn, stream); |
| 1405 | return; |
| 1406 | } |
| 1407 | if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) |
| 1408 | { |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 1409 | static const char *du_tab[] = { "x0", "y0", "a0", "a1" }; |
| 1410 | static const char *se_tab[] = { "x0", "x1", "y0", "a1" }; |
| 1411 | static const char *sf_tab[] = { "y0", "y1", "x0", "a1" }; |
| 1412 | static const char *sg_tab[] = { "m0", "m1", "a0", "a1" }; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 1413 | |
| 1414 | if (field_b & 0x2000) |
| 1415 | { |
| 1416 | fprintf_fn (stream, "p%s %s,%s,%s\t", |
| 1417 | (field_b & 0x1000) ? "add" : "sub", |
| 1418 | sx_tab[(field_b >> 6) & 3], |
| 1419 | sy_tab[(field_b >> 4) & 3], |
| 1420 | du_tab[(field_b >> 0) & 3]); |
| 1421 | } |
| 1422 | else if ((field_b & 0xf0) == 0x10 |
| 1423 | && info->mach != bfd_mach_sh_dsp |
| 1424 | && info->mach != bfd_mach_sh3_dsp) |
| 1425 | { |
| 1426 | fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); |
| 1427 | } |
| 1428 | else if ((field_b & 0xf3) != 0) |
| 1429 | { |
| 1430 | fprintf_fn (stream, ".word 0x%x\t", field_b); |
| 1431 | } |
| 1432 | fprintf_fn (stream, "pmuls%c%s,%s,%s", |
| 1433 | field_b & 0x2000 ? ' ' : '\t', |
| 1434 | se_tab[(field_b >> 10) & 3], |
| 1435 | sf_tab[(field_b >> 8) & 3], |
| 1436 | sg_tab[(field_b >> 2) & 3]); |
| 1437 | return; |
| 1438 | } |
| 1439 | |
| 1440 | nib1 = PPIC; |
| 1441 | nib2 = field_b >> 12 & 0xf; |
| 1442 | nib3 = field_b >> 8 & 0xf; |
| 1443 | nib4 = field_b >> 4 & 0xf; |
| 1444 | switch (nib3 & 0x3) |
| 1445 | { |
| 1446 | case 0: |
| 1447 | dc = ""; |
| 1448 | nib1 = PPI3; |
| 1449 | break; |
| 1450 | case 1: |
| 1451 | dc = ""; |
| 1452 | break; |
| 1453 | case 2: |
| 1454 | dc = "dct "; |
| 1455 | nib3 -= 1; |
| 1456 | break; |
| 1457 | case 3: |
| 1458 | dc = "dcf "; |
| 1459 | nib3 -= 2; |
| 1460 | break; |
| 1461 | } |
| 1462 | if (nib1 == PPI3) |
| 1463 | altnib1 = PPI3NC; |
| 1464 | else |
| 1465 | altnib1 = nib1; |
| 1466 | for (op = sh_table; op->name; op++) |
| 1467 | { |
| 1468 | if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) |
| 1469 | && op->nibbles[2] == nib2 |
| 1470 | && op->nibbles[3] == nib3) |
| 1471 | { |
| 1472 | int n; |
| 1473 | |
| 1474 | switch (op->nibbles[4]) |
| 1475 | { |
| 1476 | case HEX_0: |
| 1477 | break; |
| 1478 | case HEX_XX00: |
| 1479 | if ((nib4 & 3) != 0) |
| 1480 | continue; |
| 1481 | break; |
| 1482 | case HEX_1: |
| 1483 | if ((nib4 & 3) != 1) |
| 1484 | continue; |
| 1485 | break; |
| 1486 | case HEX_00YY: |
| 1487 | if ((nib4 & 0xc) != 0) |
| 1488 | continue; |
| 1489 | break; |
| 1490 | case HEX_4: |
| 1491 | if ((nib4 & 0xc) != 4) |
| 1492 | continue; |
| 1493 | break; |
| 1494 | default: |
| 1495 | abort (); |
| 1496 | } |
| 1497 | fprintf_fn (stream, "%s%s\t", dc, op->name); |
| 1498 | for (n = 0; n < 3 && op->arg[n] != A_END; n++) |
| 1499 | { |
| 1500 | if (n && op->arg[1] != A_END) |
| 1501 | fprintf_fn (stream, ","); |
| 1502 | switch (op->arg[n]) |
| 1503 | { |
| 1504 | case DSP_REG_N: |
| 1505 | print_dsp_reg (field_b & 0xf, fprintf_fn, stream); |
| 1506 | break; |
| 1507 | case DSP_REG_X: |
| 1508 | fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); |
| 1509 | break; |
| 1510 | case DSP_REG_Y: |
| 1511 | fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); |
| 1512 | break; |
| 1513 | case A_MACH: |
| 1514 | fprintf_fn (stream, "mach"); |
| 1515 | break; |
| 1516 | case A_MACL: |
| 1517 | fprintf_fn (stream, "macl"); |
| 1518 | break; |
| 1519 | default: |
| 1520 | abort (); |
| 1521 | } |
| 1522 | } |
| 1523 | return; |
| 1524 | } |
| 1525 | } |
| 1526 | /* Not found. */ |
| 1527 | fprintf_fn (stream, ".word 0x%x", field_b); |
| 1528 | } |
| 1529 | |
| 1530 | /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff |
| 1531 | (ie. the upper nibble is missing). */ |
| 1532 | int |
| 1533 | print_insn_sh (memaddr, info) |
| 1534 | bfd_vma memaddr; |
| 1535 | struct disassemble_info *info; |
| 1536 | { |
| 1537 | fprintf_ftype fprintf_fn = info->fprintf_func; |
| 1538 | void *stream = info->stream; |
| 1539 | unsigned char insn[4]; |
| 1540 | unsigned char nibs[8]; |
| 1541 | int status; |
| 1542 | bfd_vma relmask = ~(bfd_vma) 0; |
| 1543 | const sh_opcode_info *op; |
| 1544 | unsigned int target_arch; |
| 1545 | int allow_op32; |
| 1546 | |
| 1547 | switch (info->mach) |
| 1548 | { |
| 1549 | case bfd_mach_sh: |
| 1550 | target_arch = arch_sh1; |
| 1551 | break; |
| 1552 | case bfd_mach_sh4: |
| 1553 | target_arch = arch_sh4; |
| 1554 | break; |
| 1555 | case bfd_mach_sh5: |
| 1556 | #ifdef INCLUDE_SHMEDIA |
| 1557 | status = print_insn_sh64 (memaddr, info); |
| 1558 | if (status != -2) |
| 1559 | return status; |
| 1560 | #endif |
| 1561 | /* When we get here for sh64, it's because we want to disassemble |
| 1562 | SHcompact, i.e. arch_sh4. */ |
| 1563 | target_arch = arch_sh4; |
| 1564 | break; |
| 1565 | default: |
| 1566 | fprintf (stderr, "sh architecture not supported\n"); |
| 1567 | return -1; |
| 1568 | } |
| 1569 | |
| 1570 | status = info->read_memory_func (memaddr, insn, 2, info); |
| 1571 | |
| 1572 | if (status != 0) |
| 1573 | { |
| 1574 | info->memory_error_func (status, memaddr, info); |
| 1575 | return -1; |
| 1576 | } |
| 1577 | |
| 1578 | if (info->endian == BFD_ENDIAN_LITTLE) |
| 1579 | { |
| 1580 | nibs[0] = (insn[1] >> 4) & 0xf; |
| 1581 | nibs[1] = insn[1] & 0xf; |
| 1582 | |
| 1583 | nibs[2] = (insn[0] >> 4) & 0xf; |
| 1584 | nibs[3] = insn[0] & 0xf; |
| 1585 | } |
| 1586 | else |
| 1587 | { |
| 1588 | nibs[0] = (insn[0] >> 4) & 0xf; |
| 1589 | nibs[1] = insn[0] & 0xf; |
| 1590 | |
| 1591 | nibs[2] = (insn[1] >> 4) & 0xf; |
| 1592 | nibs[3] = insn[1] & 0xf; |
| 1593 | } |
| 1594 | status = info->read_memory_func (memaddr + 2, insn + 2, 2, info); |
| 1595 | if (status != 0) |
| 1596 | allow_op32 = 0; |
| 1597 | else |
| 1598 | { |
| 1599 | allow_op32 = 1; |
| 1600 | |
| 1601 | if (info->endian == BFD_ENDIAN_LITTLE) |
| 1602 | { |
| 1603 | nibs[4] = (insn[3] >> 4) & 0xf; |
| 1604 | nibs[5] = insn[3] & 0xf; |
| 1605 | |
| 1606 | nibs[6] = (insn[2] >> 4) & 0xf; |
| 1607 | nibs[7] = insn[2] & 0xf; |
| 1608 | } |
| 1609 | else |
| 1610 | { |
| 1611 | nibs[4] = (insn[2] >> 4) & 0xf; |
| 1612 | nibs[5] = insn[2] & 0xf; |
| 1613 | |
| 1614 | nibs[6] = (insn[3] >> 4) & 0xf; |
| 1615 | nibs[7] = insn[3] & 0xf; |
| 1616 | } |
| 1617 | } |
| 1618 | |
| 1619 | if (nibs[0] == 0xf && (nibs[1] & 4) == 0 |
| 1620 | && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up)) |
| 1621 | { |
| 1622 | if (nibs[1] & 8) |
| 1623 | { |
| 1624 | int field_b; |
| 1625 | |
| 1626 | status = info->read_memory_func (memaddr + 2, insn, 2, info); |
| 1627 | |
| 1628 | if (status != 0) |
| 1629 | { |
| 1630 | info->memory_error_func (status, memaddr + 2, info); |
| 1631 | return -1; |
| 1632 | } |
| 1633 | |
| 1634 | if (info->endian == BFD_ENDIAN_LITTLE) |
| 1635 | field_b = insn[1] << 8 | insn[0]; |
| 1636 | else |
| 1637 | field_b = insn[0] << 8 | insn[1]; |
| 1638 | |
| 1639 | print_insn_ppi (field_b, info); |
| 1640 | print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); |
| 1641 | return 4; |
| 1642 | } |
| 1643 | print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); |
| 1644 | return 2; |
| 1645 | } |
| 1646 | for (op = sh_table; op->name; op++) |
| 1647 | { |
| 1648 | int n; |
| 1649 | int imm = 0; |
| 1650 | int rn = 0; |
| 1651 | int rm = 0; |
| 1652 | int rb = 0; |
| 1653 | int disp_pc; |
| 1654 | bfd_vma disp_pc_addr = 0; |
| 1655 | int disp = 0; |
| 1656 | int has_disp = 0; |
| 1657 | int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4; |
| 1658 | |
| 1659 | if (!allow_op32 |
| 1660 | && SH_MERGE_ARCH_SET (op->arch, arch_op32)) |
| 1661 | goto fail; |
| 1662 | |
| 1663 | if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch)) |
| 1664 | goto fail; |
| 1665 | for (n = 0; n < max_n; n++) |
| 1666 | { |
| 1667 | int i = op->nibbles[n]; |
| 1668 | |
| 1669 | if (i < 16) |
| 1670 | { |
| 1671 | if (nibs[n] == i) |
| 1672 | continue; |
| 1673 | goto fail; |
| 1674 | } |
| 1675 | switch (i) |
| 1676 | { |
| 1677 | case BRANCH_8: |
| 1678 | imm = (nibs[2] << 4) | (nibs[3]); |
| 1679 | if (imm & 0x80) |
| 1680 | imm |= ~0xff; |
| 1681 | imm = ((char) imm) * 2 + 4; |
| 1682 | goto ok; |
| 1683 | case BRANCH_12: |
| 1684 | imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); |
| 1685 | if (imm & 0x800) |
| 1686 | imm |= ~0xfff; |
| 1687 | imm = imm * 2 + 4; |
| 1688 | goto ok; |
| 1689 | case IMM0_3c: |
| 1690 | if (nibs[3] & 0x8) |
| 1691 | goto fail; |
| 1692 | imm = nibs[3] & 0x7; |
| 1693 | break; |
| 1694 | case IMM0_3s: |
| 1695 | if (!(nibs[3] & 0x8)) |
| 1696 | goto fail; |
| 1697 | imm = nibs[3] & 0x7; |
| 1698 | break; |
| 1699 | case IMM0_3Uc: |
| 1700 | if (nibs[2] & 0x8) |
| 1701 | goto fail; |
| 1702 | imm = nibs[2] & 0x7; |
| 1703 | break; |
| 1704 | case IMM0_3Us: |
| 1705 | if (!(nibs[2] & 0x8)) |
| 1706 | goto fail; |
| 1707 | imm = nibs[2] & 0x7; |
| 1708 | break; |
| 1709 | case DISP0_12: |
| 1710 | case DISP1_12: |
| 1711 | disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7]; |
| 1712 | has_disp = 1; |
| 1713 | goto ok; |
| 1714 | case DISP0_12BY2: |
| 1715 | case DISP1_12BY2: |
| 1716 | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1; |
| 1717 | relmask = ~(bfd_vma) 1; |
| 1718 | has_disp = 1; |
| 1719 | goto ok; |
| 1720 | case DISP0_12BY4: |
| 1721 | case DISP1_12BY4: |
| 1722 | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2; |
| 1723 | relmask = ~(bfd_vma) 3; |
| 1724 | has_disp = 1; |
| 1725 | goto ok; |
| 1726 | case DISP0_12BY8: |
| 1727 | case DISP1_12BY8: |
| 1728 | disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3; |
| 1729 | relmask = ~(bfd_vma) 7; |
| 1730 | has_disp = 1; |
| 1731 | goto ok; |
| 1732 | case IMM0_20_4: |
| 1733 | break; |
| 1734 | case IMM0_20: |
| 1735 | imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) |
| 1736 | | (nibs[6] << 4) | nibs[7]); |
| 1737 | if (imm & 0x80000) |
| 1738 | imm -= 0x100000; |
| 1739 | goto ok; |
| 1740 | case IMM0_20BY8: |
| 1741 | imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8) |
| 1742 | | (nibs[6] << 4) | nibs[7]); |
| 1743 | imm <<= 8; |
| 1744 | if (imm & 0x8000000) |
| 1745 | imm -= 0x10000000; |
| 1746 | goto ok; |
| 1747 | case IMM0_4: |
| 1748 | case IMM1_4: |
| 1749 | imm = nibs[3]; |
| 1750 | goto ok; |
| 1751 | case IMM0_4BY2: |
| 1752 | case IMM1_4BY2: |
| 1753 | imm = nibs[3] << 1; |
| 1754 | goto ok; |
| 1755 | case IMM0_4BY4: |
| 1756 | case IMM1_4BY4: |
| 1757 | imm = nibs[3] << 2; |
| 1758 | goto ok; |
| 1759 | case IMM0_8: |
| 1760 | case IMM1_8: |
| 1761 | imm = (nibs[2] << 4) | nibs[3]; |
| 1762 | disp = imm; |
| 1763 | has_disp = 1; |
| 1764 | if (imm & 0x80) |
| 1765 | imm -= 0x100; |
| 1766 | goto ok; |
| 1767 | case PCRELIMM_8BY2: |
| 1768 | imm = ((nibs[2] << 4) | nibs[3]) << 1; |
| 1769 | relmask = ~(bfd_vma) 1; |
| 1770 | goto ok; |
| 1771 | case PCRELIMM_8BY4: |
| 1772 | imm = ((nibs[2] << 4) | nibs[3]) << 2; |
| 1773 | relmask = ~(bfd_vma) 3; |
| 1774 | goto ok; |
| 1775 | case IMM0_8BY2: |
| 1776 | case IMM1_8BY2: |
| 1777 | imm = ((nibs[2] << 4) | nibs[3]) << 1; |
| 1778 | goto ok; |
| 1779 | case IMM0_8BY4: |
| 1780 | case IMM1_8BY4: |
| 1781 | imm = ((nibs[2] << 4) | nibs[3]) << 2; |
| 1782 | goto ok; |
| 1783 | case REG_N_D: |
| 1784 | if ((nibs[n] & 1) != 0) |
| 1785 | goto fail; |
| 1786 | /* fall through */ |
| 1787 | case REG_N: |
| 1788 | rn = nibs[n]; |
| 1789 | break; |
| 1790 | case REG_M: |
| 1791 | rm = nibs[n]; |
| 1792 | break; |
| 1793 | case REG_N_B01: |
| 1794 | if ((nibs[n] & 0x3) != 1 /* binary 01 */) |
| 1795 | goto fail; |
| 1796 | rn = (nibs[n] & 0xc) >> 2; |
| 1797 | break; |
| 1798 | case REG_NM: |
| 1799 | rn = (nibs[n] & 0xc) >> 2; |
| 1800 | rm = (nibs[n] & 0x3); |
| 1801 | break; |
| 1802 | case REG_B: |
| 1803 | rb = nibs[n] & 0x07; |
| 1804 | break; |
| 1805 | case SDT_REG_N: |
| 1806 | /* sh-dsp: single data transfer. */ |
| 1807 | rn = nibs[n]; |
| 1808 | if ((rn & 0xc) != 4) |
| 1809 | goto fail; |
| 1810 | rn = rn & 0x3; |
| 1811 | rn |= (!(rn & 2)) << 2; |
| 1812 | break; |
| 1813 | case PPI: |
| 1814 | case REPEAT: |
| 1815 | goto fail; |
| 1816 | default: |
| 1817 | abort (); |
| 1818 | } |
| 1819 | } |
| 1820 | |
| 1821 | ok: |
| 1822 | /* sh2a has D_REG but not X_REG. We don't know the pattern |
| 1823 | doesn't match unless we check the output args to see if they |
| 1824 | make sense. */ |
| 1825 | if (target_arch == arch_sh2a |
| 1826 | && ((op->arg[0] == DX_REG_M && (rm & 1) != 0) |
| 1827 | || (op->arg[1] == DX_REG_N && (rn & 1) != 0))) |
| 1828 | goto fail; |
| 1829 | |
| 1830 | fprintf_fn (stream, "%s\t", op->name); |
| 1831 | disp_pc = 0; |
| 1832 | for (n = 0; n < 3 && op->arg[n] != A_END; n++) |
| 1833 | { |
| 1834 | if (n && op->arg[1] != A_END) |
| 1835 | fprintf_fn (stream, ","); |
| 1836 | switch (op->arg[n]) |
| 1837 | { |
| 1838 | case A_IMM: |
| 1839 | fprintf_fn (stream, "#%d", imm); |
| 1840 | break; |
| 1841 | case A_R0: |
| 1842 | fprintf_fn (stream, "r0"); |
| 1843 | break; |
| 1844 | case A_REG_N: |
| 1845 | fprintf_fn (stream, "r%d", rn); |
| 1846 | break; |
| 1847 | case A_INC_N: |
| 1848 | case AS_INC_N: |
| 1849 | fprintf_fn (stream, "@r%d+", rn); |
| 1850 | break; |
| 1851 | case A_DEC_N: |
| 1852 | case AS_DEC_N: |
| 1853 | fprintf_fn (stream, "@-r%d", rn); |
| 1854 | break; |
| 1855 | case A_IND_N: |
| 1856 | case AS_IND_N: |
| 1857 | fprintf_fn (stream, "@r%d", rn); |
| 1858 | break; |
| 1859 | case A_DISP_REG_N: |
| 1860 | fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn); |
| 1861 | break; |
| 1862 | case AS_PMOD_N: |
| 1863 | fprintf_fn (stream, "@r%d+r8", rn); |
| 1864 | break; |
| 1865 | case A_REG_M: |
| 1866 | fprintf_fn (stream, "r%d", rm); |
| 1867 | break; |
| 1868 | case A_INC_M: |
| 1869 | fprintf_fn (stream, "@r%d+", rm); |
| 1870 | break; |
| 1871 | case A_DEC_M: |
| 1872 | fprintf_fn (stream, "@-r%d", rm); |
| 1873 | break; |
| 1874 | case A_IND_M: |
| 1875 | fprintf_fn (stream, "@r%d", rm); |
| 1876 | break; |
| 1877 | case A_DISP_REG_M: |
| 1878 | fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm); |
| 1879 | break; |
| 1880 | case A_REG_B: |
| 1881 | fprintf_fn (stream, "r%d_bank", rb); |
| 1882 | break; |
| 1883 | case A_DISP_PC: |
| 1884 | disp_pc = 1; |
| 1885 | disp_pc_addr = imm + 4 + (memaddr & relmask); |
| 1886 | (*info->print_address_func) (disp_pc_addr, info); |
| 1887 | break; |
| 1888 | case A_IND_R0_REG_N: |
| 1889 | fprintf_fn (stream, "@(r0,r%d)", rn); |
| 1890 | break; |
| 1891 | case A_IND_R0_REG_M: |
| 1892 | fprintf_fn (stream, "@(r0,r%d)", rm); |
| 1893 | break; |
| 1894 | case A_DISP_GBR: |
| 1895 | fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm); |
| 1896 | break; |
| 1897 | case A_TBR: |
| 1898 | fprintf_fn (stream, "tbr"); |
| 1899 | break; |
| 1900 | case A_DISP2_TBR: |
| 1901 | fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm); |
| 1902 | break; |
| 1903 | case A_INC_R15: |
| 1904 | fprintf_fn (stream, "@r15+"); |
| 1905 | break; |
| 1906 | case A_DEC_R15: |
| 1907 | fprintf_fn (stream, "@-r15"); |
| 1908 | break; |
| 1909 | case A_R0_GBR: |
| 1910 | fprintf_fn (stream, "@(r0,gbr)"); |
| 1911 | break; |
| 1912 | case A_BDISP12: |
| 1913 | case A_BDISP8: |
| 1914 | { |
| 1915 | bfd_vma addr; |
| 1916 | addr = imm + memaddr; |
| 1917 | (*info->print_address_func) (addr, info); |
| 1918 | } |
| 1919 | break; |
| 1920 | case A_SR: |
| 1921 | fprintf_fn (stream, "sr"); |
| 1922 | break; |
| 1923 | case A_GBR: |
| 1924 | fprintf_fn (stream, "gbr"); |
| 1925 | break; |
| 1926 | case A_VBR: |
| 1927 | fprintf_fn (stream, "vbr"); |
| 1928 | break; |
| 1929 | case A_DSR: |
| 1930 | fprintf_fn (stream, "dsr"); |
| 1931 | break; |
| 1932 | case A_MOD: |
| 1933 | fprintf_fn (stream, "mod"); |
| 1934 | break; |
| 1935 | case A_RE: |
| 1936 | fprintf_fn (stream, "re"); |
| 1937 | break; |
| 1938 | case A_RS: |
| 1939 | fprintf_fn (stream, "rs"); |
| 1940 | break; |
| 1941 | case A_A0: |
| 1942 | fprintf_fn (stream, "a0"); |
| 1943 | break; |
| 1944 | case A_X0: |
| 1945 | fprintf_fn (stream, "x0"); |
| 1946 | break; |
| 1947 | case A_X1: |
| 1948 | fprintf_fn (stream, "x1"); |
| 1949 | break; |
| 1950 | case A_Y0: |
| 1951 | fprintf_fn (stream, "y0"); |
| 1952 | break; |
| 1953 | case A_Y1: |
| 1954 | fprintf_fn (stream, "y1"); |
| 1955 | break; |
| 1956 | case DSP_REG_M: |
| 1957 | print_dsp_reg (rm, fprintf_fn, stream); |
| 1958 | break; |
| 1959 | case A_SSR: |
| 1960 | fprintf_fn (stream, "ssr"); |
| 1961 | break; |
| 1962 | case A_SPC: |
| 1963 | fprintf_fn (stream, "spc"); |
| 1964 | break; |
| 1965 | case A_MACH: |
| 1966 | fprintf_fn (stream, "mach"); |
| 1967 | break; |
| 1968 | case A_MACL: |
| 1969 | fprintf_fn (stream, "macl"); |
| 1970 | break; |
| 1971 | case A_PR: |
| 1972 | fprintf_fn (stream, "pr"); |
| 1973 | break; |
| 1974 | case A_SGR: |
| 1975 | fprintf_fn (stream, "sgr"); |
| 1976 | break; |
| 1977 | case A_DBR: |
| 1978 | fprintf_fn (stream, "dbr"); |
| 1979 | break; |
| 1980 | case F_REG_N: |
| 1981 | fprintf_fn (stream, "fr%d", rn); |
| 1982 | break; |
| 1983 | case F_REG_M: |
| 1984 | fprintf_fn (stream, "fr%d", rm); |
| 1985 | break; |
| 1986 | case DX_REG_N: |
| 1987 | if (rn & 1) |
| 1988 | { |
| 1989 | fprintf_fn (stream, "xd%d", rn & ~1); |
| 1990 | break; |
| 1991 | } |
| 1992 | case D_REG_N: |
| 1993 | fprintf_fn (stream, "dr%d", rn); |
| 1994 | break; |
| 1995 | case DX_REG_M: |
| 1996 | if (rm & 1) |
| 1997 | { |
| 1998 | fprintf_fn (stream, "xd%d", rm & ~1); |
| 1999 | break; |
| 2000 | } |
| 2001 | case D_REG_M: |
| 2002 | fprintf_fn (stream, "dr%d", rm); |
| 2003 | break; |
| 2004 | case FPSCR_M: |
| 2005 | case FPSCR_N: |
| 2006 | fprintf_fn (stream, "fpscr"); |
| 2007 | break; |
| 2008 | case FPUL_M: |
| 2009 | case FPUL_N: |
| 2010 | fprintf_fn (stream, "fpul"); |
| 2011 | break; |
| 2012 | case F_FR0: |
| 2013 | fprintf_fn (stream, "fr0"); |
| 2014 | break; |
| 2015 | case V_REG_N: |
| 2016 | fprintf_fn (stream, "fv%d", rn * 4); |
| 2017 | break; |
| 2018 | case V_REG_M: |
| 2019 | fprintf_fn (stream, "fv%d", rm * 4); |
| 2020 | break; |
| 2021 | case XMTRX_M4: |
| 2022 | fprintf_fn (stream, "xmtrx"); |
| 2023 | break; |
| 2024 | default: |
| 2025 | abort (); |
| 2026 | } |
| 2027 | } |
| 2028 | |
| 2029 | #if 0 |
| 2030 | /* This code prints instructions in delay slots on the same line |
| 2031 | as the instruction which needs the delay slots. This can be |
| 2032 | confusing, since other disassembler don't work this way, and |
| 2033 | it means that the instructions are not all in a line. So I |
| 2034 | disabled it. Ian. */ |
| 2035 | if (!(info->flags & 1) |
| 2036 | && (op->name[0] == 'j' |
| 2037 | || (op->name[0] == 'b' |
| 2038 | && (op->name[1] == 'r' |
| 2039 | || op->name[1] == 's')) |
| 2040 | || (op->name[0] == 'r' && op->name[1] == 't') |
| 2041 | || (op->name[0] == 'b' && op->name[2] == '.'))) |
| 2042 | { |
| 2043 | info->flags |= 1; |
| 2044 | fprintf_fn (stream, "\t(slot "); |
| 2045 | print_insn_sh (memaddr + 2, info); |
| 2046 | info->flags &= ~1; |
| 2047 | fprintf_fn (stream, ")"); |
| 2048 | return 4; |
| 2049 | } |
| 2050 | #endif |
| 2051 | |
| 2052 | if (disp_pc && strcmp (op->name, "mova") != 0) |
| 2053 | { |
| 2054 | int size; |
| 2055 | bfd_byte bytes[4]; |
| 2056 | |
| 2057 | if (relmask == ~(bfd_vma) 1) |
| 2058 | size = 2; |
| 2059 | else |
| 2060 | size = 4; |
| 2061 | status = info->read_memory_func (disp_pc_addr, bytes, size, info); |
| 2062 | if (status == 0) |
| 2063 | { |
| 2064 | unsigned int val; |
| 2065 | |
| 2066 | if (size == 2) |
| 2067 | { |
| 2068 | if (info->endian == BFD_ENDIAN_LITTLE) |
| 2069 | val = bfd_getl16 (bytes); |
| 2070 | else |
| 2071 | val = bfd_getb16 (bytes); |
| 2072 | } |
| 2073 | else |
| 2074 | { |
| 2075 | if (info->endian == BFD_ENDIAN_LITTLE) |
| 2076 | val = bfd_getl32 (bytes); |
| 2077 | else |
| 2078 | val = bfd_getb32 (bytes); |
| 2079 | } |
| 2080 | if ((*info->symbol_at_address_func) (val, info)) |
| 2081 | { |
| 2082 | fprintf_fn (stream, "\t! 0x"); |
| 2083 | (*info->print_address_func) (val, info); |
| 2084 | } |
| 2085 | else |
| 2086 | fprintf_fn (stream, "\t! 0x%x", val); |
| 2087 | } |
| 2088 | } |
| 2089 | |
| 2090 | return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2; |
| 2091 | fail: |
| 2092 | ; |
| 2093 | |
| 2094 | } |
| 2095 | fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); |
| 2096 | return 2; |
| 2097 | } |