Paul Zimmerman | 104a010 | 2020-05-20 16:53:45 -0700 | [diff] [blame] | 1 | /* |
| 2 | * dwc-hsotg (dwc2) USB host controller state definitions |
| 3 | * |
| 4 | * Based on hw/usb/hcd-ehci.h |
| 5 | * |
| 6 | * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #ifndef HW_USB_DWC2_H |
| 20 | #define HW_USB_DWC2_H |
| 21 | |
| 22 | #include "qemu/timer.h" |
| 23 | #include "hw/irq.h" |
| 24 | #include "hw/sysbus.h" |
| 25 | #include "hw/usb.h" |
| 26 | #include "sysemu/dma.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 27 | #include "qom/object.h" |
Paul Zimmerman | 104a010 | 2020-05-20 16:53:45 -0700 | [diff] [blame] | 28 | |
| 29 | #define DWC2_MMIO_SIZE 0x11000 |
| 30 | |
| 31 | #define DWC2_NB_CHAN 8 /* Number of host channels */ |
| 32 | #define DWC2_MAX_XFER_SIZE 65536 /* Max transfer size expected in HCTSIZ */ |
| 33 | |
| 34 | typedef struct DWC2Packet DWC2Packet; |
| 35 | typedef struct DWC2State DWC2State; |
| 36 | typedef struct DWC2Class DWC2Class; |
| 37 | |
| 38 | enum async_state { |
| 39 | DWC2_ASYNC_NONE = 0, |
| 40 | DWC2_ASYNC_INITIALIZED, |
| 41 | DWC2_ASYNC_INFLIGHT, |
| 42 | DWC2_ASYNC_FINISHED, |
| 43 | }; |
| 44 | |
| 45 | struct DWC2Packet { |
| 46 | USBPacket packet; |
| 47 | uint32_t devadr; |
| 48 | uint32_t epnum; |
| 49 | uint32_t epdir; |
| 50 | uint32_t mps; |
| 51 | uint32_t pid; |
| 52 | uint32_t index; |
| 53 | uint32_t pcnt; |
| 54 | uint32_t len; |
| 55 | int32_t async; |
| 56 | bool small; |
| 57 | bool needs_service; |
| 58 | }; |
| 59 | |
| 60 | struct DWC2State { |
| 61 | /*< private >*/ |
| 62 | SysBusDevice parent_obj; |
| 63 | |
| 64 | /*< public >*/ |
| 65 | USBBus bus; |
| 66 | qemu_irq irq; |
| 67 | MemoryRegion *dma_mr; |
| 68 | AddressSpace dma_as; |
| 69 | MemoryRegion container; |
| 70 | MemoryRegion hsotg; |
| 71 | MemoryRegion fifos; |
| 72 | |
| 73 | union { |
| 74 | #define DWC2_GLBREG_SIZE 0x70 |
| 75 | uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)]; |
| 76 | struct { |
| 77 | uint32_t gotgctl; /* 00 */ |
| 78 | uint32_t gotgint; /* 04 */ |
| 79 | uint32_t gahbcfg; /* 08 */ |
| 80 | uint32_t gusbcfg; /* 0c */ |
| 81 | uint32_t grstctl; /* 10 */ |
| 82 | uint32_t gintsts; /* 14 */ |
| 83 | uint32_t gintmsk; /* 18 */ |
| 84 | uint32_t grxstsr; /* 1c */ |
| 85 | uint32_t grxstsp; /* 20 */ |
| 86 | uint32_t grxfsiz; /* 24 */ |
| 87 | uint32_t gnptxfsiz; /* 28 */ |
| 88 | uint32_t gnptxsts; /* 2c */ |
| 89 | uint32_t gi2cctl; /* 30 */ |
| 90 | uint32_t gpvndctl; /* 34 */ |
| 91 | uint32_t ggpio; /* 38 */ |
| 92 | uint32_t guid; /* 3c */ |
| 93 | uint32_t gsnpsid; /* 40 */ |
| 94 | uint32_t ghwcfg1; /* 44 */ |
| 95 | uint32_t ghwcfg2; /* 48 */ |
| 96 | uint32_t ghwcfg3; /* 4c */ |
| 97 | uint32_t ghwcfg4; /* 50 */ |
| 98 | uint32_t glpmcfg; /* 54 */ |
| 99 | uint32_t gpwrdn; /* 58 */ |
| 100 | uint32_t gdfifocfg; /* 5c */ |
| 101 | uint32_t gadpctl; /* 60 */ |
| 102 | uint32_t grefclk; /* 64 */ |
| 103 | uint32_t gintmsk2; /* 68 */ |
| 104 | uint32_t gintsts2; /* 6c */ |
| 105 | }; |
| 106 | }; |
| 107 | |
| 108 | union { |
| 109 | #define DWC2_FSZREG_SIZE 0x04 |
| 110 | uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)]; |
| 111 | struct { |
| 112 | uint32_t hptxfsiz; /* 100 */ |
| 113 | }; |
| 114 | }; |
| 115 | |
| 116 | union { |
| 117 | #define DWC2_HREG0_SIZE 0x44 |
| 118 | uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)]; |
| 119 | struct { |
| 120 | uint32_t hcfg; /* 400 */ |
| 121 | uint32_t hfir; /* 404 */ |
| 122 | uint32_t hfnum; /* 408 */ |
| 123 | uint32_t rsvd0; /* 40c */ |
| 124 | uint32_t hptxsts; /* 410 */ |
| 125 | uint32_t haint; /* 414 */ |
| 126 | uint32_t haintmsk; /* 418 */ |
| 127 | uint32_t hflbaddr; /* 41c */ |
| 128 | uint32_t rsvd1[8]; /* 420-43c */ |
| 129 | uint32_t hprt0; /* 440 */ |
| 130 | }; |
| 131 | }; |
| 132 | |
| 133 | #define DWC2_HREG1_SIZE (0x20 * DWC2_NB_CHAN) |
| 134 | uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)]; |
| 135 | |
| 136 | #define hcchar(_ch) hreg1[((_ch) << 3) + 0] /* 500, 520, ... */ |
| 137 | #define hcsplt(_ch) hreg1[((_ch) << 3) + 1] /* 504, 524, ... */ |
| 138 | #define hcint(_ch) hreg1[((_ch) << 3) + 2] /* 508, 528, ... */ |
| 139 | #define hcintmsk(_ch) hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */ |
| 140 | #define hctsiz(_ch) hreg1[((_ch) << 3) + 4] /* 510, 530, ... */ |
| 141 | #define hcdma(_ch) hreg1[((_ch) << 3) + 5] /* 514, 534, ... */ |
| 142 | #define hcdmab(_ch) hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */ |
| 143 | |
| 144 | union { |
| 145 | #define DWC2_PCGREG_SIZE 0x08 |
| 146 | uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)]; |
| 147 | struct { |
| 148 | uint32_t pcgctl; /* e00 */ |
| 149 | uint32_t pcgcctl1; /* e04 */ |
| 150 | }; |
| 151 | }; |
| 152 | |
| 153 | /* TODO - implement FIFO registers for slave mode */ |
| 154 | #define DWC2_HFIFO_SIZE (0x1000 * DWC2_NB_CHAN) |
| 155 | |
| 156 | /* |
| 157 | * Internal state |
| 158 | */ |
| 159 | QEMUTimer *eof_timer; |
| 160 | QEMUTimer *frame_timer; |
| 161 | QEMUBH *async_bh; |
| 162 | int64_t sof_time; |
| 163 | int64_t usb_frame_time; |
| 164 | int64_t usb_bit_time; |
| 165 | uint32_t usb_version; |
| 166 | uint16_t frame_number; |
| 167 | uint16_t fi; |
| 168 | uint16_t next_chan; |
| 169 | bool working; |
| 170 | USBPort uport; |
| 171 | DWC2Packet packet[DWC2_NB_CHAN]; /* one packet per chan */ |
| 172 | uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */ |
| 173 | }; |
| 174 | |
| 175 | struct DWC2Class { |
| 176 | /*< private >*/ |
| 177 | SysBusDeviceClass parent_class; |
| 178 | ResettablePhases parent_phases; |
| 179 | |
| 180 | /*< public >*/ |
| 181 | }; |
| 182 | |
| 183 | #define TYPE_DWC2_USB "dwc2-usb" |
Eduardo Habkost | 8110fa1 | 2020-08-31 17:07:33 -0400 | [diff] [blame] | 184 | DECLARE_OBJ_CHECKERS(DWC2State, DWC2Class, |
| 185 | DWC2_USB, TYPE_DWC2_USB) |
Paul Zimmerman | 104a010 | 2020-05-20 16:53:45 -0700 | [diff] [blame] | 186 | |
| 187 | #endif |