bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * common defines for all CPUs |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
| 20 | #ifndef CPU_DEFS_H |
| 21 | #define CPU_DEFS_H |
| 22 | |
| 23 | #include "config.h" |
| 24 | #include <setjmp.h> |
bellard | ed1c0bc | 2004-02-16 22:17:43 +0000 | [diff] [blame] | 25 | #include <inttypes.h> |
| 26 | #include "osdep.h" |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 27 | |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 28 | #ifndef TARGET_LONG_BITS |
| 29 | #error TARGET_LONG_BITS must be defined before including this header |
| 30 | #endif |
| 31 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 32 | #ifndef TARGET_PHYS_ADDR_BITS |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 33 | #if TARGET_LONG_BITS >= HOST_LONG_BITS |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 34 | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 35 | #else |
| 36 | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS |
| 37 | #endif |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 38 | #endif |
| 39 | |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 40 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
| 41 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 42 | /* target_ulong is the type of a virtual address */ |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 43 | #if TARGET_LONG_SIZE == 4 |
| 44 | typedef int32_t target_long; |
| 45 | typedef uint32_t target_ulong; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 46 | #define TARGET_FMT_lx "%08x" |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 47 | #elif TARGET_LONG_SIZE == 8 |
| 48 | typedef int64_t target_long; |
| 49 | typedef uint64_t target_ulong; |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 50 | #define TARGET_FMT_lx "%016" PRIx64 |
bellard | 35b66fc | 2004-01-24 15:26:06 +0000 | [diff] [blame] | 51 | #else |
| 52 | #error TARGET_LONG_SIZE undefined |
| 53 | #endif |
| 54 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 55 | /* target_phys_addr_t is the type of a physical address (its size can |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 56 | be different from 'target_ulong'). We have sizeof(target_phys_addr) |
| 57 | = max(sizeof(unsigned long), |
| 58 | sizeof(size_of_target_physical_address)) because we must pass a |
| 59 | host pointer to memory operations in some cases */ |
| 60 | |
bellard | ab6d960 | 2004-04-25 21:25:15 +0000 | [diff] [blame] | 61 | #if TARGET_PHYS_ADDR_BITS == 32 |
| 62 | typedef uint32_t target_phys_addr_t; |
| 63 | #elif TARGET_PHYS_ADDR_BITS == 64 |
| 64 | typedef uint64_t target_phys_addr_t; |
| 65 | #else |
| 66 | #error TARGET_PHYS_ADDR_BITS undefined |
| 67 | #endif |
| 68 | |
bellard | ff7b8f5 | 2005-08-21 09:24:05 +0000 | [diff] [blame] | 69 | /* address in the RAM (different from a physical address) */ |
| 70 | typedef unsigned long ram_addr_t; |
| 71 | |
bellard | f193c79 | 2004-03-21 17:06:25 +0000 | [diff] [blame] | 72 | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
| 73 | |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 74 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
| 75 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
| 76 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 77 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 78 | #define MAX_BREAKPOINTS 32 |
| 79 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 80 | #define TB_JMP_CACHE_BITS 12 |
| 81 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
| 82 | |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 83 | #define CPU_TLB_BITS 8 |
| 84 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 85 | |
| 86 | typedef struct CPUTLBEntry { |
bellard | db8d746 | 2003-10-27 21:12:17 +0000 | [diff] [blame] | 87 | /* bit 31 to TARGET_PAGE_BITS : virtual address |
| 88 | bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io |
| 89 | zone number |
| 90 | bit 3 : indicates that the entry is invalid |
| 91 | bit 2..0 : zero |
| 92 | */ |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 93 | target_ulong addr_read; |
| 94 | target_ulong addr_write; |
| 95 | target_ulong addr_code; |
bellard | db8d746 | 2003-10-27 21:12:17 +0000 | [diff] [blame] | 96 | /* addend to virtual address to get physical address */ |
bellard | 4f2ac23 | 2004-04-26 19:44:02 +0000 | [diff] [blame] | 97 | target_phys_addr_t addend; |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 98 | } CPUTLBEntry; |
| 99 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 100 | #define CPU_COMMON \ |
| 101 | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
| 102 | /* soft mmu support */ \ |
| 103 | /* in order to avoid passing too many arguments to the memory \ |
| 104 | write helpers, we store some rarely used information in the CPU \ |
| 105 | context) */ \ |
| 106 | unsigned long mem_write_pc; /* host pc at which the memory was \ |
| 107 | written */ \ |
| 108 | target_ulong mem_write_vaddr; /* target virtual addr at which the \ |
| 109 | memory was written */ \ |
| 110 | /* 0 = kernel, 1 = user */ \ |
bellard | 84b7b8e | 2005-11-28 21:19:04 +0000 | [diff] [blame] | 111 | CPUTLBEntry tlb_table[2][CPU_TLB_SIZE]; \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 112 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
| 113 | \ |
| 114 | /* from this point: preserved by CPU reset */ \ |
| 115 | /* ice debug support */ \ |
| 116 | target_ulong breakpoints[MAX_BREAKPOINTS]; \ |
| 117 | int nb_breakpoints; \ |
| 118 | int singlestep_enabled; \ |
| 119 | \ |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 120 | void *next_cpu; /* next CPU sharing TB cache */ \ |
| 121 | int cpu_index; /* CPU index (informative) */ \ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 122 | /* user data */ \ |
| 123 | void *opaque; |
| 124 | |
bellard | ab93bbe | 2003-08-10 21:35:13 +0000 | [diff] [blame] | 125 | #endif |