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bellardab93bbe2003-08-10 21:35:13 +00001/*
2 * common defines for all CPUs
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef CPU_DEFS_H
21#define CPU_DEFS_H
22
23#include "config.h"
24#include <setjmp.h>
bellarded1c0bc2004-02-16 22:17:43 +000025#include <inttypes.h>
26#include "osdep.h"
bellardab93bbe2003-08-10 21:35:13 +000027
bellard35b66fc2004-01-24 15:26:06 +000028#ifndef TARGET_LONG_BITS
29#error TARGET_LONG_BITS must be defined before including this header
30#endif
31
bellardab6d9602004-04-25 21:25:15 +000032#ifndef TARGET_PHYS_ADDR_BITS
bellard4f2ac232004-04-26 19:44:02 +000033#if TARGET_LONG_BITS >= HOST_LONG_BITS
bellardab6d9602004-04-25 21:25:15 +000034#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
bellard4f2ac232004-04-26 19:44:02 +000035#else
36#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
37#endif
bellardab6d9602004-04-25 21:25:15 +000038#endif
39
bellard35b66fc2004-01-24 15:26:06 +000040#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
41
bellardab6d9602004-04-25 21:25:15 +000042/* target_ulong is the type of a virtual address */
bellard35b66fc2004-01-24 15:26:06 +000043#if TARGET_LONG_SIZE == 4
44typedef int32_t target_long;
45typedef uint32_t target_ulong;
bellardc27004e2005-01-03 23:35:10 +000046#define TARGET_FMT_lx "%08x"
bellard35b66fc2004-01-24 15:26:06 +000047#elif TARGET_LONG_SIZE == 8
48typedef int64_t target_long;
49typedef uint64_t target_ulong;
bellard26a76462006-06-25 18:15:32 +000050#define TARGET_FMT_lx "%016" PRIx64
bellard35b66fc2004-01-24 15:26:06 +000051#else
52#error TARGET_LONG_SIZE undefined
53#endif
54
bellardab6d9602004-04-25 21:25:15 +000055/* target_phys_addr_t is the type of a physical address (its size can
bellard4f2ac232004-04-26 19:44:02 +000056 be different from 'target_ulong'). We have sizeof(target_phys_addr)
57 = max(sizeof(unsigned long),
58 sizeof(size_of_target_physical_address)) because we must pass a
59 host pointer to memory operations in some cases */
60
bellardab6d9602004-04-25 21:25:15 +000061#if TARGET_PHYS_ADDR_BITS == 32
62typedef uint32_t target_phys_addr_t;
63#elif TARGET_PHYS_ADDR_BITS == 64
64typedef uint64_t target_phys_addr_t;
65#else
66#error TARGET_PHYS_ADDR_BITS undefined
67#endif
68
bellardff7b8f52005-08-21 09:24:05 +000069/* address in the RAM (different from a physical address) */
70typedef unsigned long ram_addr_t;
71
bellardf193c792004-03-21 17:06:25 +000072#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
73
bellard2be00712005-07-02 22:09:27 +000074#define EXCP_INTERRUPT 0x10000 /* async interruption */
75#define EXCP_HLT 0x10001 /* hlt instruction reached */
76#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
bellard5a1e3cf2005-11-23 21:02:53 +000077#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
bellardab93bbe2003-08-10 21:35:13 +000078#define MAX_BREAKPOINTS 32
79
bellarda316d332005-11-20 10:32:34 +000080#define TB_JMP_CACHE_BITS 12
81#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
82
bellard84b7b8e2005-11-28 21:19:04 +000083#define CPU_TLB_BITS 8
84#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
bellardab93bbe2003-08-10 21:35:13 +000085
86typedef struct CPUTLBEntry {
bellarddb8d7462003-10-27 21:12:17 +000087 /* bit 31 to TARGET_PAGE_BITS : virtual address
88 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
89 zone number
90 bit 3 : indicates that the entry is invalid
91 bit 2..0 : zero
92 */
bellard84b7b8e2005-11-28 21:19:04 +000093 target_ulong addr_read;
94 target_ulong addr_write;
95 target_ulong addr_code;
bellarddb8d7462003-10-27 21:12:17 +000096 /* addend to virtual address to get physical address */
bellard4f2ac232004-04-26 19:44:02 +000097 target_phys_addr_t addend;
bellardab93bbe2003-08-10 21:35:13 +000098} CPUTLBEntry;
99
bellarda316d332005-11-20 10:32:34 +0000100#define CPU_COMMON \
101 struct TranslationBlock *current_tb; /* currently executing TB */ \
102 /* soft mmu support */ \
103 /* in order to avoid passing too many arguments to the memory \
104 write helpers, we store some rarely used information in the CPU \
105 context) */ \
106 unsigned long mem_write_pc; /* host pc at which the memory was \
107 written */ \
108 target_ulong mem_write_vaddr; /* target virtual addr at which the \
109 memory was written */ \
110 /* 0 = kernel, 1 = user */ \
bellard84b7b8e2005-11-28 21:19:04 +0000111 CPUTLBEntry tlb_table[2][CPU_TLB_SIZE]; \
bellarda316d332005-11-20 10:32:34 +0000112 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
113 \
114 /* from this point: preserved by CPU reset */ \
115 /* ice debug support */ \
116 target_ulong breakpoints[MAX_BREAKPOINTS]; \
117 int nb_breakpoints; \
118 int singlestep_enabled; \
119 \
bellard6a00d602005-11-21 23:25:50 +0000120 void *next_cpu; /* next CPU sharing TB cache */ \
121 int cpu_index; /* CPU index (informative) */ \
bellarda316d332005-11-20 10:32:34 +0000122 /* user data */ \
123 void *opaque;
124
bellardab93bbe2003-08-10 21:35:13 +0000125#endif