balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * TI OMAP processors emulation. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Nokia Corporation |
| 5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 or |
| 10 | * (at your option) version 3 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | #include "hw.h" |
| 23 | #include "arm-misc.h" |
| 24 | #include "omap.h" |
| 25 | #include "sysemu.h" |
| 26 | #include "qemu-timer.h" |
| 27 | #include "qemu-char.h" |
| 28 | #include "flash.h" |
balrog | afbb519 | 2008-07-21 20:40:22 +0000 | [diff] [blame] | 29 | #include "soc_dma.h" |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 30 | #include "audio/audio.h" |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 31 | |
| 32 | /* GP timers */ |
| 33 | struct omap_gp_timer_s { |
| 34 | qemu_irq irq; |
| 35 | qemu_irq wkup; |
| 36 | qemu_irq in; |
| 37 | qemu_irq out; |
| 38 | omap_clk clk; |
| 39 | target_phys_addr_t base; |
| 40 | QEMUTimer *timer; |
| 41 | QEMUTimer *match; |
| 42 | struct omap_target_agent_s *ta; |
| 43 | |
| 44 | int in_val; |
| 45 | int out_val; |
| 46 | int64_t time; |
| 47 | int64_t rate; |
| 48 | int64_t ticks_per_sec; |
| 49 | |
| 50 | int16_t config; |
| 51 | int status; |
| 52 | int it_ena; |
| 53 | int wu_ena; |
| 54 | int enable; |
| 55 | int inout; |
| 56 | int capt2; |
| 57 | int pt; |
| 58 | enum { |
| 59 | gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both |
| 60 | } trigger; |
| 61 | enum { |
| 62 | gpt_capture_none, gpt_capture_rising, |
| 63 | gpt_capture_falling, gpt_capture_both |
| 64 | } capture; |
| 65 | int scpwm; |
| 66 | int ce; |
| 67 | int pre; |
| 68 | int ptv; |
| 69 | int ar; |
| 70 | int st; |
| 71 | int posted; |
| 72 | uint32_t val; |
| 73 | uint32_t load_val; |
| 74 | uint32_t capture_val[2]; |
| 75 | uint32_t match_val; |
| 76 | int capt_num; |
| 77 | |
| 78 | uint16_t writeh; /* LSB */ |
| 79 | uint16_t readh; /* MSB */ |
| 80 | }; |
| 81 | |
| 82 | #define GPT_TCAR_IT (1 << 2) |
| 83 | #define GPT_OVF_IT (1 << 1) |
| 84 | #define GPT_MAT_IT (1 << 0) |
| 85 | |
| 86 | static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) |
| 87 | { |
| 88 | if (timer->it_ena & it) { |
| 89 | if (!timer->status) |
| 90 | qemu_irq_raise(timer->irq); |
| 91 | |
| 92 | timer->status |= it; |
| 93 | /* Or are the status bits set even when masked? |
| 94 | * i.e. is masking applied before or after the status register? */ |
| 95 | } |
| 96 | |
| 97 | if (timer->wu_ena & it) |
| 98 | qemu_irq_pulse(timer->wkup); |
| 99 | } |
| 100 | |
| 101 | static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) |
| 102 | { |
| 103 | if (!timer->inout && timer->out_val != level) { |
| 104 | timer->out_val = level; |
| 105 | qemu_set_irq(timer->out, level); |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) |
| 110 | { |
| 111 | uint64_t distance; |
| 112 | |
| 113 | if (timer->st && timer->rate) { |
| 114 | distance = qemu_get_clock(vm_clock) - timer->time; |
| 115 | distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); |
| 116 | |
| 117 | if (distance >= 0xffffffff - timer->val) |
| 118 | return 0xffffffff; |
| 119 | else |
| 120 | return timer->val + distance; |
| 121 | } else |
| 122 | return timer->val; |
| 123 | } |
| 124 | |
| 125 | static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) |
| 126 | { |
| 127 | if (timer->st) { |
| 128 | timer->val = omap_gp_timer_read(timer); |
| 129 | timer->time = qemu_get_clock(vm_clock); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) |
| 134 | { |
| 135 | int64_t expires, matches; |
| 136 | |
| 137 | if (timer->st && timer->rate) { |
| 138 | expires = muldiv64(0x100000000ll - timer->val, |
| 139 | timer->ticks_per_sec, timer->rate); |
| 140 | qemu_mod_timer(timer->timer, timer->time + expires); |
| 141 | |
| 142 | if (timer->ce && timer->match_val >= timer->val) { |
| 143 | matches = muldiv64(timer->match_val - timer->val, |
| 144 | timer->ticks_per_sec, timer->rate); |
| 145 | qemu_mod_timer(timer->match, timer->time + matches); |
| 146 | } else |
| 147 | qemu_del_timer(timer->match); |
| 148 | } else { |
| 149 | qemu_del_timer(timer->timer); |
| 150 | qemu_del_timer(timer->match); |
| 151 | omap_gp_timer_out(timer, timer->scpwm); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) |
| 156 | { |
| 157 | if (timer->pt) |
| 158 | /* TODO in overflow-and-match mode if the first event to |
| 159 | * occurs is the match, don't toggle. */ |
| 160 | omap_gp_timer_out(timer, !timer->out_val); |
| 161 | else |
| 162 | /* TODO inverted pulse on timer->out_val == 1? */ |
| 163 | qemu_irq_pulse(timer->out); |
| 164 | } |
| 165 | |
| 166 | static void omap_gp_timer_tick(void *opaque) |
| 167 | { |
| 168 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
| 169 | |
| 170 | if (!timer->ar) { |
| 171 | timer->st = 0; |
| 172 | timer->val = 0; |
| 173 | } else { |
| 174 | timer->val = timer->load_val; |
| 175 | timer->time = qemu_get_clock(vm_clock); |
| 176 | } |
| 177 | |
| 178 | if (timer->trigger == gpt_trigger_overflow || |
| 179 | timer->trigger == gpt_trigger_both) |
| 180 | omap_gp_timer_trigger(timer); |
| 181 | |
| 182 | omap_gp_timer_intr(timer, GPT_OVF_IT); |
| 183 | omap_gp_timer_update(timer); |
| 184 | } |
| 185 | |
| 186 | static void omap_gp_timer_match(void *opaque) |
| 187 | { |
| 188 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
| 189 | |
| 190 | if (timer->trigger == gpt_trigger_both) |
| 191 | omap_gp_timer_trigger(timer); |
| 192 | |
| 193 | omap_gp_timer_intr(timer, GPT_MAT_IT); |
| 194 | } |
| 195 | |
| 196 | static void omap_gp_timer_input(void *opaque, int line, int on) |
| 197 | { |
| 198 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
| 199 | int trigger; |
| 200 | |
| 201 | switch (s->capture) { |
| 202 | default: |
| 203 | case gpt_capture_none: |
| 204 | trigger = 0; |
| 205 | break; |
| 206 | case gpt_capture_rising: |
| 207 | trigger = !s->in_val && on; |
| 208 | break; |
| 209 | case gpt_capture_falling: |
| 210 | trigger = s->in_val && !on; |
| 211 | break; |
| 212 | case gpt_capture_both: |
| 213 | trigger = (s->in_val == !on); |
| 214 | break; |
| 215 | } |
| 216 | s->in_val = on; |
| 217 | |
| 218 | if (s->inout && trigger && s->capt_num < 2) { |
| 219 | s->capture_val[s->capt_num] = omap_gp_timer_read(s); |
| 220 | |
| 221 | if (s->capt2 == s->capt_num ++) |
| 222 | omap_gp_timer_intr(s, GPT_TCAR_IT); |
| 223 | } |
| 224 | } |
| 225 | |
| 226 | static void omap_gp_timer_clk_update(void *opaque, int line, int on) |
| 227 | { |
| 228 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
| 229 | |
| 230 | omap_gp_timer_sync(timer); |
| 231 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; |
| 232 | omap_gp_timer_update(timer); |
| 233 | } |
| 234 | |
| 235 | static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) |
| 236 | { |
| 237 | omap_clk_adduser(timer->clk, |
| 238 | qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]); |
| 239 | timer->rate = omap_clk_getrate(timer->clk); |
| 240 | } |
| 241 | |
| 242 | static void omap_gp_timer_reset(struct omap_gp_timer_s *s) |
| 243 | { |
| 244 | s->config = 0x000; |
| 245 | s->status = 0; |
| 246 | s->it_ena = 0; |
| 247 | s->wu_ena = 0; |
| 248 | s->inout = 0; |
| 249 | s->capt2 = 0; |
| 250 | s->capt_num = 0; |
| 251 | s->pt = 0; |
| 252 | s->trigger = gpt_trigger_none; |
| 253 | s->capture = gpt_capture_none; |
| 254 | s->scpwm = 0; |
| 255 | s->ce = 0; |
| 256 | s->pre = 0; |
| 257 | s->ptv = 0; |
| 258 | s->ar = 0; |
| 259 | s->st = 0; |
| 260 | s->posted = 1; |
| 261 | s->val = 0x00000000; |
| 262 | s->load_val = 0x00000000; |
| 263 | s->capture_val[0] = 0x00000000; |
| 264 | s->capture_val[1] = 0x00000000; |
| 265 | s->match_val = 0x00000000; |
| 266 | omap_gp_timer_update(s); |
| 267 | } |
| 268 | |
| 269 | static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) |
| 270 | { |
| 271 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
| 272 | int offset = addr - s->base; |
| 273 | |
| 274 | switch (offset) { |
| 275 | case 0x00: /* TIDR */ |
| 276 | return 0x21; |
| 277 | |
| 278 | case 0x10: /* TIOCP_CFG */ |
| 279 | return s->config; |
| 280 | |
| 281 | case 0x14: /* TISTAT */ |
| 282 | /* ??? When's this bit reset? */ |
| 283 | return 1; /* RESETDONE */ |
| 284 | |
| 285 | case 0x18: /* TISR */ |
| 286 | return s->status; |
| 287 | |
| 288 | case 0x1c: /* TIER */ |
| 289 | return s->it_ena; |
| 290 | |
| 291 | case 0x20: /* TWER */ |
| 292 | return s->wu_ena; |
| 293 | |
| 294 | case 0x24: /* TCLR */ |
| 295 | return (s->inout << 14) | |
| 296 | (s->capt2 << 13) | |
| 297 | (s->pt << 12) | |
| 298 | (s->trigger << 10) | |
| 299 | (s->capture << 8) | |
| 300 | (s->scpwm << 7) | |
| 301 | (s->ce << 6) | |
| 302 | (s->pre << 5) | |
| 303 | (s->ptv << 2) | |
| 304 | (s->ar << 1) | |
| 305 | (s->st << 0); |
| 306 | |
| 307 | case 0x28: /* TCRR */ |
| 308 | return omap_gp_timer_read(s); |
| 309 | |
| 310 | case 0x2c: /* TLDR */ |
| 311 | return s->load_val; |
| 312 | |
| 313 | case 0x30: /* TTGR */ |
| 314 | return 0xffffffff; |
| 315 | |
| 316 | case 0x34: /* TWPS */ |
| 317 | return 0x00000000; /* No posted writes pending. */ |
| 318 | |
| 319 | case 0x38: /* TMAR */ |
| 320 | return s->match_val; |
| 321 | |
| 322 | case 0x3c: /* TCAR1 */ |
| 323 | return s->capture_val[0]; |
| 324 | |
| 325 | case 0x40: /* TSICR */ |
| 326 | return s->posted << 2; |
| 327 | |
| 328 | case 0x44: /* TCAR2 */ |
| 329 | return s->capture_val[1]; |
| 330 | } |
| 331 | |
| 332 | OMAP_BAD_REG(addr); |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) |
| 337 | { |
| 338 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
| 339 | uint32_t ret; |
| 340 | |
| 341 | if (addr & 2) |
| 342 | return s->readh; |
| 343 | else { |
| 344 | ret = omap_gp_timer_readw(opaque, addr); |
| 345 | s->readh = ret >> 16; |
| 346 | return ret & 0xffff; |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | static CPUReadMemoryFunc *omap_gp_timer_readfn[] = { |
| 351 | omap_badwidth_read32, |
| 352 | omap_gp_timer_readh, |
| 353 | omap_gp_timer_readw, |
| 354 | }; |
| 355 | |
| 356 | static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, |
| 357 | uint32_t value) |
| 358 | { |
| 359 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
| 360 | int offset = addr - s->base; |
| 361 | |
| 362 | switch (offset) { |
| 363 | case 0x00: /* TIDR */ |
| 364 | case 0x14: /* TISTAT */ |
| 365 | case 0x34: /* TWPS */ |
| 366 | case 0x3c: /* TCAR1 */ |
| 367 | case 0x44: /* TCAR2 */ |
| 368 | OMAP_RO_REG(addr); |
| 369 | break; |
| 370 | |
| 371 | case 0x10: /* TIOCP_CFG */ |
| 372 | s->config = value & 0x33d; |
| 373 | if (((value >> 3) & 3) == 3) /* IDLEMODE */ |
| 374 | fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n", |
| 375 | __FUNCTION__); |
| 376 | if (value & 2) /* SOFTRESET */ |
| 377 | omap_gp_timer_reset(s); |
| 378 | break; |
| 379 | |
| 380 | case 0x18: /* TISR */ |
| 381 | if (value & GPT_TCAR_IT) |
| 382 | s->capt_num = 0; |
| 383 | if (s->status && !(s->status &= ~value)) |
| 384 | qemu_irq_lower(s->irq); |
| 385 | break; |
| 386 | |
| 387 | case 0x1c: /* TIER */ |
| 388 | s->it_ena = value & 7; |
| 389 | break; |
| 390 | |
| 391 | case 0x20: /* TWER */ |
| 392 | s->wu_ena = value & 7; |
| 393 | break; |
| 394 | |
| 395 | case 0x24: /* TCLR */ |
| 396 | omap_gp_timer_sync(s); |
| 397 | s->inout = (value >> 14) & 1; |
| 398 | s->capt2 = (value >> 13) & 1; |
| 399 | s->pt = (value >> 12) & 1; |
| 400 | s->trigger = (value >> 10) & 3; |
| 401 | if (s->capture == gpt_capture_none && |
| 402 | ((value >> 8) & 3) != gpt_capture_none) |
| 403 | s->capt_num = 0; |
| 404 | s->capture = (value >> 8) & 3; |
| 405 | s->scpwm = (value >> 7) & 1; |
| 406 | s->ce = (value >> 6) & 1; |
| 407 | s->pre = (value >> 5) & 1; |
| 408 | s->ptv = (value >> 2) & 7; |
| 409 | s->ar = (value >> 1) & 1; |
| 410 | s->st = (value >> 0) & 1; |
| 411 | if (s->inout && s->trigger != gpt_trigger_none) |
| 412 | fprintf(stderr, "%s: GP timer pin must be an output " |
| 413 | "for this trigger mode\n", __FUNCTION__); |
| 414 | if (!s->inout && s->capture != gpt_capture_none) |
| 415 | fprintf(stderr, "%s: GP timer pin must be an input " |
| 416 | "for this capture mode\n", __FUNCTION__); |
| 417 | if (s->trigger == gpt_trigger_none) |
| 418 | omap_gp_timer_out(s, s->scpwm); |
| 419 | /* TODO: make sure this doesn't overflow 32-bits */ |
| 420 | s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0); |
| 421 | omap_gp_timer_update(s); |
| 422 | break; |
| 423 | |
| 424 | case 0x28: /* TCRR */ |
| 425 | s->time = qemu_get_clock(vm_clock); |
| 426 | s->val = value; |
| 427 | omap_gp_timer_update(s); |
| 428 | break; |
| 429 | |
| 430 | case 0x2c: /* TLDR */ |
| 431 | s->load_val = value; |
| 432 | break; |
| 433 | |
| 434 | case 0x30: /* TTGR */ |
| 435 | s->time = qemu_get_clock(vm_clock); |
| 436 | s->val = s->load_val; |
| 437 | omap_gp_timer_update(s); |
| 438 | break; |
| 439 | |
| 440 | case 0x38: /* TMAR */ |
| 441 | omap_gp_timer_sync(s); |
| 442 | s->match_val = value; |
| 443 | omap_gp_timer_update(s); |
| 444 | break; |
| 445 | |
| 446 | case 0x40: /* TSICR */ |
| 447 | s->posted = (value >> 2) & 1; |
| 448 | if (value & 2) /* How much exactly are we supposed to reset? */ |
| 449 | omap_gp_timer_reset(s); |
| 450 | break; |
| 451 | |
| 452 | default: |
| 453 | OMAP_BAD_REG(addr); |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, |
| 458 | uint32_t value) |
| 459 | { |
| 460 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
| 461 | |
| 462 | if (addr & 2) |
| 463 | return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); |
| 464 | else |
| 465 | s->writeh = (uint16_t) value; |
| 466 | } |
| 467 | |
| 468 | static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = { |
| 469 | omap_badwidth_write32, |
| 470 | omap_gp_timer_writeh, |
| 471 | omap_gp_timer_write, |
| 472 | }; |
| 473 | |
| 474 | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
| 475 | qemu_irq irq, omap_clk fclk, omap_clk iclk) |
| 476 | { |
| 477 | int iomemtype; |
| 478 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) |
| 479 | qemu_mallocz(sizeof(struct omap_gp_timer_s)); |
| 480 | |
| 481 | s->ta = ta; |
| 482 | s->irq = irq; |
| 483 | s->clk = fclk; |
| 484 | s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s); |
| 485 | s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s); |
| 486 | s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0]; |
| 487 | omap_gp_timer_reset(s); |
| 488 | omap_gp_timer_clk_setup(s); |
| 489 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 490 | iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 491 | omap_gp_timer_writefn, s); |
| 492 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 493 | |
| 494 | return s; |
| 495 | } |
| 496 | |
| 497 | /* 32-kHz Sync Timer of the OMAP2 */ |
| 498 | static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { |
| 499 | return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec); |
| 500 | } |
| 501 | |
| 502 | static void omap_synctimer_reset(struct omap_synctimer_s *s) |
| 503 | { |
| 504 | s->val = omap_synctimer_read(s); |
| 505 | } |
| 506 | |
| 507 | static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) |
| 508 | { |
| 509 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
| 510 | int offset = addr - s->base; |
| 511 | |
| 512 | switch (offset) { |
| 513 | case 0x00: /* 32KSYNCNT_REV */ |
| 514 | return 0x21; |
| 515 | |
| 516 | case 0x10: /* CR */ |
| 517 | return omap_synctimer_read(s) - s->val; |
| 518 | } |
| 519 | |
| 520 | OMAP_BAD_REG(addr); |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr) |
| 525 | { |
| 526 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; |
| 527 | uint32_t ret; |
| 528 | |
| 529 | if (addr & 2) |
| 530 | return s->readh; |
| 531 | else { |
| 532 | ret = omap_synctimer_readw(opaque, addr); |
| 533 | s->readh = ret >> 16; |
| 534 | return ret & 0xffff; |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | static CPUReadMemoryFunc *omap_synctimer_readfn[] = { |
| 539 | omap_badwidth_read32, |
| 540 | omap_synctimer_readh, |
| 541 | omap_synctimer_readw, |
| 542 | }; |
| 543 | |
| 544 | static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, |
| 545 | uint32_t value) |
| 546 | { |
| 547 | OMAP_BAD_REG(addr); |
| 548 | } |
| 549 | |
| 550 | static CPUWriteMemoryFunc *omap_synctimer_writefn[] = { |
| 551 | omap_badwidth_write32, |
| 552 | omap_synctimer_write, |
| 553 | omap_synctimer_write, |
| 554 | }; |
| 555 | |
| 556 | void omap_synctimer_init(struct omap_target_agent_s *ta, |
| 557 | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk) |
| 558 | { |
| 559 | struct omap_synctimer_s *s = &mpu->synctimer; |
| 560 | |
| 561 | omap_synctimer_reset(s); |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 562 | s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 563 | omap_synctimer_readfn, omap_synctimer_writefn, s)); |
| 564 | } |
| 565 | |
| 566 | /* General-Purpose Interface of OMAP2 */ |
| 567 | struct omap2_gpio_s { |
| 568 | target_phys_addr_t base; |
| 569 | qemu_irq irq[2]; |
| 570 | qemu_irq wkup; |
| 571 | qemu_irq *in; |
| 572 | qemu_irq handler[32]; |
| 573 | |
| 574 | uint8_t config[2]; |
| 575 | uint32_t inputs; |
| 576 | uint32_t outputs; |
| 577 | uint32_t dir; |
| 578 | uint32_t level[2]; |
| 579 | uint32_t edge[2]; |
| 580 | uint32_t mask[2]; |
| 581 | uint32_t wumask; |
| 582 | uint32_t ints[2]; |
| 583 | uint32_t debounce; |
| 584 | uint8_t delay; |
| 585 | }; |
| 586 | |
| 587 | static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s, |
| 588 | int line) |
| 589 | { |
| 590 | qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); |
| 591 | } |
| 592 | |
| 593 | static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line) |
| 594 | { |
| 595 | if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ |
| 596 | return; |
| 597 | if (!(s->config[0] & (3 << 3))) /* Force Idle */ |
| 598 | return; |
| 599 | if (!(s->wumask & (1 << line))) |
| 600 | return; |
| 601 | |
| 602 | qemu_irq_raise(s->wkup); |
| 603 | } |
| 604 | |
| 605 | static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s, |
| 606 | uint32_t diff) |
| 607 | { |
| 608 | int ln; |
| 609 | |
| 610 | s->outputs ^= diff; |
| 611 | diff &= ~s->dir; |
| 612 | while ((ln = ffs(diff))) { |
| 613 | ln --; |
| 614 | qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); |
| 615 | diff &= ~(1 << ln); |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line) |
| 620 | { |
| 621 | s->ints[line] |= s->dir & |
| 622 | ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); |
| 623 | omap_gpio_module_int_update(s, line); |
| 624 | } |
| 625 | |
| 626 | static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line) |
| 627 | { |
| 628 | s->ints[0] |= 1 << line; |
| 629 | omap_gpio_module_int_update(s, 0); |
| 630 | s->ints[1] |= 1 << line; |
| 631 | omap_gpio_module_int_update(s, 1); |
| 632 | omap_gpio_module_wake(s, line); |
| 633 | } |
| 634 | |
| 635 | static void omap_gpio_module_set(void *opaque, int line, int level) |
| 636 | { |
| 637 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
| 638 | |
| 639 | if (level) { |
| 640 | if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) |
| 641 | omap_gpio_module_int(s, line); |
| 642 | s->inputs |= 1 << line; |
| 643 | } else { |
| 644 | if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) |
| 645 | omap_gpio_module_int(s, line); |
| 646 | s->inputs &= ~(1 << line); |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | static void omap_gpio_module_reset(struct omap2_gpio_s *s) |
| 651 | { |
| 652 | s->config[0] = 0; |
| 653 | s->config[1] = 2; |
| 654 | s->ints[0] = 0; |
| 655 | s->ints[1] = 0; |
| 656 | s->mask[0] = 0; |
| 657 | s->mask[1] = 0; |
| 658 | s->wumask = 0; |
| 659 | s->dir = ~0; |
| 660 | s->level[0] = 0; |
| 661 | s->level[1] = 0; |
| 662 | s->edge[0] = 0; |
| 663 | s->edge[1] = 0; |
| 664 | s->debounce = 0; |
| 665 | s->delay = 0; |
| 666 | } |
| 667 | |
| 668 | static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) |
| 669 | { |
| 670 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
| 671 | int offset = addr - s->base; |
| 672 | |
| 673 | switch (offset) { |
| 674 | case 0x00: /* GPIO_REVISION */ |
| 675 | return 0x18; |
| 676 | |
| 677 | case 0x10: /* GPIO_SYSCONFIG */ |
| 678 | return s->config[0]; |
| 679 | |
| 680 | case 0x14: /* GPIO_SYSSTATUS */ |
| 681 | return 0x01; |
| 682 | |
| 683 | case 0x18: /* GPIO_IRQSTATUS1 */ |
| 684 | return s->ints[0]; |
| 685 | |
| 686 | case 0x1c: /* GPIO_IRQENABLE1 */ |
| 687 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
| 688 | case 0x64: /* GPIO_SETIRQENABLE1 */ |
| 689 | return s->mask[0]; |
| 690 | |
| 691 | case 0x20: /* GPIO_WAKEUPENABLE */ |
| 692 | case 0x80: /* GPIO_CLEARWKUENA */ |
| 693 | case 0x84: /* GPIO_SETWKUENA */ |
| 694 | return s->wumask; |
| 695 | |
| 696 | case 0x28: /* GPIO_IRQSTATUS2 */ |
| 697 | return s->ints[1]; |
| 698 | |
| 699 | case 0x2c: /* GPIO_IRQENABLE2 */ |
| 700 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 701 | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 702 | return s->mask[1]; |
| 703 | |
| 704 | case 0x30: /* GPIO_CTRL */ |
| 705 | return s->config[1]; |
| 706 | |
| 707 | case 0x34: /* GPIO_OE */ |
| 708 | return s->dir; |
| 709 | |
| 710 | case 0x38: /* GPIO_DATAIN */ |
| 711 | return s->inputs; |
| 712 | |
| 713 | case 0x3c: /* GPIO_DATAOUT */ |
| 714 | case 0x90: /* GPIO_CLEARDATAOUT */ |
| 715 | case 0x94: /* GPIO_SETDATAOUT */ |
| 716 | return s->outputs; |
| 717 | |
| 718 | case 0x40: /* GPIO_LEVELDETECT0 */ |
| 719 | return s->level[0]; |
| 720 | |
| 721 | case 0x44: /* GPIO_LEVELDETECT1 */ |
| 722 | return s->level[1]; |
| 723 | |
| 724 | case 0x48: /* GPIO_RISINGDETECT */ |
| 725 | return s->edge[0]; |
| 726 | |
| 727 | case 0x4c: /* GPIO_FALLINGDETECT */ |
| 728 | return s->edge[1]; |
| 729 | |
| 730 | case 0x50: /* GPIO_DEBOUNCENABLE */ |
| 731 | return s->debounce; |
| 732 | |
| 733 | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 734 | return s->delay; |
| 735 | } |
| 736 | |
| 737 | OMAP_BAD_REG(addr); |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, |
| 742 | uint32_t value) |
| 743 | { |
| 744 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
| 745 | int offset = addr - s->base; |
| 746 | uint32_t diff; |
| 747 | int ln; |
| 748 | |
| 749 | switch (offset) { |
| 750 | case 0x00: /* GPIO_REVISION */ |
| 751 | case 0x14: /* GPIO_SYSSTATUS */ |
| 752 | case 0x38: /* GPIO_DATAIN */ |
| 753 | OMAP_RO_REG(addr); |
| 754 | break; |
| 755 | |
| 756 | case 0x10: /* GPIO_SYSCONFIG */ |
| 757 | if (((value >> 3) & 3) == 3) |
| 758 | fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__); |
| 759 | if (value & 2) |
| 760 | omap_gpio_module_reset(s); |
| 761 | s->config[0] = value & 0x1d; |
| 762 | break; |
| 763 | |
| 764 | case 0x18: /* GPIO_IRQSTATUS1 */ |
| 765 | if (s->ints[0] & value) { |
| 766 | s->ints[0] &= ~value; |
| 767 | omap_gpio_module_level_update(s, 0); |
| 768 | } |
| 769 | break; |
| 770 | |
| 771 | case 0x1c: /* GPIO_IRQENABLE1 */ |
| 772 | s->mask[0] = value; |
| 773 | omap_gpio_module_int_update(s, 0); |
| 774 | break; |
| 775 | |
| 776 | case 0x20: /* GPIO_WAKEUPENABLE */ |
| 777 | s->wumask = value; |
| 778 | break; |
| 779 | |
| 780 | case 0x28: /* GPIO_IRQSTATUS2 */ |
| 781 | if (s->ints[1] & value) { |
| 782 | s->ints[1] &= ~value; |
| 783 | omap_gpio_module_level_update(s, 1); |
| 784 | } |
| 785 | break; |
| 786 | |
| 787 | case 0x2c: /* GPIO_IRQENABLE2 */ |
| 788 | s->mask[1] = value; |
| 789 | omap_gpio_module_int_update(s, 1); |
| 790 | break; |
| 791 | |
| 792 | case 0x30: /* GPIO_CTRL */ |
| 793 | s->config[1] = value & 7; |
| 794 | break; |
| 795 | |
| 796 | case 0x34: /* GPIO_OE */ |
| 797 | diff = s->outputs & (s->dir ^ value); |
| 798 | s->dir = value; |
| 799 | |
| 800 | value = s->outputs & ~s->dir; |
| 801 | while ((ln = ffs(diff))) { |
| 802 | diff &= ~(1 <<-- ln); |
| 803 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
| 804 | } |
| 805 | |
| 806 | omap_gpio_module_level_update(s, 0); |
| 807 | omap_gpio_module_level_update(s, 1); |
| 808 | break; |
| 809 | |
| 810 | case 0x3c: /* GPIO_DATAOUT */ |
| 811 | omap_gpio_module_out_update(s, s->outputs ^ value); |
| 812 | break; |
| 813 | |
| 814 | case 0x40: /* GPIO_LEVELDETECT0 */ |
| 815 | s->level[0] = value; |
| 816 | omap_gpio_module_level_update(s, 0); |
| 817 | omap_gpio_module_level_update(s, 1); |
| 818 | break; |
| 819 | |
| 820 | case 0x44: /* GPIO_LEVELDETECT1 */ |
| 821 | s->level[1] = value; |
| 822 | omap_gpio_module_level_update(s, 0); |
| 823 | omap_gpio_module_level_update(s, 1); |
| 824 | break; |
| 825 | |
| 826 | case 0x48: /* GPIO_RISINGDETECT */ |
| 827 | s->edge[0] = value; |
| 828 | break; |
| 829 | |
| 830 | case 0x4c: /* GPIO_FALLINGDETECT */ |
| 831 | s->edge[1] = value; |
| 832 | break; |
| 833 | |
| 834 | case 0x50: /* GPIO_DEBOUNCENABLE */ |
| 835 | s->debounce = value; |
| 836 | break; |
| 837 | |
| 838 | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 839 | s->delay = value; |
| 840 | break; |
| 841 | |
| 842 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
| 843 | s->mask[0] &= ~value; |
| 844 | omap_gpio_module_int_update(s, 0); |
| 845 | break; |
| 846 | |
| 847 | case 0x64: /* GPIO_SETIRQENABLE1 */ |
| 848 | s->mask[0] |= value; |
| 849 | omap_gpio_module_int_update(s, 0); |
| 850 | break; |
| 851 | |
| 852 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 853 | s->mask[1] &= ~value; |
| 854 | omap_gpio_module_int_update(s, 1); |
| 855 | break; |
| 856 | |
| 857 | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 858 | s->mask[1] |= value; |
| 859 | omap_gpio_module_int_update(s, 1); |
| 860 | break; |
| 861 | |
| 862 | case 0x80: /* GPIO_CLEARWKUENA */ |
| 863 | s->wumask &= ~value; |
| 864 | break; |
| 865 | |
| 866 | case 0x84: /* GPIO_SETWKUENA */ |
| 867 | s->wumask |= value; |
| 868 | break; |
| 869 | |
| 870 | case 0x90: /* GPIO_CLEARDATAOUT */ |
| 871 | omap_gpio_module_out_update(s, s->outputs & value); |
| 872 | break; |
| 873 | |
| 874 | case 0x94: /* GPIO_SETDATAOUT */ |
| 875 | omap_gpio_module_out_update(s, ~s->outputs & value); |
| 876 | break; |
| 877 | |
| 878 | default: |
| 879 | OMAP_BAD_REG(addr); |
| 880 | return; |
| 881 | } |
| 882 | } |
| 883 | |
| 884 | static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr) |
| 885 | { |
| 886 | return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); |
| 887 | } |
| 888 | |
| 889 | static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr, |
| 890 | uint32_t value) |
| 891 | { |
| 892 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
| 893 | int offset = addr - s->base; |
| 894 | uint32_t cur = 0; |
| 895 | uint32_t mask = 0xffff; |
| 896 | |
| 897 | switch (offset & ~3) { |
| 898 | case 0x00: /* GPIO_REVISION */ |
| 899 | case 0x14: /* GPIO_SYSSTATUS */ |
| 900 | case 0x38: /* GPIO_DATAIN */ |
| 901 | OMAP_RO_REG(addr); |
| 902 | break; |
| 903 | |
| 904 | case 0x10: /* GPIO_SYSCONFIG */ |
| 905 | case 0x1c: /* GPIO_IRQENABLE1 */ |
| 906 | case 0x20: /* GPIO_WAKEUPENABLE */ |
| 907 | case 0x2c: /* GPIO_IRQENABLE2 */ |
| 908 | case 0x30: /* GPIO_CTRL */ |
| 909 | case 0x34: /* GPIO_OE */ |
| 910 | case 0x3c: /* GPIO_DATAOUT */ |
| 911 | case 0x40: /* GPIO_LEVELDETECT0 */ |
| 912 | case 0x44: /* GPIO_LEVELDETECT1 */ |
| 913 | case 0x48: /* GPIO_RISINGDETECT */ |
| 914 | case 0x4c: /* GPIO_FALLINGDETECT */ |
| 915 | case 0x50: /* GPIO_DEBOUNCENABLE */ |
| 916 | case 0x54: /* GPIO_DEBOUNCINGTIME */ |
| 917 | cur = omap_gpio_module_read(opaque, addr & ~3) & |
| 918 | ~(mask << ((addr & 3) << 3)); |
| 919 | |
| 920 | /* Fall through. */ |
| 921 | case 0x18: /* GPIO_IRQSTATUS1 */ |
| 922 | case 0x28: /* GPIO_IRQSTATUS2 */ |
| 923 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
| 924 | case 0x64: /* GPIO_SETIRQENABLE1 */ |
| 925 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
| 926 | case 0x74: /* GPIO_SETIREQNEABLE2 */ |
| 927 | case 0x80: /* GPIO_CLEARWKUENA */ |
| 928 | case 0x84: /* GPIO_SETWKUENA */ |
| 929 | case 0x90: /* GPIO_CLEARDATAOUT */ |
| 930 | case 0x94: /* GPIO_SETDATAOUT */ |
| 931 | value <<= (addr & 3) << 3; |
| 932 | omap_gpio_module_write(opaque, addr, cur | value); |
| 933 | break; |
| 934 | |
| 935 | default: |
| 936 | OMAP_BAD_REG(addr); |
| 937 | return; |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | static CPUReadMemoryFunc *omap_gpio_module_readfn[] = { |
| 942 | omap_gpio_module_readp, |
| 943 | omap_gpio_module_readp, |
| 944 | omap_gpio_module_read, |
| 945 | }; |
| 946 | |
| 947 | static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = { |
| 948 | omap_gpio_module_writep, |
| 949 | omap_gpio_module_writep, |
| 950 | omap_gpio_module_write, |
| 951 | }; |
| 952 | |
| 953 | static void omap_gpio_module_init(struct omap2_gpio_s *s, |
| 954 | struct omap_target_agent_s *ta, int region, |
| 955 | qemu_irq mpu, qemu_irq dsp, qemu_irq wkup, |
| 956 | omap_clk fclk, omap_clk iclk) |
| 957 | { |
| 958 | int iomemtype; |
| 959 | |
| 960 | s->irq[0] = mpu; |
| 961 | s->irq[1] = dsp; |
| 962 | s->wkup = wkup; |
| 963 | s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32); |
| 964 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 965 | iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 966 | omap_gpio_module_writefn, s); |
| 967 | s->base = omap_l4_attach(ta, region, iomemtype); |
| 968 | } |
| 969 | |
| 970 | struct omap_gpif_s { |
| 971 | struct omap2_gpio_s module[5]; |
| 972 | int modules; |
| 973 | |
| 974 | target_phys_addr_t topbase; |
| 975 | int autoidle; |
| 976 | int gpo; |
| 977 | }; |
| 978 | |
| 979 | static void omap_gpif_reset(struct omap_gpif_s *s) |
| 980 | { |
| 981 | int i; |
| 982 | |
| 983 | for (i = 0; i < s->modules; i ++) |
| 984 | omap_gpio_module_reset(s->module + i); |
| 985 | |
| 986 | s->autoidle = 0; |
| 987 | s->gpo = 0; |
| 988 | } |
| 989 | |
| 990 | static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) |
| 991 | { |
| 992 | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
| 993 | int offset = addr - s->topbase; |
| 994 | |
| 995 | switch (offset) { |
| 996 | case 0x00: /* IPGENERICOCPSPL_REVISION */ |
| 997 | return 0x18; |
| 998 | |
| 999 | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
| 1000 | return s->autoidle; |
| 1001 | |
| 1002 | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
| 1003 | return 0x01; |
| 1004 | |
| 1005 | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
| 1006 | return 0x00; |
| 1007 | |
| 1008 | case 0x40: /* IPGENERICOCPSPL_GPO */ |
| 1009 | return s->gpo; |
| 1010 | |
| 1011 | case 0x50: /* IPGENERICOCPSPL_GPI */ |
| 1012 | return 0x00; |
| 1013 | } |
| 1014 | |
| 1015 | OMAP_BAD_REG(addr); |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, |
| 1020 | uint32_t value) |
| 1021 | { |
| 1022 | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
| 1023 | int offset = addr - s->topbase; |
| 1024 | |
| 1025 | switch (offset) { |
| 1026 | case 0x00: /* IPGENERICOCPSPL_REVISION */ |
| 1027 | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
| 1028 | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
| 1029 | case 0x50: /* IPGENERICOCPSPL_GPI */ |
| 1030 | OMAP_RO_REG(addr); |
| 1031 | break; |
| 1032 | |
| 1033 | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
| 1034 | if (value & (1 << 1)) /* SOFTRESET */ |
| 1035 | omap_gpif_reset(s); |
| 1036 | s->autoidle = value & 1; |
| 1037 | break; |
| 1038 | |
| 1039 | case 0x40: /* IPGENERICOCPSPL_GPO */ |
| 1040 | s->gpo = value & 1; |
| 1041 | break; |
| 1042 | |
| 1043 | default: |
| 1044 | OMAP_BAD_REG(addr); |
| 1045 | return; |
| 1046 | } |
| 1047 | } |
| 1048 | |
| 1049 | static CPUReadMemoryFunc *omap_gpif_top_readfn[] = { |
| 1050 | omap_gpif_top_read, |
| 1051 | omap_gpif_top_read, |
| 1052 | omap_gpif_top_read, |
| 1053 | }; |
| 1054 | |
| 1055 | static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = { |
| 1056 | omap_gpif_top_write, |
| 1057 | omap_gpif_top_write, |
| 1058 | omap_gpif_top_write, |
| 1059 | }; |
| 1060 | |
| 1061 | struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
| 1062 | qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules) |
| 1063 | { |
| 1064 | int iomemtype, i; |
| 1065 | struct omap_gpif_s *s = (struct omap_gpif_s *) |
| 1066 | qemu_mallocz(sizeof(struct omap_gpif_s)); |
| 1067 | int region[4] = { 0, 2, 4, 5 }; |
| 1068 | |
| 1069 | s->modules = modules; |
| 1070 | for (i = 0; i < modules; i ++) |
| 1071 | omap_gpio_module_init(s->module + i, ta, region[i], |
| 1072 | irq[i], 0, 0, fclk[i], iclk); |
| 1073 | |
| 1074 | omap_gpif_reset(s); |
| 1075 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 1076 | iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1077 | omap_gpif_top_writefn, s); |
| 1078 | s->topbase = omap_l4_attach(ta, 1, iomemtype); |
| 1079 | |
| 1080 | return s; |
| 1081 | } |
| 1082 | |
| 1083 | qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start) |
| 1084 | { |
| 1085 | if (start >= s->modules * 32 || start < 0) |
| 1086 | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", |
| 1087 | __FUNCTION__, start); |
| 1088 | return s->module[start >> 5].in + (start & 31); |
| 1089 | } |
| 1090 | |
| 1091 | void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler) |
| 1092 | { |
| 1093 | if (line >= s->modules * 32 || line < 0) |
| 1094 | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); |
| 1095 | s->module[line >> 5].handler[line & 31] = handler; |
| 1096 | } |
| 1097 | |
| 1098 | /* Multichannel SPI */ |
| 1099 | struct omap_mcspi_s { |
| 1100 | target_phys_addr_t base; |
| 1101 | qemu_irq irq; |
| 1102 | int chnum; |
| 1103 | |
| 1104 | uint32_t sysconfig; |
| 1105 | uint32_t systest; |
| 1106 | uint32_t irqst; |
| 1107 | uint32_t irqen; |
| 1108 | uint32_t wken; |
| 1109 | uint32_t control; |
| 1110 | |
| 1111 | struct omap_mcspi_ch_s { |
| 1112 | qemu_irq txdrq; |
| 1113 | qemu_irq rxdrq; |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1114 | uint32_t (*txrx)(void *opaque, uint32_t, int); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1115 | void *opaque; |
| 1116 | |
| 1117 | uint32_t tx; |
| 1118 | uint32_t rx; |
| 1119 | |
| 1120 | uint32_t config; |
| 1121 | uint32_t status; |
| 1122 | uint32_t control; |
| 1123 | } ch[4]; |
| 1124 | }; |
| 1125 | |
| 1126 | static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) |
| 1127 | { |
| 1128 | qemu_set_irq(s->irq, s->irqst & s->irqen); |
| 1129 | } |
| 1130 | |
| 1131 | static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch) |
| 1132 | { |
| 1133 | qemu_set_irq(ch->txdrq, |
| 1134 | (ch->control & 1) && /* EN */ |
| 1135 | (ch->config & (1 << 14)) && /* DMAW */ |
| 1136 | (ch->status & (1 << 1)) && /* TXS */ |
| 1137 | ((ch->config >> 12) & 3) != 1); /* TRM */ |
| 1138 | qemu_set_irq(ch->rxdrq, |
| 1139 | (ch->control & 1) && /* EN */ |
| 1140 | (ch->config & (1 << 15)) && /* DMAW */ |
| 1141 | (ch->status & (1 << 0)) && /* RXS */ |
| 1142 | ((ch->config >> 12) & 3) != 2); /* TRM */ |
| 1143 | } |
| 1144 | |
| 1145 | static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum) |
| 1146 | { |
| 1147 | struct omap_mcspi_ch_s *ch = s->ch + chnum; |
| 1148 | |
| 1149 | if (!(ch->control & 1)) /* EN */ |
| 1150 | return; |
| 1151 | if ((ch->status & (1 << 0)) && /* RXS */ |
| 1152 | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
| 1153 | !(ch->config & (1 << 19))) /* TURBO */ |
| 1154 | goto intr_update; |
| 1155 | if ((ch->status & (1 << 1)) && /* TXS */ |
| 1156 | ((ch->config >> 12) & 3) != 1) /* TRM */ |
| 1157 | goto intr_update; |
| 1158 | |
| 1159 | if (!(s->control & 1) || /* SINGLE */ |
| 1160 | (ch->config & (1 << 20))) { /* FORCE */ |
| 1161 | if (ch->txrx) |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1162 | ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */ |
| 1163 | 1 + (0x1f & (ch->config >> 7))); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1164 | } |
| 1165 | |
| 1166 | ch->tx = 0; |
| 1167 | ch->status |= 1 << 2; /* EOT */ |
| 1168 | ch->status |= 1 << 1; /* TXS */ |
| 1169 | if (((ch->config >> 12) & 3) != 2) /* TRM */ |
| 1170 | ch->status |= 1 << 0; /* RXS */ |
| 1171 | |
| 1172 | intr_update: |
| 1173 | if ((ch->status & (1 << 0)) && /* RXS */ |
| 1174 | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
| 1175 | !(ch->config & (1 << 19))) /* TURBO */ |
| 1176 | s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */ |
| 1177 | if ((ch->status & (1 << 1)) && /* TXS */ |
| 1178 | ((ch->config >> 12) & 3) != 1) /* TRM */ |
| 1179 | s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */ |
| 1180 | omap_mcspi_interrupt_update(s); |
| 1181 | omap_mcspi_dmarequest_update(ch); |
| 1182 | } |
| 1183 | |
| 1184 | static void omap_mcspi_reset(struct omap_mcspi_s *s) |
| 1185 | { |
| 1186 | int ch; |
| 1187 | |
| 1188 | s->sysconfig = 0; |
| 1189 | s->systest = 0; |
| 1190 | s->irqst = 0; |
| 1191 | s->irqen = 0; |
| 1192 | s->wken = 0; |
| 1193 | s->control = 4; |
| 1194 | |
| 1195 | for (ch = 0; ch < 4; ch ++) { |
| 1196 | s->ch[ch].config = 0x060000; |
| 1197 | s->ch[ch].status = 2; /* TXS */ |
| 1198 | s->ch[ch].control = 0; |
| 1199 | |
| 1200 | omap_mcspi_dmarequest_update(s->ch + ch); |
| 1201 | } |
| 1202 | |
| 1203 | omap_mcspi_interrupt_update(s); |
| 1204 | } |
| 1205 | |
| 1206 | static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) |
| 1207 | { |
| 1208 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
| 1209 | int offset = addr - s->base; |
| 1210 | int ch = 0; |
| 1211 | uint32_t ret; |
| 1212 | |
| 1213 | switch (offset) { |
| 1214 | case 0x00: /* MCSPI_REVISION */ |
| 1215 | return 0x91; |
| 1216 | |
| 1217 | case 0x10: /* MCSPI_SYSCONFIG */ |
| 1218 | return s->sysconfig; |
| 1219 | |
| 1220 | case 0x14: /* MCSPI_SYSSTATUS */ |
| 1221 | return 1; /* RESETDONE */ |
| 1222 | |
| 1223 | case 0x18: /* MCSPI_IRQSTATUS */ |
| 1224 | return s->irqst; |
| 1225 | |
| 1226 | case 0x1c: /* MCSPI_IRQENABLE */ |
| 1227 | return s->irqen; |
| 1228 | |
| 1229 | case 0x20: /* MCSPI_WAKEUPENABLE */ |
| 1230 | return s->wken; |
| 1231 | |
| 1232 | case 0x24: /* MCSPI_SYST */ |
| 1233 | return s->systest; |
| 1234 | |
| 1235 | case 0x28: /* MCSPI_MODULCTRL */ |
| 1236 | return s->control; |
| 1237 | |
| 1238 | case 0x68: ch ++; |
| 1239 | case 0x54: ch ++; |
| 1240 | case 0x40: ch ++; |
| 1241 | case 0x2c: /* MCSPI_CHCONF */ |
| 1242 | return s->ch[ch].config; |
| 1243 | |
| 1244 | case 0x6c: ch ++; |
| 1245 | case 0x58: ch ++; |
| 1246 | case 0x44: ch ++; |
| 1247 | case 0x30: /* MCSPI_CHSTAT */ |
| 1248 | return s->ch[ch].status; |
| 1249 | |
| 1250 | case 0x70: ch ++; |
| 1251 | case 0x5c: ch ++; |
| 1252 | case 0x48: ch ++; |
| 1253 | case 0x34: /* MCSPI_CHCTRL */ |
| 1254 | return s->ch[ch].control; |
| 1255 | |
| 1256 | case 0x74: ch ++; |
| 1257 | case 0x60: ch ++; |
| 1258 | case 0x4c: ch ++; |
| 1259 | case 0x38: /* MCSPI_TX */ |
| 1260 | return s->ch[ch].tx; |
| 1261 | |
| 1262 | case 0x78: ch ++; |
| 1263 | case 0x64: ch ++; |
| 1264 | case 0x50: ch ++; |
| 1265 | case 0x3c: /* MCSPI_RX */ |
| 1266 | s->ch[ch].status &= ~(1 << 0); /* RXS */ |
| 1267 | ret = s->ch[ch].rx; |
| 1268 | omap_mcspi_transfer_run(s, ch); |
| 1269 | return ret; |
| 1270 | } |
| 1271 | |
| 1272 | OMAP_BAD_REG(addr); |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
| 1276 | static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, |
| 1277 | uint32_t value) |
| 1278 | { |
| 1279 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
| 1280 | int offset = addr - s->base; |
| 1281 | int ch = 0; |
| 1282 | |
| 1283 | switch (offset) { |
| 1284 | case 0x00: /* MCSPI_REVISION */ |
| 1285 | case 0x14: /* MCSPI_SYSSTATUS */ |
| 1286 | case 0x30: /* MCSPI_CHSTAT0 */ |
| 1287 | case 0x3c: /* MCSPI_RX0 */ |
| 1288 | case 0x44: /* MCSPI_CHSTAT1 */ |
| 1289 | case 0x50: /* MCSPI_RX1 */ |
| 1290 | case 0x58: /* MCSPI_CHSTAT2 */ |
| 1291 | case 0x64: /* MCSPI_RX2 */ |
| 1292 | case 0x6c: /* MCSPI_CHSTAT3 */ |
| 1293 | case 0x78: /* MCSPI_RX3 */ |
| 1294 | OMAP_RO_REG(addr); |
| 1295 | return; |
| 1296 | |
| 1297 | case 0x10: /* MCSPI_SYSCONFIG */ |
| 1298 | if (value & (1 << 1)) /* SOFTRESET */ |
| 1299 | omap_mcspi_reset(s); |
| 1300 | s->sysconfig = value & 0x31d; |
| 1301 | break; |
| 1302 | |
| 1303 | case 0x18: /* MCSPI_IRQSTATUS */ |
| 1304 | if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) { |
| 1305 | s->irqst &= ~value; |
| 1306 | omap_mcspi_interrupt_update(s); |
| 1307 | } |
| 1308 | break; |
| 1309 | |
| 1310 | case 0x1c: /* MCSPI_IRQENABLE */ |
| 1311 | s->irqen = value & 0x1777f; |
| 1312 | omap_mcspi_interrupt_update(s); |
| 1313 | break; |
| 1314 | |
| 1315 | case 0x20: /* MCSPI_WAKEUPENABLE */ |
| 1316 | s->wken = value & 1; |
| 1317 | break; |
| 1318 | |
| 1319 | case 0x24: /* MCSPI_SYST */ |
| 1320 | if (s->control & (1 << 3)) /* SYSTEM_TEST */ |
| 1321 | if (value & (1 << 11)) { /* SSB */ |
| 1322 | s->irqst |= 0x1777f; |
| 1323 | omap_mcspi_interrupt_update(s); |
| 1324 | } |
| 1325 | s->systest = value & 0xfff; |
| 1326 | break; |
| 1327 | |
| 1328 | case 0x28: /* MCSPI_MODULCTRL */ |
| 1329 | if (value & (1 << 3)) /* SYSTEM_TEST */ |
| 1330 | if (s->systest & (1 << 11)) { /* SSB */ |
| 1331 | s->irqst |= 0x1777f; |
| 1332 | omap_mcspi_interrupt_update(s); |
| 1333 | } |
| 1334 | s->control = value & 0xf; |
| 1335 | break; |
| 1336 | |
| 1337 | case 0x68: ch ++; |
| 1338 | case 0x54: ch ++; |
| 1339 | case 0x40: ch ++; |
| 1340 | case 0x2c: /* MCSPI_CHCONF */ |
| 1341 | if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ |
| 1342 | omap_mcspi_dmarequest_update(s->ch + ch); |
| 1343 | if (((value >> 12) & 3) == 3) /* TRM */ |
| 1344 | fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__); |
| 1345 | if (((value >> 7) & 0x1f) < 3) /* WL */ |
| 1346 | fprintf(stderr, "%s: invalid WL value (%i)\n", |
| 1347 | __FUNCTION__, (value >> 7) & 0x1f); |
| 1348 | s->ch[ch].config = value & 0x7fffff; |
| 1349 | break; |
| 1350 | |
| 1351 | case 0x70: ch ++; |
| 1352 | case 0x5c: ch ++; |
| 1353 | case 0x48: ch ++; |
| 1354 | case 0x34: /* MCSPI_CHCTRL */ |
| 1355 | if (value & ~s->ch[ch].control & 1) { /* EN */ |
| 1356 | s->ch[ch].control |= 1; |
| 1357 | omap_mcspi_transfer_run(s, ch); |
| 1358 | } else |
| 1359 | s->ch[ch].control = value & 1; |
| 1360 | break; |
| 1361 | |
| 1362 | case 0x74: ch ++; |
| 1363 | case 0x60: ch ++; |
| 1364 | case 0x4c: ch ++; |
| 1365 | case 0x38: /* MCSPI_TX */ |
| 1366 | s->ch[ch].tx = value; |
| 1367 | s->ch[ch].status &= ~(1 << 1); /* TXS */ |
| 1368 | omap_mcspi_transfer_run(s, ch); |
| 1369 | break; |
| 1370 | |
| 1371 | default: |
| 1372 | OMAP_BAD_REG(addr); |
| 1373 | return; |
| 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | static CPUReadMemoryFunc *omap_mcspi_readfn[] = { |
| 1378 | omap_badwidth_read32, |
| 1379 | omap_badwidth_read32, |
| 1380 | omap_mcspi_read, |
| 1381 | }; |
| 1382 | |
| 1383 | static CPUWriteMemoryFunc *omap_mcspi_writefn[] = { |
| 1384 | omap_badwidth_write32, |
| 1385 | omap_badwidth_write32, |
| 1386 | omap_mcspi_write, |
| 1387 | }; |
| 1388 | |
| 1389 | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
| 1390 | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
| 1391 | { |
| 1392 | int iomemtype; |
| 1393 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) |
| 1394 | qemu_mallocz(sizeof(struct omap_mcspi_s)); |
| 1395 | struct omap_mcspi_ch_s *ch = s->ch; |
| 1396 | |
| 1397 | s->irq = irq; |
| 1398 | s->chnum = chnum; |
| 1399 | while (chnum --) { |
| 1400 | ch->txdrq = *drq ++; |
| 1401 | ch->rxdrq = *drq ++; |
| 1402 | ch ++; |
| 1403 | } |
| 1404 | omap_mcspi_reset(s); |
| 1405 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 1406 | iomemtype = l4_register_io_memory(0, omap_mcspi_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1407 | omap_mcspi_writefn, s); |
| 1408 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 1409 | |
| 1410 | return s; |
| 1411 | } |
| 1412 | |
| 1413 | void omap_mcspi_attach(struct omap_mcspi_s *s, |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 1414 | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 1415 | int chipselect) |
| 1416 | { |
| 1417 | if (chipselect < 0 || chipselect >= s->chnum) |
| 1418 | cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", |
| 1419 | __FUNCTION__, chipselect); |
| 1420 | |
| 1421 | s->ch[chipselect].txrx = txrx; |
| 1422 | s->ch[chipselect].opaque = opaque; |
| 1423 | } |
| 1424 | |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1425 | /* Enhanced Audio Controller (CODEC only) */ |
| 1426 | struct omap_eac_s { |
| 1427 | target_phys_addr_t base; |
| 1428 | qemu_irq irq; |
| 1429 | |
| 1430 | uint16_t sysconfig; |
| 1431 | uint8_t config[4]; |
| 1432 | uint8_t control; |
| 1433 | uint8_t address; |
| 1434 | uint16_t data; |
| 1435 | uint8_t vtol; |
| 1436 | uint8_t vtsl; |
| 1437 | uint16_t mixer; |
| 1438 | uint16_t gain[4]; |
| 1439 | uint8_t att; |
| 1440 | uint16_t max[7]; |
| 1441 | |
| 1442 | struct { |
| 1443 | qemu_irq txdrq; |
| 1444 | qemu_irq rxdrq; |
| 1445 | uint32_t (*txrx)(void *opaque, uint32_t, int); |
| 1446 | void *opaque; |
| 1447 | |
| 1448 | #define EAC_BUF_LEN 1024 |
| 1449 | uint32_t rxbuf[EAC_BUF_LEN]; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1450 | int rxoff; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1451 | int rxlen; |
| 1452 | int rxavail; |
| 1453 | uint32_t txbuf[EAC_BUF_LEN]; |
| 1454 | int txlen; |
| 1455 | int txavail; |
| 1456 | |
| 1457 | int enable; |
| 1458 | int rate; |
| 1459 | |
| 1460 | uint16_t config[4]; |
| 1461 | |
| 1462 | /* These need to be moved to the actual codec */ |
| 1463 | QEMUSoundCard card; |
| 1464 | SWVoiceIn *in_voice; |
| 1465 | SWVoiceOut *out_voice; |
| 1466 | int hw_enable; |
| 1467 | } codec; |
| 1468 | |
| 1469 | struct { |
| 1470 | uint8_t control; |
| 1471 | uint16_t config; |
| 1472 | } modem, bt; |
| 1473 | }; |
| 1474 | |
| 1475 | static inline void omap_eac_interrupt_update(struct omap_eac_s *s) |
| 1476 | { |
| 1477 | qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ |
| 1478 | } |
| 1479 | |
| 1480 | static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) |
| 1481 | { |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1482 | qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) && |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1483 | ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ |
| 1484 | } |
| 1485 | |
| 1486 | static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) |
| 1487 | { |
| 1488 | qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && |
| 1489 | ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ |
| 1490 | } |
| 1491 | |
| 1492 | static inline void omap_eac_in_refill(struct omap_eac_s *s) |
| 1493 | { |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1494 | int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2; |
| 1495 | int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2; |
| 1496 | int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start); |
| 1497 | int recv = 1; |
| 1498 | uint8_t *buf = (uint8_t *) s->codec.rxbuf + start; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1499 | |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1500 | left -= leftwrap; |
| 1501 | start = 0; |
| 1502 | while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start, |
| 1503 | leftwrap)) > 0) { /* Be defensive */ |
| 1504 | start += recv; |
| 1505 | leftwrap -= recv; |
| 1506 | } |
| 1507 | if (recv <= 0) |
| 1508 | s->codec.rxavail = 0; |
| 1509 | else |
| 1510 | s->codec.rxavail -= start >> 2; |
| 1511 | s->codec.rxlen += start >> 2; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1512 | |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1513 | if (recv > 0 && left > 0) { |
| 1514 | start = 0; |
| 1515 | while (left && (recv = AUD_read(s->codec.in_voice, |
| 1516 | (uint8_t *) s->codec.rxbuf + start, |
| 1517 | left)) > 0) { /* Be defensive */ |
| 1518 | start += recv; |
| 1519 | left -= recv; |
| 1520 | } |
| 1521 | if (recv <= 0) |
| 1522 | s->codec.rxavail = 0; |
| 1523 | else |
| 1524 | s->codec.rxavail -= start >> 2; |
| 1525 | s->codec.rxlen += start >> 2; |
| 1526 | } |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1527 | } |
| 1528 | |
| 1529 | static inline void omap_eac_out_empty(struct omap_eac_s *s) |
| 1530 | { |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1531 | int left = s->codec.txlen << 2; |
| 1532 | int start = 0; |
| 1533 | int sent = 1; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1534 | |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1535 | while (left && (sent = AUD_write(s->codec.out_voice, |
| 1536 | (uint8_t *) s->codec.txbuf + start, |
| 1537 | left)) > 0) { /* Be defensive */ |
| 1538 | start += sent; |
| 1539 | left -= sent; |
| 1540 | } |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1541 | |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1542 | if (!sent) { |
| 1543 | s->codec.txavail = 0; |
| 1544 | omap_eac_out_dmarequest_update(s); |
| 1545 | } |
| 1546 | |
| 1547 | if (start) |
| 1548 | s->codec.txlen = 0; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1549 | } |
| 1550 | |
| 1551 | static void omap_eac_in_cb(void *opaque, int avail_b) |
| 1552 | { |
| 1553 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
| 1554 | |
| 1555 | s->codec.rxavail = avail_b >> 2; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1556 | omap_eac_in_refill(s); |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1557 | /* TODO: possibly discard current buffer if overrun */ |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1558 | omap_eac_in_dmarequest_update(s); |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1559 | } |
| 1560 | |
| 1561 | static void omap_eac_out_cb(void *opaque, int free_b) |
| 1562 | { |
| 1563 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
| 1564 | |
| 1565 | s->codec.txavail = free_b >> 2; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1566 | if (s->codec.txlen) |
| 1567 | omap_eac_out_empty(s); |
| 1568 | else |
| 1569 | omap_eac_out_dmarequest_update(s); |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1570 | } |
| 1571 | |
| 1572 | static void omap_eac_enable_update(struct omap_eac_s *s) |
| 1573 | { |
| 1574 | s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ |
| 1575 | (s->codec.config[1] & 2) && /* AUDEN */ |
| 1576 | s->codec.hw_enable; |
| 1577 | } |
| 1578 | |
| 1579 | static const int omap_eac_fsint[4] = { |
| 1580 | 8000, |
| 1581 | 11025, |
| 1582 | 22050, |
| 1583 | 44100, |
| 1584 | }; |
| 1585 | |
| 1586 | static const int omap_eac_fsint2[8] = { |
| 1587 | 8000, |
| 1588 | 11025, |
| 1589 | 22050, |
| 1590 | 44100, |
| 1591 | 48000, |
| 1592 | 0, 0, 0, |
| 1593 | }; |
| 1594 | |
| 1595 | static const int omap_eac_fsint3[16] = { |
| 1596 | 8000, |
| 1597 | 11025, |
| 1598 | 16000, |
| 1599 | 22050, |
| 1600 | 24000, |
| 1601 | 32000, |
| 1602 | 44100, |
| 1603 | 48000, |
| 1604 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 1605 | }; |
| 1606 | |
| 1607 | static void omap_eac_rate_update(struct omap_eac_s *s) |
| 1608 | { |
| 1609 | int fsint[3]; |
| 1610 | |
| 1611 | fsint[2] = (s->codec.config[3] >> 9) & 0xf; |
| 1612 | fsint[1] = (s->codec.config[2] >> 0) & 0x7; |
| 1613 | fsint[0] = (s->codec.config[0] >> 6) & 0x3; |
| 1614 | if (fsint[2] < 0xf) |
| 1615 | s->codec.rate = omap_eac_fsint3[fsint[2]]; |
| 1616 | else if (fsint[1] < 0x7) |
| 1617 | s->codec.rate = omap_eac_fsint2[fsint[1]]; |
| 1618 | else |
| 1619 | s->codec.rate = omap_eac_fsint[fsint[0]]; |
| 1620 | } |
| 1621 | |
| 1622 | static void omap_eac_volume_update(struct omap_eac_s *s) |
| 1623 | { |
| 1624 | /* TODO */ |
| 1625 | } |
| 1626 | |
| 1627 | static void omap_eac_format_update(struct omap_eac_s *s) |
| 1628 | { |
| 1629 | audsettings_t fmt; |
| 1630 | |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1631 | /* The hardware buffers at most one sample */ |
| 1632 | if (s->codec.rxlen) |
| 1633 | s->codec.rxlen = 1; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1634 | |
| 1635 | if (s->codec.in_voice) { |
| 1636 | AUD_set_active_in(s->codec.in_voice, 0); |
| 1637 | AUD_close_in(&s->codec.card, s->codec.in_voice); |
| 1638 | s->codec.in_voice = 0; |
| 1639 | } |
| 1640 | if (s->codec.out_voice) { |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1641 | omap_eac_out_empty(s); |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1642 | AUD_set_active_out(s->codec.out_voice, 0); |
| 1643 | AUD_close_out(&s->codec.card, s->codec.out_voice); |
| 1644 | s->codec.out_voice = 0; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1645 | s->codec.txavail = 0; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1646 | } |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1647 | /* Discard what couldn't be written */ |
| 1648 | s->codec.txlen = 0; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1649 | |
| 1650 | omap_eac_enable_update(s); |
| 1651 | if (!s->codec.enable) |
| 1652 | return; |
| 1653 | |
| 1654 | omap_eac_rate_update(s); |
| 1655 | fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ |
| 1656 | fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ |
| 1657 | fmt.freq = s->codec.rate; |
| 1658 | /* TODO: signedness possibly depends on the CODEC hardware - or |
| 1659 | * does I2S specify it? */ |
| 1660 | /* All register writes are 16 bits so we we store 16-bit samples |
| 1661 | * in the buffers regardless of AGCFR[B8_16] value. */ |
| 1662 | fmt.fmt = AUD_FMT_U16; |
| 1663 | |
| 1664 | s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, |
| 1665 | "eac.codec.in", s, omap_eac_in_cb, &fmt); |
| 1666 | s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, |
| 1667 | "eac.codec.out", s, omap_eac_out_cb, &fmt); |
| 1668 | |
| 1669 | omap_eac_volume_update(s); |
| 1670 | |
| 1671 | AUD_set_active_in(s->codec.in_voice, 1); |
| 1672 | AUD_set_active_out(s->codec.out_voice, 1); |
| 1673 | } |
| 1674 | |
| 1675 | static void omap_eac_reset(struct omap_eac_s *s) |
| 1676 | { |
| 1677 | s->sysconfig = 0; |
| 1678 | s->config[0] = 0x0c; |
| 1679 | s->config[1] = 0x09; |
| 1680 | s->config[2] = 0xab; |
| 1681 | s->config[3] = 0x03; |
| 1682 | s->control = 0x00; |
| 1683 | s->address = 0x00; |
| 1684 | s->data = 0x0000; |
| 1685 | s->vtol = 0x00; |
| 1686 | s->vtsl = 0x00; |
| 1687 | s->mixer = 0x0000; |
| 1688 | s->gain[0] = 0xe7e7; |
| 1689 | s->gain[1] = 0x6767; |
| 1690 | s->gain[2] = 0x6767; |
| 1691 | s->gain[3] = 0x6767; |
| 1692 | s->att = 0xce; |
| 1693 | s->max[0] = 0; |
| 1694 | s->max[1] = 0; |
| 1695 | s->max[2] = 0; |
| 1696 | s->max[3] = 0; |
| 1697 | s->max[4] = 0; |
| 1698 | s->max[5] = 0; |
| 1699 | s->max[6] = 0; |
| 1700 | |
| 1701 | s->modem.control = 0x00; |
| 1702 | s->modem.config = 0x0000; |
| 1703 | s->bt.control = 0x00; |
| 1704 | s->bt.config = 0x0000; |
| 1705 | s->codec.config[0] = 0x0649; |
| 1706 | s->codec.config[1] = 0x0000; |
| 1707 | s->codec.config[2] = 0x0007; |
| 1708 | s->codec.config[3] = 0x1ffc; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1709 | s->codec.rxoff = 0; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1710 | s->codec.rxlen = 0; |
| 1711 | s->codec.txlen = 0; |
| 1712 | s->codec.rxavail = 0; |
| 1713 | s->codec.txavail = 0; |
| 1714 | |
| 1715 | omap_eac_format_update(s); |
| 1716 | omap_eac_interrupt_update(s); |
| 1717 | } |
| 1718 | |
| 1719 | static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) |
| 1720 | { |
| 1721 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
| 1722 | int offset = addr - s->base; |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1723 | uint32_t ret; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1724 | |
| 1725 | switch (offset) { |
| 1726 | case 0x000: /* CPCFR1 */ |
| 1727 | return s->config[0]; |
| 1728 | case 0x004: /* CPCFR2 */ |
| 1729 | return s->config[1]; |
| 1730 | case 0x008: /* CPCFR3 */ |
| 1731 | return s->config[2]; |
| 1732 | case 0x00c: /* CPCFR4 */ |
| 1733 | return s->config[3]; |
| 1734 | |
| 1735 | case 0x010: /* CPTCTL */ |
| 1736 | return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | |
| 1737 | ((s->codec.txlen < s->codec.txavail) << 5); |
| 1738 | |
| 1739 | case 0x014: /* CPTTADR */ |
| 1740 | return s->address; |
| 1741 | case 0x018: /* CPTDATL */ |
| 1742 | return s->data & 0xff; |
| 1743 | case 0x01c: /* CPTDATH */ |
| 1744 | return s->data >> 8; |
| 1745 | case 0x020: /* CPTVSLL */ |
| 1746 | return s->vtol; |
| 1747 | case 0x024: /* CPTVSLH */ |
| 1748 | return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ |
| 1749 | case 0x040: /* MPCTR */ |
| 1750 | return s->modem.control; |
| 1751 | case 0x044: /* MPMCCFR */ |
| 1752 | return s->modem.config; |
| 1753 | case 0x060: /* BPCTR */ |
| 1754 | return s->bt.control; |
| 1755 | case 0x064: /* BPMCCFR */ |
| 1756 | return s->bt.config; |
| 1757 | case 0x080: /* AMSCFR */ |
| 1758 | return s->mixer; |
| 1759 | case 0x084: /* AMVCTR */ |
| 1760 | return s->gain[0]; |
| 1761 | case 0x088: /* AM1VCTR */ |
| 1762 | return s->gain[1]; |
| 1763 | case 0x08c: /* AM2VCTR */ |
| 1764 | return s->gain[2]; |
| 1765 | case 0x090: /* AM3VCTR */ |
| 1766 | return s->gain[3]; |
| 1767 | case 0x094: /* ASTCTR */ |
| 1768 | return s->att; |
| 1769 | case 0x098: /* APD1LCR */ |
| 1770 | return s->max[0]; |
| 1771 | case 0x09c: /* APD1RCR */ |
| 1772 | return s->max[1]; |
| 1773 | case 0x0a0: /* APD2LCR */ |
| 1774 | return s->max[2]; |
| 1775 | case 0x0a4: /* APD2RCR */ |
| 1776 | return s->max[3]; |
| 1777 | case 0x0a8: /* APD3LCR */ |
| 1778 | return s->max[4]; |
| 1779 | case 0x0ac: /* APD3RCR */ |
| 1780 | return s->max[5]; |
| 1781 | case 0x0b0: /* APD4R */ |
| 1782 | return s->max[6]; |
| 1783 | case 0x0b4: /* ADWR */ |
| 1784 | /* This should be write-only? Docs list it as read-only. */ |
| 1785 | return 0x0000; |
| 1786 | case 0x0b8: /* ADRDR */ |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1787 | if (likely(s->codec.rxlen > 1)) { |
| 1788 | ret = s->codec.rxbuf[s->codec.rxoff ++]; |
| 1789 | s->codec.rxlen --; |
| 1790 | s->codec.rxoff &= EAC_BUF_LEN - 1; |
| 1791 | return ret; |
| 1792 | } else if (s->codec.rxlen) { |
| 1793 | ret = s->codec.rxbuf[s->codec.rxoff ++]; |
| 1794 | s->codec.rxlen --; |
| 1795 | s->codec.rxoff &= EAC_BUF_LEN - 1; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1796 | if (s->codec.rxavail) |
| 1797 | omap_eac_in_refill(s); |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1798 | omap_eac_in_dmarequest_update(s); |
| 1799 | return ret; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1800 | } |
| 1801 | return 0x0000; |
| 1802 | case 0x0bc: /* AGCFR */ |
| 1803 | return s->codec.config[0]; |
| 1804 | case 0x0c0: /* AGCTR */ |
| 1805 | return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); |
| 1806 | case 0x0c4: /* AGCFR2 */ |
| 1807 | return s->codec.config[2]; |
| 1808 | case 0x0c8: /* AGCFR3 */ |
| 1809 | return s->codec.config[3]; |
| 1810 | case 0x0cc: /* MBPDMACTR */ |
| 1811 | case 0x0d0: /* MPDDMARR */ |
| 1812 | case 0x0d8: /* MPUDMARR */ |
| 1813 | case 0x0e4: /* BPDDMARR */ |
| 1814 | case 0x0ec: /* BPUDMARR */ |
| 1815 | return 0x0000; |
| 1816 | |
| 1817 | case 0x100: /* VERSION_NUMBER */ |
| 1818 | return 0x0010; |
| 1819 | |
| 1820 | case 0x104: /* SYSCONFIG */ |
| 1821 | return s->sysconfig; |
| 1822 | |
| 1823 | case 0x108: /* SYSSTATUS */ |
| 1824 | return 1 | 0xe; /* RESETDONE | stuff */ |
| 1825 | } |
| 1826 | |
| 1827 | OMAP_BAD_REG(addr); |
| 1828 | return 0; |
| 1829 | } |
| 1830 | |
| 1831 | static void omap_eac_write(void *opaque, target_phys_addr_t addr, |
| 1832 | uint32_t value) |
| 1833 | { |
| 1834 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; |
| 1835 | int offset = addr - s->base; |
| 1836 | |
| 1837 | switch (offset) { |
| 1838 | case 0x098: /* APD1LCR */ |
| 1839 | case 0x09c: /* APD1RCR */ |
| 1840 | case 0x0a0: /* APD2LCR */ |
| 1841 | case 0x0a4: /* APD2RCR */ |
| 1842 | case 0x0a8: /* APD3LCR */ |
| 1843 | case 0x0ac: /* APD3RCR */ |
| 1844 | case 0x0b0: /* APD4R */ |
| 1845 | case 0x0b8: /* ADRDR */ |
| 1846 | case 0x0d0: /* MPDDMARR */ |
| 1847 | case 0x0d8: /* MPUDMARR */ |
| 1848 | case 0x0e4: /* BPDDMARR */ |
| 1849 | case 0x0ec: /* BPUDMARR */ |
| 1850 | case 0x100: /* VERSION_NUMBER */ |
| 1851 | case 0x108: /* SYSSTATUS */ |
| 1852 | OMAP_RO_REG(addr); |
| 1853 | return; |
| 1854 | |
| 1855 | case 0x000: /* CPCFR1 */ |
| 1856 | s->config[0] = value & 0xff; |
| 1857 | omap_eac_format_update(s); |
| 1858 | break; |
| 1859 | case 0x004: /* CPCFR2 */ |
| 1860 | s->config[1] = value & 0xff; |
| 1861 | omap_eac_format_update(s); |
| 1862 | break; |
| 1863 | case 0x008: /* CPCFR3 */ |
| 1864 | s->config[2] = value & 0xff; |
| 1865 | omap_eac_format_update(s); |
| 1866 | break; |
| 1867 | case 0x00c: /* CPCFR4 */ |
| 1868 | s->config[3] = value & 0xff; |
| 1869 | omap_eac_format_update(s); |
| 1870 | break; |
| 1871 | |
| 1872 | case 0x010: /* CPTCTL */ |
| 1873 | /* Assuming TXF and TXE bits are read-only... */ |
| 1874 | s->control = value & 0x5f; |
| 1875 | omap_eac_interrupt_update(s); |
| 1876 | break; |
| 1877 | |
| 1878 | case 0x014: /* CPTTADR */ |
| 1879 | s->address = value & 0xff; |
| 1880 | break; |
| 1881 | case 0x018: /* CPTDATL */ |
| 1882 | s->data &= 0xff00; |
| 1883 | s->data |= value & 0xff; |
| 1884 | break; |
| 1885 | case 0x01c: /* CPTDATH */ |
| 1886 | s->data &= 0x00ff; |
| 1887 | s->data |= value << 8; |
| 1888 | break; |
| 1889 | case 0x020: /* CPTVSLL */ |
| 1890 | s->vtol = value & 0xf8; |
| 1891 | break; |
| 1892 | case 0x024: /* CPTVSLH */ |
| 1893 | s->vtsl = value & 0x9f; |
| 1894 | break; |
| 1895 | case 0x040: /* MPCTR */ |
| 1896 | s->modem.control = value & 0x8f; |
| 1897 | break; |
| 1898 | case 0x044: /* MPMCCFR */ |
| 1899 | s->modem.config = value & 0x7fff; |
| 1900 | break; |
| 1901 | case 0x060: /* BPCTR */ |
| 1902 | s->bt.control = value & 0x8f; |
| 1903 | break; |
| 1904 | case 0x064: /* BPMCCFR */ |
| 1905 | s->bt.config = value & 0x7fff; |
| 1906 | break; |
| 1907 | case 0x080: /* AMSCFR */ |
| 1908 | s->mixer = value & 0x0fff; |
| 1909 | break; |
| 1910 | case 0x084: /* AMVCTR */ |
| 1911 | s->gain[0] = value & 0xffff; |
| 1912 | break; |
| 1913 | case 0x088: /* AM1VCTR */ |
| 1914 | s->gain[1] = value & 0xff7f; |
| 1915 | break; |
| 1916 | case 0x08c: /* AM2VCTR */ |
| 1917 | s->gain[2] = value & 0xff7f; |
| 1918 | break; |
| 1919 | case 0x090: /* AM3VCTR */ |
| 1920 | s->gain[3] = value & 0xff7f; |
| 1921 | break; |
| 1922 | case 0x094: /* ASTCTR */ |
| 1923 | s->att = value & 0xff; |
| 1924 | break; |
| 1925 | |
| 1926 | case 0x0b4: /* ADWR */ |
| 1927 | s->codec.txbuf[s->codec.txlen ++] = value; |
| 1928 | if (unlikely(s->codec.txlen == EAC_BUF_LEN || |
| 1929 | s->codec.txlen == s->codec.txavail)) { |
| 1930 | if (s->codec.txavail) |
| 1931 | omap_eac_out_empty(s); |
balrog | ab17b46 | 2008-07-29 17:29:41 +0000 | [diff] [blame] | 1932 | /* Discard what couldn't be written */ |
| 1933 | s->codec.txlen = 0; |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 1934 | } |
| 1935 | break; |
| 1936 | |
| 1937 | case 0x0bc: /* AGCFR */ |
| 1938 | s->codec.config[0] = value & 0x07ff; |
| 1939 | omap_eac_format_update(s); |
| 1940 | break; |
| 1941 | case 0x0c0: /* AGCTR */ |
| 1942 | s->codec.config[1] = value & 0x780f; |
| 1943 | omap_eac_format_update(s); |
| 1944 | break; |
| 1945 | case 0x0c4: /* AGCFR2 */ |
| 1946 | s->codec.config[2] = value & 0x003f; |
| 1947 | omap_eac_format_update(s); |
| 1948 | break; |
| 1949 | case 0x0c8: /* AGCFR3 */ |
| 1950 | s->codec.config[3] = value & 0xffff; |
| 1951 | omap_eac_format_update(s); |
| 1952 | break; |
| 1953 | case 0x0cc: /* MBPDMACTR */ |
| 1954 | case 0x0d4: /* MPDDMAWR */ |
| 1955 | case 0x0e0: /* MPUDMAWR */ |
| 1956 | case 0x0e8: /* BPDDMAWR */ |
| 1957 | case 0x0f0: /* BPUDMAWR */ |
| 1958 | break; |
| 1959 | |
| 1960 | case 0x104: /* SYSCONFIG */ |
| 1961 | if (value & (1 << 1)) /* SOFTRESET */ |
| 1962 | omap_eac_reset(s); |
| 1963 | s->sysconfig = value & 0x31d; |
| 1964 | break; |
| 1965 | |
| 1966 | default: |
| 1967 | OMAP_BAD_REG(addr); |
| 1968 | return; |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | static CPUReadMemoryFunc *omap_eac_readfn[] = { |
| 1973 | omap_badwidth_read16, |
| 1974 | omap_eac_read, |
| 1975 | omap_badwidth_read16, |
| 1976 | }; |
| 1977 | |
| 1978 | static CPUWriteMemoryFunc *omap_eac_writefn[] = { |
| 1979 | omap_badwidth_write16, |
| 1980 | omap_eac_write, |
| 1981 | omap_badwidth_write16, |
| 1982 | }; |
| 1983 | |
| 1984 | struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
| 1985 | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
| 1986 | { |
| 1987 | int iomemtype; |
| 1988 | struct omap_eac_s *s = (struct omap_eac_s *) |
| 1989 | qemu_mallocz(sizeof(struct omap_eac_s)); |
| 1990 | |
| 1991 | s->irq = irq; |
| 1992 | s->codec.rxdrq = *drq ++; |
| 1993 | s->codec.txdrq = *drq ++; |
| 1994 | omap_eac_reset(s); |
| 1995 | |
| 1996 | #ifdef HAS_AUDIO |
| 1997 | /* TODO: do AUD_init globally for machine */ |
| 1998 | AUD_register_card(AUD_init(), "OMAP EAC", &s->codec.card); |
| 1999 | |
| 2000 | iomemtype = cpu_register_io_memory(0, omap_eac_readfn, |
| 2001 | omap_eac_writefn, s); |
| 2002 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 2003 | #endif |
| 2004 | |
| 2005 | return s; |
| 2006 | } |
| 2007 | |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 2008 | /* STI/XTI (emulation interface) console - reverse engineered only */ |
| 2009 | struct omap_sti_s { |
| 2010 | target_phys_addr_t base; |
| 2011 | target_phys_addr_t channel_base; |
| 2012 | qemu_irq irq; |
| 2013 | CharDriverState *chr; |
| 2014 | |
| 2015 | uint32_t sysconfig; |
| 2016 | uint32_t systest; |
| 2017 | uint32_t irqst; |
| 2018 | uint32_t irqen; |
| 2019 | uint32_t clkcontrol; |
| 2020 | uint32_t serial_config; |
| 2021 | }; |
| 2022 | |
| 2023 | #define STI_TRACE_CONSOLE_CHANNEL 239 |
| 2024 | #define STI_TRACE_CONTROL_CHANNEL 253 |
| 2025 | |
| 2026 | static inline void omap_sti_interrupt_update(struct omap_sti_s *s) |
| 2027 | { |
| 2028 | qemu_set_irq(s->irq, s->irqst & s->irqen); |
| 2029 | } |
| 2030 | |
| 2031 | static void omap_sti_reset(struct omap_sti_s *s) |
| 2032 | { |
| 2033 | s->sysconfig = 0; |
| 2034 | s->irqst = 0; |
| 2035 | s->irqen = 0; |
| 2036 | s->clkcontrol = 0; |
| 2037 | s->serial_config = 0; |
| 2038 | |
| 2039 | omap_sti_interrupt_update(s); |
| 2040 | } |
| 2041 | |
| 2042 | static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) |
| 2043 | { |
| 2044 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 2045 | int offset = addr - s->base; |
| 2046 | |
| 2047 | switch (offset) { |
| 2048 | case 0x00: /* STI_REVISION */ |
| 2049 | return 0x10; |
| 2050 | |
| 2051 | case 0x10: /* STI_SYSCONFIG */ |
| 2052 | return s->sysconfig; |
| 2053 | |
| 2054 | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
| 2055 | return 0x00; |
| 2056 | |
| 2057 | case 0x18: /* STI_IRQSTATUS */ |
| 2058 | return s->irqst; |
| 2059 | |
| 2060 | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
| 2061 | return s->irqen; |
| 2062 | |
| 2063 | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
| 2064 | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 2065 | /* TODO */ |
| 2066 | return 0; |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 2067 | |
| 2068 | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
| 2069 | return s->clkcontrol; |
| 2070 | |
| 2071 | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
| 2072 | return s->serial_config; |
| 2073 | } |
| 2074 | |
| 2075 | OMAP_BAD_REG(addr); |
| 2076 | return 0; |
| 2077 | } |
| 2078 | |
| 2079 | static void omap_sti_write(void *opaque, target_phys_addr_t addr, |
| 2080 | uint32_t value) |
| 2081 | { |
| 2082 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 2083 | int offset = addr - s->base; |
| 2084 | |
| 2085 | switch (offset) { |
| 2086 | case 0x00: /* STI_REVISION */ |
| 2087 | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ |
| 2088 | OMAP_RO_REG(addr); |
| 2089 | return; |
| 2090 | |
| 2091 | case 0x10: /* STI_SYSCONFIG */ |
| 2092 | if (value & (1 << 1)) /* SOFTRESET */ |
| 2093 | omap_sti_reset(s); |
| 2094 | s->sysconfig = value & 0xfe; |
| 2095 | break; |
| 2096 | |
| 2097 | case 0x18: /* STI_IRQSTATUS */ |
| 2098 | s->irqst &= ~value; |
| 2099 | omap_sti_interrupt_update(s); |
| 2100 | break; |
| 2101 | |
| 2102 | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ |
| 2103 | s->irqen = value & 0xffff; |
| 2104 | omap_sti_interrupt_update(s); |
| 2105 | break; |
| 2106 | |
| 2107 | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ |
| 2108 | s->clkcontrol = value & 0xff; |
| 2109 | break; |
| 2110 | |
| 2111 | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ |
| 2112 | s->serial_config = value & 0xff; |
| 2113 | break; |
| 2114 | |
| 2115 | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ |
| 2116 | case 0x28: /* STI_RX_DR / XTI_RXDATA */ |
balrog | e927bb0 | 2008-05-07 14:30:38 +0000 | [diff] [blame] | 2117 | /* TODO */ |
| 2118 | return; |
| 2119 | |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 2120 | default: |
| 2121 | OMAP_BAD_REG(addr); |
| 2122 | return; |
| 2123 | } |
| 2124 | } |
| 2125 | |
| 2126 | static CPUReadMemoryFunc *omap_sti_readfn[] = { |
| 2127 | omap_badwidth_read32, |
| 2128 | omap_badwidth_read32, |
| 2129 | omap_sti_read, |
| 2130 | }; |
| 2131 | |
| 2132 | static CPUWriteMemoryFunc *omap_sti_writefn[] = { |
| 2133 | omap_badwidth_write32, |
| 2134 | omap_badwidth_write32, |
| 2135 | omap_sti_write, |
| 2136 | }; |
| 2137 | |
| 2138 | static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) |
| 2139 | { |
| 2140 | OMAP_BAD_REG(addr); |
| 2141 | return 0; |
| 2142 | } |
| 2143 | |
| 2144 | static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, |
| 2145 | uint32_t value) |
| 2146 | { |
| 2147 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; |
| 2148 | int offset = addr - s->channel_base; |
| 2149 | int ch = offset >> 6; |
| 2150 | uint8_t byte = value; |
| 2151 | |
| 2152 | if (ch == STI_TRACE_CONTROL_CHANNEL) { |
| 2153 | /* Flush channel <i>value</i>. */ |
| 2154 | qemu_chr_write(s->chr, "\r", 1); |
| 2155 | } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { |
| 2156 | if (value == 0xc0 || value == 0xc3) { |
| 2157 | /* Open channel <i>ch</i>. */ |
| 2158 | } else if (value == 0x00) |
| 2159 | qemu_chr_write(s->chr, "\n", 1); |
| 2160 | else |
| 2161 | qemu_chr_write(s->chr, &byte, 1); |
| 2162 | } |
| 2163 | } |
| 2164 | |
| 2165 | static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = { |
| 2166 | omap_sti_fifo_read, |
| 2167 | omap_badwidth_read8, |
| 2168 | omap_badwidth_read8, |
| 2169 | }; |
| 2170 | |
| 2171 | static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = { |
| 2172 | omap_sti_fifo_write, |
| 2173 | omap_badwidth_write8, |
| 2174 | omap_badwidth_write8, |
| 2175 | }; |
| 2176 | |
| 2177 | struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, |
| 2178 | target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, |
| 2179 | CharDriverState *chr) |
| 2180 | { |
| 2181 | int iomemtype; |
| 2182 | struct omap_sti_s *s = (struct omap_sti_s *) |
| 2183 | qemu_mallocz(sizeof(struct omap_sti_s)); |
| 2184 | |
| 2185 | s->irq = irq; |
| 2186 | omap_sti_reset(s); |
| 2187 | |
| 2188 | s->chr = chr ?: qemu_chr_open("null"); |
| 2189 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2190 | iomemtype = l4_register_io_memory(0, omap_sti_readfn, |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 2191 | omap_sti_writefn, s); |
| 2192 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 2193 | |
| 2194 | iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn, |
| 2195 | omap_sti_fifo_writefn, s); |
| 2196 | s->channel_base = channel_base; |
| 2197 | cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype); |
| 2198 | |
| 2199 | return s; |
| 2200 | } |
| 2201 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2202 | /* L4 Interconnect */ |
| 2203 | struct omap_target_agent_s { |
| 2204 | struct omap_l4_s *bus; |
| 2205 | int regions; |
| 2206 | struct omap_l4_region_s *start; |
| 2207 | target_phys_addr_t base; |
| 2208 | uint32_t component; |
| 2209 | uint32_t control; |
| 2210 | uint32_t status; |
| 2211 | }; |
| 2212 | |
| 2213 | struct omap_l4_s { |
| 2214 | target_phys_addr_t base; |
| 2215 | int ta_num; |
| 2216 | struct omap_target_agent_s ta[0]; |
| 2217 | }; |
| 2218 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2219 | #ifdef L4_MUX_HACK |
| 2220 | static int omap_l4_io_entries; |
| 2221 | static int omap_cpu_io_entry; |
| 2222 | static struct omap_l4_entry { |
| 2223 | CPUReadMemoryFunc **mem_read; |
| 2224 | CPUWriteMemoryFunc **mem_write; |
| 2225 | void *opaque; |
| 2226 | } *omap_l4_io_entry; |
| 2227 | static CPUReadMemoryFunc **omap_l4_io_readb_fn; |
| 2228 | static CPUReadMemoryFunc **omap_l4_io_readh_fn; |
| 2229 | static CPUReadMemoryFunc **omap_l4_io_readw_fn; |
| 2230 | static CPUWriteMemoryFunc **omap_l4_io_writeb_fn; |
| 2231 | static CPUWriteMemoryFunc **omap_l4_io_writeh_fn; |
| 2232 | static CPUWriteMemoryFunc **omap_l4_io_writew_fn; |
| 2233 | static void **omap_l4_io_opaque; |
| 2234 | |
| 2235 | int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, |
| 2236 | CPUWriteMemoryFunc **mem_write, void *opaque) |
| 2237 | { |
| 2238 | omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; |
| 2239 | omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; |
| 2240 | omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; |
| 2241 | |
| 2242 | return omap_l4_io_entries ++; |
| 2243 | } |
| 2244 | |
| 2245 | static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) |
| 2246 | { |
| 2247 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2248 | |
| 2249 | return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr); |
| 2250 | } |
| 2251 | |
| 2252 | static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) |
| 2253 | { |
| 2254 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2255 | |
| 2256 | return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr); |
| 2257 | } |
| 2258 | |
| 2259 | static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) |
| 2260 | { |
| 2261 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2262 | |
| 2263 | return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr); |
| 2264 | } |
| 2265 | |
| 2266 | static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, |
| 2267 | uint32_t value) |
| 2268 | { |
| 2269 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2270 | |
| 2271 | return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value); |
| 2272 | } |
| 2273 | |
| 2274 | static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, |
| 2275 | uint32_t value) |
| 2276 | { |
| 2277 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2278 | |
| 2279 | return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value); |
| 2280 | } |
| 2281 | |
| 2282 | static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, |
| 2283 | uint32_t value) |
| 2284 | { |
| 2285 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
| 2286 | |
| 2287 | return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value); |
| 2288 | } |
| 2289 | |
| 2290 | static CPUReadMemoryFunc *omap_l4_io_readfn[] = { |
| 2291 | omap_l4_io_readb, |
| 2292 | omap_l4_io_readh, |
| 2293 | omap_l4_io_readw, |
| 2294 | }; |
| 2295 | |
| 2296 | static CPUWriteMemoryFunc *omap_l4_io_writefn[] = { |
| 2297 | omap_l4_io_writeb, |
| 2298 | omap_l4_io_writeh, |
| 2299 | omap_l4_io_writew, |
| 2300 | }; |
| 2301 | #endif |
| 2302 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2303 | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
| 2304 | { |
| 2305 | struct omap_l4_s *bus = qemu_mallocz( |
| 2306 | sizeof(*bus) + ta_num * sizeof(*bus->ta)); |
| 2307 | |
| 2308 | bus->ta_num = ta_num; |
| 2309 | bus->base = base; |
| 2310 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2311 | #ifdef L4_MUX_HACK |
| 2312 | omap_l4_io_entries = 1; |
| 2313 | omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); |
| 2314 | |
| 2315 | omap_cpu_io_entry = |
| 2316 | cpu_register_io_memory(0, omap_l4_io_readfn, |
| 2317 | omap_l4_io_writefn, bus); |
| 2318 | # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) |
| 2319 | omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2320 | omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2321 | omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2322 | omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2323 | omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2324 | omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2325 | omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); |
| 2326 | #endif |
| 2327 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2328 | return bus; |
| 2329 | } |
| 2330 | |
| 2331 | static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) |
| 2332 | { |
| 2333 | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
| 2334 | target_phys_addr_t reg = addr - s->base; |
| 2335 | |
| 2336 | switch (reg) { |
| 2337 | case 0x00: /* COMPONENT */ |
| 2338 | return s->component; |
| 2339 | |
| 2340 | case 0x20: /* AGENT_CONTROL */ |
| 2341 | return s->control; |
| 2342 | |
| 2343 | case 0x28: /* AGENT_STATUS */ |
| 2344 | return s->status; |
| 2345 | } |
| 2346 | |
| 2347 | OMAP_BAD_REG(addr); |
| 2348 | return 0; |
| 2349 | } |
| 2350 | |
| 2351 | static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, |
| 2352 | uint32_t value) |
| 2353 | { |
| 2354 | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; |
| 2355 | target_phys_addr_t reg = addr - s->base; |
| 2356 | |
| 2357 | switch (reg) { |
| 2358 | case 0x00: /* COMPONENT */ |
| 2359 | case 0x28: /* AGENT_STATUS */ |
| 2360 | OMAP_RO_REG(addr); |
| 2361 | break; |
| 2362 | |
| 2363 | case 0x20: /* AGENT_CONTROL */ |
| 2364 | s->control = value & 0x01000700; |
| 2365 | if (value & 1) /* OCP_RESET */ |
| 2366 | s->status &= ~1; /* REQ_TIMEOUT */ |
| 2367 | break; |
| 2368 | |
| 2369 | default: |
| 2370 | OMAP_BAD_REG(addr); |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | static CPUReadMemoryFunc *omap_l4ta_readfn[] = { |
| 2375 | omap_badwidth_read16, |
| 2376 | omap_l4ta_read, |
| 2377 | omap_badwidth_read16, |
| 2378 | }; |
| 2379 | |
| 2380 | static CPUWriteMemoryFunc *omap_l4ta_writefn[] = { |
| 2381 | omap_badwidth_write32, |
| 2382 | omap_badwidth_write32, |
| 2383 | omap_l4ta_write, |
| 2384 | }; |
| 2385 | |
| 2386 | #define L4TA(n) (n) |
| 2387 | #define L4TAO(n) ((n) + 39) |
| 2388 | |
| 2389 | static struct omap_l4_region_s { |
| 2390 | target_phys_addr_t offset; |
| 2391 | size_t size; |
| 2392 | int access; |
| 2393 | } omap_l4_region[125] = { |
| 2394 | [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ |
| 2395 | [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ |
| 2396 | [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ |
| 2397 | [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ |
| 2398 | [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ |
| 2399 | [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ |
| 2400 | [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ |
| 2401 | [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ |
| 2402 | [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ |
| 2403 | [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ |
| 2404 | [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ |
| 2405 | [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ |
| 2406 | [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ |
| 2407 | [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ |
| 2408 | [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ |
| 2409 | [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ |
| 2410 | [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ |
| 2411 | [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ |
| 2412 | [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ |
| 2413 | [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ |
| 2414 | [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ |
| 2415 | [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ |
| 2416 | [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ |
| 2417 | [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ |
| 2418 | [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ |
| 2419 | [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ |
| 2420 | [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ |
| 2421 | [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ |
| 2422 | [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ |
| 2423 | [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ |
| 2424 | [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ |
| 2425 | [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ |
| 2426 | [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ |
| 2427 | [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ |
| 2428 | [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ |
| 2429 | [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ |
| 2430 | [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ |
| 2431 | [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ |
| 2432 | [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ |
| 2433 | [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ |
| 2434 | [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ |
| 2435 | [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ |
| 2436 | [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ |
| 2437 | [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ |
| 2438 | [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ |
| 2439 | [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ |
| 2440 | [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ |
| 2441 | [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ |
| 2442 | [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ |
| 2443 | [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ |
| 2444 | [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ |
| 2445 | [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ |
| 2446 | [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ |
| 2447 | [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ |
| 2448 | [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ |
| 2449 | [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ |
| 2450 | [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ |
| 2451 | [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ |
| 2452 | [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ |
| 2453 | [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ |
| 2454 | [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ |
| 2455 | [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ |
| 2456 | [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ |
| 2457 | [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ |
| 2458 | [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ |
| 2459 | [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ |
| 2460 | [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ |
| 2461 | [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ |
| 2462 | [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ |
| 2463 | [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ |
| 2464 | [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ |
| 2465 | [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ |
| 2466 | [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ |
| 2467 | [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ |
| 2468 | [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ |
| 2469 | [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ |
| 2470 | [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ |
| 2471 | [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ |
| 2472 | [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ |
| 2473 | [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ |
| 2474 | [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ |
| 2475 | [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ |
| 2476 | [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ |
| 2477 | [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ |
| 2478 | [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ |
| 2479 | [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ |
| 2480 | [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ |
| 2481 | [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ |
| 2482 | [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ |
| 2483 | [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ |
| 2484 | [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ |
| 2485 | [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ |
| 2486 | [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ |
| 2487 | [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ |
| 2488 | [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ |
| 2489 | [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ |
| 2490 | [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ |
| 2491 | [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ |
| 2492 | [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ |
| 2493 | [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ |
| 2494 | [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ |
| 2495 | [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ |
| 2496 | [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ |
| 2497 | [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ |
| 2498 | [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ |
| 2499 | [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ |
| 2500 | [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ |
| 2501 | [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ |
| 2502 | [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ |
| 2503 | [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ |
| 2504 | [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ |
| 2505 | [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ |
| 2506 | [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ |
| 2507 | [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ |
| 2508 | [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ |
| 2509 | [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ |
| 2510 | [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ |
| 2511 | [117] = { 0xa6000, 0x1000, 32 }, /* AES */ |
| 2512 | [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ |
| 2513 | [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ |
| 2514 | [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ |
| 2515 | [121] = { 0xb0000, 0x1000, 32 }, /* MG */ |
| 2516 | [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, |
| 2517 | [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ |
| 2518 | [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ |
| 2519 | }; |
| 2520 | |
| 2521 | static struct omap_l4_agent_info_s { |
| 2522 | int ta; |
| 2523 | int region; |
| 2524 | int regions; |
| 2525 | int ta_region; |
| 2526 | } omap_l4_agent_info[54] = { |
| 2527 | { 0, 0, 3, 2 }, /* L4IA initiatior agent */ |
| 2528 | { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ |
| 2529 | { L4TAO(2), 5, 2, 1 }, /* 32K timer */ |
| 2530 | { L4TAO(3), 7, 3, 2 }, /* PRCM */ |
| 2531 | { L4TA(1), 10, 2, 1 }, /* BCM */ |
| 2532 | { L4TA(2), 12, 2, 1 }, /* Test JTAG */ |
| 2533 | { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ |
| 2534 | { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ |
| 2535 | { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ |
| 2536 | { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ |
| 2537 | { L4TA(10), 28, 5, 4 }, /* Display subsystem */ |
| 2538 | { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ |
| 2539 | { L4TA(12), 38, 2, 1 }, /* sDMA */ |
| 2540 | { L4TA(13), 40, 5, 4 }, /* SSI */ |
| 2541 | { L4TAO(4), 45, 2, 1 }, /* USB */ |
| 2542 | { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ |
| 2543 | { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ |
| 2544 | { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ |
| 2545 | { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ |
| 2546 | { L4TA(18), 55, 2, 1 }, /* XTI */ |
| 2547 | { L4TA(19), 57, 2, 1 }, /* UART1 */ |
| 2548 | { L4TA(20), 59, 2, 1 }, /* UART2 */ |
| 2549 | { L4TA(21), 61, 2, 1 }, /* UART3 */ |
| 2550 | { L4TAO(5), 63, 2, 1 }, /* I2C1 */ |
| 2551 | { L4TAO(6), 65, 2, 1 }, /* I2C2 */ |
| 2552 | { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ |
| 2553 | { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ |
| 2554 | { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ |
| 2555 | { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ |
| 2556 | { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ |
| 2557 | { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ |
| 2558 | { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ |
| 2559 | { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ |
| 2560 | { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ |
| 2561 | { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ |
| 2562 | { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ |
| 2563 | { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ |
| 2564 | { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ |
| 2565 | { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ |
| 2566 | { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ |
| 2567 | { L4TA(32), 97, 2, 1 }, /* EAC */ |
| 2568 | { L4TA(33), 99, 2, 1 }, /* FAC */ |
| 2569 | { L4TA(34), 101, 2, 1 }, /* IPC */ |
| 2570 | { L4TA(35), 103, 2, 1 }, /* SPI1 */ |
| 2571 | { L4TA(36), 105, 2, 1 }, /* SPI2 */ |
| 2572 | { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ |
| 2573 | { L4TAO(10), 109, 2, 1 }, |
| 2574 | { L4TAO(11), 111, 2, 1 }, /* RNG */ |
| 2575 | { L4TAO(12), 113, 2, 1 }, /* DES3DES */ |
| 2576 | { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ |
| 2577 | { L4TA(37), 117, 2, 1 }, /* AES */ |
| 2578 | { L4TA(38), 119, 2, 1 }, /* PKA */ |
| 2579 | { -1, 121, 2, 1 }, |
| 2580 | { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ |
| 2581 | }; |
| 2582 | |
| 2583 | #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs)) |
| 2584 | #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs)) |
| 2585 | |
| 2586 | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) |
| 2587 | { |
| 2588 | int i, iomemtype; |
| 2589 | struct omap_target_agent_s *ta = 0; |
| 2590 | struct omap_l4_agent_info_s *info = 0; |
| 2591 | |
| 2592 | for (i = 0; i < bus->ta_num; i ++) |
| 2593 | if (omap_l4_agent_info[i].ta == cs) { |
| 2594 | ta = &bus->ta[i]; |
| 2595 | info = &omap_l4_agent_info[i]; |
| 2596 | break; |
| 2597 | } |
| 2598 | if (!ta) { |
| 2599 | fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs); |
| 2600 | exit(-1); |
| 2601 | } |
| 2602 | |
| 2603 | ta->bus = bus; |
| 2604 | ta->start = &omap_l4_region[info->region]; |
| 2605 | ta->regions = info->regions; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2606 | |
| 2607 | ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 2608 | ta->status = 0x00000000; |
| 2609 | ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ |
| 2610 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2611 | iomemtype = l4_register_io_memory(0, omap_l4ta_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2612 | omap_l4ta_writefn, ta); |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2613 | ta->base = omap_l4_attach(ta, info->ta_region, iomemtype); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2614 | |
| 2615 | return ta; |
| 2616 | } |
| 2617 | |
| 2618 | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
| 2619 | int iotype) |
| 2620 | { |
| 2621 | target_phys_addr_t base; |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2622 | ssize_t size; |
| 2623 | #ifdef L4_MUX_HACK |
| 2624 | int i; |
| 2625 | #endif |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2626 | |
| 2627 | if (region < 0 || region >= ta->regions) { |
| 2628 | fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region); |
| 2629 | exit(-1); |
| 2630 | } |
| 2631 | |
| 2632 | base = ta->bus->base + ta->start[region].offset; |
| 2633 | size = ta->start[region].size; |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2634 | if (iotype) { |
| 2635 | #ifndef L4_MUX_HACK |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2636 | cpu_register_physical_memory(base, size, iotype); |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2637 | #else |
| 2638 | cpu_register_physical_memory(base, size, omap_cpu_io_entry); |
| 2639 | i = (base - ta->bus->base) / TARGET_PAGE_SIZE; |
| 2640 | for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) { |
| 2641 | omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0]; |
| 2642 | omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1]; |
| 2643 | omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2]; |
| 2644 | omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0]; |
| 2645 | omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1]; |
| 2646 | omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2]; |
| 2647 | omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; |
| 2648 | } |
| 2649 | #endif |
| 2650 | } |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2651 | |
| 2652 | return base; |
| 2653 | } |
| 2654 | |
| 2655 | /* TEST-Chip-level TAP */ |
| 2656 | static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) |
| 2657 | { |
| 2658 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
| 2659 | target_phys_addr_t reg = addr - s->tap_base; |
| 2660 | |
| 2661 | switch (reg) { |
| 2662 | case 0x204: /* IDCODE_reg */ |
| 2663 | switch (s->mpu_model) { |
| 2664 | case omap2420: |
| 2665 | case omap2422: |
| 2666 | case omap2423: |
| 2667 | return 0x5b5d902f; /* ES 2.2 */ |
| 2668 | case omap2430: |
| 2669 | return 0x5b68a02f; /* ES 2.2 */ |
| 2670 | case omap3430: |
| 2671 | return 0x1b7ae02f; /* ES 2 */ |
| 2672 | default: |
| 2673 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); |
| 2674 | } |
| 2675 | |
| 2676 | case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ |
| 2677 | case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ |
| 2678 | switch (s->mpu_model) { |
| 2679 | case omap2420: |
| 2680 | return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ |
| 2681 | case omap2422: |
| 2682 | return 0x000400f0; |
| 2683 | case omap2423: |
| 2684 | return 0x000800f0; |
| 2685 | case omap2430: |
| 2686 | return 0x000000f0; |
| 2687 | case omap3430: |
| 2688 | return 0x000000f0; |
| 2689 | default: |
| 2690 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); |
| 2691 | } |
| 2692 | |
| 2693 | case 0x20c: |
| 2694 | switch (s->mpu_model) { |
| 2695 | case omap2420: |
| 2696 | case omap2422: |
| 2697 | case omap2423: |
| 2698 | return 0xcafeb5d9; /* ES 2.2 */ |
| 2699 | case omap2430: |
| 2700 | return 0xcafeb68a; /* ES 2.2 */ |
| 2701 | case omap3430: |
| 2702 | return 0xcafeb7ae; /* ES 2 */ |
| 2703 | default: |
| 2704 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); |
| 2705 | } |
| 2706 | |
| 2707 | case 0x218: /* DIE_ID_reg */ |
| 2708 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 2709 | case 0x21c: /* DIE_ID_reg */ |
| 2710 | return 0x54 << 24; |
| 2711 | case 0x220: /* DIE_ID_reg */ |
| 2712 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 2713 | case 0x224: /* DIE_ID_reg */ |
| 2714 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
| 2715 | } |
| 2716 | |
| 2717 | OMAP_BAD_REG(addr); |
| 2718 | return 0; |
| 2719 | } |
| 2720 | |
| 2721 | static void omap_tap_write(void *opaque, target_phys_addr_t addr, |
| 2722 | uint32_t value) |
| 2723 | { |
| 2724 | OMAP_BAD_REG(addr); |
| 2725 | } |
| 2726 | |
| 2727 | static CPUReadMemoryFunc *omap_tap_readfn[] = { |
| 2728 | omap_badwidth_read32, |
| 2729 | omap_badwidth_read32, |
| 2730 | omap_tap_read, |
| 2731 | }; |
| 2732 | |
| 2733 | static CPUWriteMemoryFunc *omap_tap_writefn[] = { |
| 2734 | omap_badwidth_write32, |
| 2735 | omap_badwidth_write32, |
| 2736 | omap_tap_write, |
| 2737 | }; |
| 2738 | |
| 2739 | void omap_tap_init(struct omap_target_agent_s *ta, |
| 2740 | struct omap_mpu_state_s *mpu) |
| 2741 | { |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 2742 | mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2743 | omap_tap_readfn, omap_tap_writefn, mpu)); |
| 2744 | } |
| 2745 | |
| 2746 | /* Power, Reset, and Clock Management */ |
| 2747 | struct omap_prcm_s { |
| 2748 | target_phys_addr_t base; |
| 2749 | qemu_irq irq[3]; |
| 2750 | struct omap_mpu_state_s *mpu; |
| 2751 | |
| 2752 | uint32_t irqst[3]; |
| 2753 | uint32_t irqen[3]; |
| 2754 | |
| 2755 | uint32_t sysconfig; |
| 2756 | uint32_t voltctrl; |
| 2757 | uint32_t scratch[20]; |
| 2758 | |
| 2759 | uint32_t clksrc[1]; |
| 2760 | uint32_t clkout[1]; |
| 2761 | uint32_t clkemul[1]; |
| 2762 | uint32_t clkpol[1]; |
| 2763 | uint32_t clksel[8]; |
| 2764 | uint32_t clken[12]; |
| 2765 | uint32_t clkctrl[4]; |
| 2766 | uint32_t clkidle[7]; |
| 2767 | uint32_t setuptime[2]; |
| 2768 | |
| 2769 | uint32_t wkup[3]; |
| 2770 | uint32_t wken[3]; |
| 2771 | uint32_t wkst[3]; |
| 2772 | uint32_t rst[4]; |
| 2773 | uint32_t rstctrl[1]; |
| 2774 | uint32_t power[4]; |
| 2775 | uint32_t rsttime_wkup; |
| 2776 | |
| 2777 | uint32_t ev; |
| 2778 | uint32_t evtime[2]; |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 2779 | |
| 2780 | int dpll_lock, apll_lock[2]; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2781 | }; |
| 2782 | |
| 2783 | static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) |
| 2784 | { |
| 2785 | qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); |
| 2786 | /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ |
| 2787 | } |
| 2788 | |
| 2789 | static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) |
| 2790 | { |
| 2791 | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
| 2792 | int offset = addr - s->base; |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 2793 | uint32_t ret; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2794 | |
| 2795 | switch (offset) { |
| 2796 | case 0x000: /* PRCM_REVISION */ |
| 2797 | return 0x10; |
| 2798 | |
| 2799 | case 0x010: /* PRCM_SYSCONFIG */ |
| 2800 | return s->sysconfig; |
| 2801 | |
| 2802 | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
| 2803 | return s->irqst[0]; |
| 2804 | |
| 2805 | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
| 2806 | return s->irqen[0]; |
| 2807 | |
| 2808 | case 0x050: /* PRCM_VOLTCTRL */ |
| 2809 | return s->voltctrl; |
| 2810 | case 0x054: /* PRCM_VOLTST */ |
| 2811 | return s->voltctrl & 3; |
| 2812 | |
| 2813 | case 0x060: /* PRCM_CLKSRC_CTRL */ |
| 2814 | return s->clksrc[0]; |
| 2815 | case 0x070: /* PRCM_CLKOUT_CTRL */ |
| 2816 | return s->clkout[0]; |
| 2817 | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
| 2818 | return s->clkemul[0]; |
| 2819 | case 0x080: /* PRCM_CLKCFG_CTRL */ |
| 2820 | case 0x084: /* PRCM_CLKCFG_STATUS */ |
| 2821 | return 0; |
| 2822 | |
| 2823 | case 0x090: /* PRCM_VOLTSETUP */ |
| 2824 | return s->setuptime[0]; |
| 2825 | |
| 2826 | case 0x094: /* PRCM_CLKSSETUP */ |
| 2827 | return s->setuptime[1]; |
| 2828 | |
| 2829 | case 0x098: /* PRCM_POLCTRL */ |
| 2830 | return s->clkpol[0]; |
| 2831 | |
| 2832 | case 0x0b0: /* GENERAL_PURPOSE1 */ |
| 2833 | case 0x0b4: /* GENERAL_PURPOSE2 */ |
| 2834 | case 0x0b8: /* GENERAL_PURPOSE3 */ |
| 2835 | case 0x0bc: /* GENERAL_PURPOSE4 */ |
| 2836 | case 0x0c0: /* GENERAL_PURPOSE5 */ |
| 2837 | case 0x0c4: /* GENERAL_PURPOSE6 */ |
| 2838 | case 0x0c8: /* GENERAL_PURPOSE7 */ |
| 2839 | case 0x0cc: /* GENERAL_PURPOSE8 */ |
| 2840 | case 0x0d0: /* GENERAL_PURPOSE9 */ |
| 2841 | case 0x0d4: /* GENERAL_PURPOSE10 */ |
| 2842 | case 0x0d8: /* GENERAL_PURPOSE11 */ |
| 2843 | case 0x0dc: /* GENERAL_PURPOSE12 */ |
| 2844 | case 0x0e0: /* GENERAL_PURPOSE13 */ |
| 2845 | case 0x0e4: /* GENERAL_PURPOSE14 */ |
| 2846 | case 0x0e8: /* GENERAL_PURPOSE15 */ |
| 2847 | case 0x0ec: /* GENERAL_PURPOSE16 */ |
| 2848 | case 0x0f0: /* GENERAL_PURPOSE17 */ |
| 2849 | case 0x0f4: /* GENERAL_PURPOSE18 */ |
| 2850 | case 0x0f8: /* GENERAL_PURPOSE19 */ |
| 2851 | case 0x0fc: /* GENERAL_PURPOSE20 */ |
| 2852 | return s->scratch[(offset - 0xb0) >> 2]; |
| 2853 | |
| 2854 | case 0x140: /* CM_CLKSEL_MPU */ |
| 2855 | return s->clksel[0]; |
| 2856 | case 0x148: /* CM_CLKSTCTRL_MPU */ |
| 2857 | return s->clkctrl[0]; |
| 2858 | |
| 2859 | case 0x158: /* RM_RSTST_MPU */ |
| 2860 | return s->rst[0]; |
| 2861 | case 0x1c8: /* PM_WKDEP_MPU */ |
| 2862 | return s->wkup[0]; |
| 2863 | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
| 2864 | return s->ev; |
| 2865 | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
| 2866 | return s->evtime[0]; |
| 2867 | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
| 2868 | return s->evtime[1]; |
| 2869 | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
| 2870 | return s->power[0]; |
| 2871 | case 0x1e4: /* PM_PWSTST_MPU */ |
| 2872 | return 0; |
| 2873 | |
| 2874 | case 0x200: /* CM_FCLKEN1_CORE */ |
| 2875 | return s->clken[0]; |
| 2876 | case 0x204: /* CM_FCLKEN2_CORE */ |
| 2877 | return s->clken[1]; |
| 2878 | case 0x210: /* CM_ICLKEN1_CORE */ |
| 2879 | return s->clken[2]; |
| 2880 | case 0x214: /* CM_ICLKEN2_CORE */ |
| 2881 | return s->clken[3]; |
| 2882 | case 0x21c: /* CM_ICLKEN4_CORE */ |
| 2883 | return s->clken[4]; |
| 2884 | |
| 2885 | case 0x220: /* CM_IDLEST1_CORE */ |
| 2886 | /* TODO: check the actual iclk status */ |
| 2887 | return 0x7ffffff9; |
| 2888 | case 0x224: /* CM_IDLEST2_CORE */ |
| 2889 | /* TODO: check the actual iclk status */ |
| 2890 | return 0x00000007; |
| 2891 | case 0x22c: /* CM_IDLEST4_CORE */ |
| 2892 | /* TODO: check the actual iclk status */ |
| 2893 | return 0x0000001f; |
| 2894 | |
| 2895 | case 0x230: /* CM_AUTOIDLE1_CORE */ |
| 2896 | return s->clkidle[0]; |
| 2897 | case 0x234: /* CM_AUTOIDLE2_CORE */ |
| 2898 | return s->clkidle[1]; |
| 2899 | case 0x238: /* CM_AUTOIDLE3_CORE */ |
| 2900 | return s->clkidle[2]; |
| 2901 | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
| 2902 | return s->clkidle[3]; |
| 2903 | |
| 2904 | case 0x240: /* CM_CLKSEL1_CORE */ |
| 2905 | return s->clksel[1]; |
| 2906 | case 0x244: /* CM_CLKSEL2_CORE */ |
| 2907 | return s->clksel[2]; |
| 2908 | |
| 2909 | case 0x248: /* CM_CLKSTCTRL_CORE */ |
| 2910 | return s->clkctrl[1]; |
| 2911 | |
| 2912 | case 0x2a0: /* PM_WKEN1_CORE */ |
| 2913 | return s->wken[0]; |
| 2914 | case 0x2a4: /* PM_WKEN2_CORE */ |
| 2915 | return s->wken[1]; |
| 2916 | |
| 2917 | case 0x2b0: /* PM_WKST1_CORE */ |
| 2918 | return s->wkst[0]; |
| 2919 | case 0x2b4: /* PM_WKST2_CORE */ |
| 2920 | return s->wkst[1]; |
| 2921 | case 0x2c8: /* PM_WKDEP_CORE */ |
| 2922 | return 0x1e; |
| 2923 | |
| 2924 | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
| 2925 | return s->power[1]; |
| 2926 | case 0x2e4: /* PM_PWSTST_CORE */ |
| 2927 | return 0x000030 | (s->power[1] & 0xfc00); |
| 2928 | |
| 2929 | case 0x300: /* CM_FCLKEN_GFX */ |
| 2930 | return s->clken[5]; |
| 2931 | case 0x310: /* CM_ICLKEN_GFX */ |
| 2932 | return s->clken[6]; |
| 2933 | case 0x320: /* CM_IDLEST_GFX */ |
| 2934 | /* TODO: check the actual iclk status */ |
| 2935 | return 0x00000001; |
| 2936 | case 0x340: /* CM_CLKSEL_GFX */ |
| 2937 | return s->clksel[3]; |
| 2938 | case 0x348: /* CM_CLKSTCTRL_GFX */ |
| 2939 | return s->clkctrl[2]; |
| 2940 | case 0x350: /* RM_RSTCTRL_GFX */ |
| 2941 | return s->rstctrl[0]; |
| 2942 | case 0x358: /* RM_RSTST_GFX */ |
| 2943 | return s->rst[1]; |
| 2944 | case 0x3c8: /* PM_WKDEP_GFX */ |
| 2945 | return s->wkup[1]; |
| 2946 | |
| 2947 | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
| 2948 | return s->power[2]; |
| 2949 | case 0x3e4: /* PM_PWSTST_GFX */ |
| 2950 | return s->power[2] & 3; |
| 2951 | |
| 2952 | case 0x400: /* CM_FCLKEN_WKUP */ |
| 2953 | return s->clken[7]; |
| 2954 | case 0x410: /* CM_ICLKEN_WKUP */ |
| 2955 | return s->clken[8]; |
| 2956 | case 0x420: /* CM_IDLEST_WKUP */ |
| 2957 | /* TODO: check the actual iclk status */ |
| 2958 | return 0x0000003f; |
| 2959 | case 0x430: /* CM_AUTOIDLE_WKUP */ |
| 2960 | return s->clkidle[4]; |
| 2961 | case 0x440: /* CM_CLKSEL_WKUP */ |
| 2962 | return s->clksel[4]; |
| 2963 | case 0x450: /* RM_RSTCTRL_WKUP */ |
| 2964 | return 0; |
| 2965 | case 0x454: /* RM_RSTTIME_WKUP */ |
| 2966 | return s->rsttime_wkup; |
| 2967 | case 0x458: /* RM_RSTST_WKUP */ |
| 2968 | return s->rst[2]; |
| 2969 | case 0x4a0: /* PM_WKEN_WKUP */ |
| 2970 | return s->wken[2]; |
| 2971 | case 0x4b0: /* PM_WKST_WKUP */ |
| 2972 | return s->wkst[2]; |
| 2973 | |
| 2974 | case 0x500: /* CM_CLKEN_PLL */ |
| 2975 | return s->clken[9]; |
| 2976 | case 0x520: /* CM_IDLEST_CKGEN */ |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 2977 | ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2978 | if (!(s->clksel[6] & 3)) |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 2979 | /* Core uses 32-kHz clock */ |
| 2980 | ret |= 3 << 0; |
| 2981 | else if (!s->dpll_lock) |
| 2982 | /* DPLL not locked, core uses ref_clk */ |
| 2983 | ret |= 1 << 0; |
| 2984 | else |
| 2985 | /* Core uses DPLL */ |
| 2986 | ret |= 2 << 0; |
| 2987 | return ret; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 2988 | case 0x530: /* CM_AUTOIDLE_PLL */ |
| 2989 | return s->clkidle[5]; |
| 2990 | case 0x540: /* CM_CLKSEL1_PLL */ |
| 2991 | return s->clksel[5]; |
| 2992 | case 0x544: /* CM_CLKSEL2_PLL */ |
| 2993 | return s->clksel[6]; |
| 2994 | |
| 2995 | case 0x800: /* CM_FCLKEN_DSP */ |
| 2996 | return s->clken[10]; |
| 2997 | case 0x810: /* CM_ICLKEN_DSP */ |
| 2998 | return s->clken[11]; |
| 2999 | case 0x820: /* CM_IDLEST_DSP */ |
| 3000 | /* TODO: check the actual iclk status */ |
| 3001 | return 0x00000103; |
| 3002 | case 0x830: /* CM_AUTOIDLE_DSP */ |
| 3003 | return s->clkidle[6]; |
| 3004 | case 0x840: /* CM_CLKSEL_DSP */ |
| 3005 | return s->clksel[7]; |
| 3006 | case 0x848: /* CM_CLKSTCTRL_DSP */ |
| 3007 | return s->clkctrl[3]; |
| 3008 | case 0x850: /* RM_RSTCTRL_DSP */ |
| 3009 | return 0; |
| 3010 | case 0x858: /* RM_RSTST_DSP */ |
| 3011 | return s->rst[3]; |
| 3012 | case 0x8c8: /* PM_WKDEP_DSP */ |
| 3013 | return s->wkup[2]; |
| 3014 | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
| 3015 | return s->power[3]; |
| 3016 | case 0x8e4: /* PM_PWSTST_DSP */ |
| 3017 | return 0x008030 | (s->power[3] & 0x3003); |
| 3018 | |
| 3019 | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
| 3020 | return s->irqst[1]; |
| 3021 | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
| 3022 | return s->irqen[1]; |
| 3023 | |
| 3024 | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
| 3025 | return s->irqst[2]; |
| 3026 | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
| 3027 | return s->irqen[2]; |
| 3028 | } |
| 3029 | |
| 3030 | OMAP_BAD_REG(addr); |
| 3031 | return 0; |
| 3032 | } |
| 3033 | |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 3034 | static void omap_prcm_apll_update(struct omap_prcm_s *s) |
| 3035 | { |
| 3036 | int mode[2]; |
| 3037 | |
| 3038 | mode[0] = (s->clken[9] >> 6) & 3; |
| 3039 | s->apll_lock[0] = (mode[0] == 3); |
| 3040 | mode[1] = (s->clken[9] >> 2) & 3; |
| 3041 | s->apll_lock[1] = (mode[1] == 3); |
| 3042 | /* TODO: update clocks */ |
| 3043 | |
| 3044 | if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[2] == 2) |
| 3045 | fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n", |
| 3046 | __FUNCTION__); |
| 3047 | } |
| 3048 | |
| 3049 | static void omap_prcm_dpll_update(struct omap_prcm_s *s) |
| 3050 | { |
| 3051 | omap_clk dpll = omap_findclk(s->mpu, "dpll"); |
| 3052 | omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll"); |
| 3053 | omap_clk core = omap_findclk(s->mpu, "core_clk"); |
| 3054 | int mode = (s->clken[9] >> 0) & 3; |
| 3055 | int mult, div; |
| 3056 | |
| 3057 | mult = (s->clksel[5] >> 12) & 0x3ff; |
| 3058 | div = (s->clksel[5] >> 8) & 0xf; |
| 3059 | if (mult == 0 || mult == 1) |
| 3060 | mode = 1; /* Bypass */ |
| 3061 | |
| 3062 | s->dpll_lock = 0; |
| 3063 | switch (mode) { |
| 3064 | case 0: |
| 3065 | fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__); |
| 3066 | break; |
| 3067 | case 1: /* Low-power bypass mode (Default) */ |
| 3068 | case 2: /* Fast-relock bypass mode */ |
| 3069 | omap_clk_setrate(dpll, 1, 1); |
| 3070 | omap_clk_setrate(dpll_x2, 1, 1); |
| 3071 | break; |
| 3072 | case 3: /* Lock mode */ |
| 3073 | s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ |
| 3074 | |
| 3075 | omap_clk_setrate(dpll, div + 1, mult); |
| 3076 | omap_clk_setrate(dpll_x2, div + 1, mult * 2); |
| 3077 | break; |
| 3078 | } |
| 3079 | |
| 3080 | switch ((s->clksel[6] >> 0) & 3) { |
| 3081 | case 0: |
| 3082 | omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz")); |
| 3083 | break; |
| 3084 | case 1: |
| 3085 | omap_clk_reparent(core, dpll); |
| 3086 | break; |
| 3087 | case 2: |
| 3088 | /* Default */ |
| 3089 | omap_clk_reparent(core, dpll_x2); |
| 3090 | break; |
| 3091 | case 3: |
| 3092 | fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__); |
| 3093 | break; |
| 3094 | } |
| 3095 | } |
| 3096 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3097 | static void omap_prcm_write(void *opaque, target_phys_addr_t addr, |
| 3098 | uint32_t value) |
| 3099 | { |
| 3100 | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; |
| 3101 | int offset = addr - s->base; |
| 3102 | |
| 3103 | switch (offset) { |
| 3104 | case 0x000: /* PRCM_REVISION */ |
| 3105 | case 0x054: /* PRCM_VOLTST */ |
| 3106 | case 0x084: /* PRCM_CLKCFG_STATUS */ |
| 3107 | case 0x1e4: /* PM_PWSTST_MPU */ |
| 3108 | case 0x220: /* CM_IDLEST1_CORE */ |
| 3109 | case 0x224: /* CM_IDLEST2_CORE */ |
| 3110 | case 0x22c: /* CM_IDLEST4_CORE */ |
| 3111 | case 0x2c8: /* PM_WKDEP_CORE */ |
| 3112 | case 0x2e4: /* PM_PWSTST_CORE */ |
| 3113 | case 0x320: /* CM_IDLEST_GFX */ |
| 3114 | case 0x3e4: /* PM_PWSTST_GFX */ |
| 3115 | case 0x420: /* CM_IDLEST_WKUP */ |
| 3116 | case 0x520: /* CM_IDLEST_CKGEN */ |
| 3117 | case 0x820: /* CM_IDLEST_DSP */ |
| 3118 | case 0x8e4: /* PM_PWSTST_DSP */ |
| 3119 | OMAP_RO_REG(addr); |
| 3120 | return; |
| 3121 | |
| 3122 | case 0x010: /* PRCM_SYSCONFIG */ |
| 3123 | s->sysconfig = value & 1; |
| 3124 | break; |
| 3125 | |
| 3126 | case 0x018: /* PRCM_IRQSTATUS_MPU */ |
| 3127 | s->irqst[0] &= ~value; |
| 3128 | omap_prcm_int_update(s, 0); |
| 3129 | break; |
| 3130 | case 0x01c: /* PRCM_IRQENABLE_MPU */ |
| 3131 | s->irqen[0] = value & 0x3f; |
| 3132 | omap_prcm_int_update(s, 0); |
| 3133 | break; |
| 3134 | |
| 3135 | case 0x050: /* PRCM_VOLTCTRL */ |
| 3136 | s->voltctrl = value & 0xf1c3; |
| 3137 | break; |
| 3138 | |
| 3139 | case 0x060: /* PRCM_CLKSRC_CTRL */ |
| 3140 | s->clksrc[0] = value & 0xdb; |
| 3141 | /* TODO update clocks */ |
| 3142 | break; |
| 3143 | |
| 3144 | case 0x070: /* PRCM_CLKOUT_CTRL */ |
| 3145 | s->clkout[0] = value & 0xbbbb; |
| 3146 | /* TODO update clocks */ |
| 3147 | break; |
| 3148 | |
| 3149 | case 0x078: /* PRCM_CLKEMUL_CTRL */ |
| 3150 | s->clkemul[0] = value & 1; |
| 3151 | /* TODO update clocks */ |
| 3152 | break; |
| 3153 | |
| 3154 | case 0x080: /* PRCM_CLKCFG_CTRL */ |
| 3155 | break; |
| 3156 | |
| 3157 | case 0x090: /* PRCM_VOLTSETUP */ |
| 3158 | s->setuptime[0] = value & 0xffff; |
| 3159 | break; |
| 3160 | case 0x094: /* PRCM_CLKSSETUP */ |
| 3161 | s->setuptime[1] = value & 0xffff; |
| 3162 | break; |
| 3163 | |
| 3164 | case 0x098: /* PRCM_POLCTRL */ |
| 3165 | s->clkpol[0] = value & 0x701; |
| 3166 | break; |
| 3167 | |
| 3168 | case 0x0b0: /* GENERAL_PURPOSE1 */ |
| 3169 | case 0x0b4: /* GENERAL_PURPOSE2 */ |
| 3170 | case 0x0b8: /* GENERAL_PURPOSE3 */ |
| 3171 | case 0x0bc: /* GENERAL_PURPOSE4 */ |
| 3172 | case 0x0c0: /* GENERAL_PURPOSE5 */ |
| 3173 | case 0x0c4: /* GENERAL_PURPOSE6 */ |
| 3174 | case 0x0c8: /* GENERAL_PURPOSE7 */ |
| 3175 | case 0x0cc: /* GENERAL_PURPOSE8 */ |
| 3176 | case 0x0d0: /* GENERAL_PURPOSE9 */ |
| 3177 | case 0x0d4: /* GENERAL_PURPOSE10 */ |
| 3178 | case 0x0d8: /* GENERAL_PURPOSE11 */ |
| 3179 | case 0x0dc: /* GENERAL_PURPOSE12 */ |
| 3180 | case 0x0e0: /* GENERAL_PURPOSE13 */ |
| 3181 | case 0x0e4: /* GENERAL_PURPOSE14 */ |
| 3182 | case 0x0e8: /* GENERAL_PURPOSE15 */ |
| 3183 | case 0x0ec: /* GENERAL_PURPOSE16 */ |
| 3184 | case 0x0f0: /* GENERAL_PURPOSE17 */ |
| 3185 | case 0x0f4: /* GENERAL_PURPOSE18 */ |
| 3186 | case 0x0f8: /* GENERAL_PURPOSE19 */ |
| 3187 | case 0x0fc: /* GENERAL_PURPOSE20 */ |
| 3188 | s->scratch[(offset - 0xb0) >> 2] = value; |
| 3189 | break; |
| 3190 | |
| 3191 | case 0x140: /* CM_CLKSEL_MPU */ |
| 3192 | s->clksel[0] = value & 0x1f; |
| 3193 | /* TODO update clocks */ |
| 3194 | break; |
| 3195 | case 0x148: /* CM_CLKSTCTRL_MPU */ |
| 3196 | s->clkctrl[0] = value & 0x1f; |
| 3197 | break; |
| 3198 | |
| 3199 | case 0x158: /* RM_RSTST_MPU */ |
| 3200 | s->rst[0] &= ~value; |
| 3201 | break; |
| 3202 | case 0x1c8: /* PM_WKDEP_MPU */ |
| 3203 | s->wkup[0] = value & 0x15; |
| 3204 | break; |
| 3205 | |
| 3206 | case 0x1d4: /* PM_EVGENCTRL_MPU */ |
| 3207 | s->ev = value & 0x1f; |
| 3208 | break; |
| 3209 | case 0x1d8: /* PM_EVEGENONTIM_MPU */ |
| 3210 | s->evtime[0] = value; |
| 3211 | break; |
| 3212 | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ |
| 3213 | s->evtime[1] = value; |
| 3214 | break; |
| 3215 | |
| 3216 | case 0x1e0: /* PM_PWSTCTRL_MPU */ |
| 3217 | s->power[0] = value & 0xc0f; |
| 3218 | break; |
| 3219 | |
| 3220 | case 0x200: /* CM_FCLKEN1_CORE */ |
| 3221 | s->clken[0] = value & 0xbfffffff; |
| 3222 | /* TODO update clocks */ |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 3223 | /* The EN_EAC bit only gets/puts func_96m_clk. */ |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3224 | break; |
| 3225 | case 0x204: /* CM_FCLKEN2_CORE */ |
| 3226 | s->clken[1] = value & 0x00000007; |
| 3227 | /* TODO update clocks */ |
| 3228 | break; |
| 3229 | case 0x210: /* CM_ICLKEN1_CORE */ |
| 3230 | s->clken[2] = value & 0xfffffff9; |
| 3231 | /* TODO update clocks */ |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 3232 | /* The EN_EAC bit only gets/puts core_l4_iclk. */ |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3233 | break; |
| 3234 | case 0x214: /* CM_ICLKEN2_CORE */ |
| 3235 | s->clken[3] = value & 0x00000007; |
| 3236 | /* TODO update clocks */ |
| 3237 | break; |
| 3238 | case 0x21c: /* CM_ICLKEN4_CORE */ |
| 3239 | s->clken[4] = value & 0x0000001f; |
| 3240 | /* TODO update clocks */ |
| 3241 | break; |
| 3242 | |
| 3243 | case 0x230: /* CM_AUTOIDLE1_CORE */ |
| 3244 | s->clkidle[0] = value & 0xfffffff9; |
| 3245 | /* TODO update clocks */ |
| 3246 | break; |
| 3247 | case 0x234: /* CM_AUTOIDLE2_CORE */ |
| 3248 | s->clkidle[1] = value & 0x00000007; |
| 3249 | /* TODO update clocks */ |
| 3250 | break; |
| 3251 | case 0x238: /* CM_AUTOIDLE3_CORE */ |
| 3252 | s->clkidle[2] = value & 0x00000007; |
| 3253 | /* TODO update clocks */ |
| 3254 | break; |
| 3255 | case 0x23c: /* CM_AUTOIDLE4_CORE */ |
| 3256 | s->clkidle[3] = value & 0x0000001f; |
| 3257 | /* TODO update clocks */ |
| 3258 | break; |
| 3259 | |
| 3260 | case 0x240: /* CM_CLKSEL1_CORE */ |
| 3261 | s->clksel[1] = value & 0x0fffbf7f; |
| 3262 | /* TODO update clocks */ |
| 3263 | break; |
| 3264 | |
| 3265 | case 0x244: /* CM_CLKSEL2_CORE */ |
| 3266 | s->clksel[2] = value & 0x00fffffc; |
| 3267 | /* TODO update clocks */ |
| 3268 | break; |
| 3269 | |
| 3270 | case 0x248: /* CM_CLKSTCTRL_CORE */ |
| 3271 | s->clkctrl[1] = value & 0x7; |
| 3272 | break; |
| 3273 | |
| 3274 | case 0x2a0: /* PM_WKEN1_CORE */ |
| 3275 | s->wken[0] = value & 0x04667ff8; |
| 3276 | break; |
| 3277 | case 0x2a4: /* PM_WKEN2_CORE */ |
| 3278 | s->wken[1] = value & 0x00000005; |
| 3279 | break; |
| 3280 | |
| 3281 | case 0x2b0: /* PM_WKST1_CORE */ |
| 3282 | s->wkst[0] &= ~value; |
| 3283 | break; |
| 3284 | case 0x2b4: /* PM_WKST2_CORE */ |
| 3285 | s->wkst[1] &= ~value; |
| 3286 | break; |
| 3287 | |
| 3288 | case 0x2e0: /* PM_PWSTCTRL_CORE */ |
| 3289 | s->power[1] = (value & 0x00fc3f) | (1 << 2); |
| 3290 | break; |
| 3291 | |
| 3292 | case 0x300: /* CM_FCLKEN_GFX */ |
| 3293 | s->clken[5] = value & 6; |
| 3294 | /* TODO update clocks */ |
| 3295 | break; |
| 3296 | case 0x310: /* CM_ICLKEN_GFX */ |
| 3297 | s->clken[6] = value & 1; |
| 3298 | /* TODO update clocks */ |
| 3299 | break; |
| 3300 | case 0x340: /* CM_CLKSEL_GFX */ |
| 3301 | s->clksel[3] = value & 7; |
| 3302 | /* TODO update clocks */ |
| 3303 | break; |
| 3304 | case 0x348: /* CM_CLKSTCTRL_GFX */ |
| 3305 | s->clkctrl[2] = value & 1; |
| 3306 | break; |
| 3307 | case 0x350: /* RM_RSTCTRL_GFX */ |
| 3308 | s->rstctrl[0] = value & 1; |
| 3309 | /* TODO: reset */ |
| 3310 | break; |
| 3311 | case 0x358: /* RM_RSTST_GFX */ |
| 3312 | s->rst[1] &= ~value; |
| 3313 | break; |
| 3314 | case 0x3c8: /* PM_WKDEP_GFX */ |
| 3315 | s->wkup[1] = value & 0x13; |
| 3316 | break; |
| 3317 | case 0x3e0: /* PM_PWSTCTRL_GFX */ |
| 3318 | s->power[2] = (value & 0x00c0f) | (3 << 2); |
| 3319 | break; |
| 3320 | |
| 3321 | case 0x400: /* CM_FCLKEN_WKUP */ |
| 3322 | s->clken[7] = value & 0xd; |
| 3323 | /* TODO update clocks */ |
| 3324 | break; |
| 3325 | case 0x410: /* CM_ICLKEN_WKUP */ |
| 3326 | s->clken[8] = value & 0x3f; |
| 3327 | /* TODO update clocks */ |
| 3328 | break; |
| 3329 | case 0x430: /* CM_AUTOIDLE_WKUP */ |
| 3330 | s->clkidle[4] = value & 0x0000003f; |
| 3331 | /* TODO update clocks */ |
| 3332 | break; |
| 3333 | case 0x440: /* CM_CLKSEL_WKUP */ |
| 3334 | s->clksel[4] = value & 3; |
| 3335 | /* TODO update clocks */ |
| 3336 | break; |
| 3337 | case 0x450: /* RM_RSTCTRL_WKUP */ |
| 3338 | /* TODO: reset */ |
| 3339 | if (value & 2) |
| 3340 | qemu_system_reset_request(); |
| 3341 | break; |
| 3342 | case 0x454: /* RM_RSTTIME_WKUP */ |
| 3343 | s->rsttime_wkup = value & 0x1fff; |
| 3344 | break; |
| 3345 | case 0x458: /* RM_RSTST_WKUP */ |
| 3346 | s->rst[2] &= ~value; |
| 3347 | break; |
| 3348 | case 0x4a0: /* PM_WKEN_WKUP */ |
| 3349 | s->wken[2] = value & 0x00000005; |
| 3350 | break; |
| 3351 | case 0x4b0: /* PM_WKST_WKUP */ |
| 3352 | s->wkst[2] &= ~value; |
| 3353 | break; |
| 3354 | |
| 3355 | case 0x500: /* CM_CLKEN_PLL */ |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 3356 | if (value & 0xffffff30) |
| 3357 | fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for " |
| 3358 | "future compatiblity\n", __FUNCTION__); |
| 3359 | if ((s->clken[9] ^ value) & 0xcc) { |
| 3360 | s->clken[9] &= ~0xcc; |
| 3361 | s->clken[9] |= value & 0xcc; |
| 3362 | omap_prcm_apll_update(s); |
| 3363 | } |
| 3364 | if ((s->clken[9] ^ value) & 3) { |
| 3365 | s->clken[9] &= ~3; |
| 3366 | s->clken[9] |= value & 3; |
| 3367 | omap_prcm_dpll_update(s); |
| 3368 | } |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3369 | break; |
| 3370 | case 0x530: /* CM_AUTOIDLE_PLL */ |
| 3371 | s->clkidle[5] = value & 0x000000cf; |
| 3372 | /* TODO update clocks */ |
| 3373 | break; |
| 3374 | case 0x540: /* CM_CLKSEL1_PLL */ |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 3375 | if (value & 0xfc4000d7) |
| 3376 | fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for " |
| 3377 | "future compatiblity\n", __FUNCTION__); |
| 3378 | if ((s->clksel[5] ^ value) & 0x003fff00) { |
| 3379 | s->clksel[5] = value & 0x03bfff28; |
| 3380 | omap_prcm_dpll_update(s); |
| 3381 | } |
| 3382 | /* TODO update the other clocks */ |
| 3383 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3384 | s->clksel[5] = value & 0x03bfff28; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3385 | break; |
| 3386 | case 0x544: /* CM_CLKSEL2_PLL */ |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 3387 | if (value & ~3) |
| 3388 | fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for " |
| 3389 | "future compatiblity\n", __FUNCTION__); |
| 3390 | if (s->clksel[6] != (value & 3)) { |
| 3391 | s->clksel[6] = value & 3; |
| 3392 | omap_prcm_dpll_update(s); |
| 3393 | } |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3394 | break; |
| 3395 | |
| 3396 | case 0x800: /* CM_FCLKEN_DSP */ |
| 3397 | s->clken[10] = value & 0x501; |
| 3398 | /* TODO update clocks */ |
| 3399 | break; |
| 3400 | case 0x810: /* CM_ICLKEN_DSP */ |
| 3401 | s->clken[11] = value & 0x2; |
| 3402 | /* TODO update clocks */ |
| 3403 | break; |
| 3404 | case 0x830: /* CM_AUTOIDLE_DSP */ |
| 3405 | s->clkidle[6] = value & 0x2; |
| 3406 | /* TODO update clocks */ |
| 3407 | break; |
| 3408 | case 0x840: /* CM_CLKSEL_DSP */ |
| 3409 | s->clksel[7] = value & 0x3fff; |
| 3410 | /* TODO update clocks */ |
| 3411 | break; |
| 3412 | case 0x848: /* CM_CLKSTCTRL_DSP */ |
| 3413 | s->clkctrl[3] = value & 0x101; |
| 3414 | break; |
| 3415 | case 0x850: /* RM_RSTCTRL_DSP */ |
| 3416 | /* TODO: reset */ |
| 3417 | break; |
| 3418 | case 0x858: /* RM_RSTST_DSP */ |
| 3419 | s->rst[3] &= ~value; |
| 3420 | break; |
| 3421 | case 0x8c8: /* PM_WKDEP_DSP */ |
| 3422 | s->wkup[2] = value & 0x13; |
| 3423 | break; |
| 3424 | case 0x8e0: /* PM_PWSTCTRL_DSP */ |
| 3425 | s->power[3] = (value & 0x03017) | (3 << 2); |
| 3426 | break; |
| 3427 | |
| 3428 | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ |
| 3429 | s->irqst[1] &= ~value; |
| 3430 | omap_prcm_int_update(s, 1); |
| 3431 | break; |
| 3432 | case 0x8f4: /* PRCM_IRQENABLE_DSP */ |
| 3433 | s->irqen[1] = value & 0x7; |
| 3434 | omap_prcm_int_update(s, 1); |
| 3435 | break; |
| 3436 | |
| 3437 | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ |
| 3438 | s->irqst[2] &= ~value; |
| 3439 | omap_prcm_int_update(s, 2); |
| 3440 | break; |
| 3441 | case 0x8fc: /* PRCM_IRQENABLE_IVA */ |
| 3442 | s->irqen[2] = value & 0x7; |
| 3443 | omap_prcm_int_update(s, 2); |
| 3444 | break; |
| 3445 | |
| 3446 | default: |
| 3447 | OMAP_BAD_REG(addr); |
| 3448 | return; |
| 3449 | } |
| 3450 | } |
| 3451 | |
| 3452 | static CPUReadMemoryFunc *omap_prcm_readfn[] = { |
| 3453 | omap_badwidth_read32, |
| 3454 | omap_badwidth_read32, |
| 3455 | omap_prcm_read, |
| 3456 | }; |
| 3457 | |
| 3458 | static CPUWriteMemoryFunc *omap_prcm_writefn[] = { |
| 3459 | omap_badwidth_write32, |
| 3460 | omap_badwidth_write32, |
| 3461 | omap_prcm_write, |
| 3462 | }; |
| 3463 | |
| 3464 | static void omap_prcm_reset(struct omap_prcm_s *s) |
| 3465 | { |
| 3466 | s->sysconfig = 0; |
| 3467 | s->irqst[0] = 0; |
| 3468 | s->irqst[1] = 0; |
| 3469 | s->irqst[2] = 0; |
| 3470 | s->irqen[0] = 0; |
| 3471 | s->irqen[1] = 0; |
| 3472 | s->irqen[2] = 0; |
| 3473 | s->voltctrl = 0x1040; |
| 3474 | s->ev = 0x14; |
| 3475 | s->evtime[0] = 0; |
| 3476 | s->evtime[1] = 0; |
| 3477 | s->clkctrl[0] = 0; |
| 3478 | s->clkctrl[1] = 0; |
| 3479 | s->clkctrl[2] = 0; |
| 3480 | s->clkctrl[3] = 0; |
| 3481 | s->clken[1] = 7; |
| 3482 | s->clken[3] = 7; |
| 3483 | s->clken[4] = 0; |
| 3484 | s->clken[5] = 0; |
| 3485 | s->clken[6] = 0; |
| 3486 | s->clken[7] = 0xc; |
| 3487 | s->clken[8] = 0x3e; |
| 3488 | s->clken[9] = 0x0d; |
| 3489 | s->clken[10] = 0; |
| 3490 | s->clken[11] = 0; |
| 3491 | s->clkidle[0] = 0; |
| 3492 | s->clkidle[2] = 7; |
| 3493 | s->clkidle[3] = 0; |
| 3494 | s->clkidle[4] = 0; |
| 3495 | s->clkidle[5] = 0x0c; |
| 3496 | s->clkidle[6] = 0; |
| 3497 | s->clksel[0] = 0x01; |
| 3498 | s->clksel[1] = 0x02100121; |
| 3499 | s->clksel[2] = 0x00000000; |
| 3500 | s->clksel[3] = 0x01; |
| 3501 | s->clksel[4] = 0; |
| 3502 | s->clksel[7] = 0x0121; |
| 3503 | s->wkup[0] = 0x15; |
| 3504 | s->wkup[1] = 0x13; |
| 3505 | s->wkup[2] = 0x13; |
| 3506 | s->wken[0] = 0x04667ff8; |
| 3507 | s->wken[1] = 0x00000005; |
| 3508 | s->wken[2] = 5; |
| 3509 | s->wkst[0] = 0; |
| 3510 | s->wkst[1] = 0; |
| 3511 | s->wkst[2] = 0; |
| 3512 | s->power[0] = 0x00c; |
| 3513 | s->power[1] = 4; |
| 3514 | s->power[2] = 0x0000c; |
| 3515 | s->power[3] = 0x14; |
| 3516 | s->rstctrl[0] = 1; |
| 3517 | s->rst[3] = 1; |
balrog | 51fec3c | 2008-07-21 19:52:54 +0000 | [diff] [blame] | 3518 | omap_prcm_apll_update(s); |
| 3519 | omap_prcm_dpll_update(s); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3520 | } |
| 3521 | |
| 3522 | static void omap_prcm_coldreset(struct omap_prcm_s *s) |
| 3523 | { |
| 3524 | s->setuptime[0] = 0; |
| 3525 | s->setuptime[1] = 0; |
| 3526 | memset(&s->scratch, 0, sizeof(s->scratch)); |
| 3527 | s->rst[0] = 0x01; |
| 3528 | s->rst[1] = 0x00; |
| 3529 | s->rst[2] = 0x01; |
| 3530 | s->clken[0] = 0; |
| 3531 | s->clken[2] = 0; |
| 3532 | s->clkidle[1] = 0; |
| 3533 | s->clksel[5] = 0; |
| 3534 | s->clksel[6] = 2; |
| 3535 | s->clksrc[0] = 0x43; |
| 3536 | s->clkout[0] = 0x0303; |
| 3537 | s->clkemul[0] = 0; |
| 3538 | s->clkpol[0] = 0x100; |
| 3539 | s->rsttime_wkup = 0x1002; |
| 3540 | |
| 3541 | omap_prcm_reset(s); |
| 3542 | } |
| 3543 | |
| 3544 | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
| 3545 | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
| 3546 | struct omap_mpu_state_s *mpu) |
| 3547 | { |
| 3548 | int iomemtype; |
| 3549 | struct omap_prcm_s *s = (struct omap_prcm_s *) |
| 3550 | qemu_mallocz(sizeof(struct omap_prcm_s)); |
| 3551 | |
| 3552 | s->irq[0] = mpu_int; |
| 3553 | s->irq[1] = dsp_int; |
| 3554 | s->irq[2] = iva_int; |
| 3555 | s->mpu = mpu; |
| 3556 | omap_prcm_coldreset(s); |
| 3557 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 3558 | iomemtype = l4_register_io_memory(0, omap_prcm_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3559 | omap_prcm_writefn, s); |
| 3560 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 3561 | omap_l4_attach(ta, 1, iomemtype); |
| 3562 | |
| 3563 | return s; |
| 3564 | } |
| 3565 | |
| 3566 | /* System and Pinout control */ |
| 3567 | struct omap_sysctl_s { |
| 3568 | target_phys_addr_t base; |
| 3569 | struct omap_mpu_state_s *mpu; |
| 3570 | |
| 3571 | uint32_t sysconfig; |
| 3572 | uint32_t devconfig; |
| 3573 | uint32_t psaconfig; |
| 3574 | uint32_t padconf[0x45]; |
| 3575 | uint8_t obs; |
| 3576 | uint32_t msuspendmux[5]; |
| 3577 | }; |
| 3578 | |
balrog | f451387 | 2008-07-25 21:07:21 +0000 | [diff] [blame] | 3579 | static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr) |
| 3580 | { |
| 3581 | |
| 3582 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 3583 | int offset = addr - s->base; |
| 3584 | int pad_offset, byte_offset; |
| 3585 | int value; |
| 3586 | |
| 3587 | switch (offset) { |
| 3588 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 3589 | pad_offset = (offset - 0x30) >> 2; |
| 3590 | byte_offset = (offset - 0x30) & (4 - 1); |
| 3591 | |
| 3592 | value = s->padconf[pad_offset]; |
| 3593 | value = (value >> (byte_offset * 8)) & 0xff; |
| 3594 | |
| 3595 | return value; |
| 3596 | |
| 3597 | default: |
| 3598 | break; |
| 3599 | } |
| 3600 | |
| 3601 | OMAP_BAD_REG(addr); |
| 3602 | return 0; |
| 3603 | } |
| 3604 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3605 | static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) |
| 3606 | { |
| 3607 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 3608 | int offset = addr - s->base; |
| 3609 | |
| 3610 | switch (offset) { |
| 3611 | case 0x000: /* CONTROL_REVISION */ |
| 3612 | return 0x20; |
| 3613 | |
| 3614 | case 0x010: /* CONTROL_SYSCONFIG */ |
| 3615 | return s->sysconfig; |
| 3616 | |
| 3617 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 3618 | return s->padconf[(offset - 0x30) >> 2]; |
| 3619 | |
| 3620 | case 0x270: /* CONTROL_DEBOBS */ |
| 3621 | return s->obs; |
| 3622 | |
| 3623 | case 0x274: /* CONTROL_DEVCONF */ |
| 3624 | return s->devconfig; |
| 3625 | |
| 3626 | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
| 3627 | return 0; |
| 3628 | |
| 3629 | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
| 3630 | return s->msuspendmux[0]; |
| 3631 | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
| 3632 | return s->msuspendmux[1]; |
| 3633 | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
| 3634 | return s->msuspendmux[2]; |
| 3635 | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
| 3636 | return s->msuspendmux[3]; |
| 3637 | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
| 3638 | return s->msuspendmux[4]; |
| 3639 | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
| 3640 | return 0; |
| 3641 | |
| 3642 | case 0x2b8: /* CONTROL_PSA_CTRL */ |
| 3643 | return s->psaconfig; |
| 3644 | case 0x2bc: /* CONTROL_PSA_CMD */ |
| 3645 | case 0x2c0: /* CONTROL_PSA_VALUE */ |
| 3646 | return 0; |
| 3647 | |
| 3648 | case 0x2b0: /* CONTROL_SEC_CTRL */ |
| 3649 | return 0x800000f1; |
| 3650 | case 0x2d0: /* CONTROL_SEC_EMU */ |
| 3651 | return 0x80000015; |
| 3652 | case 0x2d4: /* CONTROL_SEC_TAP */ |
| 3653 | return 0x8000007f; |
| 3654 | case 0x2b4: /* CONTROL_SEC_TEST */ |
| 3655 | case 0x2f0: /* CONTROL_SEC_STATUS */ |
| 3656 | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
| 3657 | /* Secure mode is not present on general-pusrpose device. Outside |
| 3658 | * secure mode these values cannot be read or written. */ |
| 3659 | return 0; |
| 3660 | |
| 3661 | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
| 3662 | return 0xff; |
| 3663 | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
| 3664 | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
| 3665 | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
| 3666 | /* No secure mode so no Extended Secure RAM present. */ |
| 3667 | return 0; |
| 3668 | |
| 3669 | case 0x2f8: /* CONTROL_STATUS */ |
| 3670 | /* Device Type => General-purpose */ |
| 3671 | return 0x0300; |
| 3672 | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
| 3673 | |
| 3674 | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
| 3675 | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
| 3676 | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
| 3677 | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
| 3678 | return 0xdecafbad; |
| 3679 | |
| 3680 | case 0x310: /* CONTROL_RAND_KEY_0 */ |
| 3681 | case 0x314: /* CONTROL_RAND_KEY_1 */ |
| 3682 | case 0x318: /* CONTROL_RAND_KEY_2 */ |
| 3683 | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
| 3684 | case 0x320: /* CONTROL_CUST_KEY_0 */ |
| 3685 | case 0x324: /* CONTROL_CUST_KEY_1 */ |
| 3686 | case 0x330: /* CONTROL_TEST_KEY_0 */ |
| 3687 | case 0x334: /* CONTROL_TEST_KEY_1 */ |
| 3688 | case 0x338: /* CONTROL_TEST_KEY_2 */ |
| 3689 | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
| 3690 | case 0x340: /* CONTROL_TEST_KEY_4 */ |
| 3691 | case 0x344: /* CONTROL_TEST_KEY_5 */ |
| 3692 | case 0x348: /* CONTROL_TEST_KEY_6 */ |
| 3693 | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
| 3694 | case 0x350: /* CONTROL_TEST_KEY_8 */ |
| 3695 | case 0x354: /* CONTROL_TEST_KEY_9 */ |
| 3696 | /* Can only be accessed in secure mode and when C_FieldAccEnable |
| 3697 | * bit is set in CONTROL_SEC_CTRL. |
| 3698 | * TODO: otherwise an interconnect access error is generated. */ |
| 3699 | return 0; |
| 3700 | } |
| 3701 | |
| 3702 | OMAP_BAD_REG(addr); |
| 3703 | return 0; |
| 3704 | } |
| 3705 | |
balrog | f451387 | 2008-07-25 21:07:21 +0000 | [diff] [blame] | 3706 | static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr, |
| 3707 | uint32_t value) |
| 3708 | { |
| 3709 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 3710 | int offset = addr - s->base; |
| 3711 | int pad_offset, byte_offset; |
| 3712 | int prev_value; |
| 3713 | |
| 3714 | switch (offset) { |
| 3715 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 3716 | pad_offset = (offset - 0x30) >> 2; |
| 3717 | byte_offset = (offset - 0x30) & (4 - 1); |
| 3718 | |
| 3719 | prev_value = s->padconf[pad_offset]; |
| 3720 | prev_value &= ~(0xff << (byte_offset * 8)); |
| 3721 | prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f; |
| 3722 | s->padconf[pad_offset] = prev_value; |
| 3723 | break; |
| 3724 | |
| 3725 | default: |
| 3726 | OMAP_BAD_REG(addr); |
| 3727 | break; |
| 3728 | } |
| 3729 | } |
| 3730 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3731 | static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, |
| 3732 | uint32_t value) |
| 3733 | { |
| 3734 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; |
| 3735 | int offset = addr - s->base; |
| 3736 | |
| 3737 | switch (offset) { |
| 3738 | case 0x000: /* CONTROL_REVISION */ |
| 3739 | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ |
| 3740 | case 0x2c0: /* CONTROL_PSA_VALUE */ |
| 3741 | case 0x2f8: /* CONTROL_STATUS */ |
| 3742 | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ |
| 3743 | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ |
| 3744 | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ |
| 3745 | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ |
| 3746 | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ |
| 3747 | case 0x310: /* CONTROL_RAND_KEY_0 */ |
| 3748 | case 0x314: /* CONTROL_RAND_KEY_1 */ |
| 3749 | case 0x318: /* CONTROL_RAND_KEY_2 */ |
| 3750 | case 0x31c: /* CONTROL_RAND_KEY_3 */ |
| 3751 | case 0x320: /* CONTROL_CUST_KEY_0 */ |
| 3752 | case 0x324: /* CONTROL_CUST_KEY_1 */ |
| 3753 | case 0x330: /* CONTROL_TEST_KEY_0 */ |
| 3754 | case 0x334: /* CONTROL_TEST_KEY_1 */ |
| 3755 | case 0x338: /* CONTROL_TEST_KEY_2 */ |
| 3756 | case 0x33c: /* CONTROL_TEST_KEY_3 */ |
| 3757 | case 0x340: /* CONTROL_TEST_KEY_4 */ |
| 3758 | case 0x344: /* CONTROL_TEST_KEY_5 */ |
| 3759 | case 0x348: /* CONTROL_TEST_KEY_6 */ |
| 3760 | case 0x34c: /* CONTROL_TEST_KEY_7 */ |
| 3761 | case 0x350: /* CONTROL_TEST_KEY_8 */ |
| 3762 | case 0x354: /* CONTROL_TEST_KEY_9 */ |
| 3763 | OMAP_RO_REG(addr); |
| 3764 | return; |
| 3765 | |
| 3766 | case 0x010: /* CONTROL_SYSCONFIG */ |
| 3767 | s->sysconfig = value & 0x1e; |
| 3768 | break; |
| 3769 | |
| 3770 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ |
| 3771 | /* XXX: should check constant bits */ |
| 3772 | s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f; |
| 3773 | break; |
| 3774 | |
| 3775 | case 0x270: /* CONTROL_DEBOBS */ |
| 3776 | s->obs = value & 0xff; |
| 3777 | break; |
| 3778 | |
| 3779 | case 0x274: /* CONTROL_DEVCONF */ |
| 3780 | s->devconfig = value & 0xffffc7ff; |
| 3781 | break; |
| 3782 | |
| 3783 | case 0x28c: /* CONTROL_EMU_SUPPORT */ |
| 3784 | break; |
| 3785 | |
| 3786 | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ |
| 3787 | s->msuspendmux[0] = value & 0x3fffffff; |
| 3788 | break; |
| 3789 | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ |
| 3790 | s->msuspendmux[1] = value & 0x3fffffff; |
| 3791 | break; |
| 3792 | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ |
| 3793 | s->msuspendmux[2] = value & 0x3fffffff; |
| 3794 | break; |
| 3795 | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ |
| 3796 | s->msuspendmux[3] = value & 0x3fffffff; |
| 3797 | break; |
| 3798 | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ |
| 3799 | s->msuspendmux[4] = value & 0x3fffffff; |
| 3800 | break; |
| 3801 | |
| 3802 | case 0x2b8: /* CONTROL_PSA_CTRL */ |
| 3803 | s->psaconfig = value & 0x1c; |
| 3804 | s->psaconfig |= (value & 0x20) ? 2 : 1; |
| 3805 | break; |
| 3806 | case 0x2bc: /* CONTROL_PSA_CMD */ |
| 3807 | break; |
| 3808 | |
| 3809 | case 0x2b0: /* CONTROL_SEC_CTRL */ |
| 3810 | case 0x2b4: /* CONTROL_SEC_TEST */ |
| 3811 | case 0x2d0: /* CONTROL_SEC_EMU */ |
| 3812 | case 0x2d4: /* CONTROL_SEC_TAP */ |
| 3813 | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ |
| 3814 | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ |
| 3815 | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ |
| 3816 | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ |
| 3817 | case 0x2f0: /* CONTROL_SEC_STATUS */ |
| 3818 | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ |
| 3819 | break; |
| 3820 | |
| 3821 | default: |
| 3822 | OMAP_BAD_REG(addr); |
| 3823 | return; |
| 3824 | } |
| 3825 | } |
| 3826 | |
| 3827 | static CPUReadMemoryFunc *omap_sysctl_readfn[] = { |
balrog | f451387 | 2008-07-25 21:07:21 +0000 | [diff] [blame] | 3828 | omap_sysctl_read8, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3829 | omap_badwidth_read32, /* TODO */ |
| 3830 | omap_sysctl_read, |
| 3831 | }; |
| 3832 | |
| 3833 | static CPUWriteMemoryFunc *omap_sysctl_writefn[] = { |
balrog | f451387 | 2008-07-25 21:07:21 +0000 | [diff] [blame] | 3834 | omap_sysctl_write8, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3835 | omap_badwidth_write32, /* TODO */ |
| 3836 | omap_sysctl_write, |
| 3837 | }; |
| 3838 | |
| 3839 | static void omap_sysctl_reset(struct omap_sysctl_s *s) |
| 3840 | { |
| 3841 | /* (power-on reset) */ |
| 3842 | s->sysconfig = 0; |
| 3843 | s->obs = 0; |
| 3844 | s->devconfig = 0x0c000000; |
| 3845 | s->msuspendmux[0] = 0x00000000; |
| 3846 | s->msuspendmux[1] = 0x00000000; |
| 3847 | s->msuspendmux[2] = 0x00000000; |
| 3848 | s->msuspendmux[3] = 0x00000000; |
| 3849 | s->msuspendmux[4] = 0x00000000; |
| 3850 | s->psaconfig = 1; |
| 3851 | |
| 3852 | s->padconf[0x00] = 0x000f0f0f; |
| 3853 | s->padconf[0x01] = 0x00000000; |
| 3854 | s->padconf[0x02] = 0x00000000; |
| 3855 | s->padconf[0x03] = 0x00000000; |
| 3856 | s->padconf[0x04] = 0x00000000; |
| 3857 | s->padconf[0x05] = 0x00000000; |
| 3858 | s->padconf[0x06] = 0x00000000; |
| 3859 | s->padconf[0x07] = 0x00000000; |
| 3860 | s->padconf[0x08] = 0x08080800; |
| 3861 | s->padconf[0x09] = 0x08080808; |
| 3862 | s->padconf[0x0a] = 0x08080808; |
| 3863 | s->padconf[0x0b] = 0x08080808; |
| 3864 | s->padconf[0x0c] = 0x08080808; |
| 3865 | s->padconf[0x0d] = 0x08080800; |
| 3866 | s->padconf[0x0e] = 0x08080808; |
| 3867 | s->padconf[0x0f] = 0x08080808; |
| 3868 | s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ |
| 3869 | s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 3870 | s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 3871 | s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ |
| 3872 | s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ |
| 3873 | s->padconf[0x15] = 0x18181818; |
| 3874 | s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ |
| 3875 | s->padconf[0x17] = 0x1f001f00; |
| 3876 | s->padconf[0x18] = 0x1f1f1f1f; |
| 3877 | s->padconf[0x19] = 0x00000000; |
| 3878 | s->padconf[0x1a] = 0x1f180000; |
| 3879 | s->padconf[0x1b] = 0x00001f1f; |
| 3880 | s->padconf[0x1c] = 0x1f001f00; |
| 3881 | s->padconf[0x1d] = 0x00000000; |
| 3882 | s->padconf[0x1e] = 0x00000000; |
| 3883 | s->padconf[0x1f] = 0x08000000; |
| 3884 | s->padconf[0x20] = 0x08080808; |
| 3885 | s->padconf[0x21] = 0x08080808; |
| 3886 | s->padconf[0x22] = 0x0f080808; |
| 3887 | s->padconf[0x23] = 0x0f0f0f0f; |
| 3888 | s->padconf[0x24] = 0x000f0f0f; |
| 3889 | s->padconf[0x25] = 0x1f1f1f0f; |
| 3890 | s->padconf[0x26] = 0x080f0f1f; |
| 3891 | s->padconf[0x27] = 0x070f1808; |
| 3892 | s->padconf[0x28] = 0x0f070707; |
| 3893 | s->padconf[0x29] = 0x000f0f1f; |
| 3894 | s->padconf[0x2a] = 0x0f0f0f1f; |
| 3895 | s->padconf[0x2b] = 0x08000000; |
| 3896 | s->padconf[0x2c] = 0x0000001f; |
| 3897 | s->padconf[0x2d] = 0x0f0f1f00; |
| 3898 | s->padconf[0x2e] = 0x1f1f0f0f; |
| 3899 | s->padconf[0x2f] = 0x0f1f1f1f; |
| 3900 | s->padconf[0x30] = 0x0f0f0f0f; |
| 3901 | s->padconf[0x31] = 0x0f1f0f1f; |
| 3902 | s->padconf[0x32] = 0x0f0f0f0f; |
| 3903 | s->padconf[0x33] = 0x0f1f0f1f; |
| 3904 | s->padconf[0x34] = 0x1f1f0f0f; |
| 3905 | s->padconf[0x35] = 0x0f0f1f1f; |
| 3906 | s->padconf[0x36] = 0x0f0f1f0f; |
| 3907 | s->padconf[0x37] = 0x0f0f0f0f; |
| 3908 | s->padconf[0x38] = 0x1f18180f; |
| 3909 | s->padconf[0x39] = 0x1f1f1f1f; |
| 3910 | s->padconf[0x3a] = 0x00001f1f; |
| 3911 | s->padconf[0x3b] = 0x00000000; |
| 3912 | s->padconf[0x3c] = 0x00000000; |
| 3913 | s->padconf[0x3d] = 0x0f0f0f0f; |
| 3914 | s->padconf[0x3e] = 0x18000f0f; |
| 3915 | s->padconf[0x3f] = 0x00070000; |
| 3916 | s->padconf[0x40] = 0x00000707; |
| 3917 | s->padconf[0x41] = 0x0f1f0700; |
| 3918 | s->padconf[0x42] = 0x1f1f070f; |
| 3919 | s->padconf[0x43] = 0x0008081f; |
| 3920 | s->padconf[0x44] = 0x00000800; |
| 3921 | } |
| 3922 | |
| 3923 | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
| 3924 | omap_clk iclk, struct omap_mpu_state_s *mpu) |
| 3925 | { |
| 3926 | int iomemtype; |
| 3927 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) |
| 3928 | qemu_mallocz(sizeof(struct omap_sysctl_s)); |
| 3929 | |
| 3930 | s->mpu = mpu; |
| 3931 | omap_sysctl_reset(s); |
| 3932 | |
balrog | c66fb5b | 2008-05-18 12:14:41 +0000 | [diff] [blame] | 3933 | iomemtype = l4_register_io_memory(0, omap_sysctl_readfn, |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 3934 | omap_sysctl_writefn, s); |
| 3935 | s->base = omap_l4_attach(ta, 0, iomemtype); |
| 3936 | omap_l4_attach(ta, 0, iomemtype); |
| 3937 | |
| 3938 | return s; |
| 3939 | } |
| 3940 | |
| 3941 | /* SDRAM Controller Subsystem */ |
| 3942 | struct omap_sdrc_s { |
| 3943 | target_phys_addr_t base; |
| 3944 | |
| 3945 | uint8_t config; |
| 3946 | }; |
| 3947 | |
| 3948 | static void omap_sdrc_reset(struct omap_sdrc_s *s) |
| 3949 | { |
| 3950 | s->config = 0x10; |
| 3951 | } |
| 3952 | |
| 3953 | static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) |
| 3954 | { |
| 3955 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
| 3956 | int offset = addr - s->base; |
| 3957 | |
| 3958 | switch (offset) { |
| 3959 | case 0x00: /* SDRC_REVISION */ |
| 3960 | return 0x20; |
| 3961 | |
| 3962 | case 0x10: /* SDRC_SYSCONFIG */ |
| 3963 | return s->config; |
| 3964 | |
| 3965 | case 0x14: /* SDRC_SYSSTATUS */ |
| 3966 | return 1; /* RESETDONE */ |
| 3967 | |
| 3968 | case 0x40: /* SDRC_CS_CFG */ |
| 3969 | case 0x44: /* SDRC_SHARING */ |
| 3970 | case 0x48: /* SDRC_ERR_ADDR */ |
| 3971 | case 0x4c: /* SDRC_ERR_TYPE */ |
| 3972 | case 0x60: /* SDRC_DLLA_SCTRL */ |
| 3973 | case 0x64: /* SDRC_DLLA_STATUS */ |
| 3974 | case 0x68: /* SDRC_DLLB_CTRL */ |
| 3975 | case 0x6c: /* SDRC_DLLB_STATUS */ |
| 3976 | case 0x70: /* SDRC_POWER */ |
| 3977 | case 0x80: /* SDRC_MCFG_0 */ |
| 3978 | case 0x84: /* SDRC_MR_0 */ |
| 3979 | case 0x88: /* SDRC_EMR1_0 */ |
| 3980 | case 0x8c: /* SDRC_EMR2_0 */ |
| 3981 | case 0x90: /* SDRC_EMR3_0 */ |
| 3982 | case 0x94: /* SDRC_DCDL1_CTRL */ |
| 3983 | case 0x98: /* SDRC_DCDL2_CTRL */ |
| 3984 | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
| 3985 | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
| 3986 | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
| 3987 | case 0xa8: /* SDRC_MANUAL_0 */ |
| 3988 | case 0xb0: /* SDRC_MCFG_1 */ |
| 3989 | case 0xb4: /* SDRC_MR_1 */ |
| 3990 | case 0xb8: /* SDRC_EMR1_1 */ |
| 3991 | case 0xbc: /* SDRC_EMR2_1 */ |
| 3992 | case 0xc0: /* SDRC_EMR3_1 */ |
| 3993 | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
| 3994 | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
| 3995 | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
| 3996 | case 0xd8: /* SDRC_MANUAL_1 */ |
| 3997 | return 0x00; |
| 3998 | } |
| 3999 | |
| 4000 | OMAP_BAD_REG(addr); |
| 4001 | return 0; |
| 4002 | } |
| 4003 | |
| 4004 | static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, |
| 4005 | uint32_t value) |
| 4006 | { |
| 4007 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; |
| 4008 | int offset = addr - s->base; |
| 4009 | |
| 4010 | switch (offset) { |
| 4011 | case 0x00: /* SDRC_REVISION */ |
| 4012 | case 0x14: /* SDRC_SYSSTATUS */ |
| 4013 | case 0x48: /* SDRC_ERR_ADDR */ |
| 4014 | case 0x64: /* SDRC_DLLA_STATUS */ |
| 4015 | case 0x6c: /* SDRC_DLLB_STATUS */ |
| 4016 | OMAP_RO_REG(addr); |
| 4017 | return; |
| 4018 | |
| 4019 | case 0x10: /* SDRC_SYSCONFIG */ |
| 4020 | if ((value >> 3) != 0x2) |
| 4021 | fprintf(stderr, "%s: bad SDRAM idle mode %i\n", |
| 4022 | __FUNCTION__, value >> 3); |
| 4023 | if (value & 2) |
| 4024 | omap_sdrc_reset(s); |
| 4025 | s->config = value & 0x18; |
| 4026 | break; |
| 4027 | |
| 4028 | case 0x40: /* SDRC_CS_CFG */ |
| 4029 | case 0x44: /* SDRC_SHARING */ |
| 4030 | case 0x4c: /* SDRC_ERR_TYPE */ |
| 4031 | case 0x60: /* SDRC_DLLA_SCTRL */ |
| 4032 | case 0x68: /* SDRC_DLLB_CTRL */ |
| 4033 | case 0x70: /* SDRC_POWER */ |
| 4034 | case 0x80: /* SDRC_MCFG_0 */ |
| 4035 | case 0x84: /* SDRC_MR_0 */ |
| 4036 | case 0x88: /* SDRC_EMR1_0 */ |
| 4037 | case 0x8c: /* SDRC_EMR2_0 */ |
| 4038 | case 0x90: /* SDRC_EMR3_0 */ |
| 4039 | case 0x94: /* SDRC_DCDL1_CTRL */ |
| 4040 | case 0x98: /* SDRC_DCDL2_CTRL */ |
| 4041 | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ |
| 4042 | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ |
| 4043 | case 0xa4: /* SDRC_RFR_CTRL_0 */ |
| 4044 | case 0xa8: /* SDRC_MANUAL_0 */ |
| 4045 | case 0xb0: /* SDRC_MCFG_1 */ |
| 4046 | case 0xb4: /* SDRC_MR_1 */ |
| 4047 | case 0xb8: /* SDRC_EMR1_1 */ |
| 4048 | case 0xbc: /* SDRC_EMR2_1 */ |
| 4049 | case 0xc0: /* SDRC_EMR3_1 */ |
| 4050 | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ |
| 4051 | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ |
| 4052 | case 0xd4: /* SDRC_RFR_CTRL_1 */ |
| 4053 | case 0xd8: /* SDRC_MANUAL_1 */ |
| 4054 | break; |
| 4055 | |
| 4056 | default: |
| 4057 | OMAP_BAD_REG(addr); |
| 4058 | return; |
| 4059 | } |
| 4060 | } |
| 4061 | |
| 4062 | static CPUReadMemoryFunc *omap_sdrc_readfn[] = { |
| 4063 | omap_badwidth_read32, |
| 4064 | omap_badwidth_read32, |
| 4065 | omap_sdrc_read, |
| 4066 | }; |
| 4067 | |
| 4068 | static CPUWriteMemoryFunc *omap_sdrc_writefn[] = { |
| 4069 | omap_badwidth_write32, |
| 4070 | omap_badwidth_write32, |
| 4071 | omap_sdrc_write, |
| 4072 | }; |
| 4073 | |
| 4074 | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base) |
| 4075 | { |
| 4076 | int iomemtype; |
| 4077 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) |
| 4078 | qemu_mallocz(sizeof(struct omap_sdrc_s)); |
| 4079 | |
| 4080 | s->base = base; |
| 4081 | omap_sdrc_reset(s); |
| 4082 | |
| 4083 | iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn, |
| 4084 | omap_sdrc_writefn, s); |
| 4085 | cpu_register_physical_memory(s->base, 0x1000, iomemtype); |
| 4086 | |
| 4087 | return s; |
| 4088 | } |
| 4089 | |
| 4090 | /* General-Purpose Memory Controller */ |
| 4091 | struct omap_gpmc_s { |
| 4092 | target_phys_addr_t base; |
| 4093 | qemu_irq irq; |
| 4094 | |
| 4095 | uint8_t sysconfig; |
| 4096 | uint16_t irqst; |
| 4097 | uint16_t irqen; |
| 4098 | uint16_t timeout; |
| 4099 | uint16_t config; |
| 4100 | uint32_t prefconfig[2]; |
| 4101 | int prefcontrol; |
| 4102 | int preffifo; |
| 4103 | int prefcount; |
| 4104 | struct omap_gpmc_cs_file_s { |
| 4105 | uint32_t config[7]; |
| 4106 | target_phys_addr_t base; |
| 4107 | size_t size; |
| 4108 | int iomemtype; |
| 4109 | void (*base_update)(void *opaque, target_phys_addr_t new); |
| 4110 | void (*unmap)(void *opaque); |
| 4111 | void *opaque; |
| 4112 | } cs_file[8]; |
| 4113 | int ecc_cs; |
| 4114 | int ecc_ptr; |
| 4115 | uint32_t ecc_cfg; |
| 4116 | struct ecc_state_s ecc[9]; |
| 4117 | }; |
| 4118 | |
| 4119 | static void omap_gpmc_int_update(struct omap_gpmc_s *s) |
| 4120 | { |
| 4121 | qemu_set_irq(s->irq, s->irqen & s->irqst); |
| 4122 | } |
| 4123 | |
| 4124 | static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask) |
| 4125 | { |
| 4126 | /* TODO: check for overlapping regions and report access errors */ |
| 4127 | if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) || |
| 4128 | (base < 0 || base >= 0x40) || |
| 4129 | (base & 0x0f & ~mask)) { |
| 4130 | fprintf(stderr, "%s: wrong cs address mapping/decoding!\n", |
| 4131 | __FUNCTION__); |
| 4132 | return; |
| 4133 | } |
| 4134 | |
| 4135 | if (!f->opaque) |
| 4136 | return; |
| 4137 | |
| 4138 | f->base = base << 24; |
| 4139 | f->size = (0x0fffffff & ~(mask << 24)) + 1; |
| 4140 | /* TODO: rather than setting the size of the mapping (which should be |
| 4141 | * constant), the mask should cause wrapping of the address space, so |
| 4142 | * that the same memory becomes accessible at every <i>size</i> bytes |
| 4143 | * starting from <i>base</i>. */ |
| 4144 | if (f->iomemtype) |
| 4145 | cpu_register_physical_memory(f->base, f->size, f->iomemtype); |
| 4146 | |
| 4147 | if (f->base_update) |
| 4148 | f->base_update(f->opaque, f->base); |
| 4149 | } |
| 4150 | |
| 4151 | static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f) |
| 4152 | { |
| 4153 | if (f->size) { |
| 4154 | if (f->unmap) |
| 4155 | f->unmap(f->opaque); |
| 4156 | if (f->iomemtype) |
| 4157 | cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED); |
| 4158 | f->base = 0; |
| 4159 | f->size = 0; |
| 4160 | } |
| 4161 | } |
| 4162 | |
| 4163 | static void omap_gpmc_reset(struct omap_gpmc_s *s) |
| 4164 | { |
| 4165 | int i; |
| 4166 | |
| 4167 | s->sysconfig = 0; |
| 4168 | s->irqst = 0; |
| 4169 | s->irqen = 0; |
| 4170 | omap_gpmc_int_update(s); |
| 4171 | s->timeout = 0; |
| 4172 | s->config = 0xa00; |
| 4173 | s->prefconfig[0] = 0x00004000; |
| 4174 | s->prefconfig[1] = 0x00000000; |
| 4175 | s->prefcontrol = 0; |
| 4176 | s->preffifo = 0; |
| 4177 | s->prefcount = 0; |
| 4178 | for (i = 0; i < 8; i ++) { |
| 4179 | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ |
| 4180 | omap_gpmc_cs_unmap(s->cs_file + i); |
| 4181 | s->cs_file[i].config[0] = i ? 1 << 12 : 0; |
| 4182 | s->cs_file[i].config[1] = 0x101001; |
| 4183 | s->cs_file[i].config[2] = 0x020201; |
| 4184 | s->cs_file[i].config[3] = 0x10031003; |
| 4185 | s->cs_file[i].config[4] = 0x10f1111; |
| 4186 | s->cs_file[i].config[5] = 0; |
| 4187 | s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6); |
| 4188 | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ |
| 4189 | omap_gpmc_cs_map(&s->cs_file[i], |
| 4190 | s->cs_file[i].config[6] & 0x1f, /* MASKADDR */ |
| 4191 | (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */ |
| 4192 | } |
| 4193 | omap_gpmc_cs_map(s->cs_file, 0, 0xf); |
| 4194 | s->ecc_cs = 0; |
| 4195 | s->ecc_ptr = 0; |
| 4196 | s->ecc_cfg = 0x3fcff000; |
| 4197 | for (i = 0; i < 9; i ++) |
| 4198 | ecc_reset(&s->ecc[i]); |
| 4199 | } |
| 4200 | |
| 4201 | static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) |
| 4202 | { |
| 4203 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
| 4204 | int offset = addr - s->base; |
| 4205 | int cs; |
| 4206 | struct omap_gpmc_cs_file_s *f; |
| 4207 | |
| 4208 | switch (offset) { |
| 4209 | case 0x000: /* GPMC_REVISION */ |
| 4210 | return 0x20; |
| 4211 | |
| 4212 | case 0x010: /* GPMC_SYSCONFIG */ |
| 4213 | return s->sysconfig; |
| 4214 | |
| 4215 | case 0x014: /* GPMC_SYSSTATUS */ |
| 4216 | return 1; /* RESETDONE */ |
| 4217 | |
| 4218 | case 0x018: /* GPMC_IRQSTATUS */ |
| 4219 | return s->irqst; |
| 4220 | |
| 4221 | case 0x01c: /* GPMC_IRQENABLE */ |
| 4222 | return s->irqen; |
| 4223 | |
| 4224 | case 0x040: /* GPMC_TIMEOUT_CONTROL */ |
| 4225 | return s->timeout; |
| 4226 | |
| 4227 | case 0x044: /* GPMC_ERR_ADDRESS */ |
| 4228 | case 0x048: /* GPMC_ERR_TYPE */ |
| 4229 | return 0; |
| 4230 | |
| 4231 | case 0x050: /* GPMC_CONFIG */ |
| 4232 | return s->config; |
| 4233 | |
| 4234 | case 0x054: /* GPMC_STATUS */ |
| 4235 | return 0x001; |
| 4236 | |
| 4237 | case 0x060 ... 0x1d4: |
| 4238 | cs = (offset - 0x060) / 0x30; |
| 4239 | offset -= cs * 0x30; |
| 4240 | f = s->cs_file + cs; |
balrog | f451387 | 2008-07-25 21:07:21 +0000 | [diff] [blame] | 4241 | switch (offset) { |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4242 | case 0x60: /* GPMC_CONFIG1 */ |
| 4243 | return f->config[0]; |
| 4244 | case 0x64: /* GPMC_CONFIG2 */ |
| 4245 | return f->config[1]; |
| 4246 | case 0x68: /* GPMC_CONFIG3 */ |
| 4247 | return f->config[2]; |
| 4248 | case 0x6c: /* GPMC_CONFIG4 */ |
| 4249 | return f->config[3]; |
| 4250 | case 0x70: /* GPMC_CONFIG5 */ |
| 4251 | return f->config[4]; |
| 4252 | case 0x74: /* GPMC_CONFIG6 */ |
| 4253 | return f->config[5]; |
| 4254 | case 0x78: /* GPMC_CONFIG7 */ |
| 4255 | return f->config[6]; |
| 4256 | case 0x84: /* GPMC_NAND_DATA */ |
| 4257 | return 0; |
| 4258 | } |
| 4259 | break; |
| 4260 | |
| 4261 | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ |
| 4262 | return s->prefconfig[0]; |
| 4263 | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ |
| 4264 | return s->prefconfig[1]; |
| 4265 | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ |
| 4266 | return s->prefcontrol; |
| 4267 | case 0x1f0: /* GPMC_PREFETCH_STATUS */ |
| 4268 | return (s->preffifo << 24) | |
| 4269 | ((s->preffifo > |
| 4270 | ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) | |
| 4271 | s->prefcount; |
| 4272 | |
| 4273 | case 0x1f4: /* GPMC_ECC_CONFIG */ |
| 4274 | return s->ecc_cs; |
| 4275 | case 0x1f8: /* GPMC_ECC_CONTROL */ |
| 4276 | return s->ecc_ptr; |
| 4277 | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ |
| 4278 | return s->ecc_cfg; |
| 4279 | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ |
| 4280 | cs = (offset & 0x1f) >> 2; |
| 4281 | /* TODO: check correctness */ |
| 4282 | return |
| 4283 | ((s->ecc[cs].cp & 0x07) << 0) | |
| 4284 | ((s->ecc[cs].cp & 0x38) << 13) | |
| 4285 | ((s->ecc[cs].lp[0] & 0x1ff) << 3) | |
| 4286 | ((s->ecc[cs].lp[1] & 0x1ff) << 19); |
| 4287 | |
| 4288 | case 0x230: /* GPMC_TESTMODE_CTRL */ |
| 4289 | return 0; |
| 4290 | case 0x234: /* GPMC_PSA_LSB */ |
| 4291 | case 0x238: /* GPMC_PSA_MSB */ |
| 4292 | return 0x00000000; |
| 4293 | } |
| 4294 | |
| 4295 | OMAP_BAD_REG(addr); |
| 4296 | return 0; |
| 4297 | } |
| 4298 | |
| 4299 | static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, |
| 4300 | uint32_t value) |
| 4301 | { |
| 4302 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; |
| 4303 | int offset = addr - s->base; |
| 4304 | int cs; |
| 4305 | struct omap_gpmc_cs_file_s *f; |
| 4306 | |
| 4307 | switch (offset) { |
| 4308 | case 0x000: /* GPMC_REVISION */ |
| 4309 | case 0x014: /* GPMC_SYSSTATUS */ |
| 4310 | case 0x054: /* GPMC_STATUS */ |
| 4311 | case 0x1f0: /* GPMC_PREFETCH_STATUS */ |
| 4312 | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ |
| 4313 | case 0x234: /* GPMC_PSA_LSB */ |
| 4314 | case 0x238: /* GPMC_PSA_MSB */ |
| 4315 | OMAP_RO_REG(addr); |
| 4316 | break; |
| 4317 | |
| 4318 | case 0x010: /* GPMC_SYSCONFIG */ |
| 4319 | if ((value >> 3) == 0x3) |
| 4320 | fprintf(stderr, "%s: bad SDRAM idle mode %i\n", |
| 4321 | __FUNCTION__, value >> 3); |
| 4322 | if (value & 2) |
| 4323 | omap_gpmc_reset(s); |
| 4324 | s->sysconfig = value & 0x19; |
| 4325 | break; |
| 4326 | |
| 4327 | case 0x018: /* GPMC_IRQSTATUS */ |
| 4328 | s->irqen = ~value; |
| 4329 | omap_gpmc_int_update(s); |
| 4330 | break; |
| 4331 | |
| 4332 | case 0x01c: /* GPMC_IRQENABLE */ |
| 4333 | s->irqen = value & 0xf03; |
| 4334 | omap_gpmc_int_update(s); |
| 4335 | break; |
| 4336 | |
| 4337 | case 0x040: /* GPMC_TIMEOUT_CONTROL */ |
| 4338 | s->timeout = value & 0x1ff1; |
| 4339 | break; |
| 4340 | |
| 4341 | case 0x044: /* GPMC_ERR_ADDRESS */ |
| 4342 | case 0x048: /* GPMC_ERR_TYPE */ |
| 4343 | break; |
| 4344 | |
| 4345 | case 0x050: /* GPMC_CONFIG */ |
| 4346 | s->config = value & 0xf13; |
| 4347 | break; |
| 4348 | |
| 4349 | case 0x060 ... 0x1d4: |
| 4350 | cs = (offset - 0x060) / 0x30; |
| 4351 | offset -= cs * 0x30; |
| 4352 | f = s->cs_file + cs; |
| 4353 | switch (offset) { |
| 4354 | case 0x60: /* GPMC_CONFIG1 */ |
| 4355 | f->config[0] = value & 0xffef3e13; |
| 4356 | break; |
| 4357 | case 0x64: /* GPMC_CONFIG2 */ |
| 4358 | f->config[1] = value & 0x001f1f8f; |
| 4359 | break; |
| 4360 | case 0x68: /* GPMC_CONFIG3 */ |
| 4361 | f->config[2] = value & 0x001f1f8f; |
| 4362 | break; |
| 4363 | case 0x6c: /* GPMC_CONFIG4 */ |
| 4364 | f->config[3] = value & 0x1f8f1f8f; |
| 4365 | break; |
| 4366 | case 0x70: /* GPMC_CONFIG5 */ |
| 4367 | f->config[4] = value & 0x0f1f1f1f; |
| 4368 | break; |
| 4369 | case 0x74: /* GPMC_CONFIG6 */ |
| 4370 | f->config[5] = value & 0x00000fcf; |
| 4371 | break; |
| 4372 | case 0x78: /* GPMC_CONFIG7 */ |
| 4373 | if ((f->config[6] ^ value) & 0xf7f) { |
| 4374 | if (f->config[6] & (1 << 6)) /* CSVALID */ |
| 4375 | omap_gpmc_cs_unmap(f); |
| 4376 | if (value & (1 << 6)) /* CSVALID */ |
| 4377 | omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */ |
| 4378 | (value >> 8 & 0xf)); /* BASEADDR */ |
| 4379 | } |
| 4380 | f->config[6] = value & 0x00000f7f; |
| 4381 | break; |
| 4382 | case 0x7c: /* GPMC_NAND_COMMAND */ |
| 4383 | case 0x80: /* GPMC_NAND_ADDRESS */ |
| 4384 | case 0x84: /* GPMC_NAND_DATA */ |
| 4385 | break; |
| 4386 | |
| 4387 | default: |
| 4388 | goto bad_reg; |
| 4389 | } |
| 4390 | break; |
| 4391 | |
| 4392 | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ |
| 4393 | s->prefconfig[0] = value & 0x7f8f7fbf; |
| 4394 | /* TODO: update interrupts, fifos, dmas */ |
| 4395 | break; |
| 4396 | |
| 4397 | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ |
| 4398 | s->prefconfig[1] = value & 0x3fff; |
| 4399 | break; |
| 4400 | |
| 4401 | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ |
| 4402 | s->prefcontrol = value & 1; |
| 4403 | if (s->prefcontrol) { |
| 4404 | if (s->prefconfig[0] & 1) |
| 4405 | s->preffifo = 0x40; |
| 4406 | else |
| 4407 | s->preffifo = 0x00; |
| 4408 | } |
| 4409 | /* TODO: start */ |
| 4410 | break; |
| 4411 | |
| 4412 | case 0x1f4: /* GPMC_ECC_CONFIG */ |
| 4413 | s->ecc_cs = 0x8f; |
| 4414 | break; |
| 4415 | case 0x1f8: /* GPMC_ECC_CONTROL */ |
| 4416 | if (value & (1 << 8)) |
| 4417 | for (cs = 0; cs < 9; cs ++) |
| 4418 | ecc_reset(&s->ecc[cs]); |
| 4419 | s->ecc_ptr = value & 0xf; |
| 4420 | if (s->ecc_ptr == 0 || s->ecc_ptr > 9) { |
| 4421 | s->ecc_ptr = 0; |
| 4422 | s->ecc_cs &= ~1; |
| 4423 | } |
| 4424 | break; |
| 4425 | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ |
| 4426 | s->ecc_cfg = value & 0x3fcff1ff; |
| 4427 | break; |
| 4428 | case 0x230: /* GPMC_TESTMODE_CTRL */ |
| 4429 | if (value & 7) |
| 4430 | fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__); |
| 4431 | break; |
| 4432 | |
| 4433 | default: |
| 4434 | bad_reg: |
| 4435 | OMAP_BAD_REG(addr); |
| 4436 | return; |
| 4437 | } |
| 4438 | } |
| 4439 | |
| 4440 | static CPUReadMemoryFunc *omap_gpmc_readfn[] = { |
| 4441 | omap_badwidth_read32, /* TODO */ |
| 4442 | omap_badwidth_read32, /* TODO */ |
| 4443 | omap_gpmc_read, |
| 4444 | }; |
| 4445 | |
| 4446 | static CPUWriteMemoryFunc *omap_gpmc_writefn[] = { |
| 4447 | omap_badwidth_write32, /* TODO */ |
| 4448 | omap_badwidth_write32, /* TODO */ |
| 4449 | omap_gpmc_write, |
| 4450 | }; |
| 4451 | |
| 4452 | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) |
| 4453 | { |
| 4454 | int iomemtype; |
| 4455 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) |
| 4456 | qemu_mallocz(sizeof(struct omap_gpmc_s)); |
| 4457 | |
| 4458 | s->base = base; |
| 4459 | omap_gpmc_reset(s); |
| 4460 | |
| 4461 | iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn, |
| 4462 | omap_gpmc_writefn, s); |
| 4463 | cpu_register_physical_memory(s->base, 0x1000, iomemtype); |
| 4464 | |
| 4465 | return s; |
| 4466 | } |
| 4467 | |
| 4468 | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
| 4469 | void (*base_upd)(void *opaque, target_phys_addr_t new), |
| 4470 | void (*unmap)(void *opaque), void *opaque) |
| 4471 | { |
| 4472 | struct omap_gpmc_cs_file_s *f; |
| 4473 | |
| 4474 | if (cs < 0 || cs >= 8) { |
| 4475 | fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs); |
| 4476 | exit(-1); |
| 4477 | } |
| 4478 | f = &s->cs_file[cs]; |
| 4479 | |
| 4480 | f->iomemtype = iomemtype; |
| 4481 | f->base_update = base_upd; |
| 4482 | f->unmap = unmap; |
| 4483 | f->opaque = opaque; |
| 4484 | |
| 4485 | if (f->config[6] & (1 << 6)) /* CSVALID */ |
| 4486 | omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */ |
| 4487 | (f->config[6] >> 8 & 0xf)); /* BASEADDR */ |
| 4488 | } |
| 4489 | |
| 4490 | /* General chip reset */ |
| 4491 | static void omap2_mpu_reset(void *opaque) |
| 4492 | { |
| 4493 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
| 4494 | |
| 4495 | omap_inth_reset(mpu->ih[0]); |
| 4496 | omap_dma_reset(mpu->dma); |
| 4497 | omap_prcm_reset(mpu->prcm); |
| 4498 | omap_sysctl_reset(mpu->sysc); |
| 4499 | omap_gp_timer_reset(mpu->gptimer[0]); |
| 4500 | omap_gp_timer_reset(mpu->gptimer[1]); |
| 4501 | omap_gp_timer_reset(mpu->gptimer[2]); |
| 4502 | omap_gp_timer_reset(mpu->gptimer[3]); |
| 4503 | omap_gp_timer_reset(mpu->gptimer[4]); |
| 4504 | omap_gp_timer_reset(mpu->gptimer[5]); |
| 4505 | omap_gp_timer_reset(mpu->gptimer[6]); |
| 4506 | omap_gp_timer_reset(mpu->gptimer[7]); |
| 4507 | omap_gp_timer_reset(mpu->gptimer[8]); |
| 4508 | omap_gp_timer_reset(mpu->gptimer[9]); |
| 4509 | omap_gp_timer_reset(mpu->gptimer[10]); |
| 4510 | omap_gp_timer_reset(mpu->gptimer[11]); |
| 4511 | omap_synctimer_reset(&mpu->synctimer); |
| 4512 | omap_sdrc_reset(mpu->sdrc); |
| 4513 | omap_gpmc_reset(mpu->gpmc); |
| 4514 | omap_dss_reset(mpu->dss); |
| 4515 | omap_uart_reset(mpu->uart[0]); |
| 4516 | omap_uart_reset(mpu->uart[1]); |
| 4517 | omap_uart_reset(mpu->uart[2]); |
| 4518 | omap_mmc_reset(mpu->mmc); |
| 4519 | omap_gpif_reset(mpu->gpif); |
| 4520 | omap_mcspi_reset(mpu->mcspi[0]); |
| 4521 | omap_mcspi_reset(mpu->mcspi[1]); |
| 4522 | omap_i2c_reset(mpu->i2c[0]); |
| 4523 | omap_i2c_reset(mpu->i2c[1]); |
| 4524 | cpu_reset(mpu->env); |
| 4525 | } |
| 4526 | |
| 4527 | static int omap2_validate_addr(struct omap_mpu_state_s *s, |
| 4528 | target_phys_addr_t addr) |
| 4529 | { |
| 4530 | return 1; |
| 4531 | } |
| 4532 | |
| 4533 | static const struct dma_irq_map omap2_dma_irq_map[] = { |
| 4534 | { 0, OMAP_INT_24XX_SDMA_IRQ0 }, |
| 4535 | { 0, OMAP_INT_24XX_SDMA_IRQ1 }, |
| 4536 | { 0, OMAP_INT_24XX_SDMA_IRQ2 }, |
| 4537 | { 0, OMAP_INT_24XX_SDMA_IRQ3 }, |
| 4538 | }; |
| 4539 | |
| 4540 | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
| 4541 | DisplayState *ds, const char *core) |
| 4542 | { |
| 4543 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
| 4544 | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 4545 | ram_addr_t sram_base, q2_base; |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4546 | qemu_irq *cpu_irq; |
| 4547 | qemu_irq dma_irqs[4]; |
| 4548 | omap_clk gpio_clks[4]; |
| 4549 | int sdindex; |
| 4550 | int i; |
| 4551 | |
| 4552 | /* Core */ |
| 4553 | s->mpu_model = omap2420; |
| 4554 | s->env = cpu_init(core ?: "arm1136-r2"); |
| 4555 | if (!s->env) { |
| 4556 | fprintf(stderr, "Unable to find CPU definition\n"); |
| 4557 | exit(1); |
| 4558 | } |
| 4559 | s->sdram_size = sdram_size; |
| 4560 | s->sram_size = OMAP242X_SRAM_SIZE; |
| 4561 | |
| 4562 | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
| 4563 | |
| 4564 | /* Clocks */ |
| 4565 | omap_clk_init(s); |
| 4566 | |
| 4567 | /* Memory-mapped stuff */ |
| 4568 | cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size, |
balrog | 7e7c5e4 | 2008-04-14 21:57:44 +0000 | [diff] [blame] | 4569 | (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4570 | cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size, |
| 4571 | (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
| 4572 | |
| 4573 | s->l4 = omap_l4_init(OMAP2_L4_BASE, 54); |
| 4574 | |
| 4575 | /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ |
| 4576 | cpu_irq = arm_pic_init_cpu(s->env); |
| 4577 | s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0], |
| 4578 | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
| 4579 | omap_findclk(s, "mpu_intc_fclk"), |
| 4580 | omap_findclk(s, "mpu_intc_iclk")); |
| 4581 | |
| 4582 | s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3), |
| 4583 | s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s); |
| 4584 | |
| 4585 | s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1), |
| 4586 | omap_findclk(s, "omapctrl_iclk"), s); |
| 4587 | |
| 4588 | for (i = 0; i < 4; i ++) |
| 4589 | dma_irqs[i] = |
| 4590 | s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr]; |
| 4591 | s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32, |
| 4592 | omap_findclk(s, "sdma_iclk"), |
| 4593 | omap_findclk(s, "sdma_fclk")); |
| 4594 | s->port->addr_valid = omap2_validate_addr; |
| 4595 | |
balrog | afbb519 | 2008-07-21 20:40:22 +0000 | [diff] [blame] | 4596 | /* Register SDRAM and SRAM ports for fast DMA transfers. */ |
| 4597 | soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size); |
| 4598 | soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size); |
| 4599 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4600 | s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), |
| 4601 | s->irq[0][OMAP_INT_24XX_UART1_IRQ], |
| 4602 | omap_findclk(s, "uart1_fclk"), |
| 4603 | omap_findclk(s, "uart1_iclk"), |
| 4604 | s->drq[OMAP24XX_DMA_UART1_TX], |
| 4605 | s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]); |
| 4606 | s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), |
| 4607 | s->irq[0][OMAP_INT_24XX_UART2_IRQ], |
| 4608 | omap_findclk(s, "uart2_fclk"), |
| 4609 | omap_findclk(s, "uart2_iclk"), |
| 4610 | s->drq[OMAP24XX_DMA_UART2_TX], |
| 4611 | s->drq[OMAP24XX_DMA_UART2_RX], |
| 4612 | serial_hds[0] ? serial_hds[1] : 0); |
| 4613 | s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), |
| 4614 | s->irq[0][OMAP_INT_24XX_UART3_IRQ], |
| 4615 | omap_findclk(s, "uart3_fclk"), |
| 4616 | omap_findclk(s, "uart3_iclk"), |
| 4617 | s->drq[OMAP24XX_DMA_UART3_TX], |
| 4618 | s->drq[OMAP24XX_DMA_UART3_RX], |
| 4619 | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
| 4620 | |
| 4621 | s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), |
| 4622 | s->irq[0][OMAP_INT_24XX_GPTIMER1], |
| 4623 | omap_findclk(s, "wu_gpt1_clk"), |
| 4624 | omap_findclk(s, "wu_l4_iclk")); |
| 4625 | s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), |
| 4626 | s->irq[0][OMAP_INT_24XX_GPTIMER2], |
| 4627 | omap_findclk(s, "core_gpt2_clk"), |
| 4628 | omap_findclk(s, "core_l4_iclk")); |
| 4629 | s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), |
| 4630 | s->irq[0][OMAP_INT_24XX_GPTIMER3], |
| 4631 | omap_findclk(s, "core_gpt3_clk"), |
| 4632 | omap_findclk(s, "core_l4_iclk")); |
| 4633 | s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), |
| 4634 | s->irq[0][OMAP_INT_24XX_GPTIMER4], |
| 4635 | omap_findclk(s, "core_gpt4_clk"), |
| 4636 | omap_findclk(s, "core_l4_iclk")); |
| 4637 | s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), |
| 4638 | s->irq[0][OMAP_INT_24XX_GPTIMER5], |
| 4639 | omap_findclk(s, "core_gpt5_clk"), |
| 4640 | omap_findclk(s, "core_l4_iclk")); |
| 4641 | s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), |
| 4642 | s->irq[0][OMAP_INT_24XX_GPTIMER6], |
| 4643 | omap_findclk(s, "core_gpt6_clk"), |
| 4644 | omap_findclk(s, "core_l4_iclk")); |
| 4645 | s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), |
| 4646 | s->irq[0][OMAP_INT_24XX_GPTIMER7], |
| 4647 | omap_findclk(s, "core_gpt7_clk"), |
| 4648 | omap_findclk(s, "core_l4_iclk")); |
| 4649 | s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), |
| 4650 | s->irq[0][OMAP_INT_24XX_GPTIMER8], |
| 4651 | omap_findclk(s, "core_gpt8_clk"), |
| 4652 | omap_findclk(s, "core_l4_iclk")); |
| 4653 | s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), |
| 4654 | s->irq[0][OMAP_INT_24XX_GPTIMER9], |
| 4655 | omap_findclk(s, "core_gpt9_clk"), |
| 4656 | omap_findclk(s, "core_l4_iclk")); |
| 4657 | s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), |
| 4658 | s->irq[0][OMAP_INT_24XX_GPTIMER10], |
| 4659 | omap_findclk(s, "core_gpt10_clk"), |
| 4660 | omap_findclk(s, "core_l4_iclk")); |
| 4661 | s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), |
| 4662 | s->irq[0][OMAP_INT_24XX_GPTIMER11], |
| 4663 | omap_findclk(s, "core_gpt11_clk"), |
| 4664 | omap_findclk(s, "core_l4_iclk")); |
| 4665 | s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), |
| 4666 | s->irq[0][OMAP_INT_24XX_GPTIMER12], |
| 4667 | omap_findclk(s, "core_gpt12_clk"), |
| 4668 | omap_findclk(s, "core_l4_iclk")); |
| 4669 | |
| 4670 | omap_tap_init(omap_l4ta(s->l4, 2), s); |
| 4671 | |
| 4672 | omap_synctimer_init(omap_l4tao(s->l4, 2), s, |
| 4673 | omap_findclk(s, "clk32-kHz"), |
| 4674 | omap_findclk(s, "core_l4_iclk")); |
| 4675 | |
| 4676 | s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), |
| 4677 | s->irq[0][OMAP_INT_24XX_I2C1_IRQ], |
| 4678 | &s->drq[OMAP24XX_DMA_I2C1_TX], |
| 4679 | omap_findclk(s, "i2c1.fclk"), |
| 4680 | omap_findclk(s, "i2c1.iclk")); |
| 4681 | s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), |
| 4682 | s->irq[0][OMAP_INT_24XX_I2C2_IRQ], |
| 4683 | &s->drq[OMAP24XX_DMA_I2C2_TX], |
| 4684 | omap_findclk(s, "i2c2.fclk"), |
| 4685 | omap_findclk(s, "i2c2.iclk")); |
| 4686 | |
| 4687 | gpio_clks[0] = omap_findclk(s, "gpio1_dbclk"); |
| 4688 | gpio_clks[1] = omap_findclk(s, "gpio2_dbclk"); |
| 4689 | gpio_clks[2] = omap_findclk(s, "gpio3_dbclk"); |
| 4690 | gpio_clks[3] = omap_findclk(s, "gpio4_dbclk"); |
| 4691 | s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3), |
| 4692 | &s->irq[0][OMAP_INT_24XX_GPIO_BANK1], |
| 4693 | gpio_clks, omap_findclk(s, "gpio_iclk"), 4); |
| 4694 | |
| 4695 | s->sdrc = omap_sdrc_init(0x68009000); |
| 4696 | s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]); |
| 4697 | |
| 4698 | sdindex = drive_get_index(IF_SD, 0, 0); |
| 4699 | if (sdindex == -1) { |
| 4700 | fprintf(stderr, "qemu: missing SecureDigital device\n"); |
| 4701 | exit(1); |
| 4702 | } |
| 4703 | s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv, |
| 4704 | s->irq[0][OMAP_INT_24XX_MMC_IRQ], |
| 4705 | &s->drq[OMAP24XX_DMA_MMC1_TX], |
| 4706 | omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); |
| 4707 | |
| 4708 | s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 4709 | s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ], |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4710 | &s->drq[OMAP24XX_DMA_SPI1_TX0], |
| 4711 | omap_findclk(s, "spi1_fclk"), |
| 4712 | omap_findclk(s, "spi1_iclk")); |
| 4713 | s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 4714 | s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ], |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4715 | &s->drq[OMAP24XX_DMA_SPI2_TX0], |
| 4716 | omap_findclk(s, "spi2_fclk"), |
| 4717 | omap_findclk(s, "spi2_iclk")); |
| 4718 | |
| 4719 | s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds, |
| 4720 | /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */ |
| 4721 | s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS], |
| 4722 | omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), |
| 4723 | omap_findclk(s, "dss_54m_clk"), |
| 4724 | omap_findclk(s, "dss_l3_iclk"), |
| 4725 | omap_findclk(s, "dss_l4_iclk")); |
| 4726 | |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 4727 | omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, |
| 4728 | s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"), |
| 4729 | serial_hds[0] && serial_hds[1] && serial_hds[2] ? |
| 4730 | serial_hds[3] : 0); |
| 4731 | |
balrog | 99570a4 | 2008-07-18 07:50:20 +0000 | [diff] [blame] | 4732 | s->eac = omap_eac_init(omap_l4ta(s->l4, 32), |
| 4733 | s->irq[0][OMAP_INT_24XX_EAC_IRQ], |
| 4734 | /* Ten consecutive lines */ |
| 4735 | &s->drq[OMAP24XX_DMA_EAC_AC_RD], |
| 4736 | omap_findclk(s, "func_96m_clk"), |
| 4737 | omap_findclk(s, "core_l4_iclk")); |
| 4738 | |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4739 | /* All register mappings (includin those not currenlty implemented): |
| 4740 | * SystemControlMod 48000000 - 48000fff |
| 4741 | * SystemControlL4 48001000 - 48001fff |
| 4742 | * 32kHz Timer Mod 48004000 - 48004fff |
| 4743 | * 32kHz Timer L4 48005000 - 48005fff |
| 4744 | * PRCM ModA 48008000 - 480087ff |
| 4745 | * PRCM ModB 48008800 - 48008fff |
| 4746 | * PRCM L4 48009000 - 48009fff |
| 4747 | * TEST-BCM Mod 48012000 - 48012fff |
| 4748 | * TEST-BCM L4 48013000 - 48013fff |
| 4749 | * TEST-TAP Mod 48014000 - 48014fff |
| 4750 | * TEST-TAP L4 48015000 - 48015fff |
| 4751 | * GPIO1 Mod 48018000 - 48018fff |
| 4752 | * GPIO Top 48019000 - 48019fff |
| 4753 | * GPIO2 Mod 4801a000 - 4801afff |
| 4754 | * GPIO L4 4801b000 - 4801bfff |
| 4755 | * GPIO3 Mod 4801c000 - 4801cfff |
| 4756 | * GPIO4 Mod 4801e000 - 4801efff |
| 4757 | * WDTIMER1 Mod 48020000 - 48010fff |
| 4758 | * WDTIMER Top 48021000 - 48011fff |
| 4759 | * WDTIMER2 Mod 48022000 - 48012fff |
| 4760 | * WDTIMER L4 48023000 - 48013fff |
| 4761 | * WDTIMER3 Mod 48024000 - 48014fff |
| 4762 | * WDTIMER3 L4 48025000 - 48015fff |
| 4763 | * WDTIMER4 Mod 48026000 - 48016fff |
| 4764 | * WDTIMER4 L4 48027000 - 48017fff |
| 4765 | * GPTIMER1 Mod 48028000 - 48018fff |
| 4766 | * GPTIMER1 L4 48029000 - 48019fff |
| 4767 | * GPTIMER2 Mod 4802a000 - 4801afff |
| 4768 | * GPTIMER2 L4 4802b000 - 4801bfff |
| 4769 | * L4-Config AP 48040000 - 480407ff |
| 4770 | * L4-Config IP 48040800 - 48040fff |
| 4771 | * L4-Config LA 48041000 - 48041fff |
| 4772 | * ARM11ETB Mod 48048000 - 48049fff |
| 4773 | * ARM11ETB L4 4804a000 - 4804afff |
| 4774 | * DISPLAY Top 48050000 - 480503ff |
| 4775 | * DISPLAY DISPC 48050400 - 480507ff |
| 4776 | * DISPLAY RFBI 48050800 - 48050bff |
| 4777 | * DISPLAY VENC 48050c00 - 48050fff |
| 4778 | * DISPLAY L4 48051000 - 48051fff |
| 4779 | * CAMERA Top 48052000 - 480523ff |
| 4780 | * CAMERA core 48052400 - 480527ff |
| 4781 | * CAMERA DMA 48052800 - 48052bff |
| 4782 | * CAMERA MMU 48052c00 - 48052fff |
| 4783 | * CAMERA L4 48053000 - 48053fff |
| 4784 | * SDMA Mod 48056000 - 48056fff |
| 4785 | * SDMA L4 48057000 - 48057fff |
| 4786 | * SSI Top 48058000 - 48058fff |
| 4787 | * SSI GDD 48059000 - 48059fff |
| 4788 | * SSI Port1 4805a000 - 4805afff |
| 4789 | * SSI Port2 4805b000 - 4805bfff |
| 4790 | * SSI L4 4805c000 - 4805cfff |
| 4791 | * USB Mod 4805e000 - 480fefff |
| 4792 | * USB L4 4805f000 - 480fffff |
| 4793 | * WIN_TRACER1 Mod 48060000 - 48060fff |
| 4794 | * WIN_TRACER1 L4 48061000 - 48061fff |
| 4795 | * WIN_TRACER2 Mod 48062000 - 48062fff |
| 4796 | * WIN_TRACER2 L4 48063000 - 48063fff |
| 4797 | * WIN_TRACER3 Mod 48064000 - 48064fff |
| 4798 | * WIN_TRACER3 L4 48065000 - 48065fff |
| 4799 | * WIN_TRACER4 Top 48066000 - 480660ff |
| 4800 | * WIN_TRACER4 ETT 48066100 - 480661ff |
| 4801 | * WIN_TRACER4 WT 48066200 - 480662ff |
| 4802 | * WIN_TRACER4 L4 48067000 - 48067fff |
| 4803 | * XTI Mod 48068000 - 48068fff |
| 4804 | * XTI L4 48069000 - 48069fff |
| 4805 | * UART1 Mod 4806a000 - 4806afff |
| 4806 | * UART1 L4 4806b000 - 4806bfff |
| 4807 | * UART2 Mod 4806c000 - 4806cfff |
| 4808 | * UART2 L4 4806d000 - 4806dfff |
| 4809 | * UART3 Mod 4806e000 - 4806efff |
| 4810 | * UART3 L4 4806f000 - 4806ffff |
| 4811 | * I2C1 Mod 48070000 - 48070fff |
| 4812 | * I2C1 L4 48071000 - 48071fff |
| 4813 | * I2C2 Mod 48072000 - 48072fff |
| 4814 | * I2C2 L4 48073000 - 48073fff |
| 4815 | * McBSP1 Mod 48074000 - 48074fff |
| 4816 | * McBSP1 L4 48075000 - 48075fff |
| 4817 | * McBSP2 Mod 48076000 - 48076fff |
| 4818 | * McBSP2 L4 48077000 - 48077fff |
| 4819 | * GPTIMER3 Mod 48078000 - 48078fff |
| 4820 | * GPTIMER3 L4 48079000 - 48079fff |
| 4821 | * GPTIMER4 Mod 4807a000 - 4807afff |
| 4822 | * GPTIMER4 L4 4807b000 - 4807bfff |
| 4823 | * GPTIMER5 Mod 4807c000 - 4807cfff |
| 4824 | * GPTIMER5 L4 4807d000 - 4807dfff |
| 4825 | * GPTIMER6 Mod 4807e000 - 4807efff |
| 4826 | * GPTIMER6 L4 4807f000 - 4807ffff |
| 4827 | * GPTIMER7 Mod 48080000 - 48080fff |
| 4828 | * GPTIMER7 L4 48081000 - 48081fff |
| 4829 | * GPTIMER8 Mod 48082000 - 48082fff |
| 4830 | * GPTIMER8 L4 48083000 - 48083fff |
| 4831 | * GPTIMER9 Mod 48084000 - 48084fff |
| 4832 | * GPTIMER9 L4 48085000 - 48085fff |
| 4833 | * GPTIMER10 Mod 48086000 - 48086fff |
| 4834 | * GPTIMER10 L4 48087000 - 48087fff |
| 4835 | * GPTIMER11 Mod 48088000 - 48088fff |
| 4836 | * GPTIMER11 L4 48089000 - 48089fff |
| 4837 | * GPTIMER12 Mod 4808a000 - 4808afff |
| 4838 | * GPTIMER12 L4 4808b000 - 4808bfff |
| 4839 | * EAC Mod 48090000 - 48090fff |
| 4840 | * EAC L4 48091000 - 48091fff |
| 4841 | * FAC Mod 48092000 - 48092fff |
| 4842 | * FAC L4 48093000 - 48093fff |
| 4843 | * MAILBOX Mod 48094000 - 48094fff |
| 4844 | * MAILBOX L4 48095000 - 48095fff |
| 4845 | * SPI1 Mod 48098000 - 48098fff |
| 4846 | * SPI1 L4 48099000 - 48099fff |
| 4847 | * SPI2 Mod 4809a000 - 4809afff |
| 4848 | * SPI2 L4 4809b000 - 4809bfff |
| 4849 | * MMC/SDIO Mod 4809c000 - 4809cfff |
| 4850 | * MMC/SDIO L4 4809d000 - 4809dfff |
| 4851 | * MS_PRO Mod 4809e000 - 4809efff |
| 4852 | * MS_PRO L4 4809f000 - 4809ffff |
| 4853 | * RNG Mod 480a0000 - 480a0fff |
| 4854 | * RNG L4 480a1000 - 480a1fff |
| 4855 | * DES3DES Mod 480a2000 - 480a2fff |
| 4856 | * DES3DES L4 480a3000 - 480a3fff |
| 4857 | * SHA1MD5 Mod 480a4000 - 480a4fff |
| 4858 | * SHA1MD5 L4 480a5000 - 480a5fff |
| 4859 | * AES Mod 480a6000 - 480a6fff |
| 4860 | * AES L4 480a7000 - 480a7fff |
| 4861 | * PKA Mod 480a8000 - 480a9fff |
| 4862 | * PKA L4 480aa000 - 480aafff |
| 4863 | * MG Mod 480b0000 - 480b0fff |
| 4864 | * MG L4 480b1000 - 480b1fff |
| 4865 | * HDQ/1-wire Mod 480b2000 - 480b2fff |
| 4866 | * HDQ/1-wire L4 480b3000 - 480b3fff |
| 4867 | * MPU interrupt 480fe000 - 480fefff |
balrog | 54585ff | 2008-05-04 15:26:28 +0000 | [diff] [blame] | 4868 | * STI channel base 54000000 - 5400ffff |
balrog | 827df9f | 2008-04-14 21:05:22 +0000 | [diff] [blame] | 4869 | * IVA RAM 5c000000 - 5c01ffff |
| 4870 | * IVA ROM 5c020000 - 5c027fff |
| 4871 | * IMG_BUF_A 5c040000 - 5c040fff |
| 4872 | * IMG_BUF_B 5c042000 - 5c042fff |
| 4873 | * VLCDS 5c048000 - 5c0487ff |
| 4874 | * IMX_COEF 5c049000 - 5c04afff |
| 4875 | * IMX_CMD 5c051000 - 5c051fff |
| 4876 | * VLCDQ 5c053000 - 5c0533ff |
| 4877 | * VLCDH 5c054000 - 5c054fff |
| 4878 | * SEQ_CMD 5c055000 - 5c055fff |
| 4879 | * IMX_REG 5c056000 - 5c0560ff |
| 4880 | * VLCD_REG 5c056100 - 5c0561ff |
| 4881 | * SEQ_REG 5c056200 - 5c0562ff |
| 4882 | * IMG_BUF_REG 5c056300 - 5c0563ff |
| 4883 | * SEQIRQ_REG 5c056400 - 5c0564ff |
| 4884 | * OCP_REG 5c060000 - 5c060fff |
| 4885 | * SYSC_REG 5c070000 - 5c070fff |
| 4886 | * MMU_REG 5d000000 - 5d000fff |
| 4887 | * sDMA R 68000400 - 680005ff |
| 4888 | * sDMA W 68000600 - 680007ff |
| 4889 | * Display Control 68000800 - 680009ff |
| 4890 | * DSP subsystem 68000a00 - 68000bff |
| 4891 | * MPU subsystem 68000c00 - 68000dff |
| 4892 | * IVA subsystem 68001000 - 680011ff |
| 4893 | * USB 68001200 - 680013ff |
| 4894 | * Camera 68001400 - 680015ff |
| 4895 | * VLYNQ (firewall) 68001800 - 68001bff |
| 4896 | * VLYNQ 68001e00 - 68001fff |
| 4897 | * SSI 68002000 - 680021ff |
| 4898 | * L4 68002400 - 680025ff |
| 4899 | * DSP (firewall) 68002800 - 68002bff |
| 4900 | * DSP subsystem 68002e00 - 68002fff |
| 4901 | * IVA (firewall) 68003000 - 680033ff |
| 4902 | * IVA 68003600 - 680037ff |
| 4903 | * GFX 68003a00 - 68003bff |
| 4904 | * CMDWR emulation 68003c00 - 68003dff |
| 4905 | * SMS 68004000 - 680041ff |
| 4906 | * OCM 68004200 - 680043ff |
| 4907 | * GPMC 68004400 - 680045ff |
| 4908 | * RAM (firewall) 68005000 - 680053ff |
| 4909 | * RAM (err login) 68005400 - 680057ff |
| 4910 | * ROM (firewall) 68005800 - 68005bff |
| 4911 | * ROM (err login) 68005c00 - 68005fff |
| 4912 | * GPMC (firewall) 68006000 - 680063ff |
| 4913 | * GPMC (err login) 68006400 - 680067ff |
| 4914 | * SMS (err login) 68006c00 - 68006fff |
| 4915 | * SMS registers 68008000 - 68008fff |
| 4916 | * SDRC registers 68009000 - 68009fff |
| 4917 | * GPMC registers 6800a000 6800afff |
| 4918 | */ |
| 4919 | |
| 4920 | qemu_register_reset(omap2_mpu_reset, s); |
| 4921 | |
| 4922 | return s; |
| 4923 | } |