bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Sparc SLAVIO timer controller emulation |
| 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 24 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 25 | #include "sun4m.h" |
| 26 | #include "qemu-timer.h" |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 27 | #include "sysbus.h" |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 28 | #include "trace.h" |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 29 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 30 | /* |
| 31 | * Registers of hardware timer in sun4m. |
| 32 | * |
| 33 | * This is the timer/counter part of chip STP2001 (Slave I/O), also |
| 34 | * produced as NCR89C105. See |
| 35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 36 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 37 | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 |
| 38 | * are zero. Bit 31 is 1 when count has been reached. |
| 39 | * |
bellard | ba3c64f | 2005-12-05 20:31:52 +0000 | [diff] [blame] | 40 | * Per-CPU timers interrupt local CPU, system timer uses normal |
| 41 | * interrupt routing. |
| 42 | * |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 43 | */ |
| 44 | |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 45 | #define MAX_CPUS 16 |
| 46 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 47 | typedef struct CPUTimerState { |
blueswir1 | d7edfd2 | 2007-05-27 16:37:49 +0000 | [diff] [blame] | 48 | qemu_irq irq; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 49 | ptimer_state *timer; |
| 50 | uint32_t count, counthigh, reached; |
| 51 | uint64_t limit; |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 52 | // processor only |
blueswir1 | 2254876 | 2008-05-10 10:12:00 +0000 | [diff] [blame] | 53 | uint32_t running; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 54 | } CPUTimerState; |
| 55 | |
| 56 | typedef struct SLAVIO_TIMERState { |
| 57 | SysBusDevice busdev; |
| 58 | uint32_t num_cpus; |
| 59 | CPUTimerState cputimer[MAX_CPUS + 1]; |
| 60 | uint32_t cputimer_mode; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 61 | } SLAVIO_TIMERState; |
| 62 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 63 | typedef struct TimerContext { |
| 64 | SLAVIO_TIMERState *s; |
| 65 | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
| 66 | } TimerContext; |
| 67 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 68 | #define SYS_TIMER_SIZE 0x14 |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 69 | #define CPU_TIMER_SIZE 0x10 |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 70 | |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 71 | #define TIMER_LIMIT 0 |
| 72 | #define TIMER_COUNTER 1 |
| 73 | #define TIMER_COUNTER_NORST 2 |
| 74 | #define TIMER_STATUS 3 |
| 75 | #define TIMER_MODE 4 |
| 76 | |
| 77 | #define TIMER_COUNT_MASK32 0xfffffe00 |
| 78 | #define TIMER_LIMIT_MASK32 0x7fffffff |
| 79 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
| 80 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
| 81 | #define TIMER_REACHED 0x80000000 |
| 82 | #define TIMER_PERIOD 500ULL // 500ns |
Blue Swirl | 68fb89a | 2010-04-03 06:17:35 +0000 | [diff] [blame] | 83 | #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) |
| 84 | #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 85 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 86 | static int slavio_timer_is_user(TimerContext *tc) |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 87 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 88 | SLAVIO_TIMERState *s = tc->s; |
| 89 | unsigned int timer_index = tc->timer_index; |
| 90 | |
| 91 | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 92 | } |
| 93 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 94 | // Update count, set irq, update expire_time |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 95 | // Convert from ptimer countdown units |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 96 | static void slavio_timer_get_out(CPUTimerState *t) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 97 | { |
blueswir1 | bd7e287 | 2007-12-19 17:58:24 +0000 | [diff] [blame] | 98 | uint64_t count, limit; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 99 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 100 | if (t->limit == 0) { /* free-run system or processor counter */ |
blueswir1 | bd7e287 | 2007-12-19 17:58:24 +0000 | [diff] [blame] | 101 | limit = TIMER_MAX_COUNT32; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 102 | } else { |
| 103 | limit = t->limit; |
| 104 | } |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 105 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
| 106 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 107 | trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 108 | t->count = count & TIMER_COUNT_MASK32; |
| 109 | t->counthigh = count >> 32; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | // timer callback |
| 113 | static void slavio_timer_irq(void *opaque) |
| 114 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 115 | TimerContext *tc = opaque; |
| 116 | SLAVIO_TIMERState *s = tc->s; |
| 117 | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 118 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 119 | slavio_timer_get_out(t); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 120 | trace_slavio_timer_irq(t->counthigh, t->count); |
Blue Swirl | 68fb89a | 2010-04-03 06:17:35 +0000 | [diff] [blame] | 121 | /* if limit is 0 (free-run), there will be no match */ |
| 122 | if (t->limit != 0) { |
| 123 | t->reached = TIMER_REACHED; |
| 124 | } |
Blue Swirl | 452efba | 2010-01-24 14:28:21 +0000 | [diff] [blame] | 125 | /* there is no interrupt if user timer or free-run */ |
| 126 | if (!slavio_timer_is_user(tc) && t->limit != 0) { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 127 | qemu_irq_raise(t->irq); |
| 128 | } |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 129 | } |
| 130 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 131 | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 132 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 133 | TimerContext *tc = opaque; |
| 134 | SLAVIO_TIMERState *s = tc->s; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 135 | uint32_t saddr, ret; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 136 | unsigned int timer_index = tc->timer_index; |
| 137 | CPUTimerState *t = &s->cputimer[timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 138 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 139 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 140 | switch (saddr) { |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 141 | case TIMER_LIMIT: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 142 | // read limit (system counter mode) or read most signifying |
| 143 | // part of counter (user mode) |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 144 | if (slavio_timer_is_user(tc)) { |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 145 | // read user timer MSW |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 146 | slavio_timer_get_out(t); |
| 147 | ret = t->counthigh | t->reached; |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 148 | } else { |
| 149 | // read limit |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 150 | // clear irq |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 151 | qemu_irq_lower(t->irq); |
| 152 | t->reached = 0; |
| 153 | ret = t->limit & TIMER_LIMIT_MASK32; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 154 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 155 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 156 | case TIMER_COUNTER: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 157 | // read counter and reached bit (system mode) or read lsbits |
| 158 | // of counter (user mode) |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 159 | slavio_timer_get_out(t); |
| 160 | if (slavio_timer_is_user(tc)) { // read user timer LSW |
| 161 | ret = t->count & TIMER_MAX_COUNT64; |
| 162 | } else { // read limit |
| 163 | ret = (t->count & TIMER_MAX_COUNT32) | |
| 164 | t->reached; |
| 165 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 166 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 167 | case TIMER_STATUS: |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 168 | // only available in processor counter/timer |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 169 | // read start/stop status |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 170 | if (timer_index > 0) { |
| 171 | ret = t->running; |
| 172 | } else { |
| 173 | ret = 0; |
| 174 | } |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 175 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 176 | case TIMER_MODE: |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 177 | // only available in system counter |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 178 | // read user/system mode |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 179 | ret = s->cputimer_mode; |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 180 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 181 | default: |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 182 | trace_slavio_timer_mem_readl_invalid(addr); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 183 | ret = 0; |
| 184 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 185 | } |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 186 | trace_slavio_timer_mem_readl(addr, ret); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 187 | return ret; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 188 | } |
| 189 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 190 | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 191 | uint32_t val) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 192 | { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 193 | TimerContext *tc = opaque; |
| 194 | SLAVIO_TIMERState *s = tc->s; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 195 | uint32_t saddr; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 196 | unsigned int timer_index = tc->timer_index; |
| 197 | CPUTimerState *t = &s->cputimer[timer_index]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 198 | |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 199 | trace_slavio_timer_mem_writel(addr, val); |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 200 | saddr = addr >> 2; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 201 | switch (saddr) { |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 202 | case TIMER_LIMIT: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 203 | if (slavio_timer_is_user(tc)) { |
blueswir1 | e1cb950 | 2008-01-25 19:51:27 +0000 | [diff] [blame] | 204 | uint64_t count; |
| 205 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 206 | // set user counter MSW, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 207 | t->limit = TIMER_MAX_COUNT64; |
| 208 | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); |
| 209 | t->reached = 0; |
| 210 | count = ((uint64_t)t->counthigh << 32) | t->count; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 211 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 212 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 213 | } else { |
| 214 | // set limit, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 215 | qemu_irq_lower(t->irq); |
| 216 | t->limit = val & TIMER_MAX_COUNT32; |
| 217 | if (t->timer) { |
| 218 | if (t->limit == 0) { /* free-run */ |
| 219 | ptimer_set_limit(t->timer, |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 220 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 221 | } else { |
| 222 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); |
| 223 | } |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 224 | } |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 225 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 226 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 227 | case TIMER_COUNTER: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 228 | if (slavio_timer_is_user(tc)) { |
blueswir1 | e1cb950 | 2008-01-25 19:51:27 +0000 | [diff] [blame] | 229 | uint64_t count; |
| 230 | |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 231 | // set user counter LSW, reset counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 232 | t->limit = TIMER_MAX_COUNT64; |
| 233 | t->count = val & TIMER_MAX_COUNT64; |
| 234 | t->reached = 0; |
| 235 | count = ((uint64_t)t->counthigh) << 32 | t->count; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 236 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 237 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 238 | } else { |
| 239 | trace_slavio_timer_mem_writel_counter_invalid(); |
| 240 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 241 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 242 | case TIMER_COUNTER_NORST: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 243 | // set limit without resetting counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 244 | t->limit = val & TIMER_MAX_COUNT32; |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 245 | if (t->limit == 0) { /* free-run */ |
| 246 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); |
| 247 | } else { |
| 248 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 249 | } |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 250 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 251 | case TIMER_STATUS: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 252 | if (slavio_timer_is_user(tc)) { |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 253 | // start/stop user counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 254 | if ((val & 1) && !t->running) { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 255 | trace_slavio_timer_mem_writel_status_start(timer_index); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 256 | ptimer_run(t->timer, 0); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 257 | t->running = 1; |
| 258 | } else if (!(val & 1) && t->running) { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 259 | trace_slavio_timer_mem_writel_status_stop(timer_index); |
Blue Swirl | 9ebec28 | 2009-08-31 19:30:17 +0000 | [diff] [blame] | 260 | ptimer_stop(t->timer); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 261 | t->running = 0; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 262 | } |
| 263 | } |
| 264 | break; |
blueswir1 | d2c38b2 | 2007-12-01 15:58:22 +0000 | [diff] [blame] | 265 | case TIMER_MODE: |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 266 | if (timer_index == 0) { |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 267 | unsigned int i; |
| 268 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 269 | for (i = 0; i < s->num_cpus; i++) { |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 270 | unsigned int processor = 1 << i; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 271 | CPUTimerState *curr_timer = &s->cputimer[i + 1]; |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 272 | |
| 273 | // check for a change in timer mode for this processor |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 274 | if ((val & processor) != (s->cputimer_mode & processor)) { |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 275 | if (val & processor) { // counter -> user timer |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 276 | qemu_irq_lower(curr_timer->irq); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 277 | // counters are always running |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 278 | ptimer_stop(curr_timer->timer); |
| 279 | curr_timer->running = 0; |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 280 | // user timer limit is always the same |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 281 | curr_timer->limit = TIMER_MAX_COUNT64; |
| 282 | ptimer_set_limit(curr_timer->timer, |
| 283 | LIMIT_TO_PERIODS(curr_timer->limit), |
blueswir1 | 77f193d | 2008-05-12 16:13:33 +0000 | [diff] [blame] | 284 | 1); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 285 | // set this processors user timer bit in config |
| 286 | // register |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 287 | s->cputimer_mode |= processor; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 288 | trace_slavio_timer_mem_writel_mode_user(timer_index); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 289 | } else { // user timer -> counter |
| 290 | // stop the user timer if it is running |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 291 | if (curr_timer->running) { |
| 292 | ptimer_stop(curr_timer->timer); |
| 293 | } |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 294 | // start the counter |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 295 | ptimer_run(curr_timer->timer, 0); |
| 296 | curr_timer->running = 1; |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 297 | // clear this processors user timer bit in config |
| 298 | // register |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 299 | s->cputimer_mode &= ~processor; |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 300 | trace_slavio_timer_mem_writel_mode_counter(timer_index); |
blueswir1 | 67e4275 | 2008-01-26 09:13:46 +0000 | [diff] [blame] | 301 | } |
blueswir1 | 115646b | 2007-10-07 10:00:55 +0000 | [diff] [blame] | 302 | } |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 303 | } |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 304 | } else { |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 305 | trace_slavio_timer_mem_writel_mode_invalid(); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 306 | } |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 307 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 308 | default: |
Blue Swirl | 97bf485 | 2010-10-31 09:24:14 +0000 | [diff] [blame] | 309 | trace_slavio_timer_mem_writel_invalid(addr); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 310 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 311 | } |
| 312 | } |
| 313 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 314 | static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 315 | NULL, |
| 316 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 317 | slavio_timer_mem_readl, |
| 318 | }; |
| 319 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 320 | static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 321 | NULL, |
| 322 | NULL, |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 323 | slavio_timer_mem_writel, |
| 324 | }; |
| 325 | |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 326 | static const VMStateDescription vmstate_timer = { |
| 327 | .name ="timer", |
| 328 | .version_id = 3, |
| 329 | .minimum_version_id = 3, |
| 330 | .minimum_version_id_old = 3, |
| 331 | .fields = (VMStateField []) { |
| 332 | VMSTATE_UINT64(limit, CPUTimerState), |
| 333 | VMSTATE_UINT32(count, CPUTimerState), |
| 334 | VMSTATE_UINT32(counthigh, CPUTimerState), |
| 335 | VMSTATE_UINT32(reached, CPUTimerState), |
| 336 | VMSTATE_UINT32(running, CPUTimerState), |
| 337 | VMSTATE_PTIMER(timer, CPUTimerState), |
| 338 | VMSTATE_END_OF_LIST() |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 339 | } |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 340 | }; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 341 | |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 342 | static const VMStateDescription vmstate_slavio_timer = { |
| 343 | .name ="slavio_timer", |
| 344 | .version_id = 3, |
| 345 | .minimum_version_id = 3, |
| 346 | .minimum_version_id_old = 3, |
| 347 | .fields = (VMStateField []) { |
| 348 | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
| 349 | vmstate_timer, CPUTimerState), |
| 350 | VMSTATE_END_OF_LIST() |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 351 | } |
Blue Swirl | f4b19cd | 2009-08-31 19:30:18 +0000 | [diff] [blame] | 352 | }; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 353 | |
Blue Swirl | 0e0bfee | 2009-10-24 17:35:13 +0000 | [diff] [blame] | 354 | static void slavio_timer_reset(DeviceState *d) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 355 | { |
Blue Swirl | 0e0bfee | 2009-10-24 17:35:13 +0000 | [diff] [blame] | 356 | SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 357 | unsigned int i; |
| 358 | CPUTimerState *curr_timer; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 359 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 360 | for (i = 0; i <= MAX_CPUS; i++) { |
| 361 | curr_timer = &s->cputimer[i]; |
| 362 | curr_timer->limit = 0; |
| 363 | curr_timer->count = 0; |
| 364 | curr_timer->reached = 0; |
Artyom Tarasenko | 5933e8a | 2010-08-02 19:58:21 +0200 | [diff] [blame] | 365 | if (i <= s->num_cpus) { |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 366 | ptimer_set_limit(curr_timer->timer, |
| 367 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
| 368 | ptimer_run(curr_timer->timer, 0); |
Artyom Tarasenko | 5933e8a | 2010-08-02 19:58:21 +0200 | [diff] [blame] | 369 | curr_timer->running = 1; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 370 | } |
blueswir1 | 85e3023 | 2007-12-27 20:23:20 +0000 | [diff] [blame] | 371 | } |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 372 | s->cputimer_mode = 0; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 373 | } |
| 374 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 375 | static int slavio_timer_init1(SysBusDevice *dev) |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 376 | { |
| 377 | int io; |
| 378 | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); |
blueswir1 | 8d05ea8 | 2007-05-24 19:48:41 +0000 | [diff] [blame] | 379 | QEMUBH *bh; |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 380 | unsigned int i; |
| 381 | TimerContext *tc; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 382 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 383 | for (i = 0; i <= MAX_CPUS; i++) { |
| 384 | tc = qemu_mallocz(sizeof(TimerContext)); |
| 385 | tc->s = s; |
| 386 | tc->timer_index = i; |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 387 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 388 | bh = qemu_bh_new(slavio_timer_irq, tc); |
| 389 | s->cputimer[i].timer = ptimer_init(bh); |
| 390 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 391 | |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 392 | io = cpu_register_io_memory(slavio_timer_mem_read, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 393 | slavio_timer_mem_write, tc, |
| 394 | DEVICE_NATIVE_ENDIAN); |
Blue Swirl | 7204ff9 | 2009-08-08 20:08:15 +0000 | [diff] [blame] | 395 | if (i == 0) { |
| 396 | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); |
| 397 | } else { |
| 398 | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); |
| 399 | } |
| 400 | |
| 401 | sysbus_init_irq(dev, &s->cputimer[i].irq); |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 402 | } |
| 403 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 404 | return 0; |
blueswir1 | 81732d1 | 2007-10-06 11:25:43 +0000 | [diff] [blame] | 405 | } |
| 406 | |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 407 | static SysBusDeviceInfo slavio_timer_info = { |
| 408 | .init = slavio_timer_init1, |
| 409 | .qdev.name = "slavio_timer", |
| 410 | .qdev.size = sizeof(SLAVIO_TIMERState), |
Blue Swirl | 0e0bfee | 2009-10-24 17:35:13 +0000 | [diff] [blame] | 411 | .qdev.vmsd = &vmstate_slavio_timer, |
| 412 | .qdev.reset = slavio_timer_reset, |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 413 | .qdev.props = (Property[]) { |
Gerd Hoffmann | 18c637d | 2009-08-03 17:35:32 +0200 | [diff] [blame] | 414 | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
| 415 | DEFINE_PROP_END_OF_LIST(), |
Blue Swirl | c70c59e | 2009-07-15 08:53:09 +0000 | [diff] [blame] | 416 | } |
| 417 | }; |
| 418 | |
| 419 | static void slavio_timer_register_devices(void) |
| 420 | { |
| 421 | sysbus_register_withprop(&slavio_timer_info); |
| 422 | } |
| 423 | |
| 424 | device_init(slavio_timer_register_devices) |