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bellardc896fe22008-02-01 10:05:41 +00001Tiny Code Generator - Fabrice Bellard.
2
31) Introduction
4
5TCG (Tiny Code Generator) began as a generic backend for a C
6compiler. It was simplified to be used in QEMU. It also has its roots
7in the QOP code generator written by Paul Brook.
8
92) Definitions
10
11The TCG "target" is the architecture for which we generate the
12code. It is of course not the same as the "target" of QEMU which is
13the emulated architecture. As TCG started as a generic C backend used
14for cross compiling, it is assumed that the TCG target is different
15from the host, although it is never the case for QEMU.
16
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +080017In this document, we use "guest" to specify what architecture we are
18emulating; "target" always means the TCG target, the machine on which
19we are running QEMU.
20
bellardc896fe22008-02-01 10:05:41 +000021A TCG "function" corresponds to a QEMU Translated Block (TB).
22
bellard0a6b7b72008-05-25 18:24:40 +000023A TCG "temporary" is a variable only live in a basic
24block. Temporaries are allocated explicitly in each function.
bellardc896fe22008-02-01 10:05:41 +000025
bellard0a6b7b72008-05-25 18:24:40 +000026A TCG "local temporary" is a variable only live in a function. Local
27temporaries are allocated explicitly in each function.
28
29A TCG "global" is a variable which is live in all the functions
30(equivalent of a C global variable). They are defined before the
31functions defined. A TCG global can be a memory location (e.g. a QEMU
32CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
33or a memory location which is stored in a register outside QEMU TBs
34(not implemented yet).
bellardc896fe22008-02-01 10:05:41 +000035
36A TCG "basic block" corresponds to a list of instructions terminated
37by a branch instruction.
38
Richard Henderson20022fa2014-03-18 08:21:44 -070039An operation with "undefined behavior" may result in a crash.
40
41An operation with "unspecified behavior" shall not crash. However,
42the result may be one of several possibilities so may be considered
43an "undefined result".
44
bellardc896fe22008-02-01 10:05:41 +0000453) Intermediate representation
46
473.1) Introduction
48
bellard0a6b7b72008-05-25 18:24:40 +000049TCG instructions operate on variables which are temporaries, local
50temporaries or globals. TCG instructions and variables are strongly
51typed. Two types are supported: 32 bit integers and 64 bit
52integers. Pointers are defined as an alias to 32 bit or 64 bit
53integers depending on the TCG target word size.
bellardc896fe22008-02-01 10:05:41 +000054
55Each instruction has a fixed number of output variable operands, input
56variable operands and always constant operands.
57
58The notable exception is the call instruction which has a variable
59number of outputs and inputs.
60
bellard0a6b7b72008-05-25 18:24:40 +000061In the textual form, output operands usually come first, followed by
62input operands, followed by constant operands. The output type is
63included in the instruction name. Constants are prefixed with a '$'.
bellardc896fe22008-02-01 10:05:41 +000064
65add_i32 t0, t1, t2 (t0 <- t1 + t2)
66
bellardc896fe22008-02-01 10:05:41 +0000673.2) Assumptions
68
69* Basic blocks
70
71- Basic blocks end after branches (e.g. brcond_i32 instruction),
72 goto_tb and exit_tb instructions.
aurel3286e840e2008-12-07 15:21:23 +000073- Basic blocks start after the end of a previous basic block, or at a
74 set_label instruction.
bellardc896fe22008-02-01 10:05:41 +000075
bellard0a6b7b72008-05-25 18:24:40 +000076After the end of a basic block, the content of temporaries is
77destroyed, but local temporaries and globals are preserved.
bellardc896fe22008-02-01 10:05:41 +000078
79* Floating point types are not supported yet
80
81* Pointers: depending on the TCG target, pointer size is 32 bit or 64
82 bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
83 TCG_TYPE_I64.
84
85* Helpers:
86
87Using the tcg_gen_helper_x_y it is possible to call any function
Stefan Weilaa95e3a2011-01-07 21:34:50 +010088taking i32, i64 or pointer types. By default, before calling a helper,
Aurelien Jarnoa3f50542010-03-05 22:48:03 +010089all globals are stored at their canonical location and it is assumed
Aurelien Jarno78505272012-10-09 21:53:08 +020090that the function can modify them. By default, the helper is allowed to
91modify the CPU state or raise an exception.
92
93This can be overridden using the following function modifiers:
94- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
95 either directly or via an exception. They will not be saved to their
96 canonical locations before calling the helper.
97- TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
98 They will only be saved to their canonical location before calling helpers,
99 but they won't be reloaded afterwise.
100- TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
101 the return value is not used.
102
103Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS.
bellardc896fe22008-02-01 10:05:41 +0000104
105On some TCG targets (e.g. x86), several calling conventions are
106supported.
107
108* Branches:
109
Aurelien Jarno626cd052012-10-01 21:00:43 +0200110Use the instruction 'br' to jump to a label.
bellardc896fe22008-02-01 10:05:41 +0000111
1123.3) Code Optimizations
113
114When generating instructions, you can count on at least the following
115optimizations:
116
117- Single instructions are simplified, e.g.
118
119 and_i32 t0, t0, $0xffffffff
120
121 is suppressed.
122
123- A liveness analysis is done at the basic block level. The
bellard0a6b7b72008-05-25 18:24:40 +0000124 information is used to suppress moves from a dead variable to
bellardc896fe22008-02-01 10:05:41 +0000125 another one. It is also used to remove instructions which compute
126 dead results. The later is especially useful for condition code
bellard9804c8e2008-02-01 13:01:47 +0000127 optimization in QEMU.
bellardc896fe22008-02-01 10:05:41 +0000128
129 In the following example:
130
131 add_i32 t0, t1, t2
132 add_i32 t0, t0, $1
133 mov_i32 t0, $1
134
135 only the last instruction is kept.
136
bellardc896fe22008-02-01 10:05:41 +00001373.4) Instruction Reference
138
139********* Function call
140
141* call <ret> <params> ptr
142
143call function 'ptr' (pointer type)
144
145<ret> optional 32 bit or 64 bit return value
146<params> optional 32 bit or 64 bit parameters
147
148********* Jumps/Labels
149
bellardc896fe22008-02-01 10:05:41 +0000150* set_label $label
151
152Define label 'label' at the current program point.
153
154* br $label
155
156Jump to label.
157
Richard Henderson5a696f62012-09-21 17:18:09 -0700158* brcond_i32/i64 t0, t1, cond, label
bellardc896fe22008-02-01 10:05:41 +0000159
160Conditional jump if t0 cond t1 is true. cond can be:
161 TCG_COND_EQ
162 TCG_COND_NE
163 TCG_COND_LT /* signed */
164 TCG_COND_GE /* signed */
165 TCG_COND_LE /* signed */
166 TCG_COND_GT /* signed */
167 TCG_COND_LTU /* unsigned */
168 TCG_COND_GEU /* unsigned */
169 TCG_COND_LEU /* unsigned */
170 TCG_COND_GTU /* unsigned */
171
172********* Arithmetic
173
174* add_i32/i64 t0, t1, t2
175
176t0=t1+t2
177
178* sub_i32/i64 t0, t1, t2
179
180t0=t1-t2
181
pbrook390efc52008-05-11 14:35:37 +0000182* neg_i32/i64 t0, t1
183
184t0=-t1 (two's complement)
185
bellardc896fe22008-02-01 10:05:41 +0000186* mul_i32/i64 t0, t1, t2
187
188t0=t1*t2
189
190* div_i32/i64 t0, t1, t2
191
192t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
193
194* divu_i32/i64 t0, t1, t2
195
196t0=t1/t2 (unsigned). Undefined behavior if division by zero.
197
198* rem_i32/i64 t0, t1, t2
199
200t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
201
202* remu_i32/i64 t0, t1, t2
203
204t0=t1%t2 (unsigned). Undefined behavior if division by zero.
205
bellardc896fe22008-02-01 10:05:41 +0000206********* Logical
207
aurel325e854042008-03-12 21:40:02 +0000208* and_i32/i64 t0, t1, t2
209
bellardc896fe22008-02-01 10:05:41 +0000210t0=t1&t2
211
212* or_i32/i64 t0, t1, t2
213
214t0=t1|t2
215
216* xor_i32/i64 t0, t1, t2
217
218t0=t1^t2
219
bellard0a6b7b72008-05-25 18:24:40 +0000220* not_i32/i64 t0, t1
221
222t0=~t1
223
aurel32f24cb332008-10-21 11:28:59 +0000224* andc_i32/i64 t0, t1, t2
225
226t0=t1&~t2
227
228* eqv_i32/i64 t0, t1, t2
229
Richard Henderson8d625cf2010-03-19 13:02:02 -0700230t0=~(t1^t2), or equivalently, t0=t1^~t2
aurel32f24cb332008-10-21 11:28:59 +0000231
232* nand_i32/i64 t0, t1, t2
233
234t0=~(t1&t2)
235
236* nor_i32/i64 t0, t1, t2
237
238t0=~(t1|t2)
239
240* orc_i32/i64 t0, t1, t2
241
242t0=t1|~t2
243
aurel3215824572008-11-03 07:08:36 +0000244********* Shifts/Rotates
bellardc896fe22008-02-01 10:05:41 +0000245
246* shl_i32/i64 t0, t1, t2
247
Richard Henderson20022fa2014-03-18 08:21:44 -0700248t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000249
250* shr_i32/i64 t0, t1, t2
251
Richard Henderson20022fa2014-03-18 08:21:44 -0700252t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000253
254* sar_i32/i64 t0, t1, t2
255
Richard Henderson20022fa2014-03-18 08:21:44 -0700256t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
bellardc896fe22008-02-01 10:05:41 +0000257
aurel3215824572008-11-03 07:08:36 +0000258* rotl_i32/i64 t0, t1, t2
259
Richard Henderson20022fa2014-03-18 08:21:44 -0700260Rotation of t2 bits to the left.
261Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
aurel3215824572008-11-03 07:08:36 +0000262
263* rotr_i32/i64 t0, t1, t2
264
Richard Henderson20022fa2014-03-18 08:21:44 -0700265Rotation of t2 bits to the right.
266Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
aurel3215824572008-11-03 07:08:36 +0000267
bellardc896fe22008-02-01 10:05:41 +0000268********* Misc
269
270* mov_i32/i64 t0, t1
271
272t0 = t1
273
274Move t1 to t0 (both operands must have the same type).
275
276* ext8s_i32/i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000277ext8u_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000278ext16s_i32/i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000279ext16u_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000280ext32s_i64 t0, t1
pbrook86831432008-05-11 12:22:01 +0000281ext32u_i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000282
pbrook86831432008-05-11 12:22:01 +00002838, 16 or 32 bit sign/zero extension (both operands must have the same type)
bellardc896fe22008-02-01 10:05:41 +0000284
aurel324ad4ce12009-03-13 09:35:26 +0000285* bswap16_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000286
Aurelien Jarno837d9872010-04-10 03:36:21 +020028716 bit byte swap on a 32/64 bit value. It assumes that the two/six high order
288bytes are set to zero.
bellardc896fe22008-02-01 10:05:41 +0000289
aurel324ad4ce12009-03-13 09:35:26 +0000290* bswap32_i32/i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000291
Aurelien Jarno837d9872010-04-10 03:36:21 +020029232 bit byte swap on a 32/64 bit value. With a 64 bit value, it assumes that
293the four high order bytes are set to zero.
bellardc896fe22008-02-01 10:05:41 +0000294
aurel324ad4ce12009-03-13 09:35:26 +0000295* bswap64_i64 t0, t1
bellardc896fe22008-02-01 10:05:41 +0000296
29764 bit byte swap
298
bellard5ff9d6a2008-02-04 00:37:54 +0000299* discard_i32/i64 t0
300
301Indicate that the value of t0 won't be used later. It is useful to
302force dead code elimination.
303
Edgar E. Iglesias3a34dfd2011-01-20 12:16:57 +0100304* deposit_i32/i64 dest, t1, t2, pos, len
Richard Hendersonb7767f02011-01-10 19:23:42 -0800305
306Deposit T2 as a bitfield into T1, placing the result in DEST.
Edgar E. Iglesias3a34dfd2011-01-20 12:16:57 +0100307The bitfield is described by POS/LEN, which are immediate values:
Richard Hendersonb7767f02011-01-10 19:23:42 -0800308
309 LEN - the length of the bitfield
310 POS - the position of the first bit, counting from the LSB
311
312For example, pos=8, len=4 indicates a 4-bit field at bit 8.
313This operation would be equivalent to
314
315 dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
316
Richard Henderson4bb7a412013-09-09 17:03:24 -0700317* trunc_shr_i32 t0, t1, pos
318
319For 64-bit hosts only, right shift the 64-bit input T1 by POS and
320truncate to 32-bit output T0. Depending on the host, this may be
321a simple mov/shift, or may require additional canonicalization.
Richard Hendersonb7767f02011-01-10 19:23:42 -0800322
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800323********* Conditional moves
324
Richard Henderson5a696f62012-09-21 17:18:09 -0700325* setcond_i32/i64 dest, t1, t2, cond
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800326
327dest = (t1 cond t2)
328
329Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
330
Richard Henderson5a696f62012-09-21 17:18:09 -0700331* movcond_i32/i64 dest, c1, c2, v1, v2, cond
Richard Hendersonffc5ea02012-09-21 10:13:34 -0700332
333dest = (c1 cond c2 ? v1 : v2)
334
335Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2.
336
bellardc896fe22008-02-01 10:05:41 +0000337********* Type conversions
338
339* ext_i32_i64 t0, t1
340Convert t1 (32 bit) to t0 (64 bit) and does sign extension
341
342* extu_i32_i64 t0, t1
343Convert t1 (32 bit) to t0 (64 bit) and does zero extension
344
345* trunc_i64_i32 t0, t1
346Truncate t1 (64 bit) to t0 (32 bit)
347
pbrook36aa55d2008-09-21 13:48:32 +0000348* concat_i32_i64 t0, t1, t2
349Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
350from t2 (32 bit).
351
blueswir1945ca822008-09-21 18:32:28 +0000352* concat32_i64 t0, t1, t2
353Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
354from t2 (64 bit).
355
bellardc896fe22008-02-01 10:05:41 +0000356********* Load/Store
357
358* ld_i32/i64 t0, t1, offset
359ld8s_i32/i64 t0, t1, offset
360ld8u_i32/i64 t0, t1, offset
361ld16s_i32/i64 t0, t1, offset
362ld16u_i32/i64 t0, t1, offset
363ld32s_i64 t0, t1, offset
364ld32u_i64 t0, t1, offset
365
366t0 = read(t1 + offset)
367Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
368offset must be a constant.
369
370* st_i32/i64 t0, t1, offset
371st8_i32/i64 t0, t1, offset
372st16_i32/i64 t0, t1, offset
373st32_i64 t0, t1, offset
374
375write(t0, t1 + offset)
376Write 8, 16, 32 or 64 bits to host memory.
377
Aurelien Jarnob202d412012-10-09 21:53:08 +0200378All this opcodes assume that the pointed host memory doesn't correspond
379to a global. In the latter case the behaviour is unpredictable.
380
Richard Hendersond7156f72013-02-19 23:51:52 -0800381********* Multiword arithmetic support
382
383* add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
384* sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
385
386Similar to add/sub, except that the double-word inputs T1 and T2 are
387formed from two single-word arguments, and the double-word output T0
388is returned in two single-word outputs.
389
390* mulu2_i32/i64 t0_low, t0_high, t1, t2
391
392Similar to mul, except two unsigned inputs T1 and T2 yielding the full
393double-word product T0. The later is returned in two single-word outputs.
394
Richard Henderson4d3203f2013-02-19 23:51:53 -0800395* muls2_i32/i64 t0_low, t0_high, t1, t2
396
397Similar to mulu2, except the two inputs T1 and T2 are signed.
398
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800399********* 64-bit guest on 32-bit host support
Richard Hendersona38e6092010-01-07 10:07:35 -0800400
401The following opcodes are internal to TCG. Thus they are to be implemented by
40232-bit host code generators, but are not to be emitted by guest translators.
403They are emitted as needed by inline functions within "tcg-op.h".
404
Richard Henderson5a696f62012-09-21 17:18:09 -0700405* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
Richard Hendersona38e6092010-01-07 10:07:35 -0800406
407Similar to brcond, except that the 64-bit values T0 and T1
408are formed from two 32-bit arguments.
409
Richard Henderson5a696f62012-09-21 17:18:09 -0700410* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800411
412Similar to setcond, except that the 64-bit values T1 and T2 are
413formed from two 32-bit arguments. The result is a 32-bit value.
414
bellardc896fe22008-02-01 10:05:41 +0000415********* QEMU specific operations
416
Mike Frysinger759c90b2011-01-09 03:45:45 -0500417* exit_tb t0
bellardc896fe22008-02-01 10:05:41 +0000418
419Exit the current TB and return the value t0 (word type).
420
421* goto_tb index
422
423Exit the current TB and jump to the TB index 'index' (constant) if the
424current TB was linked to this TB. Otherwise execute the next
Max Filippov9bacf412012-09-21 04:18:07 +0400425instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
426at most once with each slot index per TB.
bellardc896fe22008-02-01 10:05:41 +0000427
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700428* qemu_ld_i32/i64 t0, t1, flags, memidx
429* qemu_st_i32/i64 t0, t1, flags, memidx
bellardc896fe22008-02-01 10:05:41 +0000430
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700431Load data at the guest address t1 into t0, or store data in t0 at guest
432address t1. The _i32/_i64 size applies to the size of the input/output
433register t0 only. The address t1 is always sized according to the guest,
434and the width of the memory operation is controlled by flags.
Richard Henderson86feb1c2010-03-19 12:00:26 -0700435
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700436Both t0 and t1 may be split into little-endian ordered pairs of registers
437if dealing with 64-bit quantities on a 32-bit host.
bellardc896fe22008-02-01 10:05:41 +0000438
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700439The memidx selects the qemu tlb index to use (e.g. user or kernel access).
440The flags are the TCGMemOp bits, selecting the sign, width, and endianness
441of the memory access.
bellardc896fe22008-02-01 10:05:41 +0000442
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700443For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
44464-bit memory access specified in flags.
445
446*********
bellardc896fe22008-02-01 10:05:41 +0000447
448Note 1: Some shortcuts are defined when the last operand is known to be
449a constant (e.g. addi for add, movi for mov).
450
451Note 2: When using TCG, the opcodes must never be generated directly
452as some of them may not be available as "real" opcodes. Always use the
453function tcg_gen_xxx(args).
454
4554) Backend
456
457tcg-target.h contains the target specific definitions. tcg-target.c
458contains the target specific code.
459
4604.1) Assumptions
461
462The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
46364 bit. It is expected that the pointer has the same size as the word.
464
465On a 32 bit target, all 64 bit operations are converted to 32 bits. A
466few specific operations must be implemented to allow it (see add2_i32,
467sub2_i32, brcond2_i32).
468
469Floating point operations are not supported in this version. A
470previous incarnation of the code generator had full support of them,
471but it is better to concentrate on integer operations first.
472
473On a 64 bit target, no assumption is made in TCG about the storage of
474the 32 bit values in 64 bit registers.
475
4764.2) Constraints
477
478GCC like constraints are used to define the constraints of every
479instruction. Memory constraints are not supported in this
480version. Aliases are specified in the input operands as for GCC.
481
pbrook0c5f3c82008-11-04 13:17:17 +0000482The same register may be used for both an input and an output, even when
483they are not explicitly aliased. If an op expands to multiple target
484instructions then care must be taken to avoid clobbering input values.
485GCC style "early clobber" outputs are not currently supported.
486
bellardc896fe22008-02-01 10:05:41 +0000487A target can define specific register or constant constraints. If an
488operation uses a constant input constraint which does not allow all
489constants, it must also accept registers in order to have a fallback.
490
491The movi_i32 and movi_i64 operations must accept any constants.
492
493The mov_i32 and mov_i64 operations must accept any registers of the
494same type.
495
496The ld/st instructions must accept signed 32 bit constant offsets. It
497can be implemented by reserving a specific register to compute the
498address if the offset is too big.
499
500The ld/st instructions must accept any destination (ld) or source (st)
501register.
502
5034.3) Function call assumptions
504
505- The only supported types for parameters and return value are: 32 and
506 64 bit integers and pointer.
507- The stack grows downwards.
508- The first N parameters are passed in registers.
509- The next parameters are passed on the stack by storing them as words.
510- Some registers are clobbered during the call.
511- The function can return 0 or 1 value in registers. On a 32 bit
512 target, functions must be able to return 2 values in registers for
513 64 bit return type.
514
aurel3286e840e2008-12-07 15:21:23 +00005155) Recommended coding rules for best performance
bellard0a6b7b72008-05-25 18:24:40 +0000516
517- Use globals to represent the parts of the QEMU CPU state which are
518 often modified, e.g. the integer registers and the condition
519 codes. TCG will be able to use host registers to store them.
520
521- Avoid globals stored in fixed registers. They must be used only to
522 store the pointer to the CPU state and possibly to store a pointer
aurel3286e840e2008-12-07 15:21:23 +0000523 to a register window.
bellard0a6b7b72008-05-25 18:24:40 +0000524
525- Use temporaries. Use local temporaries only when really needed,
526 e.g. when you need to use a value after a jump. Local temporaries
527 introduce a performance hit in the current TCG implementation: their
528 content is saved to memory at end of each basic block.
529
530- Free temporaries and local temporaries when they are no longer used
531 (tcg_temp_free). Since tcg_const_x() also creates a temporary, you
532 should free it after it is used. Freeing temporaries does not yield
533 a better generated code, but it reduces the memory usage of TCG and
534 the speed of the translation.
535
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800536- Don't hesitate to use helpers for complicated or seldom used guest
Stefan Weilaa95e3a2011-01-07 21:34:50 +0100537 instructions. There is little performance advantage in using TCG to
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800538 implement guest instructions taking more than about twenty TCG
Peter Maydell107a47c2011-06-22 15:40:06 +0100539 instructions. Note that this rule of thumb is more applicable to
540 helpers doing complex logic or arithmetic, where the C compiler has
541 scope to do a good job of optimisation; it is less relevant where
542 the instruction is mostly doing loads and stores, and in those cases
543 inline TCG may still be faster for longer sequences.
544
545- The hard limit on the number of TCG instructions you can generate
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800546 per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
Peter Maydell107a47c2011-06-22 15:40:06 +0100547 you cannot exceed this without risking a buffer overrun.
bellard0a6b7b72008-05-25 18:24:40 +0000548
549- Use the 'discard' instruction if you know that TCG won't be able to
550 prove that a given global is "dead" at a given program point. The
陳韋任 (Wei-Ren Chen)294e4662013-03-20 11:42:08 +0800551 x86 guest uses it to improve the condition codes optimisation.