bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU Parallel PORT emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | e57a8c0 | 2005-11-10 23:58:52 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 5 | * Copyright (c) 2007 Marko Kohtala |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6 | * |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
Peter Maydell | b6a0aa0 | 2016-01-26 18:17:03 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Markus Armbruster | da34e65 | 2016-03-14 09:01:28 +0100 | [diff] [blame] | 26 | #include "qapi/error.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 27 | #include "hw/hw.h" |
Marc-André Lureau | 7566c6e | 2017-01-26 17:33:39 +0400 | [diff] [blame] | 28 | #include "chardev/char-parallel.h" |
Marc-André Lureau | 4d43a60 | 2017-01-26 18:26:44 +0400 | [diff] [blame] | 29 | #include "chardev/char-fe.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 30 | #include "hw/isa/isa.h" |
Philippe Mathieu-Daudé | bb3d5ea | 2018-03-08 23:39:22 +0100 | [diff] [blame] | 31 | #include "hw/char/parallel.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 32 | #include "sysemu/sysemu.h" |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 33 | |
| 34 | //#define DEBUG_PARALLEL |
| 35 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 36 | #ifdef DEBUG_PARALLEL |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 37 | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 38 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 39 | #define pdebug(fmt, ...) ((void)0) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 40 | #endif |
| 41 | |
| 42 | #define PARA_REG_DATA 0 |
| 43 | #define PARA_REG_STS 1 |
| 44 | #define PARA_REG_CTR 2 |
| 45 | #define PARA_REG_EPP_ADDR 3 |
| 46 | #define PARA_REG_EPP_DATA 4 |
| 47 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 48 | /* |
| 49 | * These are the definitions for the Printer Status Register |
| 50 | */ |
| 51 | #define PARA_STS_BUSY 0x80 /* Busy complement */ |
| 52 | #define PARA_STS_ACK 0x40 /* Acknowledge */ |
| 53 | #define PARA_STS_PAPER 0x20 /* Out of paper */ |
| 54 | #define PARA_STS_ONLINE 0x10 /* Online */ |
| 55 | #define PARA_STS_ERROR 0x08 /* Error complement */ |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 56 | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * These are the definitions for the Printer Control Register |
| 60 | */ |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 61 | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 62 | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
| 63 | #define PARA_CTR_SELECT 0x08 /* Select In complement */ |
| 64 | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
| 65 | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
| 66 | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
| 67 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 68 | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) |
| 69 | |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 70 | typedef struct ParallelState { |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 71 | MemoryRegion iomem; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 72 | uint8_t dataw; |
| 73 | uint8_t datar; |
| 74 | uint8_t status; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 75 | uint8_t control; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 76 | qemu_irq irq; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 77 | int irq_pending; |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 78 | CharBackend chr; |
bellard | e57a8c0 | 2005-11-10 23:58:52 +0000 | [diff] [blame] | 79 | int hw_driver; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 80 | int epp_timeout; |
| 81 | uint32_t last_read_offset; /* For debugging */ |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 82 | /* Memory-mapped interface */ |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 83 | int it_shift; |
Marc-André Lureau | e305a16 | 2016-07-13 02:11:59 +0200 | [diff] [blame] | 84 | PortioList portio_list; |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 85 | } ParallelState; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 86 | |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 87 | #define TYPE_ISA_PARALLEL "isa-parallel" |
| 88 | #define ISA_PARALLEL(obj) \ |
| 89 | OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) |
| 90 | |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 91 | typedef struct ISAParallelState { |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 92 | ISADevice parent_obj; |
| 93 | |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 94 | uint32_t index; |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 95 | uint32_t iobase; |
| 96 | uint32_t isairq; |
| 97 | ParallelState state; |
| 98 | } ISAParallelState; |
| 99 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 100 | static void parallel_update_irq(ParallelState *s) |
| 101 | { |
| 102 | if (s->irq_pending) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 103 | qemu_irq_raise(s->irq); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 104 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 105 | qemu_irq_lower(s->irq); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 106 | } |
| 107 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 108 | static void |
| 109 | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 110 | { |
| 111 | ParallelState *s = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 112 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 113 | pdebug("write addr=0x%02x val=0x%02x\n", addr, val); |
| 114 | |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 115 | addr &= 7; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 116 | switch(addr) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 117 | case PARA_REG_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 118 | s->dataw = val; |
| 119 | parallel_update_irq(s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 120 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 121 | case PARA_REG_CTR: |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 122 | val |= 0xc0; |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 123 | if ((val & PARA_CTR_INIT) == 0 ) { |
| 124 | s->status = PARA_STS_BUSY; |
| 125 | s->status |= PARA_STS_ACK; |
| 126 | s->status |= PARA_STS_ONLINE; |
| 127 | s->status |= PARA_STS_ERROR; |
| 128 | } |
| 129 | else if (val & PARA_CTR_SELECT) { |
| 130 | if (val & PARA_CTR_STROBE) { |
| 131 | s->status &= ~PARA_STS_BUSY; |
| 132 | if ((s->control & PARA_CTR_STROBE) == 0) |
Daniel P. Berrange | 6ab3fc3 | 2016-09-06 14:56:04 +0100 | [diff] [blame] | 133 | /* XXX this blocks entire thread. Rewrite to use |
| 134 | * qemu_chr_fe_write and background I/O callbacks */ |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 135 | qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 136 | } else { |
| 137 | if (s->control & PARA_CTR_INTEN) { |
| 138 | s->irq_pending = 1; |
| 139 | } |
| 140 | } |
| 141 | } |
| 142 | parallel_update_irq(s); |
| 143 | s->control = val; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 144 | break; |
| 145 | } |
| 146 | } |
| 147 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 148 | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
| 149 | { |
| 150 | ParallelState *s = opaque; |
| 151 | uint8_t parm = val; |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 152 | int dir; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 153 | |
| 154 | /* Sometimes programs do several writes for timing purposes on old |
| 155 | HW. Take care not to waste time on writes that do nothing. */ |
| 156 | |
| 157 | s->last_read_offset = ~0U; |
| 158 | |
| 159 | addr &= 7; |
| 160 | switch(addr) { |
| 161 | case PARA_REG_DATA: |
| 162 | if (s->dataw == val) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 163 | return; |
| 164 | pdebug("wd%02x\n", val); |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 165 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 166 | s->dataw = val; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 167 | break; |
| 168 | case PARA_REG_STS: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 169 | pdebug("ws%02x\n", val); |
| 170 | if (val & PARA_STS_TMOUT) |
| 171 | s->epp_timeout = 0; |
| 172 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 173 | case PARA_REG_CTR: |
| 174 | val |= 0xc0; |
| 175 | if (s->control == val) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 176 | return; |
| 177 | pdebug("wc%02x\n", val); |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 178 | |
| 179 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { |
| 180 | if (val & PARA_CTR_DIR) { |
| 181 | dir = 1; |
| 182 | } else { |
| 183 | dir = 0; |
| 184 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 185 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
aurel32 | 563e3c6 | 2008-08-22 08:57:09 +0000 | [diff] [blame] | 186 | parm &= ~PARA_CTR_DIR; |
| 187 | } |
| 188 | |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 189 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 190 | s->control = val; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 191 | break; |
| 192 | case PARA_REG_EPP_ADDR: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 193 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
| 194 | /* Controls not correct for EPP address cycle, so do nothing */ |
| 195 | pdebug("wa%02x s\n", val); |
| 196 | else { |
| 197 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 198 | if (qemu_chr_fe_ioctl(&s->chr, |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 199 | CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 200 | s->epp_timeout = 1; |
| 201 | pdebug("wa%02x t\n", val); |
| 202 | } |
| 203 | else |
| 204 | pdebug("wa%02x\n", val); |
| 205 | } |
| 206 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 207 | case PARA_REG_EPP_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 208 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
| 209 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 210 | pdebug("we%02x s\n", val); |
| 211 | else { |
| 212 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 213 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 214 | s->epp_timeout = 1; |
| 215 | pdebug("we%02x t\n", val); |
| 216 | } |
| 217 | else |
| 218 | pdebug("we%02x\n", val); |
| 219 | } |
| 220 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 221 | } |
| 222 | } |
| 223 | |
| 224 | static void |
| 225 | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) |
| 226 | { |
| 227 | ParallelState *s = opaque; |
| 228 | uint16_t eppdata = cpu_to_le16(val); |
| 229 | int err; |
| 230 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 231 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 232 | }; |
| 233 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 234 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 235 | pdebug("we%04x s\n", val); |
| 236 | return; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 237 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 238 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 239 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 240 | s->epp_timeout = 1; |
| 241 | pdebug("we%04x t\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 242 | } |
| 243 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 244 | pdebug("we%04x\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | static void |
| 248 | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) |
| 249 | { |
| 250 | ParallelState *s = opaque; |
| 251 | uint32_t eppdata = cpu_to_le32(val); |
| 252 | int err; |
| 253 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 254 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 255 | }; |
| 256 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 257 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 258 | pdebug("we%08x s\n", val); |
| 259 | return; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 260 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 261 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 262 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 263 | s->epp_timeout = 1; |
| 264 | pdebug("we%08x t\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 265 | } |
| 266 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 267 | pdebug("we%08x\n", val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 271 | { |
| 272 | ParallelState *s = opaque; |
| 273 | uint32_t ret = 0xff; |
| 274 | |
| 275 | addr &= 7; |
| 276 | switch(addr) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 277 | case PARA_REG_DATA: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 278 | if (s->control & PARA_CTR_DIR) |
| 279 | ret = s->datar; |
| 280 | else |
| 281 | ret = s->dataw; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 282 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 283 | case PARA_REG_STS: |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 284 | ret = s->status; |
| 285 | s->irq_pending = 0; |
| 286 | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
| 287 | /* XXX Fixme: wait 5 microseconds */ |
| 288 | if (s->status & PARA_STS_ACK) |
| 289 | s->status &= ~PARA_STS_ACK; |
| 290 | else { |
| 291 | /* XXX Fixme: wait 5 microseconds */ |
| 292 | s->status |= PARA_STS_ACK; |
| 293 | s->status |= PARA_STS_BUSY; |
| 294 | } |
| 295 | } |
| 296 | parallel_update_irq(s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 297 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 298 | case PARA_REG_CTR: |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 299 | ret = s->control; |
| 300 | break; |
| 301 | } |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 302 | pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); |
| 303 | return ret; |
| 304 | } |
| 305 | |
| 306 | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
| 307 | { |
| 308 | ParallelState *s = opaque; |
| 309 | uint8_t ret = 0xff; |
| 310 | addr &= 7; |
| 311 | switch(addr) { |
| 312 | case PARA_REG_DATA: |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 313 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 314 | if (s->last_read_offset != addr || s->datar != ret) |
| 315 | pdebug("rd%02x\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 316 | s->datar = ret; |
| 317 | break; |
| 318 | case PARA_REG_STS: |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 319 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 320 | ret &= ~PARA_STS_TMOUT; |
| 321 | if (s->epp_timeout) |
| 322 | ret |= PARA_STS_TMOUT; |
| 323 | if (s->last_read_offset != addr || s->status != ret) |
| 324 | pdebug("rs%02x\n", ret); |
| 325 | s->status = ret; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 326 | break; |
| 327 | case PARA_REG_CTR: |
| 328 | /* s->control has some bits fixed to 1. It is zero only when |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 329 | it has not been yet written to. */ |
| 330 | if (s->control == 0) { |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 331 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 332 | if (s->last_read_offset != addr) |
| 333 | pdebug("rc%02x\n", ret); |
| 334 | s->control = ret; |
| 335 | } |
| 336 | else { |
| 337 | ret = s->control; |
| 338 | if (s->last_read_offset != addr) |
| 339 | pdebug("rc%02x\n", ret); |
| 340 | } |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 341 | break; |
| 342 | case PARA_REG_EPP_ADDR: |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 343 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
| 344 | (PARA_CTR_DIR | PARA_CTR_INIT)) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 345 | /* Controls not correct for EPP addr cycle, so do nothing */ |
| 346 | pdebug("ra%02x s\n", ret); |
| 347 | else { |
| 348 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 349 | if (qemu_chr_fe_ioctl(&s->chr, |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 350 | CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 351 | s->epp_timeout = 1; |
| 352 | pdebug("ra%02x t\n", ret); |
| 353 | } |
| 354 | else |
| 355 | pdebug("ra%02x\n", ret); |
| 356 | } |
| 357 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 358 | case PARA_REG_EPP_DATA: |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 359 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
| 360 | (PARA_CTR_DIR | PARA_CTR_INIT)) |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 361 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 362 | pdebug("re%02x s\n", ret); |
| 363 | else { |
| 364 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 365 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 366 | s->epp_timeout = 1; |
| 367 | pdebug("re%02x t\n", ret); |
| 368 | } |
| 369 | else |
| 370 | pdebug("re%02x\n", ret); |
| 371 | } |
| 372 | break; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 373 | } |
| 374 | s->last_read_offset = addr; |
| 375 | return ret; |
| 376 | } |
| 377 | |
| 378 | static uint32_t |
| 379 | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) |
| 380 | { |
| 381 | ParallelState *s = opaque; |
| 382 | uint32_t ret; |
| 383 | uint16_t eppdata = ~0; |
| 384 | int err; |
| 385 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 386 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 387 | }; |
| 388 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 389 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 390 | pdebug("re%04x s\n", eppdata); |
| 391 | return eppdata; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 392 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 393 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 394 | ret = le16_to_cpu(eppdata); |
| 395 | |
| 396 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 397 | s->epp_timeout = 1; |
| 398 | pdebug("re%04x t\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 399 | } |
| 400 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 401 | pdebug("re%04x\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 402 | return ret; |
| 403 | } |
| 404 | |
| 405 | static uint32_t |
| 406 | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) |
| 407 | { |
| 408 | ParallelState *s = opaque; |
| 409 | uint32_t ret; |
| 410 | uint32_t eppdata = ~0U; |
| 411 | int err; |
| 412 | struct ParallelIOArg ioarg = { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 413 | .buffer = &eppdata, .count = sizeof(eppdata) |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 414 | }; |
| 415 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 416 | /* Controls not correct for EPP data cycle, so do nothing */ |
| 417 | pdebug("re%08x s\n", eppdata); |
| 418 | return eppdata; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 419 | } |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 420 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 421 | ret = le32_to_cpu(eppdata); |
| 422 | |
| 423 | if (err) { |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 424 | s->epp_timeout = 1; |
| 425 | pdebug("re%08x t\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 426 | } |
| 427 | else |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 428 | pdebug("re%08x\n", ret); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 429 | return ret; |
| 430 | } |
| 431 | |
| 432 | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
| 433 | { |
Blue Swirl | 7f5b7d3 | 2010-04-25 18:58:25 +0000 | [diff] [blame] | 434 | pdebug("wecp%d=%02x\n", addr & 7, val); |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
| 438 | { |
| 439 | uint8_t ret = 0xff; |
Blue Swirl | 7f5b7d3 | 2010-04-25 18:58:25 +0000 | [diff] [blame] | 440 | |
| 441 | pdebug("recp%d:%02x\n", addr & 7, ret); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 442 | return ret; |
| 443 | } |
| 444 | |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 445 | static void parallel_reset(void *opaque) |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 446 | { |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 447 | ParallelState *s = opaque; |
| 448 | |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 449 | s->datar = ~0; |
| 450 | s->dataw = ~0; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 451 | s->status = PARA_STS_BUSY; |
| 452 | s->status |= PARA_STS_ACK; |
| 453 | s->status |= PARA_STS_ONLINE; |
| 454 | s->status |= PARA_STS_ERROR; |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 455 | s->status |= PARA_STS_TMOUT; |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 456 | s->control = PARA_CTR_SELECT; |
| 457 | s->control |= PARA_CTR_INIT; |
balrog | 52ccc5e | 2008-02-10 13:34:48 +0000 | [diff] [blame] | 458 | s->control |= 0xc0; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 459 | s->irq_pending = 0; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 460 | s->hw_driver = 0; |
| 461 | s->epp_timeout = 0; |
| 462 | s->last_read_offset = ~0U; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 463 | } |
| 464 | |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 465 | static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
| 466 | |
Richard Henderson | 1922abd | 2011-08-15 15:55:09 -0700 | [diff] [blame] | 467 | static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
| 468 | { 0, 8, 1, |
| 469 | .read = parallel_ioport_read_hw, |
| 470 | .write = parallel_ioport_write_hw }, |
| 471 | { 4, 1, 2, |
| 472 | .read = parallel_ioport_eppdata_read_hw2, |
| 473 | .write = parallel_ioport_eppdata_write_hw2 }, |
| 474 | { 4, 1, 4, |
| 475 | .read = parallel_ioport_eppdata_read_hw4, |
| 476 | .write = parallel_ioport_eppdata_write_hw4 }, |
| 477 | { 0x400, 8, 1, |
| 478 | .read = parallel_ioport_ecp_read, |
| 479 | .write = parallel_ioport_ecp_write }, |
| 480 | PORTIO_END_OF_LIST(), |
| 481 | }; |
| 482 | |
| 483 | static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { |
| 484 | { 0, 8, 1, |
| 485 | .read = parallel_ioport_read_sw, |
| 486 | .write = parallel_ioport_write_sw }, |
| 487 | PORTIO_END_OF_LIST(), |
| 488 | }; |
| 489 | |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 490 | |
| 491 | static const VMStateDescription vmstate_parallel_isa = { |
| 492 | .name = "parallel_isa", |
| 493 | .version_id = 1, |
| 494 | .minimum_version_id = 1, |
| 495 | .fields = (VMStateField[]) { |
| 496 | VMSTATE_UINT8(state.dataw, ISAParallelState), |
| 497 | VMSTATE_UINT8(state.datar, ISAParallelState), |
| 498 | VMSTATE_UINT8(state.status, ISAParallelState), |
| 499 | VMSTATE_UINT8(state.control, ISAParallelState), |
| 500 | VMSTATE_INT32(state.irq_pending, ISAParallelState), |
| 501 | VMSTATE_INT32(state.epp_timeout, ISAParallelState), |
| 502 | VMSTATE_END_OF_LIST() |
| 503 | } |
| 504 | }; |
| 505 | |
Peng Hao | 98fab4c | 2017-07-12 23:41:59 +0800 | [diff] [blame] | 506 | static int parallel_can_receive(void *opaque) |
| 507 | { |
| 508 | return 1; |
| 509 | } |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 510 | |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 511 | static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 512 | { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 513 | static int index; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 514 | ISADevice *isadev = ISA_DEVICE(dev); |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 515 | ISAParallelState *isa = ISA_PARALLEL(dev); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 516 | ParallelState *s = &isa->state; |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 517 | int base; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 518 | uint8_t dummy; |
| 519 | |
Anton Nefedov | 3065070 | 2017-07-06 15:08:52 +0300 | [diff] [blame] | 520 | if (!qemu_chr_fe_backend_connected(&s->chr)) { |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 521 | error_setg(errp, "Can't create parallel device, empty char device"); |
| 522 | return; |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 523 | } |
| 524 | |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 525 | if (isa->index == -1) { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 526 | isa->index = index; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 527 | } |
| 528 | if (isa->index >= MAX_PARALLEL_PORTS) { |
| 529 | error_setg(errp, "Max. supported number of parallel ports is %d.", |
| 530 | MAX_PARALLEL_PORTS); |
| 531 | return; |
| 532 | } |
| 533 | if (isa->iobase == -1) { |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 534 | isa->iobase = isa_parallel_io[isa->index]; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 535 | } |
Gerd Hoffmann | e8ee28f | 2009-10-13 13:38:39 +0200 | [diff] [blame] | 536 | index++; |
| 537 | |
| 538 | base = isa->iobase; |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 539 | isa_init_irq(isadev, &s->irq, isa->isairq); |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 540 | qemu_register_reset(parallel_reset, s); |
bellard | 6508fe5 | 2005-01-15 12:02:56 +0000 | [diff] [blame] | 541 | |
Peng Hao | 98fab4c | 2017-07-12 23:41:59 +0800 | [diff] [blame] | 542 | qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, |
| 543 | NULL, NULL, s, NULL, true); |
Marc-André Lureau | 5345fdb | 2016-10-22 12:52:55 +0300 | [diff] [blame] | 544 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 545 | s->hw_driver = 1; |
ths | 0fa7f15 | 2007-06-07 21:07:11 +0000 | [diff] [blame] | 546 | s->status = dummy; |
ths | 5867c88 | 2007-02-17 23:44:43 +0000 | [diff] [blame] | 547 | } |
| 548 | |
Marc-André Lureau | e305a16 | 2016-07-13 02:11:59 +0200 | [diff] [blame] | 549 | isa_register_portio_list(isadev, &s->portio_list, base, |
Richard Henderson | 1922abd | 2011-08-15 15:55:09 -0700 | [diff] [blame] | 550 | (s->hw_driver |
| 551 | ? &isa_parallel_portio_hw_list[0] |
| 552 | : &isa_parallel_portio_sw_list[0]), |
| 553 | s, "parallel"); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 554 | } |
| 555 | |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 556 | /* Memory mapped interface */ |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 557 | static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 558 | { |
| 559 | ParallelState *s = opaque; |
| 560 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 561 | return parallel_ioport_read_sw(s, addr >> s->it_shift) & |
| 562 | MAKE_64BIT_MASK(0, size * 8); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 563 | } |
| 564 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 565 | static void parallel_mm_writefn(void *opaque, hwaddr addr, |
| 566 | uint64_t value, unsigned size) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 567 | { |
| 568 | ParallelState *s = opaque; |
| 569 | |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 570 | parallel_ioport_write_sw(s, addr >> s->it_shift, |
| 571 | value & MAKE_64BIT_MASK(0, size * 8)); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 574 | static const MemoryRegionOps parallel_mm_ops = { |
Peter Maydell | 05b4940 | 2018-06-15 14:57:13 +0100 | [diff] [blame] | 575 | .read = parallel_mm_readfn, |
| 576 | .write = parallel_mm_writefn, |
| 577 | .valid.min_access_size = 1, |
| 578 | .valid.max_access_size = 4, |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 579 | .endianness = DEVICE_NATIVE_ENDIAN, |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 580 | }; |
| 581 | |
| 582 | /* If fd is zero, it means that the parallel device uses the console */ |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 583 | bool parallel_mm_init(MemoryRegion *address_space, |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 584 | hwaddr base, int it_shift, qemu_irq irq, |
Marc-André Lureau | 0ec7b3e | 2016-12-07 16:20:22 +0300 | [diff] [blame] | 585 | Chardev *chr) |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 586 | { |
| 587 | ParallelState *s; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 588 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 589 | s = g_malloc0(sizeof(ParallelState)); |
aurel32 | 33093a0 | 2008-12-07 23:26:09 +0000 | [diff] [blame] | 590 | s->irq = irq; |
Marc-André Lureau | becdfa0 | 2016-10-22 12:52:51 +0300 | [diff] [blame] | 591 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 592 | s->it_shift = it_shift; |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 593 | qemu_register_reset(parallel_reset, s); |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 594 | |
Paolo Bonzini | 2c9b15c | 2013-06-06 05:41:28 -0400 | [diff] [blame] | 595 | memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, |
Avi Kivity | 63858cd | 2011-10-06 16:44:26 +0200 | [diff] [blame] | 596 | "parallel", 8 << it_shift); |
| 597 | memory_region_add_subregion(address_space, base, &s->iomem); |
Blue Swirl | defdb20 | 2011-02-05 14:51:57 +0000 | [diff] [blame] | 598 | return true; |
ths | d60532c | 2007-06-18 18:55:46 +0000 | [diff] [blame] | 599 | } |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 600 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 601 | static Property parallel_isa_properties[] = { |
| 602 | DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), |
Paolo Bonzini | c7bcc85 | 2014-02-08 11:01:53 +0100 | [diff] [blame] | 603 | DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 604 | DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
| 605 | DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), |
| 606 | DEFINE_PROP_END_OF_LIST(), |
| 607 | }; |
| 608 | |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 609 | static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
| 610 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 611 | DeviceClass *dc = DEVICE_CLASS(klass); |
Andreas Färber | db895a1 | 2012-11-25 02:37:14 +0100 | [diff] [blame] | 612 | |
| 613 | dc->realize = parallel_isa_realizefn; |
Pavel Dovgalyuk | 461a275 | 2014-08-28 15:18:46 +0400 | [diff] [blame] | 614 | dc->vmsd = &vmstate_parallel_isa; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 615 | dc->props = parallel_isa_properties; |
Marcel Apfelbaum | 125ee0e | 2013-07-29 17:17:45 +0300 | [diff] [blame] | 616 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 617 | } |
| 618 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 619 | static const TypeInfo parallel_isa_info = { |
Andreas Färber | b0dc5ee | 2013-04-27 22:18:45 +0200 | [diff] [blame] | 620 | .name = TYPE_ISA_PARALLEL, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 621 | .parent = TYPE_ISA_DEVICE, |
| 622 | .instance_size = sizeof(ISAParallelState), |
| 623 | .class_init = parallel_isa_class_initfn, |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 624 | }; |
| 625 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 626 | static void parallel_register_types(void) |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 627 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 628 | type_register_static(¶llel_isa_info); |
Gerd Hoffmann | 021f067 | 2009-09-22 13:53:22 +0200 | [diff] [blame] | 629 | } |
| 630 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 631 | type_init(parallel_register_types) |