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bellard6508fe52005-01-15 12:02:56 +00001/*
2 * QEMU Parallel PORT emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellarde57a8c02005-11-10 23:58:52 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5867c882007-02-17 23:44:43 +00005 * Copyright (c) 2007 Marko Kohtala
ths5fafdf22007-09-16 21:08:06 +00006 *
bellard6508fe52005-01-15 12:02:56 +00007 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
Peter Maydellb6a0aa02016-01-26 18:17:03 +000025#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010026#include "qapi/error.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010027#include "hw/hw.h"
Marc-André Lureau7566c6e2017-01-26 17:33:39 +040028#include "chardev/char-parallel.h"
Marc-André Lureau4d43a602017-01-26 18:26:44 +040029#include "chardev/char-fe.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010030#include "hw/isa/isa.h"
Philippe Mathieu-Daudébb3d5ea2018-03-08 23:39:22 +010031#include "hw/char/parallel.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010032#include "sysemu/sysemu.h"
bellard6508fe52005-01-15 12:02:56 +000033
34//#define DEBUG_PARALLEL
35
ths5867c882007-02-17 23:44:43 +000036#ifdef DEBUG_PARALLEL
Blue Swirl001faf32009-05-13 17:53:17 +000037#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
ths5867c882007-02-17 23:44:43 +000038#else
Blue Swirl001faf32009-05-13 17:53:17 +000039#define pdebug(fmt, ...) ((void)0)
ths5867c882007-02-17 23:44:43 +000040#endif
41
42#define PARA_REG_DATA 0
43#define PARA_REG_STS 1
44#define PARA_REG_CTR 2
45#define PARA_REG_EPP_ADDR 3
46#define PARA_REG_EPP_DATA 4
47
bellard6508fe52005-01-15 12:02:56 +000048/*
49 * These are the definitions for the Printer Status Register
50 */
51#define PARA_STS_BUSY 0x80 /* Busy complement */
52#define PARA_STS_ACK 0x40 /* Acknowledge */
53#define PARA_STS_PAPER 0x20 /* Out of paper */
54#define PARA_STS_ONLINE 0x10 /* Online */
55#define PARA_STS_ERROR 0x08 /* Error complement */
ths5867c882007-02-17 23:44:43 +000056#define PARA_STS_TMOUT 0x01 /* EPP timeout */
bellard6508fe52005-01-15 12:02:56 +000057
58/*
59 * These are the definitions for the Printer Control Register
60 */
ths5867c882007-02-17 23:44:43 +000061#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
bellard6508fe52005-01-15 12:02:56 +000062#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
63#define PARA_CTR_SELECT 0x08 /* Select In complement */
64#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
65#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
66#define PARA_CTR_STROBE 0x01 /* Strobe complement */
67
ths5867c882007-02-17 23:44:43 +000068#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
69
Blue Swirldefdb202011-02-05 14:51:57 +000070typedef struct ParallelState {
Avi Kivity63858cd2011-10-06 16:44:26 +020071 MemoryRegion iomem;
ths5867c882007-02-17 23:44:43 +000072 uint8_t dataw;
73 uint8_t datar;
74 uint8_t status;
bellard6508fe52005-01-15 12:02:56 +000075 uint8_t control;
pbrookd537cf62007-04-07 18:14:41 +000076 qemu_irq irq;
bellard6508fe52005-01-15 12:02:56 +000077 int irq_pending;
Marc-André Lureaubecdfa02016-10-22 12:52:51 +030078 CharBackend chr;
bellarde57a8c02005-11-10 23:58:52 +000079 int hw_driver;
ths5867c882007-02-17 23:44:43 +000080 int epp_timeout;
81 uint32_t last_read_offset; /* For debugging */
thsd60532c2007-06-18 18:55:46 +000082 /* Memory-mapped interface */
thsd60532c2007-06-18 18:55:46 +000083 int it_shift;
Marc-André Lureaue305a162016-07-13 02:11:59 +020084 PortioList portio_list;
Blue Swirldefdb202011-02-05 14:51:57 +000085} ParallelState;
bellard6508fe52005-01-15 12:02:56 +000086
Andreas Färberb0dc5ee2013-04-27 22:18:45 +020087#define TYPE_ISA_PARALLEL "isa-parallel"
88#define ISA_PARALLEL(obj) \
89 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
90
Gerd Hoffmann021f0672009-09-22 13:53:22 +020091typedef struct ISAParallelState {
Andreas Färberb0dc5ee2013-04-27 22:18:45 +020092 ISADevice parent_obj;
93
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +020094 uint32_t index;
Gerd Hoffmann021f0672009-09-22 13:53:22 +020095 uint32_t iobase;
96 uint32_t isairq;
97 ParallelState state;
98} ISAParallelState;
99
bellard6508fe52005-01-15 12:02:56 +0000100static void parallel_update_irq(ParallelState *s)
101{
102 if (s->irq_pending)
pbrookd537cf62007-04-07 18:14:41 +0000103 qemu_irq_raise(s->irq);
bellard6508fe52005-01-15 12:02:56 +0000104 else
pbrookd537cf62007-04-07 18:14:41 +0000105 qemu_irq_lower(s->irq);
bellard6508fe52005-01-15 12:02:56 +0000106}
107
ths5867c882007-02-17 23:44:43 +0000108static void
109parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
bellard6508fe52005-01-15 12:02:56 +0000110{
111 ParallelState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000112
ths5867c882007-02-17 23:44:43 +0000113 pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
114
bellard6508fe52005-01-15 12:02:56 +0000115 addr &= 7;
bellard6508fe52005-01-15 12:02:56 +0000116 switch(addr) {
ths5867c882007-02-17 23:44:43 +0000117 case PARA_REG_DATA:
ths0fa7f152007-06-07 21:07:11 +0000118 s->dataw = val;
119 parallel_update_irq(s);
bellard6508fe52005-01-15 12:02:56 +0000120 break;
ths5867c882007-02-17 23:44:43 +0000121 case PARA_REG_CTR:
balrog52ccc5e2008-02-10 13:34:48 +0000122 val |= 0xc0;
ths0fa7f152007-06-07 21:07:11 +0000123 if ((val & PARA_CTR_INIT) == 0 ) {
124 s->status = PARA_STS_BUSY;
125 s->status |= PARA_STS_ACK;
126 s->status |= PARA_STS_ONLINE;
127 s->status |= PARA_STS_ERROR;
128 }
129 else if (val & PARA_CTR_SELECT) {
130 if (val & PARA_CTR_STROBE) {
131 s->status &= ~PARA_STS_BUSY;
132 if ((s->control & PARA_CTR_STROBE) == 0)
Daniel P. Berrange6ab3fc32016-09-06 14:56:04 +0100133 /* XXX this blocks entire thread. Rewrite to use
134 * qemu_chr_fe_write and background I/O callbacks */
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300135 qemu_chr_fe_write_all(&s->chr, &s->dataw, 1);
ths0fa7f152007-06-07 21:07:11 +0000136 } else {
137 if (s->control & PARA_CTR_INTEN) {
138 s->irq_pending = 1;
139 }
140 }
141 }
142 parallel_update_irq(s);
143 s->control = val;
bellard6508fe52005-01-15 12:02:56 +0000144 break;
145 }
146}
147
ths5867c882007-02-17 23:44:43 +0000148static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
149{
150 ParallelState *s = opaque;
151 uint8_t parm = val;
aurel32563e3c62008-08-22 08:57:09 +0000152 int dir;
ths5867c882007-02-17 23:44:43 +0000153
154 /* Sometimes programs do several writes for timing purposes on old
155 HW. Take care not to waste time on writes that do nothing. */
156
157 s->last_read_offset = ~0U;
158
159 addr &= 7;
160 switch(addr) {
161 case PARA_REG_DATA:
162 if (s->dataw == val)
ths0fa7f152007-06-07 21:07:11 +0000163 return;
164 pdebug("wd%02x\n", val);
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300165 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
ths0fa7f152007-06-07 21:07:11 +0000166 s->dataw = val;
ths5867c882007-02-17 23:44:43 +0000167 break;
168 case PARA_REG_STS:
ths0fa7f152007-06-07 21:07:11 +0000169 pdebug("ws%02x\n", val);
170 if (val & PARA_STS_TMOUT)
171 s->epp_timeout = 0;
172 break;
ths5867c882007-02-17 23:44:43 +0000173 case PARA_REG_CTR:
174 val |= 0xc0;
175 if (s->control == val)
ths0fa7f152007-06-07 21:07:11 +0000176 return;
177 pdebug("wc%02x\n", val);
aurel32563e3c62008-08-22 08:57:09 +0000178
179 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
180 if (val & PARA_CTR_DIR) {
181 dir = 1;
182 } else {
183 dir = 0;
184 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300185 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
aurel32563e3c62008-08-22 08:57:09 +0000186 parm &= ~PARA_CTR_DIR;
187 }
188
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300189 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
ths0fa7f152007-06-07 21:07:11 +0000190 s->control = val;
ths5867c882007-02-17 23:44:43 +0000191 break;
192 case PARA_REG_EPP_ADDR:
ths0fa7f152007-06-07 21:07:11 +0000193 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
194 /* Controls not correct for EPP address cycle, so do nothing */
195 pdebug("wa%02x s\n", val);
196 else {
197 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300198 if (qemu_chr_fe_ioctl(&s->chr,
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300199 CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000200 s->epp_timeout = 1;
201 pdebug("wa%02x t\n", val);
202 }
203 else
204 pdebug("wa%02x\n", val);
205 }
206 break;
ths5867c882007-02-17 23:44:43 +0000207 case PARA_REG_EPP_DATA:
ths0fa7f152007-06-07 21:07:11 +0000208 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
209 /* Controls not correct for EPP data cycle, so do nothing */
210 pdebug("we%02x s\n", val);
211 else {
212 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300213 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000214 s->epp_timeout = 1;
215 pdebug("we%02x t\n", val);
216 }
217 else
218 pdebug("we%02x\n", val);
219 }
220 break;
ths5867c882007-02-17 23:44:43 +0000221 }
222}
223
224static void
225parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
226{
227 ParallelState *s = opaque;
228 uint16_t eppdata = cpu_to_le16(val);
229 int err;
230 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000231 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000232 };
233 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
ths0fa7f152007-06-07 21:07:11 +0000234 /* Controls not correct for EPP data cycle, so do nothing */
235 pdebug("we%04x s\n", val);
236 return;
ths5867c882007-02-17 23:44:43 +0000237 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300238 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
ths5867c882007-02-17 23:44:43 +0000239 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000240 s->epp_timeout = 1;
241 pdebug("we%04x t\n", val);
ths5867c882007-02-17 23:44:43 +0000242 }
243 else
ths0fa7f152007-06-07 21:07:11 +0000244 pdebug("we%04x\n", val);
ths5867c882007-02-17 23:44:43 +0000245}
246
247static void
248parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
249{
250 ParallelState *s = opaque;
251 uint32_t eppdata = cpu_to_le32(val);
252 int err;
253 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000254 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000255 };
256 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
ths0fa7f152007-06-07 21:07:11 +0000257 /* Controls not correct for EPP data cycle, so do nothing */
258 pdebug("we%08x s\n", val);
259 return;
ths5867c882007-02-17 23:44:43 +0000260 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300261 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
ths5867c882007-02-17 23:44:43 +0000262 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000263 s->epp_timeout = 1;
264 pdebug("we%08x t\n", val);
ths5867c882007-02-17 23:44:43 +0000265 }
266 else
ths0fa7f152007-06-07 21:07:11 +0000267 pdebug("we%08x\n", val);
ths5867c882007-02-17 23:44:43 +0000268}
269
270static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
bellard6508fe52005-01-15 12:02:56 +0000271{
272 ParallelState *s = opaque;
273 uint32_t ret = 0xff;
274
275 addr &= 7;
276 switch(addr) {
ths5867c882007-02-17 23:44:43 +0000277 case PARA_REG_DATA:
ths0fa7f152007-06-07 21:07:11 +0000278 if (s->control & PARA_CTR_DIR)
279 ret = s->datar;
280 else
281 ret = s->dataw;
bellard6508fe52005-01-15 12:02:56 +0000282 break;
ths5867c882007-02-17 23:44:43 +0000283 case PARA_REG_STS:
ths0fa7f152007-06-07 21:07:11 +0000284 ret = s->status;
285 s->irq_pending = 0;
286 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
287 /* XXX Fixme: wait 5 microseconds */
288 if (s->status & PARA_STS_ACK)
289 s->status &= ~PARA_STS_ACK;
290 else {
291 /* XXX Fixme: wait 5 microseconds */
292 s->status |= PARA_STS_ACK;
293 s->status |= PARA_STS_BUSY;
294 }
295 }
296 parallel_update_irq(s);
bellard6508fe52005-01-15 12:02:56 +0000297 break;
ths5867c882007-02-17 23:44:43 +0000298 case PARA_REG_CTR:
bellard6508fe52005-01-15 12:02:56 +0000299 ret = s->control;
300 break;
301 }
ths5867c882007-02-17 23:44:43 +0000302 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
303 return ret;
304}
305
306static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
307{
308 ParallelState *s = opaque;
309 uint8_t ret = 0xff;
310 addr &= 7;
311 switch(addr) {
312 case PARA_REG_DATA:
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300313 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
ths0fa7f152007-06-07 21:07:11 +0000314 if (s->last_read_offset != addr || s->datar != ret)
315 pdebug("rd%02x\n", ret);
ths5867c882007-02-17 23:44:43 +0000316 s->datar = ret;
317 break;
318 case PARA_REG_STS:
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300319 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
ths0fa7f152007-06-07 21:07:11 +0000320 ret &= ~PARA_STS_TMOUT;
321 if (s->epp_timeout)
322 ret |= PARA_STS_TMOUT;
323 if (s->last_read_offset != addr || s->status != ret)
324 pdebug("rs%02x\n", ret);
325 s->status = ret;
ths5867c882007-02-17 23:44:43 +0000326 break;
327 case PARA_REG_CTR:
328 /* s->control has some bits fixed to 1. It is zero only when
ths0fa7f152007-06-07 21:07:11 +0000329 it has not been yet written to. */
330 if (s->control == 0) {
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300331 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
ths0fa7f152007-06-07 21:07:11 +0000332 if (s->last_read_offset != addr)
333 pdebug("rc%02x\n", ret);
334 s->control = ret;
335 }
336 else {
337 ret = s->control;
338 if (s->last_read_offset != addr)
339 pdebug("rc%02x\n", ret);
340 }
ths5867c882007-02-17 23:44:43 +0000341 break;
342 case PARA_REG_EPP_ADDR:
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300343 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
344 (PARA_CTR_DIR | PARA_CTR_INIT))
ths0fa7f152007-06-07 21:07:11 +0000345 /* Controls not correct for EPP addr cycle, so do nothing */
346 pdebug("ra%02x s\n", ret);
347 else {
348 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300349 if (qemu_chr_fe_ioctl(&s->chr,
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300350 CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000351 s->epp_timeout = 1;
352 pdebug("ra%02x t\n", ret);
353 }
354 else
355 pdebug("ra%02x\n", ret);
356 }
357 break;
ths5867c882007-02-17 23:44:43 +0000358 case PARA_REG_EPP_DATA:
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300359 if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) !=
360 (PARA_CTR_DIR | PARA_CTR_INIT))
ths0fa7f152007-06-07 21:07:11 +0000361 /* Controls not correct for EPP data cycle, so do nothing */
362 pdebug("re%02x s\n", ret);
363 else {
364 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300365 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
ths0fa7f152007-06-07 21:07:11 +0000366 s->epp_timeout = 1;
367 pdebug("re%02x t\n", ret);
368 }
369 else
370 pdebug("re%02x\n", ret);
371 }
372 break;
ths5867c882007-02-17 23:44:43 +0000373 }
374 s->last_read_offset = addr;
375 return ret;
376}
377
378static uint32_t
379parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
380{
381 ParallelState *s = opaque;
382 uint32_t ret;
383 uint16_t eppdata = ~0;
384 int err;
385 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000386 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000387 };
388 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
ths0fa7f152007-06-07 21:07:11 +0000389 /* Controls not correct for EPP data cycle, so do nothing */
390 pdebug("re%04x s\n", eppdata);
391 return eppdata;
ths5867c882007-02-17 23:44:43 +0000392 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300393 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ths5867c882007-02-17 23:44:43 +0000394 ret = le16_to_cpu(eppdata);
395
396 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000397 s->epp_timeout = 1;
398 pdebug("re%04x t\n", ret);
ths5867c882007-02-17 23:44:43 +0000399 }
400 else
ths0fa7f152007-06-07 21:07:11 +0000401 pdebug("re%04x\n", ret);
ths5867c882007-02-17 23:44:43 +0000402 return ret;
403}
404
405static uint32_t
406parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
407{
408 ParallelState *s = opaque;
409 uint32_t ret;
410 uint32_t eppdata = ~0U;
411 int err;
412 struct ParallelIOArg ioarg = {
ths0fa7f152007-06-07 21:07:11 +0000413 .buffer = &eppdata, .count = sizeof(eppdata)
ths5867c882007-02-17 23:44:43 +0000414 };
415 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
ths0fa7f152007-06-07 21:07:11 +0000416 /* Controls not correct for EPP data cycle, so do nothing */
417 pdebug("re%08x s\n", eppdata);
418 return eppdata;
ths5867c882007-02-17 23:44:43 +0000419 }
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300420 err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
ths5867c882007-02-17 23:44:43 +0000421 ret = le32_to_cpu(eppdata);
422
423 if (err) {
ths0fa7f152007-06-07 21:07:11 +0000424 s->epp_timeout = 1;
425 pdebug("re%08x t\n", ret);
ths5867c882007-02-17 23:44:43 +0000426 }
427 else
ths0fa7f152007-06-07 21:07:11 +0000428 pdebug("re%08x\n", ret);
ths5867c882007-02-17 23:44:43 +0000429 return ret;
430}
431
432static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
433{
Blue Swirl7f5b7d32010-04-25 18:58:25 +0000434 pdebug("wecp%d=%02x\n", addr & 7, val);
ths5867c882007-02-17 23:44:43 +0000435}
436
437static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
438{
439 uint8_t ret = 0xff;
Blue Swirl7f5b7d32010-04-25 18:58:25 +0000440
441 pdebug("recp%d:%02x\n", addr & 7, ret);
bellard6508fe52005-01-15 12:02:56 +0000442 return ret;
443}
444
aurel3233093a02008-12-07 23:26:09 +0000445static void parallel_reset(void *opaque)
bellard6508fe52005-01-15 12:02:56 +0000446{
aurel3233093a02008-12-07 23:26:09 +0000447 ParallelState *s = opaque;
448
ths5867c882007-02-17 23:44:43 +0000449 s->datar = ~0;
450 s->dataw = ~0;
bellard6508fe52005-01-15 12:02:56 +0000451 s->status = PARA_STS_BUSY;
452 s->status |= PARA_STS_ACK;
453 s->status |= PARA_STS_ONLINE;
454 s->status |= PARA_STS_ERROR;
balrog52ccc5e2008-02-10 13:34:48 +0000455 s->status |= PARA_STS_TMOUT;
bellard6508fe52005-01-15 12:02:56 +0000456 s->control = PARA_CTR_SELECT;
457 s->control |= PARA_CTR_INIT;
balrog52ccc5e2008-02-10 13:34:48 +0000458 s->control |= 0xc0;
ths5867c882007-02-17 23:44:43 +0000459 s->irq_pending = 0;
ths5867c882007-02-17 23:44:43 +0000460 s->hw_driver = 0;
461 s->epp_timeout = 0;
462 s->last_read_offset = ~0U;
thsd60532c2007-06-18 18:55:46 +0000463}
464
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200465static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
466
Richard Henderson1922abd2011-08-15 15:55:09 -0700467static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
468 { 0, 8, 1,
469 .read = parallel_ioport_read_hw,
470 .write = parallel_ioport_write_hw },
471 { 4, 1, 2,
472 .read = parallel_ioport_eppdata_read_hw2,
473 .write = parallel_ioport_eppdata_write_hw2 },
474 { 4, 1, 4,
475 .read = parallel_ioport_eppdata_read_hw4,
476 .write = parallel_ioport_eppdata_write_hw4 },
477 { 0x400, 8, 1,
478 .read = parallel_ioport_ecp_read,
479 .write = parallel_ioport_ecp_write },
480 PORTIO_END_OF_LIST(),
481};
482
483static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
484 { 0, 8, 1,
485 .read = parallel_ioport_read_sw,
486 .write = parallel_ioport_write_sw },
487 PORTIO_END_OF_LIST(),
488};
489
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400490
491static const VMStateDescription vmstate_parallel_isa = {
492 .name = "parallel_isa",
493 .version_id = 1,
494 .minimum_version_id = 1,
495 .fields = (VMStateField[]) {
496 VMSTATE_UINT8(state.dataw, ISAParallelState),
497 VMSTATE_UINT8(state.datar, ISAParallelState),
498 VMSTATE_UINT8(state.status, ISAParallelState),
499 VMSTATE_UINT8(state.control, ISAParallelState),
500 VMSTATE_INT32(state.irq_pending, ISAParallelState),
501 VMSTATE_INT32(state.epp_timeout, ISAParallelState),
502 VMSTATE_END_OF_LIST()
503 }
504};
505
Peng Hao98fab4c2017-07-12 23:41:59 +0800506static int parallel_can_receive(void *opaque)
507{
508 return 1;
509}
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400510
Andreas Färberdb895a12012-11-25 02:37:14 +0100511static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
thsd60532c2007-06-18 18:55:46 +0000512{
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200513 static int index;
Andreas Färberdb895a12012-11-25 02:37:14 +0100514 ISADevice *isadev = ISA_DEVICE(dev);
Andreas Färberb0dc5ee2013-04-27 22:18:45 +0200515 ISAParallelState *isa = ISA_PARALLEL(dev);
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200516 ParallelState *s = &isa->state;
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200517 int base;
thsd60532c2007-06-18 18:55:46 +0000518 uint8_t dummy;
519
Anton Nefedov30650702017-07-06 15:08:52 +0300520 if (!qemu_chr_fe_backend_connected(&s->chr)) {
Andreas Färberdb895a12012-11-25 02:37:14 +0100521 error_setg(errp, "Can't create parallel device, empty char device");
522 return;
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200523 }
524
Andreas Färberdb895a12012-11-25 02:37:14 +0100525 if (isa->index == -1) {
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200526 isa->index = index;
Andreas Färberdb895a12012-11-25 02:37:14 +0100527 }
528 if (isa->index >= MAX_PARALLEL_PORTS) {
529 error_setg(errp, "Max. supported number of parallel ports is %d.",
530 MAX_PARALLEL_PORTS);
531 return;
532 }
533 if (isa->iobase == -1) {
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200534 isa->iobase = isa_parallel_io[isa->index];
Andreas Färberdb895a12012-11-25 02:37:14 +0100535 }
Gerd Hoffmanne8ee28f2009-10-13 13:38:39 +0200536 index++;
537
538 base = isa->iobase;
Andreas Färberdb895a12012-11-25 02:37:14 +0100539 isa_init_irq(isadev, &s->irq, isa->isairq);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200540 qemu_register_reset(parallel_reset, s);
bellard6508fe52005-01-15 12:02:56 +0000541
Peng Hao98fab4c2017-07-12 23:41:59 +0800542 qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL,
543 NULL, NULL, s, NULL, true);
Marc-André Lureau5345fdb2016-10-22 12:52:55 +0300544 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
ths5867c882007-02-17 23:44:43 +0000545 s->hw_driver = 1;
ths0fa7f152007-06-07 21:07:11 +0000546 s->status = dummy;
ths5867c882007-02-17 23:44:43 +0000547 }
548
Marc-André Lureaue305a162016-07-13 02:11:59 +0200549 isa_register_portio_list(isadev, &s->portio_list, base,
Richard Henderson1922abd2011-08-15 15:55:09 -0700550 (s->hw_driver
551 ? &isa_parallel_portio_hw_list[0]
552 : &isa_parallel_portio_sw_list[0]),
553 s, "parallel");
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200554}
555
thsd60532c2007-06-18 18:55:46 +0000556/* Memory mapped interface */
Peter Maydell05b49402018-06-15 14:57:13 +0100557static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size)
thsd60532c2007-06-18 18:55:46 +0000558{
559 ParallelState *s = opaque;
560
Peter Maydell05b49402018-06-15 14:57:13 +0100561 return parallel_ioport_read_sw(s, addr >> s->it_shift) &
562 MAKE_64BIT_MASK(0, size * 8);
thsd60532c2007-06-18 18:55:46 +0000563}
564
Peter Maydell05b49402018-06-15 14:57:13 +0100565static void parallel_mm_writefn(void *opaque, hwaddr addr,
566 uint64_t value, unsigned size)
thsd60532c2007-06-18 18:55:46 +0000567{
568 ParallelState *s = opaque;
569
Peter Maydell05b49402018-06-15 14:57:13 +0100570 parallel_ioport_write_sw(s, addr >> s->it_shift,
571 value & MAKE_64BIT_MASK(0, size * 8));
thsd60532c2007-06-18 18:55:46 +0000572}
573
Avi Kivity63858cd2011-10-06 16:44:26 +0200574static const MemoryRegionOps parallel_mm_ops = {
Peter Maydell05b49402018-06-15 14:57:13 +0100575 .read = parallel_mm_readfn,
576 .write = parallel_mm_writefn,
577 .valid.min_access_size = 1,
578 .valid.max_access_size = 4,
Avi Kivity63858cd2011-10-06 16:44:26 +0200579 .endianness = DEVICE_NATIVE_ENDIAN,
thsd60532c2007-06-18 18:55:46 +0000580};
581
582/* If fd is zero, it means that the parallel device uses the console */
Avi Kivity63858cd2011-10-06 16:44:26 +0200583bool parallel_mm_init(MemoryRegion *address_space,
Avi Kivitya8170e52012-10-23 12:30:10 +0200584 hwaddr base, int it_shift, qemu_irq irq,
Marc-André Lureau0ec7b3e2016-12-07 16:20:22 +0300585 Chardev *chr)
thsd60532c2007-06-18 18:55:46 +0000586{
587 ParallelState *s;
thsd60532c2007-06-18 18:55:46 +0000588
Anthony Liguori7267c092011-08-20 22:09:37 -0500589 s = g_malloc0(sizeof(ParallelState));
aurel3233093a02008-12-07 23:26:09 +0000590 s->irq = irq;
Marc-André Lureaubecdfa02016-10-22 12:52:51 +0300591 qemu_chr_fe_init(&s->chr, chr, &error_abort);
thsd60532c2007-06-18 18:55:46 +0000592 s->it_shift = it_shift;
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200593 qemu_register_reset(parallel_reset, s);
thsd60532c2007-06-18 18:55:46 +0000594
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400595 memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
Avi Kivity63858cd2011-10-06 16:44:26 +0200596 "parallel", 8 << it_shift);
597 memory_region_add_subregion(address_space, base, &s->iomem);
Blue Swirldefdb202011-02-05 14:51:57 +0000598 return true;
thsd60532c2007-06-18 18:55:46 +0000599}
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200600
Anthony Liguori39bffca2011-12-07 21:34:16 -0600601static Property parallel_isa_properties[] = {
602 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
Paolo Bonzinic7bcc852014-02-08 11:01:53 +0100603 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600604 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
605 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
606 DEFINE_PROP_END_OF_LIST(),
607};
608
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600609static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
610{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600611 DeviceClass *dc = DEVICE_CLASS(klass);
Andreas Färberdb895a12012-11-25 02:37:14 +0100612
613 dc->realize = parallel_isa_realizefn;
Pavel Dovgalyuk461a2752014-08-28 15:18:46 +0400614 dc->vmsd = &vmstate_parallel_isa;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600615 dc->props = parallel_isa_properties;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300616 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600617}
618
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100619static const TypeInfo parallel_isa_info = {
Andreas Färberb0dc5ee2013-04-27 22:18:45 +0200620 .name = TYPE_ISA_PARALLEL,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600621 .parent = TYPE_ISA_DEVICE,
622 .instance_size = sizeof(ISAParallelState),
623 .class_init = parallel_isa_class_initfn,
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200624};
625
Andreas Färber83f7d432012-02-09 15:20:55 +0100626static void parallel_register_types(void)
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200627{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600628 type_register_static(&parallel_isa_info);
Gerd Hoffmann021f0672009-09-22 13:53:22 +0200629}
630
Andreas Färber83f7d432012-02-09 15:20:55 +0100631type_init(parallel_register_types)