pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 1 | #include "hw.h" |
| 2 | #include "sh.h" |
Blue Swirl | ca20cf3 | 2009-09-20 14:58:02 +0000 | [diff] [blame] | 3 | #include "loader.h" |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 4 | |
| 5 | #define CE1 0x0100 |
| 6 | #define CE2 0x0200 |
| 7 | #define RE 0x0400 |
| 8 | #define WE 0x0800 |
| 9 | #define ALE 0x1000 |
| 10 | #define CLE 0x2000 |
| 11 | #define RDY1 0x4000 |
| 12 | #define RDY2 0x8000 |
| 13 | #define RDY(n) ((n) == 0 ? RDY1 : RDY2) |
| 14 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 15 | typedef enum { WAIT, READ1, READ2, READ3 } state_t; |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 16 | |
| 17 | typedef struct { |
| 18 | uint8_t *flash_contents; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 19 | state_t state; |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 20 | uint32_t address; |
| 21 | uint8_t address_cycle; |
| 22 | } tc58128_dev; |
| 23 | |
| 24 | static tc58128_dev tc58128_devs[2]; |
| 25 | |
| 26 | #define FLASH_SIZE (16*1024*1024) |
| 27 | |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 28 | static void init_dev(tc58128_dev * dev, const char *filename) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 29 | { |
| 30 | int ret, blocks; |
| 31 | |
| 32 | dev->state = WAIT; |
Peter Maydell | 35914dc | 2011-11-09 19:34:28 +0000 | [diff] [blame] | 33 | dev->flash_contents = g_malloc(FLASH_SIZE); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 34 | memset(dev->flash_contents, 0xff, FLASH_SIZE); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 35 | if (filename) { |
| 36 | /* Load flash image skipping the first block */ |
| 37 | ret = load_image(filename, dev->flash_contents + 528 * 32); |
| 38 | if (ret < 0) { |
| 39 | fprintf(stderr, "ret=%d\n", ret); |
| 40 | fprintf(stderr, "qemu: could not load flash image %s\n", |
| 41 | filename); |
| 42 | exit(1); |
| 43 | } else { |
| 44 | /* Build first block with number of blocks */ |
| 45 | blocks = (ret + 528 * 32 - 1) / (528 * 32); |
| 46 | dev->flash_contents[0] = blocks & 0xff; |
| 47 | dev->flash_contents[1] = (blocks >> 8) & 0xff; |
| 48 | dev->flash_contents[2] = (blocks >> 16) & 0xff; |
| 49 | dev->flash_contents[3] = (blocks >> 24) & 0xff; |
| 50 | fprintf(stderr, "loaded %d bytes for %s into flash\n", ret, |
| 51 | filename); |
| 52 | } |
| 53 | } |
| 54 | } |
| 55 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 56 | static void handle_command(tc58128_dev * dev, uint8_t command) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 57 | { |
| 58 | switch (command) { |
| 59 | case 0xff: |
| 60 | fprintf(stderr, "reset flash device\n"); |
| 61 | dev->state = WAIT; |
| 62 | break; |
| 63 | case 0x00: |
| 64 | fprintf(stderr, "read mode 1\n"); |
| 65 | dev->state = READ1; |
| 66 | dev->address_cycle = 0; |
| 67 | break; |
| 68 | case 0x01: |
| 69 | fprintf(stderr, "read mode 2\n"); |
| 70 | dev->state = READ2; |
| 71 | dev->address_cycle = 0; |
| 72 | break; |
| 73 | case 0x50: |
| 74 | fprintf(stderr, "read mode 3\n"); |
| 75 | dev->state = READ3; |
| 76 | dev->address_cycle = 0; |
| 77 | break; |
| 78 | default: |
| 79 | fprintf(stderr, "unknown flash command 0x%02x\n", command); |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 80 | abort(); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 81 | } |
| 82 | } |
| 83 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 84 | static void handle_address(tc58128_dev * dev, uint8_t data) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 85 | { |
| 86 | switch (dev->state) { |
| 87 | case READ1: |
| 88 | case READ2: |
| 89 | case READ3: |
| 90 | switch (dev->address_cycle) { |
| 91 | case 0: |
| 92 | dev->address = data; |
| 93 | if (dev->state == READ2) |
| 94 | dev->address |= 0x100; |
| 95 | else if (dev->state == READ3) |
| 96 | dev->address |= 0x200; |
| 97 | break; |
| 98 | case 1: |
| 99 | dev->address += data * 528 * 0x100; |
| 100 | break; |
| 101 | case 2: |
| 102 | dev->address += data * 528; |
| 103 | fprintf(stderr, "address pointer in flash: 0x%08x\n", |
| 104 | dev->address); |
| 105 | break; |
| 106 | default: |
| 107 | /* Invalid data */ |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 108 | abort(); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 109 | } |
| 110 | dev->address_cycle++; |
| 111 | break; |
| 112 | default: |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 113 | abort(); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 114 | } |
| 115 | } |
| 116 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 117 | static uint8_t handle_read(tc58128_dev * dev) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 118 | { |
| 119 | #if 0 |
| 120 | if (dev->address % 0x100000 == 0) |
| 121 | fprintf(stderr, "reading flash at address 0x%08x\n", dev->address); |
| 122 | #endif |
| 123 | return dev->flash_contents[dev->address++]; |
| 124 | } |
| 125 | |
| 126 | /* We never mark the device as busy, so interrupts cannot be triggered |
| 127 | XXXXX */ |
| 128 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 129 | static int tc58128_cb(uint16_t porta, uint16_t portb, |
| 130 | uint16_t * periph_pdtra, uint16_t * periph_portadir, |
| 131 | uint16_t * periph_pdtrb, uint16_t * periph_portbdir) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 132 | { |
| 133 | int dev; |
| 134 | |
| 135 | if ((porta & CE1) == 0) |
| 136 | dev = 0; |
| 137 | else if ((porta & CE2) == 0) |
| 138 | dev = 1; |
| 139 | else |
| 140 | return 0; /* No device selected */ |
| 141 | |
| 142 | if ((porta & RE) && (porta & WE)) { |
| 143 | /* Nothing to do, assert ready and return to input state */ |
| 144 | *periph_portadir &= 0xff00; |
| 145 | *periph_portadir |= RDY(dev); |
| 146 | *periph_pdtra |= RDY(dev); |
| 147 | return 1; |
| 148 | } |
| 149 | |
| 150 | if (porta & CLE) { |
| 151 | /* Command */ |
| 152 | assert((porta & WE) == 0); |
| 153 | handle_command(&tc58128_devs[dev], porta & 0x00ff); |
| 154 | } else if (porta & ALE) { |
| 155 | assert((porta & WE) == 0); |
| 156 | handle_address(&tc58128_devs[dev], porta & 0x00ff); |
| 157 | } else if ((porta & RE) == 0) { |
| 158 | *periph_portadir |= 0x00ff; |
| 159 | *periph_pdtra &= 0xff00; |
| 160 | *periph_pdtra |= handle_read(&tc58128_devs[dev]); |
| 161 | } else { |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 162 | abort(); |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 163 | } |
| 164 | return 1; |
| 165 | } |
| 166 | |
| 167 | static sh7750_io_device tc58128 = { |
| 168 | RE | WE, /* Port A triggers */ |
| 169 | 0, /* Port B triggers */ |
| 170 | tc58128_cb /* Callback */ |
| 171 | }; |
| 172 | |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 173 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) |
bellard | 27c7ca7 | 2006-04-27 21:32:09 +0000 | [diff] [blame] | 174 | { |
| 175 | init_dev(&tc58128_devs[0], zone1); |
| 176 | init_dev(&tc58128_devs[1], zone2); |
| 177 | return sh7750_register_io_device(s, &tc58128); |
| 178 | } |