blob: 88227e343e25f71894fef2b6e8c347fbc8e26812 [file] [log] [blame]
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
Peter Maydellb6a0aa02016-01-26 18:17:03 +000023#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010024#include "qapi/error.h"
Markus Armbruster15280c32018-02-01 12:18:36 +010025#include "qapi/qmp/qnum.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030026#include "acpi-build.h"
Gerd Hoffmanneb66ffa2020-05-20 15:19:47 +020027#include "acpi-common.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030028#include "qemu/bitmap.h"
Paolo Bonzini07fb6172014-07-28 17:34:15 +020029#include "qemu/error-report.h"
Markus Armbruster674b0a52022-12-22 11:03:24 +010030#include "hw/pci/pci_bridge.h"
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +010031#include "hw/cxl/cxl.h"
Markus Armbruster2e5b09f2019-07-09 17:20:52 +020032#include "hw/core/cpu.h"
Thomas Huthfcf5ef22016-10-11 08:56:52 +020033#include "target/i386/cpu.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030034#include "hw/timer/hpet.h"
Shannon Zhao395e5fb2015-04-03 18:03:33 +080035#include "hw/acpi/acpi-defs.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030036#include "hw/acpi/acpi.h"
Igor Mammedov679dd1a2016-06-15 11:25:23 +020037#include "hw/acpi/cpu.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030038#include "hw/nvram/fw_cfg.h"
Michael S. Tsirkin0058ae12015-01-19 23:58:55 +020039#include "hw/acpi/bios-linker-loader.h"
Igor Mammedov5876d9b2022-06-08 09:53:21 -040040#include "hw/acpi/acpi_aml_interface.h"
Liav Albani5334bf52022-03-04 21:10:30 +053041#include "hw/input/i8042.h"
Igor Mammedovbef34922014-06-02 15:25:26 +020042#include "hw/acpi/memory_hotplug.h"
Stefan Berger711b20b2014-08-11 16:33:36 -040043#include "sysemu/tpm.h"
44#include "hw/acpi/tpm.h"
Ben Warrend03637b2017-02-16 15:15:36 -080045#include "hw/acpi/vmgenid.h"
Eric DeVolder8486f122022-01-28 15:38:06 -050046#include "hw/acpi/erst.h"
Mark Cave-Ayland2bfd0842022-05-28 10:02:11 +010047#include "hw/acpi/piix4.h"
Stefan Berger5cb18b32015-05-26 16:51:07 -040048#include "sysemu/tpm_backend.h"
Philippe Mathieu-Daudébcdb9062019-10-04 01:03:53 +020049#include "hw/rtc/mc146818rtc_regs.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020050#include "migration/vmstate.h"
David Hildenbrand2cc0e2e2018-04-23 18:51:16 +020051#include "hw/mem/memory-device.h"
Philippe Mathieu-Daudé4b997692020-02-28 12:46:47 +010052#include "hw/mem/nvdimm.h"
Igor Mammedov1f3aba32016-06-16 14:23:48 +020053#include "sysemu/numa.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020054#include "sysemu/reset.h"
Jon Doron6775d152020-04-24 15:34:43 +030055#include "hw/hyperv/vmbus-bridge.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030056
57/* Supported chipsets: */
Bernhard Beschow1a6981b2023-02-13 18:30:33 +010058#include "hw/southbridge/ich9.h"
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +030059#include "hw/acpi/pcihp.h"
Paolo Bonzini89a289c2019-12-12 14:14:40 +010060#include "hw/i386/fw_cfg.h"
Bernhard Beschow71671812023-02-13 18:30:32 +010061#include "hw/i386/pc.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030062#include "hw/pci/pci_bus.h"
Bernhard Beschowb496a172022-10-28 12:34:19 +020063#include "hw/pci-host/i440fx.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030064#include "hw/pci-host/q35.h"
Peter Xu1cf5fd52016-07-14 13:56:12 +080065#include "hw/i386/x86-iommu.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030066
Igor Mammedov19934e02015-01-30 13:29:36 +000067#include "hw/acpi/aml-build.h"
Wei Yang82f76c62019-06-10 09:18:30 +080068#include "hw/acpi/utils.h"
Wei Yang48cefd92019-04-19 08:30:51 +080069#include "hw/acpi/pci.h"
Ben Widawsky2a3282c2022-04-29 15:40:49 +010070#include "hw/acpi/cxl.h"
Igor Mammedov19934e02015-01-30 13:29:36 +000071
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030072#include "qom/qom-qobject.h"
David Kiariefb9f5922016-09-20 18:42:34 +030073#include "hw/i386/amd_iommu.h"
74#include "hw/i386/intel_iommu.h"
Jean-Philippe Brucker36efa252021-10-26 19:20:23 +010075#include "hw/virtio/virtio-iommu.h"
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030076
Liu Jingqie6f123c2019-12-13 09:19:25 +080077#include "hw/acpi/hmat.h"
Jean-Philippe Brucker36efa252021-10-26 19:20:23 +010078#include "hw/acpi/viot.h"
Corey Minyard86e91dd2016-06-10 04:15:42 -050079
Eric DeVolder8486f122022-01-28 15:38:06 -050080#include CONFIG_DEVICES
81
Paolo Bonzini07fb6172014-07-28 17:34:15 +020082/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
84 * a little bit, there should be plenty of free space since the DSDT
85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
86 */
Paolo Bonzini07fb6172014-07-28 17:34:15 +020087#define ACPI_BUILD_ALIGN_SIZE 0x1000
88
Michael S. Tsirkin868270f2014-07-28 23:07:11 +020089#define ACPI_BUILD_TABLE_SIZE 0x20000
Paolo Bonzini18045fb2014-07-28 17:34:16 +020090
Gonglei8b310fc2014-11-13 10:59:37 +080091/* #define DEBUG_ACPI_BUILD */
92#ifdef DEBUG_ACPI_BUILD
93#define ACPI_BUILD_DPRINTF(fmt, ...) \
94 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
95#else
96#define ACPI_BUILD_DPRINTF(fmt, ...)
97#endif
98
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +030099typedef struct AcpiPmInfo {
100 bool s3_disabled;
101 bool s4_disabled;
Igor Mammedov133a2da2014-07-28 17:34:18 +0200102 bool pcihp_bridge_en;
Igor Mammedov6d837f12020-09-23 05:46:46 -0400103 bool smi_on_cpuhp;
Igor Mammedov892aae72020-12-07 09:07:34 -0500104 bool smi_on_cpu_unplug;
Ani Sinhadf4008c2020-09-18 14:11:08 +0530105 bool pcihp_root_en;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300106 uint8_t s4_val;
Igor Mammedov937d1b52018-02-28 15:23:51 +0100107 AcpiFadtData fadt;
Igor Mammedovddf1ec22015-02-18 19:14:44 +0000108 uint16_t cpu_hp_io_base;
Igor Mammedov500b11e2015-02-18 19:14:50 +0000109 uint16_t pcihp_io_base;
110 uint16_t pcihp_io_len;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300111} AcpiPmInfo;
112
113typedef struct AcpiMiscInfo {
114 bool has_hpet;
Stefan Berger11fb99e2021-06-15 16:21:17 +0200115#ifdef CONFIG_TPM
Stefan Berger5cb18b32015-05-26 16:51:07 -0400116 TPMVersion tpm_version;
Stefan Berger11fb99e2021-06-15 16:21:17 +0200117#endif
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300118} AcpiMiscInfo;
119
Stefan Berger0fe24662019-01-15 02:27:51 +0400120typedef struct FwCfgTPMConfig {
121 uint32_t tpmppi_address;
122 uint8_t tpm_version;
123 uint8_t tpmppi_version;
124} QEMU_PACKED FwCfgTPMConfig;
125
Gerd Hoffmann4a441832019-06-07 09:34:29 +0200126static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
127
Kwangwoo Lee5c94b822020-04-21 13:59:29 +0100128const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
129 .space_id = AML_AS_SYSTEM_IO,
130 .address = NVDIMM_ACPI_IO_BASE,
131 .bit_width = NVDIMM_ACPI_IO_LEN << 3
132};
133
Like Xu0e11fc62019-05-19 04:54:25 +0800134static void init_common_fadt_data(MachineState *ms, Object *o,
135 AcpiFadtData *data)
Igor Mammedov937d1b52018-02-28 15:23:51 +0100136{
Isaku Yamahata33b44fd2021-02-17 21:51:13 -0800137 X86MachineState *x86ms = X86_MACHINE(ms);
138 /*
139 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
140 * behavior for compatibility irrelevant to smm_enabled, which doesn't
141 * comforms to ACPI spec.
142 */
143 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
144 true : x86_machine_is_smm_enabled(x86ms);
Igor Mammedov937d1b52018-02-28 15:23:51 +0100145 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
146 AmlAddressSpace as = AML_AS_SYSTEM_IO;
147 AcpiFadtData fadt = {
148 .rev = 3,
149 .flags =
150 (1 << ACPI_FADT_F_WBINVD) |
151 (1 << ACPI_FADT_F_PROC_C1) |
152 (1 << ACPI_FADT_F_SLP_BUTTON) |
153 (1 << ACPI_FADT_F_RTC_S4) |
154 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
155 /* APIC destination mode ("Flat Logical") has an upper limit of 8
156 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
157 * used
158 */
Like Xu0e11fc62019-05-19 04:54:25 +0800159 ((ms->smp.max_cpus > 8) ?
160 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
Igor Mammedov937d1b52018-02-28 15:23:51 +0100161 .int_model = 1 /* Multiple APIC */,
162 .rtc_century = RTC_CENTURY,
163 .plvl2_lat = 0xfff /* C2 state not supported */,
164 .plvl3_lat = 0xfff /* C3 state not supported */,
Isaku Yamahata33b44fd2021-02-17 21:51:13 -0800165 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
Igor Mammedov937d1b52018-02-28 15:23:51 +0100166 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
167 .acpi_enable_cmd =
Isaku Yamahata33b44fd2021-02-17 21:51:13 -0800168 smm_enabled ?
169 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
170 0,
Igor Mammedov937d1b52018-02-28 15:23:51 +0100171 .acpi_disable_cmd =
Isaku Yamahata33b44fd2021-02-17 21:51:13 -0800172 smm_enabled ?
173 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
174 0,
Igor Mammedov937d1b52018-02-28 15:23:51 +0100175 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
176 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
177 .address = io + 0x04 },
178 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
179 .gpe0_blk = { .space_id = as, .bit_width =
180 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
181 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
182 },
183 };
Liav Albani5334bf52022-03-04 21:10:30 +0530184
185 /*
186 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
187 * Flags, bit offset 1 - 8042.
188 */
189 fadt.iapc_boot_arch = iapc_boot_arch_8042();
190
Igor Mammedov937d1b52018-02-28 15:23:51 +0100191 *data = fadt;
192}
193
Like Xu0e11fc62019-05-19 04:54:25 +0800194static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300195{
Paolo Bonziniee3b34c2024-02-23 13:43:57 +0100196 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM, NULL);
197 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE, NULL);
Igor Mammedov697155c2018-02-28 15:23:47 +0100198 Object *obj = piix ? piix : lpc;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300199 QObject *o;
Daniel P. Berrange94aaca62015-07-31 11:14:35 +0100200 pm->cpu_hp_io_base = 0;
Igor Mammedov500b11e2015-02-18 19:14:50 +0000201 pm->pcihp_io_base = 0;
202 pm->pcihp_io_len = 0;
Igor Mammedov6d837f12020-09-23 05:46:46 -0400203 pm->smi_on_cpuhp = false;
Igor Mammedov892aae72020-12-07 09:07:34 -0500204 pm->smi_on_cpu_unplug = false;
Igor Mammedov937d1b52018-02-28 15:23:51 +0100205
Philippe Mathieu-Daudé6fa51712019-04-27 16:40:25 +0200206 assert(obj);
Like Xua0628592019-05-19 04:54:20 +0800207 init_common_fadt_data(machine, obj, &pm->fadt);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300208 if (piix) {
Igor Mammedov3a3fcc72017-07-24 15:50:20 +0200209 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
Igor Mammedov937d1b52018-02-28 15:23:51 +0100210 pm->fadt.rev = 1;
Igor Mammedovddf1ec22015-02-18 19:14:44 +0000211 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300212 }
213 if (lpc) {
Igor Mammedov6d837f12020-09-23 05:46:46 -0400214 uint64_t smi_features = object_property_get_uint(lpc,
215 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
Igor Mammedov937d1b52018-02-28 15:23:51 +0100216 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
217 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
218 pm->fadt.reset_reg = r;
219 pm->fadt.reset_val = 0xf;
220 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
Igor Mammedovddf1ec22015-02-18 19:14:44 +0000221 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
Igor Mammedov6d837f12020-09-23 05:46:46 -0400222 pm->smi_on_cpuhp =
223 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
Igor Mammedov892aae72020-12-07 09:07:34 -0500224 pm->smi_on_cpu_unplug =
225 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300226 }
Julia Suvorovacaf108b2021-07-13 02:42:00 +0200227 pm->pcihp_io_base =
228 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
229 pm->pcihp_io_len =
230 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300231
232 /* Fill in optional s3/s4 related properties */
233 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
234 if (o) {
Max Reitz7dc847e2018-02-24 16:40:29 +0100235 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300236 } else {
237 pm->s3_disabled = false;
238 }
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200239 qobject_unref(o);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300240 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
241 if (o) {
Max Reitz7dc847e2018-02-24 16:40:29 +0100242 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300243 } else {
244 pm->s4_disabled = false;
245 }
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200246 qobject_unref(o);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300247 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
248 if (o) {
Max Reitz7dc847e2018-02-24 16:40:29 +0100249 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300250 } else {
251 pm->s4_val = false;
252 }
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200253 qobject_unref(o);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300254
Igor Mammedov133a2da2014-07-28 17:34:18 +0200255 pm->pcihp_bridge_en =
Ani Sinhaaa294662021-08-16 14:02:14 +0530256 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
Igor Mammedov133a2da2014-07-28 17:34:18 +0200257 NULL);
Ani Sinhadf4008c2020-09-18 14:11:08 +0530258 pm->pcihp_root_en =
Ani Sinhaaa294662021-08-16 14:02:14 +0530259 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
Ani Sinhadf4008c2020-09-18 14:11:08 +0530260 NULL);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300261}
262
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300263static void acpi_get_misc_info(AcpiMiscInfo *info)
264{
265 info->has_hpet = hpet_find();
Stefan Berger11fb99e2021-06-15 16:21:17 +0200266#ifdef CONFIG_TPM
Marc-André Lureau3dfd5a22017-11-06 19:39:15 +0100267 info->tpm_version = tpm_get_version(tpm_find());
Stefan Berger11fb99e2021-06-15 16:21:17 +0200268#endif
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300269}
270
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +0300271/*
272 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
273 * On i386 arch we only have two pci hosts, so we can look only for them.
274 */
Julia Suvorovac0e427d2021-07-13 02:42:01 +0200275Object *acpi_get_i386_pci_host(void)
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +0300276{
277 PCIHostState *host;
278
Eduardo Habkostb914e742021-08-05 15:34:31 -0400279 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +0300280 if (!host) {
Eduardo Habkostb914e742021-08-05 15:34:31 -0400281 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +0300282 }
283
284 return OBJECT(host);
285}
286
Markus Armbruster01c97422016-06-15 19:56:31 +0200287static void acpi_get_pci_holes(Range *hole, Range *hole64)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300288{
289 Object *pci_host;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300290
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +0300291 pci_host = acpi_get_i386_pci_host();
Julia Suvorovac0e427d2021-07-13 02:42:01 +0200292
293 if (!pci_host) {
294 return;
295 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300296
Markus Armbrustera0efbf12016-07-01 13:47:47 +0200297 range_set_bounds1(hole,
Marc-André Lureau60555362017-06-07 20:36:21 +0400298 object_property_get_uint(pci_host,
299 PCI_HOST_PROP_PCI_HOLE_START,
300 NULL),
301 object_property_get_uint(pci_host,
302 PCI_HOST_PROP_PCI_HOLE_END,
303 NULL));
Markus Armbrustera0efbf12016-07-01 13:47:47 +0200304 range_set_bounds1(hole64,
Marc-André Lureau60555362017-06-07 20:36:21 +0400305 object_property_get_uint(pci_host,
306 PCI_HOST_PROP_PCI_HOLE64_START,
307 NULL),
308 object_property_get_uint(pci_host,
309 PCI_HOST_PROP_PCI_HOLE64_END,
310 NULL));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300311}
312
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300313static void acpi_align_size(GArray *blob, unsigned align)
314{
315 /* Align size to multiple of given size. This reduces the chance
316 * we need to change size in the future (breaking cross version migration).
317 */
Michael S. Tsirkin134d42d2013-11-26 00:00:39 +0200318 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300319}
320
Igor Mammedovcf684102021-09-24 08:28:00 -0400321/*
322 * ACPI spec 1.0b,
323 * 5.2.6 Firmware ACPI Control Structure
324 */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300325static void
Wei Yang009180b2019-01-30 11:02:07 +0800326build_facs(GArray *table_data)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300327{
Igor Mammedovcf684102021-09-24 08:28:00 -0400328 const char *sig = "FACS";
329 const uint8_t reserved[40] = {};
330
331 g_array_append_vals(table_data, sig, 4); /* Signature */
332 build_append_int_noprefix(table_data, 64, 4); /* Length */
333 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
334 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
335 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
336 build_append_int_noprefix(table_data, 0, 4); /* Flags */
337 g_array_append_vals(table_data, reserved, 40); /* Reserved */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300338}
339
Igor Mammedov5840a162022-07-01 09:35:07 -0400340Aml *aml_pci_device_dsm(void)
341{
342 Aml *method;
343
344 method = aml_method("_DSM", 4, AML_SERIALIZED);
345 {
346 Aml *params = aml_local(0);
347 Aml *pkg = aml_package(2);
Igor Mammedov44d975e2023-07-20 15:38:54 +0200348 aml_append(pkg, aml_int(0));
349 aml_append(pkg, aml_int(0));
Igor Mammedov5840a162022-07-01 09:35:07 -0400350 aml_append(method, aml_store(pkg, params));
351 aml_append(method,
Igor Mammedov44d975e2023-07-20 15:38:54 +0200352 aml_store(aml_name("BSEL"), aml_index(params, aml_int(0))));
353 aml_append(method,
354 aml_store(aml_name("ASUN"), aml_index(params, aml_int(1))));
355 aml_append(method,
Igor Mammedov5840a162022-07-01 09:35:07 -0400356 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
357 aml_arg(2), aml_arg(3), params))
358 );
359 }
360 return method;
361}
362
Igor Mammedov0a4584f2023-03-02 17:15:23 +0100363static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar)
364{
365 Aml *UUID, *ifctx1;
366 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
367
368 aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar));
369 /*
370 * PCI Firmware Specification 3.1
371 * 4.6. _DSM Definitions for PCI
372 */
373 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
374 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
375 {
376 /* call is for unsupported UUID, bail out */
377 aml_append(ifctx1, aml_return(retvar));
378 }
379 aml_append(ctx, ifctx1);
380
381 ifctx1 = aml_if(aml_lless(aml_arg(1), aml_int(2)));
382 {
383 /* call is for unsupported REV, bail out */
384 aml_append(ifctx1, aml_return(retvar));
385 }
386 aml_append(ctx, ifctx1);
387}
388
Igor Mammedovfe0d5f52023-03-02 17:15:26 +0100389static Aml *aml_pci_edsm(void)
390{
391 Aml *method, *ifctx;
392 Aml *zero = aml_int(0);
393 Aml *func = aml_arg(2);
394 Aml *ret = aml_local(0);
395 Aml *aidx = aml_local(1);
396 Aml *params = aml_arg(4);
397
398 method = aml_method("EDSM", 5, AML_SERIALIZED);
399
400 /* get supported functions */
401 ifctx = aml_if(aml_equal(func, zero));
402 {
403 /* 1: have supported functions */
404 /* 7: support for function 7 */
405 const uint8_t caps = 1 | BIT(7);
406 build_append_pci_dsm_func0_common(ifctx, ret);
407 aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero)));
408 aml_append(ifctx, aml_return(ret));
409 }
410 aml_append(method, ifctx);
411
412 /* handle specific functions requests */
413 /*
414 * PCI Firmware Specification 3.1
415 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
416 * Operating Systems
417 */
418 ifctx = aml_if(aml_equal(func, aml_int(7)));
419 {
420 Aml *pkg = aml_package(2);
421 aml_append(pkg, zero);
422 /* optional, if not impl. should return null string */
423 aml_append(pkg, aml_string("%s", ""));
424 aml_append(ifctx, aml_store(pkg, ret));
425
426 /*
427 * IASL is fine when initializing Package with computational data,
428 * however it makes guest unhappy /it fails to process such AML/.
429 * So use runtime assignment to set acpi-index after initializer
430 * to make OSPM happy.
431 */
432 aml_append(ifctx,
433 aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx));
434 aml_append(ifctx, aml_store(aidx, aml_index(ret, zero)));
435 aml_append(ifctx, aml_return(ret));
436 }
437 aml_append(method, ifctx);
438
439 return method;
440}
Igor Mammedov0a4584f2023-03-02 17:15:23 +0100441
Igor Mammedov7fb1d732023-03-02 17:15:30 +0100442static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev)
443{
444 Aml *method;
445
446 g_assert(pdev->acpi_index != 0);
447 method = aml_method("_DSM", 4, AML_SERIALIZED);
448 {
449 Aml *params = aml_local(0);
450 Aml *pkg = aml_package(1);
451 aml_append(pkg, aml_int(pdev->acpi_index));
452 aml_append(method, aml_store(pkg, params));
453 aml_append(method,
454 aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1),
455 aml_arg(2), aml_arg(3), params))
456 );
457 }
458 return method;
459}
460
Igor Mammedov62b52c22015-02-20 18:22:18 +0000461static void build_append_pcihp_notify_entry(Aml *method, int slot)
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300462{
Igor Mammedov62b52c22015-02-20 18:22:18 +0000463 Aml *if_ctx;
464 int32_t devfn = PCI_DEVFN(slot, 0);
Igor Mammedovb23046a2015-02-20 18:22:16 +0000465
Igor Mammedov55304272015-12-10 00:41:17 +0100466 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
Igor Mammedov62b52c22015-02-20 18:22:18 +0000467 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
468 aml_append(method, if_ctx);
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300469}
470
Igor Mammedov6fe55182023-01-12 15:03:05 +0100471static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus)
Igor Mammedova06c15a2023-01-12 15:03:03 +0100472{
473 const PCIDevice *pdev = bus->devices[devfn];
474
Igor Mammedov6fe55182023-01-12 15:03:05 +0100475 if (PCI_FUNC(devfn)) {
476 if (IS_PCI_BRIDGE(pdev)) {
477 /*
478 * Ignore only hotplugged PCI bridges on !0 functions, but
479 * allow describing cold plugged bridges on all functions
480 */
481 if (DEVICE(pdev)->hotplugged) {
Igor Mammedova06c15a2023-01-12 15:03:03 +0100482 return true;
483 }
484 }
Igor Mammedov6fe55182023-01-12 15:03:05 +0100485 }
486 return false;
487}
488
489static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus)
490{
Igor Mammedov64a55102023-01-12 15:03:08 +0100491 PCIDevice *pdev = bus->devices[devfn];
492 if (pdev) {
493 return is_devfn_ignored_generic(devfn, bus) ||
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100494 !DEVICE_GET_CLASS(pdev)->hotpluggable ||
Igor Mammedov64a55102023-01-12 15:03:08 +0100495 /* Cold plugged bridges aren't themselves hot-pluggable */
496 (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged);
Igor Mammedova06c15a2023-01-12 15:03:03 +0100497 } else { /* non populated slots */
Igor Mammedov6fe55182023-01-12 15:03:05 +0100498 /*
Igor Mammedova06c15a2023-01-12 15:03:03 +0100499 * hotplug is supported only for non-multifunction device
500 * so generate device description only for function 0
501 */
Igor Mammedov6fe55182023-01-12 15:03:05 +0100502 if (PCI_FUNC(devfn) ||
Igor Mammedova06c15a2023-01-12 15:03:03 +0100503 (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) {
504 return true;
505 }
506 }
507 return false;
508}
509
Igor Mammedov02c10612023-03-02 17:15:41 +0100510void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus)
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300511{
Igor Mammedovd7346e62021-07-23 05:04:24 -0400512 int devfn;
Igor Mammedov6fe55182023-01-12 15:03:05 +0100513 Aml *dev, *notify_method = NULL, *method;
Igor Mammedov62dd55f2023-03-02 17:15:40 +0100514 QObject *bsel = object_property_get_qobject(OBJECT(bus),
515 ACPI_PCIHP_PROP_BSEL, NULL);
Igor Mammedov6fe55182023-01-12 15:03:05 +0100516 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
Igor Mammedov62dd55f2023-03-02 17:15:40 +0100517 qobject_unref(bsel);
Igor Mammedov133a2da2014-07-28 17:34:18 +0200518
Igor Mammedov6fe55182023-01-12 15:03:05 +0100519 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
520 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300521
Igor Mammedovd7346e62021-07-23 05:04:24 -0400522 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
Igor Mammedovd7346e62021-07-23 05:04:24 -0400523 int slot = PCI_SLOT(devfn);
Igor Mammedov6fe55182023-01-12 15:03:05 +0100524 int adr = slot << 16 | PCI_FUNC(devfn);
Igor Mammedova06c15a2023-01-12 15:03:03 +0100525
Igor Mammedov6fe55182023-01-12 15:03:05 +0100526 if (is_devfn_ignored_hotplug(devfn, bus)) {
Igor Mammedova06c15a2023-01-12 15:03:03 +0100527 continue;
528 }
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300529
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100530 if (bus->devices[devfn]) {
Igor Mammedov6fe55182023-01-12 15:03:05 +0100531 dev = aml_scope("S%.02X", devfn);
532 } else {
533 dev = aml_device("S%.02X", devfn);
534 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
Igor Mammedovd7346e62021-07-23 05:04:24 -0400535 }
536
Igor Mammedov6fe55182023-01-12 15:03:05 +0100537 /*
538 * Can't declare _SUN here for every device as it changes 'slot'
539 * enumeration order in linux kernel, so use another variable for it
540 */
541 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
542 aml_append(dev, aml_pci_device_dsm());
Igor Mammedov62b52c22015-02-20 18:22:18 +0000543
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100544 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
545 /* add _EJ0 to make slot hotpluggable */
546 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
547 aml_append(method,
548 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
549 );
550 aml_append(dev, method);
Igor Mammedov3216ab22022-07-01 09:35:15 -0400551
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100552 build_append_pcihp_notify_entry(notify_method, slot);
Igor Mammedov3216ab22022-07-01 09:35:15 -0400553
Igor Mammedovd7346e62021-07-23 05:04:24 -0400554 /* device descriptor has been composed, add it into parent context */
Igor Mammedov62b52c22015-02-20 18:22:18 +0000555 aml_append(parent_scope, dev);
Michael S. Tsirkin8dcf5252014-02-04 17:43:47 +0200556 }
Igor Mammedov6fe55182023-01-12 15:03:05 +0100557 aml_append(parent_scope, notify_method);
558}
559
560void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus)
561{
Igor Mammedov6fe55182023-01-12 15:03:05 +0100562 int devfn;
563 Aml *dev;
564
Igor Mammedov6fe55182023-01-12 15:03:05 +0100565 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
566 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
567 int adr = PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn);
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100568 PCIDevice *pdev = bus->devices[devfn];
Igor Mammedov6fe55182023-01-12 15:03:05 +0100569
Igor Mammedov17f4ced2023-01-12 15:03:11 +0100570 if (!pdev || is_devfn_ignored_generic(devfn, bus)) {
Igor Mammedov6fe55182023-01-12 15:03:05 +0100571 continue;
572 }
573
574 /* start to compose PCI device descriptor */
575 dev = aml_device("S%.02X", devfn);
576 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
577
578 call_dev_aml_func(DEVICE(bus->devices[devfn]), dev);
Igor Mammedov7fb1d732023-03-02 17:15:30 +0100579 /* add _DSM if device has acpi-index set */
Igor Mammedov419233b2023-03-02 17:15:39 +0100580 if (pdev->acpi_index &&
Igor Mammedov7fb1d732023-03-02 17:15:30 +0100581 !object_property_get_bool(OBJECT(pdev), "hotpluggable",
582 &error_abort)) {
583 aml_append(dev, aml_pci_static_endpoint_dsm(pdev));
584 }
Igor Mammedov6fe55182023-01-12 15:03:05 +0100585
586 /* device descriptor has been composed, add it into parent context */
587 aml_append(parent_scope, dev);
588 }
Igor Mammedovddab4d32023-01-12 15:02:53 +0100589}
590
Igor Mammedov219e6382023-01-12 15:02:54 +0100591static bool build_append_notfication_callback(Aml *parent_scope,
Igor Mammedovddab4d32023-01-12 15:02:53 +0100592 const PCIBus *bus)
593{
594 Aml *method;
595 PCIBus *sec;
596 QObject *bsel;
Igor Mammedov219e6382023-01-12 15:02:54 +0100597 int nr_notifiers = 0;
Igor Mammedov11215a32023-03-02 17:15:16 +0100598 GQueue *pcnt_bus_list = g_queue_new();
Igor Mammedovddab4d32023-01-12 15:02:53 +0100599
600 QLIST_FOREACH(sec, &bus->child, sibling) {
601 Aml *br_scope = aml_scope("S%.02X", sec->parent_dev->devfn);
Igor Mammedov11215a32023-03-02 17:15:16 +0100602 if (pci_bus_is_root(sec)) {
Igor Mammedovddab4d32023-01-12 15:02:53 +0100603 continue;
604 }
Igor Mammedov219e6382023-01-12 15:02:54 +0100605 nr_notifiers = nr_notifiers +
606 build_append_notfication_callback(br_scope, sec);
Igor Mammedov11215a32023-03-02 17:15:16 +0100607 /*
608 * add new child scope to parent
609 * and keep track of bus that have PCNT,
610 * bus list is used later to call children PCNTs from this level PCNT
611 */
612 if (nr_notifiers) {
613 g_queue_push_tail(pcnt_bus_list, sec);
614 aml_append(parent_scope, br_scope);
615 }
Igor Mammedovddab4d32023-01-12 15:02:53 +0100616 }
617
Igor Mammedov19f50522023-01-12 15:02:50 +0100618 /*
619 * Append PCNT method to notify about events on local and child buses.
Igor Mammedovddab4d32023-01-12 15:02:53 +0100620 * ps: hostbridge might not have hotplug (bsel) enabled but might have
621 * child bridges that do have bsel.
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300622 */
Igor Mammedov19f50522023-01-12 15:02:50 +0100623 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
Marc-André Lureau01b2ffc2017-06-07 20:35:58 +0400624
Igor Mammedov19f50522023-01-12 15:02:50 +0100625 /* If bus supports hotplug select it and notify about local events */
Igor Mammedovddab4d32023-01-12 15:02:53 +0100626 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
Igor Mammedov19f50522023-01-12 15:02:50 +0100627 if (bsel) {
628 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
Michael S. Tsirkin99fd4372013-10-14 18:01:29 +0300629
Igor Mammedov19f50522023-01-12 15:02:50 +0100630 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
631 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
632 aml_int(1))); /* Device Check */
633 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
634 aml_int(3))); /* Eject Request */
Igor Mammedov219e6382023-01-12 15:02:54 +0100635 nr_notifiers++;
Ani Sinhadf4008c2020-09-18 14:11:08 +0530636 }
Igor Mammedov19f50522023-01-12 15:02:50 +0100637
638 /* Notify about child bus events in any case */
Igor Mammedov11215a32023-03-02 17:15:16 +0100639 while ((sec = g_queue_pop_head(pcnt_bus_list))) {
Igor Mammedov19f50522023-01-12 15:02:50 +0100640 aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn));
641 }
642
643 aml_append(parent_scope, method);
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +0200644 qobject_unref(bsel);
Igor Mammedov11215a32023-03-02 17:15:16 +0100645 g_queue_free(pcnt_bus_list);
Igor Mammedov219e6382023-01-12 15:02:54 +0100646 return !!nr_notifiers;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +0300647}
648
Igor Mammedov5840a162022-07-01 09:35:07 -0400649static Aml *aml_pci_pdsm(void)
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400650{
Igor Mammedov0a4584f2023-03-02 17:15:23 +0100651 Aml *method, *ifctx, *ifctx1;
Igor Mammedova12cf692022-07-01 09:35:03 -0400652 Aml *ret = aml_local(0);
653 Aml *caps = aml_local(1);
654 Aml *acpi_index = aml_local(2);
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400655 Aml *zero = aml_int(0);
Igor Mammedova12cf692022-07-01 09:35:03 -0400656 Aml *one = aml_int(1);
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400657 Aml *func = aml_arg(2);
Igor Mammedov467d0992022-07-01 09:35:04 -0400658 Aml *params = aml_arg(4);
659 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
660 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400661
Igor Mammedov467d0992022-07-01 09:35:04 -0400662 method = aml_method("PDSM", 5, AML_SERIALIZED);
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400663
Igor Mammedova12cf692022-07-01 09:35:03 -0400664 /* get supported functions */
665 ifctx = aml_if(aml_equal(func, zero));
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400666 {
Igor Mammedov0a4584f2023-03-02 17:15:23 +0100667 build_append_pci_dsm_func0_common(ifctx, ret);
668
Igor Mammedova12cf692022-07-01 09:35:03 -0400669 aml_append(ifctx, aml_store(zero, caps));
Igor Mammedova12cf692022-07-01 09:35:03 -0400670 aml_append(ifctx,
671 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
672 /*
673 * advertise function 7 if device has acpi-index
674 * acpi_index values:
675 * 0: not present (default value)
676 * FFFFFFFF: not supported (old QEMU without PIDX reg)
677 * other: device's acpi-index
678 */
679 ifctx1 = aml_if(aml_lnot(
680 aml_or(aml_equal(acpi_index, zero),
681 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
682 ));
683 {
684 /* have supported functions */
685 aml_append(ifctx1, aml_or(caps, one, caps));
686 /* support for function 7 */
687 aml_append(ifctx1,
688 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
689 }
690 aml_append(ifctx, ifctx1);
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400691
Igor Mammedova12cf692022-07-01 09:35:03 -0400692 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
693 aml_append(ifctx, aml_return(ret));
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400694 }
695 aml_append(method, ifctx);
Igor Mammedova12cf692022-07-01 09:35:03 -0400696
697 /* handle specific functions requests */
698 /*
699 * PCI Firmware Specification 3.1
700 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
701 * Operating Systems
702 */
703 ifctx = aml_if(aml_equal(func, aml_int(7)));
704 {
705 Aml *pkg = aml_package(2);
706
707 aml_append(pkg, zero);
708 /*
709 * optional, if not impl. should return null string
710 */
711 aml_append(pkg, aml_string("%s", ""));
712 aml_append(ifctx, aml_store(pkg, ret));
713
714 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
715 /*
716 * update acpi-index to actual value
717 */
718 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
Igor Mammedov467d0992022-07-01 09:35:04 -0400719 aml_append(ifctx, aml_return(ret));
Igor Mammedova12cf692022-07-01 09:35:03 -0400720 }
721
722 aml_append(method, ifctx);
Igor Mammedovb7f23f62021-03-15 14:01:01 -0400723 return method;
724}
725
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300726/*
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000727 * build_prt - Define interrupt routing rules
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300728 *
729 * Returns an array of 128 routes, one for each device,
730 * based on device location.
Michael Tokarevbad5cfc2023-07-14 14:16:12 +0300731 * The main goal is to equally distribute the interrupts
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300732 * over the 4 existing ACPI links (works only for i440fx).
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000733 * The hash function is: (slot + pin) & 3 -> "LNK[D|A|B|C]".
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300734 *
735 */
Igor Mammedov196e2132015-12-28 18:02:42 +0100736static Aml *build_prt(bool is_pci0_prt)
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300737{
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000738 const int nroutes = 128;
739 Aml *rt_pkg, *method;
740 int pin;
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300741
Xiao Guangrong4dbfc882015-12-17 13:37:13 +0000742 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000743 rt_pkg = aml_varpackage(nroutes);
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300744
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000745 for (pin = 0; pin < nroutes; pin++) {
746 Aml *pkg = aml_package(4);
747 int slot = pin >> 2;
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300748
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000749 aml_append(pkg, aml_int((slot << 16) | 0xFFFF));
750 aml_append(pkg, aml_int(pin & 3));
751 /* device 1 is the power-management device, needs SCI */
752 if (is_pci0_prt && pin == 4) {
753 aml_append(pkg, aml_name("%s", "LNKS"));
Igor Mammedov196e2132015-12-28 18:02:42 +0100754 } else {
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000755 static const char link_name[][5] = {"LNKD", "LNKA", "LNKB", "LNKC"};
756 int hash = (slot + pin) & 3;
757 aml_append(pkg, aml_name("%s", link_name[hash]));
Igor Mammedov196e2132015-12-28 18:02:42 +0100758 }
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000759 aml_append(pkg, aml_int(0));
760 aml_append(rt_pkg, pkg);
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300761 }
Ricardo Ribalda99cb2c62024-08-14 11:56:10 +0000762
763 aml_append(method, aml_return(rt_pkg));
Marcel Apfelbaum0d8935e2015-06-02 14:23:02 +0300764
765 return method;
766}
767
Igor Mammedova57d7082015-12-28 18:02:29 +0100768static void build_hpet_aml(Aml *table)
769{
770 Aml *crs;
771 Aml *field;
772 Aml *method;
773 Aml *if_ctx;
774 Aml *scope = aml_scope("_SB");
775 Aml *dev = aml_device("HPET");
776 Aml *zero = aml_int(0);
777 Aml *id = aml_local(0);
778 Aml *period = aml_local(1);
779
780 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
781 aml_append(dev, aml_name_decl("_UID", zero));
782
783 aml_append(dev,
Xiao Guangrong3f3009c2016-03-01 18:56:05 +0800784 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
785 HPET_LEN));
Igor Mammedova57d7082015-12-28 18:02:29 +0100786 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
787 aml_append(field, aml_named_field("VEND", 32));
788 aml_append(field, aml_named_field("PRD", 32));
789 aml_append(dev, field);
790
791 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
792 aml_append(method, aml_store(aml_name("VEND"), id));
793 aml_append(method, aml_store(aml_name("PRD"), period));
794 aml_append(method, aml_shiftright(id, aml_int(16), id));
795 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
796 aml_equal(id, aml_int(0xffff))));
797 {
798 aml_append(if_ctx, aml_return(zero));
799 }
800 aml_append(method, if_ctx);
801
802 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
803 aml_lgreater(period, aml_int(100000000))));
804 {
805 aml_append(if_ctx, aml_return(zero));
806 }
807 aml_append(method, if_ctx);
808
809 aml_append(method, aml_return(aml_int(0x0F)));
810 aml_append(dev, method);
811
812 crs = aml_resource_template();
813 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
814 aml_append(dev, aml_name_decl("_CRS", crs));
815
816 aml_append(scope, dev);
817 aml_append(table, scope);
818}
819
Jon Doron6775d152020-04-24 15:34:43 +0300820static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
821{
822 Aml *dev;
823 Aml *method;
824 Aml *crs;
825
826 dev = aml_device("VMBS");
827 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
828 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
829 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
830 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
831
832 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
833 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
834 aml_name("STA")));
835 aml_append(dev, method);
836
837 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
838 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
839 aml_name("STA")));
840 aml_append(dev, method);
841
842 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
843 aml_append(method, aml_return(aml_name("STA")));
844 aml_append(dev, method);
845
846 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
847
848 crs = aml_resource_template();
Jon Doron8f06f222020-06-17 19:09:02 +0300849 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
Jon Doron6775d152020-04-24 15:34:43 +0300850 aml_append(dev, aml_name_decl("_CRS", crs));
851
852 return dev;
853}
854
Igor Mammedov3892a2b2015-12-28 18:02:30 +0100855static void build_dbg_aml(Aml *table)
856{
857 Aml *field;
858 Aml *method;
859 Aml *while_ctx;
860 Aml *scope = aml_scope("\\");
861 Aml *buf = aml_local(0);
862 Aml *len = aml_local(1);
863 Aml *idx = aml_local(2);
864
865 aml_append(scope,
Xiao Guangrong3f3009c2016-03-01 18:56:05 +0800866 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
Igor Mammedov3892a2b2015-12-28 18:02:30 +0100867 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
868 aml_append(field, aml_named_field("DBGB", 8));
869 aml_append(scope, field);
870
871 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
872
873 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
874 aml_append(method, aml_to_buffer(buf, buf));
875 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
876 aml_append(method, aml_store(aml_int(0), idx));
877
878 while_ctx = aml_while(aml_lless(idx, len));
879 aml_append(while_ctx,
880 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
881 aml_append(while_ctx, aml_increment(idx));
882 aml_append(method, while_ctx);
883
884 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
885 aml_append(scope, method);
886
887 aml_append(table, scope);
888}
889
Igor Mammedovc35b6e82015-12-28 18:02:39 +0100890static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
891{
892 Aml *dev;
893 Aml *crs;
894 Aml *method;
895 uint32_t irqs[] = {5, 10, 11};
896
897 dev = aml_device("%s", name);
898 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
899 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
900
901 crs = aml_resource_template();
902 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
903 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
904 aml_append(dev, aml_name_decl("_PRS", crs));
905
906 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
907 aml_append(method, aml_return(aml_call1("IQST", reg)));
908 aml_append(dev, method);
909
910 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
911 aml_append(method, aml_or(reg, aml_int(0x80), reg));
912 aml_append(dev, method);
913
914 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
915 aml_append(method, aml_return(aml_call1("IQCR", reg)));
916 aml_append(dev, method);
917
918 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
919 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
920 aml_append(method, aml_store(aml_name("PRRI"), reg));
921 aml_append(dev, method);
922
923 return dev;
924 }
925
Igor Mammedov80b32df2015-12-28 18:02:45 +0100926static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
927{
928 Aml *dev;
929 Aml *crs;
930 Aml *method;
931 uint32_t irqs;
932
933 dev = aml_device("%s", name);
934 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
935 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
936
937 crs = aml_resource_template();
938 irqs = gsi;
939 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
940 AML_SHARED, &irqs, 1));
941 aml_append(dev, aml_name_decl("_PRS", crs));
942
943 aml_append(dev, aml_name_decl("_CRS", crs));
944
Marcel Apfelbaumc82f5032016-03-07 21:14:37 +0200945 /*
946 * _DIS can be no-op because the interrupt cannot be disabled.
947 */
948 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
949 aml_append(dev, method);
950
Igor Mammedov80b32df2015-12-28 18:02:45 +0100951 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
952 aml_append(dev, method);
953
954 return dev;
955}
956
Igor Mammedov16682a92015-12-28 18:02:47 +0100957/* _CRS method - get current settings */
958static Aml *build_iqcr_method(bool is_piix4)
959{
960 Aml *if_ctx;
961 uint32_t irqs;
962 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
963 Aml *crs = aml_resource_template();
964
965 irqs = 0;
966 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
967 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
968 aml_append(method, aml_name_decl("PRR0", crs));
969
970 aml_append(method,
971 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
972
973 if (is_piix4) {
974 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
975 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
976 aml_append(method, if_ctx);
977 } else {
978 aml_append(method,
979 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
980 aml_name("PRRI")));
981 }
982
983 aml_append(method, aml_return(aml_name("PRR0")));
984 return method;
985}
986
Igor Mammedov78e1ad02015-12-28 18:02:48 +0100987/* _STA method - get status */
988static Aml *build_irq_status_method(void)
989{
990 Aml *if_ctx;
991 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
992
993 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
994 aml_append(if_ctx, aml_return(aml_int(0x09)));
995 aml_append(method, if_ctx);
996 aml_append(method, aml_return(aml_int(0x0B)));
997 return method;
998}
999
Igor Mammedove4db2792015-12-28 18:02:37 +01001000static void build_piix4_pci0_int(Aml *table)
1001{
Igor Mammedovc35b6e82015-12-28 18:02:39 +01001002 Aml *dev;
1003 Aml *crs;
Igor Mammedovc35b6e82015-12-28 18:02:39 +01001004 Aml *method;
1005 uint32_t irqs;
Igor Mammedove4db2792015-12-28 18:02:37 +01001006 Aml *sb_scope = aml_scope("_SB");
Igor Mammedov196e2132015-12-28 18:02:42 +01001007 Aml *pci0_scope = aml_scope("PCI0");
1008
1009 aml_append(pci0_scope, build_prt(true));
1010 aml_append(sb_scope, pci0_scope);
Igor Mammedove4db2792015-12-28 18:02:37 +01001011
Igor Mammedov78e1ad02015-12-28 18:02:48 +01001012 aml_append(sb_scope, build_irq_status_method());
Igor Mammedov16682a92015-12-28 18:02:47 +01001013 aml_append(sb_scope, build_iqcr_method(true));
Igor Mammedov100681c2015-12-28 18:02:40 +01001014
Igor Mammedovc35b6e82015-12-28 18:02:39 +01001015 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1016 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1017 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1018 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1019
1020 dev = aml_device("LNKS");
1021 {
1022 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1023 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1024
1025 crs = aml_resource_template();
1026 irqs = 9;
1027 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1028 AML_ACTIVE_HIGH, AML_SHARED,
1029 &irqs, 1));
1030 aml_append(dev, aml_name_decl("_PRS", crs));
1031
1032 /* The SCI cannot be disabled and is always attached to GSI 9,
1033 * so these are no-ops. We only need this link to override the
1034 * polarity to active high and match the content of the MADT.
1035 */
1036 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1037 aml_append(method, aml_return(aml_int(0x0b)));
1038 aml_append(dev, method);
1039
1040 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1041 aml_append(dev, method);
1042
1043 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1044 aml_append(method, aml_return(aml_name("_PRS")));
1045 aml_append(dev, method);
1046
1047 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1048 aml_append(dev, method);
1049 }
1050 aml_append(sb_scope, dev);
1051
Igor Mammedove4db2792015-12-28 18:02:37 +01001052 aml_append(table, sb_scope);
1053}
1054
Igor Mammedov22b5b8b2015-12-28 18:02:51 +01001055static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1056{
1057 int i;
1058 int head;
1059 Aml *pkg;
1060 char base = name[3] < 'E' ? 'A' : 'E';
1061 char *s = g_strdup(name);
1062 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1063
1064 assert(strlen(s) == 4);
1065
1066 head = name[3] - base;
1067 for (i = 0; i < 4; i++) {
1068 if (head + i > 3) {
1069 head = i * -1;
1070 }
1071 s[3] = base + head + i;
1072 pkg = aml_package(4);
1073 aml_append(pkg, a_nr);
1074 aml_append(pkg, aml_int(i));
1075 aml_append(pkg, aml_name("%s", s));
1076 aml_append(pkg, aml_int(0));
1077 aml_append(ctx, pkg);
1078 }
1079 g_free(s);
1080}
1081
1082static Aml *build_q35_routing_table(const char *str)
1083{
1084 int i;
1085 Aml *pkg;
1086 char *name = g_strdup_printf("%s ", str);
1087
1088 pkg = aml_package(128);
1089 for (i = 0; i < 0x18; i++) {
1090 name[3] = 'E' + (i & 0x3);
1091 append_q35_prt_entry(pkg, i, name);
1092 }
1093
1094 name[3] = 'E';
1095 append_q35_prt_entry(pkg, 0x18, name);
1096
1097 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1098 for (i = 0x0019; i < 0x1e; i++) {
1099 name[3] = 'A';
1100 append_q35_prt_entry(pkg, i, name);
1101 }
1102
1103 /* PCIe->PCI bridge. use PIRQ[E-H] */
1104 name[3] = 'E';
1105 append_q35_prt_entry(pkg, 0x1e, name);
1106 name[3] = 'A';
1107 append_q35_prt_entry(pkg, 0x1f, name);
1108
1109 g_free(name);
1110 return pkg;
1111}
1112
Igor Mammedov80b32df2015-12-28 18:02:45 +01001113static void build_q35_pci0_int(Aml *table)
1114{
Igor Mammedov0dafe3b2015-12-28 18:02:50 +01001115 Aml *method;
Igor Mammedov80b32df2015-12-28 18:02:45 +01001116 Aml *sb_scope = aml_scope("_SB");
Igor Mammedov0dafe3b2015-12-28 18:02:50 +01001117 Aml *pci0_scope = aml_scope("PCI0");
1118
Igor Mammedove9fce792015-12-28 18:02:53 +01001119 /* Zero => PIC mode, One => APIC Mode */
1120 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1121 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1122 {
1123 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1124 }
1125 aml_append(table, method);
1126
Igor Mammedov22b5b8b2015-12-28 18:02:51 +01001127 aml_append(pci0_scope,
Igor Mammedov65aef4d2015-12-28 18:02:52 +01001128 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1129 aml_append(pci0_scope,
Igor Mammedov22b5b8b2015-12-28 18:02:51 +01001130 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1131
Igor Mammedov0dafe3b2015-12-28 18:02:50 +01001132 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1133 {
1134 Aml *if_ctx;
1135 Aml *else_ctx;
1136
1137 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1138 section 6.2.8.1 */
1139 /* Note: we provide the same info as the PCI routing
1140 table of the Bochs BIOS */
1141 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1142 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1143 aml_append(method, if_ctx);
1144 else_ctx = aml_else();
1145 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1146 aml_append(method, else_ctx);
1147 }
1148 aml_append(pci0_scope, method);
1149 aml_append(sb_scope, pci0_scope);
Igor Mammedov80b32df2015-12-28 18:02:45 +01001150
Igor Mammedov78e1ad02015-12-28 18:02:48 +01001151 aml_append(sb_scope, build_irq_status_method());
Igor Mammedov16682a92015-12-28 18:02:47 +01001152 aml_append(sb_scope, build_iqcr_method(false));
1153
Igor Mammedov12e3b1f2015-12-28 18:02:46 +01001154 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1155 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1156 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1157 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1158 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1159 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1160 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1161 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1162
Marcel Apfelbaum6a991e02016-03-13 13:40:29 +02001163 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1164 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1165 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1166 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1167 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1168 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1169 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1170 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
Igor Mammedov80b32df2015-12-28 18:02:45 +01001171
1172 aml_append(table, sb_scope);
1173}
1174
Isaku Yamahatae3fb55f2021-02-17 21:51:15 -08001175static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1176{
1177 Aml *dev;
1178 Aml *resource_template;
1179
1180 /* DRAM controller */
1181 dev = aml_device("DRAC");
1182 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1183
1184 resource_template = aml_resource_template();
1185 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1186 aml_append(resource_template,
1187 aml_qword_memory(AML_POS_DECODE,
1188 AML_MIN_FIXED,
1189 AML_MAX_FIXED,
1190 AML_NON_CACHEABLE,
1191 AML_READ_WRITE,
1192 0x0000000000000000,
1193 mcfg->base,
1194 mcfg->base + mcfg->size - 1,
1195 0x0000000000000000,
1196 mcfg->size));
1197 } else {
1198 aml_append(resource_template,
1199 aml_dword_memory(AML_POS_DECODE,
1200 AML_MIN_FIXED,
1201 AML_MAX_FIXED,
1202 AML_NON_CACHEABLE,
1203 AML_READ_WRITE,
1204 0x0000000000000000,
1205 mcfg->base,
1206 mcfg->base + mcfg->size - 1,
1207 0x0000000000000000,
1208 mcfg->size));
1209 }
1210 aml_append(dev, aml_name_decl("_CRS", resource_template));
1211
1212 return dev;
1213}
1214
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001215static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
Igor Mammedovb616ec42015-12-28 18:02:43 +01001216{
1217 Aml *scope;
1218 Aml *field;
1219 Aml *method;
1220
1221 scope = aml_scope("_SB.PCI0");
1222
1223 aml_append(scope,
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001224 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
Igor Mammedovb616ec42015-12-28 18:02:43 +01001225 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1226 aml_append(field, aml_named_field("PCIU", 32));
1227 aml_append(field, aml_named_field("PCID", 32));
1228 aml_append(scope, field);
1229
1230 aml_append(scope,
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001231 aml_operation_region("SEJ", AML_SYSTEM_IO,
1232 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
Igor Mammedovb616ec42015-12-28 18:02:43 +01001233 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1234 aml_append(field, aml_named_field("B0EJ", 32));
1235 aml_append(scope, field);
1236
1237 aml_append(scope,
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001238 aml_operation_region("BNMR", AML_SYSTEM_IO,
1239 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
Igor Mammedovb616ec42015-12-28 18:02:43 +01001240 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1241 aml_append(field, aml_named_field("BNUM", 32));
Igor Mammedovb32bd762021-03-15 14:00:58 -04001242 aml_append(field, aml_named_field("PIDX", 32));
Igor Mammedovb616ec42015-12-28 18:02:43 +01001243 aml_append(scope, field);
1244
1245 aml_append(scope, aml_mutex("BLCK", 0));
1246
1247 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1248 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1249 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1250 aml_append(method,
1251 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1252 aml_append(method, aml_release(aml_name("BLCK")));
1253 aml_append(method, aml_return(aml_int(0)));
1254 aml_append(scope, method);
1255
Igor Mammedovb32bd762021-03-15 14:00:58 -04001256 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1257 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1258 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1259 aml_append(method,
1260 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1261 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1262 aml_append(method, aml_release(aml_name("BLCK")));
1263 aml_append(method, aml_return(aml_local(0)));
1264 aml_append(scope, method);
1265
Igor Mammedov5840a162022-07-01 09:35:07 -04001266 aml_append(scope, aml_pci_pdsm());
Igor Mammedovb7f23f62021-03-15 14:01:01 -04001267
Igor Mammedovb616ec42015-12-28 18:02:43 +01001268 aml_append(table, scope);
1269}
1270
Julia Suvorova211afe52021-11-12 06:08:56 -05001271static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
Igor Mammedovf97a88a2015-12-28 18:02:54 +01001272{
1273 Aml *if_ctx;
1274 Aml *if_ctx2;
1275 Aml *else_ctx;
1276 Aml *method;
1277 Aml *a_cwd1 = aml_name("CDW1");
Michael S. Tsirkinb3c782d2017-02-28 16:13:28 +02001278 Aml *a_ctrl = aml_local(0);
Igor Mammedovf97a88a2015-12-28 18:02:54 +01001279
1280 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1281 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1282
1283 if_ctx = aml_if(aml_equal(
1284 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1285 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1286 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1287
Igor Mammedovf97a88a2015-12-28 18:02:54 +01001288 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1289
1290 /*
1291 * Always allow native PME, AER (no dependencies)
Aleksandr Bezzubikova41c78c2017-07-29 02:37:49 +03001292 * Allow SHPC (PCI bridges can have SHPC controller)
Julia Suvorova211afe52021-11-12 06:08:56 -05001293 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
Igor Mammedovf97a88a2015-12-28 18:02:54 +01001294 */
Julia Suvorova211afe52021-11-12 06:08:56 -05001295 aml_append(if_ctx, aml_and(a_ctrl,
1296 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
Igor Mammedovf97a88a2015-12-28 18:02:54 +01001297
1298 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1299 /* Unknown revision */
1300 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1301 aml_append(if_ctx, if_ctx2);
1302
1303 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1304 /* Capabilities bits were masked */
1305 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1306 aml_append(if_ctx, if_ctx2);
1307
1308 /* Update DWORD3 in the buffer */
1309 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1310 aml_append(method, if_ctx);
1311
1312 else_ctx = aml_else();
1313 /* Unrecognized UUID */
1314 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1315 aml_append(method, else_ctx);
1316
1317 aml_append(method, aml_return(aml_arg(3)));
1318 return method;
1319}
Igor Mammedovb616ec42015-12-28 18:02:43 +01001320
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001321static void build_acpi0017(Aml *table)
1322{
1323 Aml *dev, *scope, *method;
1324
1325 scope = aml_scope("_SB");
1326 dev = aml_device("CXLM");
1327 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1328
1329 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
Jonathan Camerond9ae5802024-01-26 12:01:31 +00001330 aml_append(method, aml_return(aml_int(0x0B)));
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001331 aml_append(dev, method);
Dave Jiang6cdd46f2023-10-12 13:56:22 +01001332 build_cxl_dsm_method(dev);
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001333
1334 aml_append(scope, dev);
1335 aml_append(table, scope);
1336}
1337
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001338static void
Igor Mammedov0e9b9ed2016-05-19 15:19:25 +02001339build_dsdt(GArray *table_data, BIOSLinker *linker,
Igor Mammedovadcb89d2016-02-26 14:59:26 +01001340 AcpiPmInfo *pm, AcpiMiscInfo *misc,
Markus Armbruster01c97422016-06-15 19:56:31 +02001341 Range *pci_hole, Range *pci_hole64, MachineState *machine)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001342{
Paolo Bonziniee3b34c2024-02-23 13:43:57 +01001343 Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE,
1344 NULL);
1345 Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE, NULL);
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001346 CrsRangeEntry *entry;
1347 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001348 CrsRangeSet crs_range_set;
Eduardo Habkostfb306ff2015-12-11 16:42:26 -02001349 PCMachineState *pcms = PC_MACHINE(machine);
Igor Mammedov679dd1a2016-06-15 11:25:23 +02001350 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02001351 X86MachineState *x86ms = X86_MACHINE(machine);
Gerd Hoffmann4a441832019-06-07 09:34:29 +02001352 AcpiMcfgInfo mcfg;
Isaku Yamahatae3fb55f2021-02-17 21:51:15 -08001353 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
Igor Mammedovbef34922014-06-02 15:25:26 +02001354 uint32_t nr_mem = machine->ram_slots;
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001355 int root_bus_limit = 0xFF;
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001356 PCIBus *bus = NULL;
Stefan Berger11fb99e2021-06-15 16:21:17 +02001357#ifdef CONFIG_TPM
Stefan Bergerac6dd312019-01-15 02:27:52 +04001358 TPMIf *tpm = tpm_find();
Stefan Berger11fb99e2021-06-15 16:21:17 +02001359#endif
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001360 bool cxl_present = false;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001361 int i;
Jon Doron8f814ea2020-07-15 11:43:25 +03001362 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
Igor Mammedov5c142bc2021-09-24 08:27:40 -04001363 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1364 .oem_table_id = x86ms->oem_table_id };
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001365
Bernhard Beschowb496a172022-10-28 12:34:19 +02001366 assert(!!i440fx != !!q35);
Bernhard Beschowbbaa5c42022-10-28 12:34:18 +02001367
Igor Mammedov5c142bc2021-09-24 08:27:40 -04001368 acpi_table_begin(&table, table_data);
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001369 dsdt = init_aml_allocator();
Laszlo Ersek2fd71f12014-03-17 17:05:17 +01001370
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001371 build_dbg_aml(dsdt);
Bernhard Beschowb496a172022-10-28 12:34:19 +02001372 if (i440fx) {
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001373 sb_scope = aml_scope("_SB");
1374 dev = aml_device("PCI0");
1375 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
Vitaly Cheptsov0a343a52021-03-01 22:59:18 +03001376 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
Igor Mammedovfe0d5f52023-03-02 17:15:26 +01001377 aml_append(dev, aml_pci_edsm());
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001378 aml_append(sb_scope, dev);
1379 aml_append(dsdt, sb_scope);
1380
Ani Sinhadf4008c2020-09-18 14:11:08 +05301381 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001382 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
Ani Sinhadf4008c2020-09-18 14:11:08 +05301383 }
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001384 build_piix4_pci0_int(dsdt);
Bernhard Beschowb496a172022-10-28 12:34:19 +02001385 } else if (q35) {
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001386 sb_scope = aml_scope("_SB");
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001387 dev = aml_device("PCI0");
1388 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1389 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
Vitaly Cheptsov0a343a52021-03-01 22:59:18 +03001390 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
Julia Suvorova211afe52021-11-12 06:08:56 -05001391 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
Igor Mammedovfe0d5f52023-03-02 17:15:26 +01001392 aml_append(dev, aml_pci_edsm());
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001393 aml_append(sb_scope, dev);
Isaku Yamahatae3fb55f2021-02-17 21:51:15 -08001394 if (mcfg_valid) {
1395 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1396 }
Igor Mammedov998ba952020-09-23 05:46:47 -04001397
1398 if (pm->smi_on_cpuhp) {
1399 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1400 dev = aml_device("PCI0.SMI0");
1401 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1402 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1403 crs = aml_resource_template();
1404 aml_append(crs,
1405 aml_io(
1406 AML_DECODE16,
Bernhard Beschow5cdb6392023-09-08 10:42:32 +02001407 pm->fadt.smi_cmd,
1408 pm->fadt.smi_cmd,
Igor Mammedov998ba952020-09-23 05:46:47 -04001409 1,
1410 2)
1411 );
1412 aml_append(dev, aml_name_decl("_CRS", crs));
1413 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
Bernhard Beschow5cdb6392023-09-08 10:42:32 +02001414 aml_int(pm->fadt.smi_cmd), 2));
Igor Mammedov998ba952020-09-23 05:46:47 -04001415 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1416 AML_WRITE_AS_ZEROS);
1417 aml_append(field, aml_named_field("SMIC", 8));
1418 aml_append(field, aml_reserved_field(8));
1419 aml_append(dev, field);
1420 aml_append(sb_scope, dev);
1421 }
1422
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001423 aml_append(dsdt, sb_scope);
1424
Julia Suvorovacaf108b2021-07-13 02:42:00 +02001425 if (pm->pcihp_bridge_en) {
1426 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1427 }
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001428 build_q35_pci0_int(dsdt);
1429 }
1430
Igor Mammedove05acc32022-07-01 09:35:00 -04001431 if (misc->has_hpet) {
1432 build_hpet_aml(dsdt);
1433 }
1434
Jon Doron8f814ea2020-07-15 11:43:25 +03001435 if (vmbus_bridge) {
1436 sb_scope = aml_scope("_SB");
1437 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1438 aml_append(dsdt, sb_scope);
1439 }
1440
Igor Mammedovd12dbd42022-10-17 12:21:45 +02001441 scope = aml_scope("_GPE");
1442 {
1443 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1444 if (machine->nvdimms_state->is_enabled) {
1445 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1446 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1447 aml_int(0x80)));
1448 aml_append(scope, method);
1449 }
1450 }
1451 aml_append(dsdt, scope);
1452
Igor Mammedov679dd1a2016-06-15 11:25:23 +02001453 if (pcmc->legacy_cpu_hotplug) {
1454 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1455 } else {
1456 CPUHotplugFeatures opts = {
Igor Mammedov998ba952020-09-23 05:46:47 -04001457 .acpi_1_compatible = true, .has_legacy_cphp = true,
1458 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
Igor Mammedov69dea9d2020-12-07 09:07:36 -05001459 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
Igor Mammedov679dd1a2016-06-15 11:25:23 +02001460 };
Bernhard Beschow9a4fedc2023-09-08 10:42:28 +02001461 build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
Salil Mehtaefdb43b2024-07-16 12:15:00 +01001462 pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
1463 AML_SYSTEM_IO);
Igor Mammedov679dd1a2016-06-15 11:25:23 +02001464 }
Shameer Kolothum091c4662019-09-18 14:06:23 +01001465
1466 if (pcms->memhp_io_base && nr_mem) {
1467 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1468 "\\_GPE._E03", AML_SYSTEM_IO,
1469 pcms->memhp_io_base);
1470 }
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001471
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001472 crs_range_set_init(&crs_range_set);
Bernhard Beschowb54a9d42024-02-24 14:58:47 +01001473 bus = PC_MACHINE(machine)->pcibus;
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001474 if (bus) {
1475 QLIST_FOREACH(bus, &bus->child, sibling) {
1476 uint8_t bus_num = pci_bus_num(bus);
Marcel Apfelbaum0e79e512015-06-02 14:23:10 +03001477 uint8_t numa_node = pci_bus_numa_node(bus);
Jonathan Camerondc907b5c2024-09-16 18:10:13 +01001478 uint32_t uid;
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001479
1480 /* look only for expander root buses */
1481 if (!pci_bus_is_root(bus)) {
1482 continue;
1483 }
1484
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001485 if (bus_num < root_bus_limit) {
1486 root_bus_limit = bus_num - 1;
1487 }
1488
Jonathan Camerondc907b5c2024-09-16 18:10:13 +01001489 uid = object_property_get_uint(OBJECT(bus), "acpi_uid",
1490 &error_fatal);
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001491 scope = aml_scope("\\_SB");
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001492
1493 if (pci_bus_is_cxl(bus)) {
1494 dev = aml_device("CL%.02X", bus_num);
1495 } else {
1496 dev = aml_device("PC%.02X", bus_num);
1497 }
Jonathan Camerondc907b5c2024-09-16 18:10:13 +01001498 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001499 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001500 if (pci_bus_is_cxl(bus)) {
Ani Sinha7b393b72023-09-22 18:12:02 +05301501 struct Aml *aml_pkg = aml_package(2);
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001502
Ben Widawsky2a3282c2022-04-29 15:40:49 +01001503 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
Ani Sinha7b393b72023-09-22 18:12:02 +05301504 aml_append(aml_pkg, aml_eisaid("PNP0A08"));
1505 aml_append(aml_pkg, aml_eisaid("PNP0A03"));
1506 aml_append(dev, aml_name_decl("_CID", aml_pkg));
Ben Widawsky2a3282c2022-04-29 15:40:49 +01001507 build_cxl_osc_method(dev);
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001508 } else if (pci_bus_is_express(bus)) {
Evgeny Yakovlevee4b0c82019-07-19 11:54:29 +03001509 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1510 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
Julia Suvorova211afe52021-11-12 06:08:56 -05001511
1512 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1513 aml_append(dev, build_q35_osc_method(true));
Evgeny Yakovlevee4b0c82019-07-19 11:54:29 +03001514 } else {
1515 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
Marcel Apfelbaum077dd742017-02-28 16:13:29 +02001516 }
Marcel Apfelbaum0e79e512015-06-02 14:23:10 +03001517
1518 if (numa_node != NUMA_NODE_UNASSIGNED) {
1519 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1520 }
1521
Igor Mammedov196e2132015-12-28 18:02:42 +01001522 aml_append(dev, build_prt(false));
Jiahui Cene41ee852021-01-14 18:06:38 +08001523 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1524 0, 0, 0, 0);
Marcel Apfelbauma43c6e22015-06-02 14:23:03 +03001525 aml_append(dev, aml_name_decl("_CRS", crs));
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001526 aml_append(scope, dev);
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001527 aml_append(dsdt, scope);
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001528
1529 /* Handle the ranges for the PXB expanders */
1530 if (pci_bus_is_cxl(bus)) {
Jonathan Cameron1ebf9002022-06-08 15:54:39 +01001531 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001532 uint64_t base = mr->addr;
1533
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001534 cxl_present = true;
Ben Widawsky6e4e3ae2022-04-29 15:40:48 +01001535 crs_range_insert(crs_range_set.mem_ranges, base,
1536 base + memory_region_size(mr) - 1);
1537 }
Marcel Apfelbauma4894202015-06-02 14:23:01 +03001538 }
1539 }
1540
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01001541 if (cxl_present) {
1542 build_acpi0017(dsdt);
1543 }
1544
Gerd Hoffmann4a441832019-06-07 09:34:29 +02001545 /*
1546 * At this point crs_range_set has all the ranges used by pci
1547 * busses *other* than PCI0. These ranges will be excluded from
1548 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1549 * too.
1550 */
Isaku Yamahatae3fb55f2021-02-17 21:51:15 -08001551 if (mcfg_valid) {
Gerd Hoffmann4a441832019-06-07 09:34:29 +02001552 crs_range_insert(crs_range_set.mem_ranges,
1553 mcfg.base, mcfg.base + mcfg.size - 1);
1554 }
1555
Igor Mammedov500b11e2015-02-18 19:14:50 +00001556 scope = aml_scope("\\_SB.PCI0");
Igor Mammedov60efd422015-02-20 18:22:05 +00001557 /* build PCI0._CRS */
1558 crs = aml_resource_template();
1559 aml_append(crs,
Shannon Zhaoff80dc72015-05-29 11:28:54 +01001560 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001561 0x0000, 0x0, root_bus_limit,
1562 0x0000, root_bus_limit + 1));
Shannon Zhaoff80dc72015-05-29 11:28:54 +01001563 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
Igor Mammedov60efd422015-02-20 18:22:05 +00001564
1565 aml_append(crs,
Shannon Zhaoff80dc72015-05-29 11:28:54 +01001566 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1567 AML_POS_DECODE, AML_ENTIRE_RANGE,
Igor Mammedov60efd422015-02-20 18:22:05 +00001568 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001569
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001570 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1571 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1572 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001573 aml_append(crs,
1574 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1575 AML_POS_DECODE, AML_ENTIRE_RANGE,
1576 0x0000, entry->base, entry->limit,
1577 0x0000, entry->limit - entry->base + 1));
1578 }
1579
Igor Mammedov60efd422015-02-20 18:22:05 +00001580 aml_append(crs,
Shannon Zhaoff80dc72015-05-29 11:28:54 +01001581 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1582 AML_CACHEABLE, AML_READ_WRITE,
Igor Mammedov60efd422015-02-20 18:22:05 +00001583 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001584
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001585 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
Markus Armbrustera0efbf12016-07-01 13:47:47 +02001586 range_lob(pci_hole),
1587 range_upb(pci_hole));
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001588 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1589 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001590 aml_append(crs,
1591 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1592 AML_NON_CACHEABLE, AML_READ_WRITE,
1593 0, entry->base, entry->limit,
1594 0, entry->limit - entry->base + 1));
1595 }
1596
Markus Armbrustera0efbf12016-07-01 13:47:47 +02001597 if (!range_is_empty(pci_hole64)) {
Marcel Apfelbaum16de88a2016-07-17 19:53:13 +03001598 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1599 range_lob(pci_hole64),
1600 range_upb(pci_hole64));
1601 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1602 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1603 aml_append(crs,
1604 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1605 AML_MAX_FIXED,
1606 AML_CACHEABLE, AML_READ_WRITE,
1607 0, entry->base, entry->limit,
1608 0, entry->limit - entry->base + 1));
1609 }
Igor Mammedov60efd422015-02-20 18:22:05 +00001610 }
Igor Mammedov2b1c2e82016-04-08 13:23:13 +02001611
Stefan Berger11fb99e2021-06-15 16:21:17 +02001612#ifdef CONFIG_TPM
Eric Auger43bc7f82020-03-05 17:51:40 +01001613 if (TPM_IS_TIS_ISA(tpm_find())) {
Igor Mammedov2b1c2e82016-04-08 13:23:13 +02001614 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1615 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1616 }
Stefan Berger11fb99e2021-06-15 16:21:17 +02001617#endif
Igor Mammedov60efd422015-02-20 18:22:05 +00001618 aml_append(scope, aml_name_decl("_CRS", crs));
1619
Igor Mammedovd31c9092015-02-20 18:22:08 +00001620 /* reserve GPE0 block resources */
1621 dev = aml_device("GPE0");
1622 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1623 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1624 /* device present, functioning, decoding, not shown in UI */
1625 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1626 crs = aml_resource_template();
1627 aml_append(crs,
Igor Mammedov937d1b52018-02-28 15:23:51 +01001628 aml_io(
1629 AML_DECODE16,
1630 pm->fadt.gpe0_blk.address,
1631 pm->fadt.gpe0_blk.address,
1632 1,
1633 pm->fadt.gpe0_blk.bit_width / 8)
Igor Mammedovd31c9092015-02-20 18:22:08 +00001634 );
1635 aml_append(dev, aml_name_decl("_CRS", crs));
1636 aml_append(scope, dev);
1637
Marcel Apfelbaum2df5a7b2016-07-17 19:53:12 +03001638 crs_range_set_free(&crs_range_set);
Marcel Apfelbaumdcdca292015-06-02 14:23:04 +03001639
Igor Mammedov500b11e2015-02-18 19:14:50 +00001640 /* reserve PCIHP resources */
Ani Sinhadf4008c2020-09-18 14:11:08 +05301641 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
Igor Mammedov500b11e2015-02-18 19:14:50 +00001642 dev = aml_device("PHPR");
1643 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1644 aml_append(dev,
1645 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1646 /* device present, functioning, decoding, not shown in UI */
1647 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1648 crs = aml_resource_template();
1649 aml_append(crs,
Shannon Zhaoff80dc72015-05-29 11:28:54 +01001650 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
Igor Mammedov500b11e2015-02-18 19:14:50 +00001651 pm->pcihp_io_len)
1652 );
1653 aml_append(dev, aml_name_decl("_CRS", crs));
1654 aml_append(scope, dev);
1655 }
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001656 aml_append(dsdt, scope);
Igor Mammedov500b11e2015-02-18 19:14:50 +00001657
Igor Mammedovebc30282015-02-18 19:14:29 +00001658 /* create S3_ / S4_ / S5_ packages if necessary */
1659 scope = aml_scope("\\");
1660 if (!pm->s3_disabled) {
1661 pkg = aml_package(4);
1662 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1663 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1664 aml_append(pkg, aml_int(0)); /* reserved */
1665 aml_append(pkg, aml_int(0)); /* reserved */
1666 aml_append(scope, aml_name_decl("_S3", pkg));
1667 }
1668
1669 if (!pm->s4_disabled) {
1670 pkg = aml_package(4);
1671 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1672 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1673 aml_append(pkg, aml_int(pm->s4_val));
1674 aml_append(pkg, aml_int(0)); /* reserved */
1675 aml_append(pkg, aml_int(0)); /* reserved */
1676 aml_append(scope, aml_name_decl("_S4", pkg));
1677 }
1678
1679 pkg = aml_package(4);
1680 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1681 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1682 aml_append(pkg, aml_int(0)); /* reserved */
1683 aml_append(pkg, aml_int(0)); /* reserved */
1684 aml_append(scope, aml_name_decl("_S5", pkg));
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001685 aml_append(dsdt, scope);
Igor Mammedovebc30282015-02-18 19:14:29 +00001686
Gabriel L. Somloe2ec7562016-02-19 13:20:27 -05001687 /* create fw_cfg node, unconditionally */
1688 {
Gabriel L. Somloe2ec7562016-02-19 13:20:27 -05001689 scope = aml_scope("\\_SB.PCI0");
Gerd Hoffmann0575c2f2020-06-19 11:19:00 +02001690 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
Gabriel L. Somloe2ec7562016-02-19 13:20:27 -05001691 aml_append(dsdt, scope);
1692 }
1693
Gal Hammer7824df32015-04-21 11:26:12 +03001694 sb_scope = aml_scope("\\_SB");
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001695 {
Igor Mammedovd3ecb222022-06-08 09:53:37 -04001696 Object *pci_host = acpi_get_i386_pci_host();
Julia Suvorovac0e427d2021-07-13 02:42:01 +02001697
Igor Mammedov8b35ab22016-12-06 00:32:25 +01001698 if (pci_host) {
Ani Sinha7b393b72023-09-22 18:12:02 +05301699 PCIBus *pbus = PCI_HOST_BRIDGE(pci_host)->bus;
1700 Aml *ascope = aml_scope("PCI0");
Igor Mammedov8b35ab22016-12-06 00:32:25 +01001701 /* Scan all PCI buses. Generate tables to support hotplug. */
Ani Sinha7b393b72023-09-22 18:12:02 +05301702 build_append_pci_bus_devices(ascope, pbus);
1703 if (object_property_find(OBJECT(pbus), ACPI_PCIHP_PROP_BSEL)) {
1704 build_append_pcihp_slots(ascope, pbus);
Igor Mammedov02c10612023-03-02 17:15:41 +01001705 }
Ani Sinha7b393b72023-09-22 18:12:02 +05301706 aml_append(sb_scope, ascope);
Igor Mammedov8b35ab22016-12-06 00:32:25 +01001707 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001708 }
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001709
Stefan Berger11fb99e2021-06-15 16:21:17 +02001710#ifdef CONFIG_TPM
Stefan Bergerac6dd312019-01-15 02:27:52 +04001711 if (TPM_IS_CRB(tpm)) {
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001712 dev = aml_device("TPM");
1713 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
Stefan Berger59036462022-01-04 12:58:05 -05001714 aml_append(dev, aml_name_decl("_STR",
1715 aml_string("TPM 2.0 Device")));
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001716 crs = aml_resource_template();
1717 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1718 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1719 aml_append(dev, aml_name_decl("_CRS", crs));
1720
Gerd Hoffmann88b36482020-04-29 15:59:52 +02001721 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
Stefan Berger59036462022-01-04 12:58:05 -05001722 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001723
Stefan Bergerac6dd312019-01-15 02:27:52 +04001724 tpm_build_ppi_acpi(tpm, dev);
1725
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001726 aml_append(sb_scope, dev);
1727 }
Stefan Berger11fb99e2021-06-15 16:21:17 +02001728#endif
Marc-André Lureau4ab6cb42018-01-29 19:33:07 +01001729
Sean Christophersonc8a98992021-07-19 19:21:22 +08001730 if (pcms->sgx_epc.size != 0) {
1731 uint64_t epc_base = pcms->sgx_epc.base;
1732 uint64_t epc_size = pcms->sgx_epc.size;
1733
1734 dev = aml_device("EPC");
1735 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1736 aml_append(dev, aml_name_decl("_STR",
1737 aml_unicode("Enclave Page Cache 1.0")));
1738 crs = aml_resource_template();
1739 aml_append(crs,
1740 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1741 AML_MAX_FIXED, AML_NON_CACHEABLE,
1742 AML_READ_WRITE, 0, epc_base,
1743 epc_base + epc_size - 1, 0, epc_size));
1744 aml_append(dev, aml_name_decl("_CRS", crs));
1745
1746 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1747 aml_append(method, aml_return(aml_int(0x0f)));
1748 aml_append(dev, method);
1749
1750 aml_append(sb_scope, dev);
1751 }
Igor Mammedov8b35ab22016-12-06 00:32:25 +01001752 aml_append(dsdt, sb_scope);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001753
Igor Mammedovd12dbd42022-10-17 12:21:45 +02001754 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
Igor Mammedov219e6382023-01-12 15:02:54 +01001755 bool has_pcnt;
1756
Igor Mammedovddab4d32023-01-12 15:02:53 +01001757 Object *pci_host = acpi_get_i386_pci_host();
Ani Sinha7b393b72023-09-22 18:12:02 +05301758 PCIBus *b = PCI_HOST_BRIDGE(pci_host)->bus;
Igor Mammedovddab4d32023-01-12 15:02:53 +01001759
1760 scope = aml_scope("\\_SB.PCI0");
Ani Sinha7b393b72023-09-22 18:12:02 +05301761 has_pcnt = build_append_notfication_callback(scope, b);
Igor Mammedov219e6382023-01-12 15:02:54 +01001762 if (has_pcnt) {
1763 aml_append(dsdt, scope);
1764 }
Igor Mammedovddab4d32023-01-12 15:02:53 +01001765
Igor Mammedovd12dbd42022-10-17 12:21:45 +02001766 scope = aml_scope("_GPE");
1767 {
1768 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
Igor Mammedov219e6382023-01-12 15:02:54 +01001769 if (has_pcnt) {
1770 aml_append(method,
1771 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1772 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1773 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1774 }
Igor Mammedovd12dbd42022-10-17 12:21:45 +02001775 aml_append(scope, method);
1776 }
1777 aml_append(dsdt, scope);
1778 }
1779
Igor Mammedov011bb742015-02-18 19:14:16 +00001780 /* copy AML table into ACPI tables blob and patch header there */
Igor Mammedov41fa5c02016-01-22 15:36:06 +01001781 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
Igor Mammedov5c142bc2021-09-24 08:27:40 -04001782 acpi_table_end(linker, &table);
Igor Mammedov011bb742015-02-18 19:14:16 +00001783 free_aml_allocator();
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001784}
1785
Igor Mammedov43dde172021-09-24 08:27:41 -04001786/*
1787 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1788 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1789 */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001790static void
Marian Postevca602b4582021-01-19 02:32:13 +02001791build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1792 const char *oem_table_id)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001793{
Igor Mammedov43dde172021-09-24 08:27:41 -04001794 AcpiTable table = { .sig = "HPET", .rev = 1,
1795 .oem_id = oem_id, .oem_table_id = oem_table_id };
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001796
Igor Mammedov43dde172021-09-24 08:27:41 -04001797 acpi_table_begin(&table, table_data);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001798 /* Note timer_block_id value must be kept in sync with value advertised by
1799 * emulated hpet
1800 */
Igor Mammedov43dde172021-09-24 08:27:41 -04001801 /* Event Timer Block ID */
1802 build_append_int_noprefix(table_data, 0x8086a201, 4);
1803 /* BASE_ADDRESS */
1804 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1805 /* HPET Number */
1806 build_append_int_noprefix(table_data, 0, 1);
1807 /* Main Counter Minimum Clock_tick in Periodic Mode */
1808 build_append_int_noprefix(table_data, 0, 2);
1809 /* Page Protection And OEM Attribute */
1810 build_append_int_noprefix(table_data, 0, 1);
1811 acpi_table_end(linker, &table);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001812}
1813
Stefan Berger11fb99e2021-06-15 16:21:17 +02001814#ifdef CONFIG_TPM
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001815/*
1816 * TCPA Description Table
1817 *
1818 * Following Level 00, Rev 00.37 of specs:
1819 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1820 * 7.1.2 ACPI Table Layout
1821 */
Stefan Berger711b20b2014-08-11 16:33:36 -04001822static void
Marian Postevca602b4582021-01-19 02:32:13 +02001823build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1824 const char *oem_id, const char *oem_table_id)
Stefan Berger711b20b2014-08-11 16:33:36 -04001825{
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001826 unsigned log_addr_offset;
1827 AcpiTable table = { .sig = "TCPA", .rev = 2,
1828 .oem_id = oem_id, .oem_table_id = oem_table_id };
Stefan Berger711b20b2014-08-11 16:33:36 -04001829
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001830 acpi_table_begin(&table, table_data);
1831 /* Platform Class */
1832 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1833 /* Log Area Minimum Length (LAML) */
1834 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1835 /* Log Area Start Address (LASA) */
1836 log_addr_offset = table_data->len;
1837 build_append_int_noprefix(table_data, 0, 8);
Stefan Berger711b20b2014-08-11 16:33:36 -04001838
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001839 /* allocate/reserve space for TPM log area */
1840 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
Igor Mammedovad9671b2016-05-19 15:19:26 +02001841 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
Stefan Berger42a5b302014-10-24 13:21:04 -04001842 false /* high memory */);
Stefan Berger711b20b2014-08-11 16:33:36 -04001843 /* log area start address to be filled by Guest linker */
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001844 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1845 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
Stefan Berger711b20b2014-08-11 16:33:36 -04001846
Igor Mammedov57cb8cf2021-09-24 08:27:42 -04001847 acpi_table_end(linker, &table);
Stefan Berger711b20b2014-08-11 16:33:36 -04001848}
Stefan Berger11fb99e2021-06-15 16:21:17 +02001849#endif
Stefan Berger711b20b2014-08-11 16:33:36 -04001850
Paolo Bonzinid471bf32018-06-29 16:22:13 +02001851#define HOLE_640K_START (640 * KiB)
1852#define HOLE_640K_END (1 * MiB)
Eduardo Habkost49264032017-09-01 10:10:02 +08001853
Igor Mammedove5b6d552021-09-24 08:27:44 -04001854/*
1855 * ACPI spec, Revision 3.0
1856 * 5.2.15 System Resource Affinity Table (SRAT)
1857 */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001858static void
Igor Mammedov0e9b9ed2016-05-19 15:19:25 +02001859build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001860{
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001861 int i;
Igor Mammedove5b6d552021-09-24 08:27:44 -04001862 int numa_mem_start, slots;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001863 uint64_t mem_len, mem_base, next_base;
Igor Mammedov5803fce2016-02-26 14:59:23 +01001864 MachineClass *mc = MACHINE_GET_CLASS(machine);
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02001865 X86MachineState *x86ms = X86_MACHINE(machine);
Igor Mammedov80e5db32017-01-18 18:13:20 +01001866 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
Jingqi Liue77af212021-08-23 09:12:54 +08001867 int nb_numa_nodes = machine->numa_state->num_nodes;
1868 NodeInfo *numa_info = machine->numa_state->nodes;
Igor Mammedov255bf202021-09-24 08:27:43 -04001869 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1870 .oem_table_id = x86ms->oem_table_id };
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001871
Igor Mammedov255bf202021-09-24 08:27:43 -04001872 acpi_table_begin(&table, table_data);
1873 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1874 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001875
Igor Mammedov5803fce2016-02-26 14:59:23 +01001876 for (i = 0; i < apic_ids->len; i++) {
Igor Mammedovd41f3e72017-05-30 18:23:58 +02001877 int node_id = apic_ids->cpus[i].props.node_id;
Igor Mammedov5eff33a2016-10-19 14:05:32 +02001878 uint32_t apic_id = apic_ids->cpus[i].arch_id;
Igor Mammedov5803fce2016-02-26 14:59:23 +01001879
Igor Mammedov5eff33a2016-10-19 14:05:32 +02001880 if (apic_id < 255) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001881 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1882 build_append_int_noprefix(table_data, 0, 1); /* Type */
1883 build_append_int_noprefix(table_data, 16, 1); /* Length */
1884 /* Proximity Domain [7:0] */
1885 build_append_int_noprefix(table_data, node_id, 1);
1886 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1887 /* Flags, Table 5-36 */
1888 build_append_int_noprefix(table_data, 1, 4);
1889 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1890 /* Proximity Domain [31:8] */
1891 build_append_int_noprefix(table_data, 0, 3);
1892 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
Igor Mammedov5eff33a2016-10-19 14:05:32 +02001893 } else {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001894 /*
1895 * ACPI spec, Revision 4.0
1896 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1897 */
1898 build_append_int_noprefix(table_data, 2, 1); /* Type */
1899 build_append_int_noprefix(table_data, 24, 1); /* Length */
1900 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1901 /* Proximity Domain */
1902 build_append_int_noprefix(table_data, node_id, 4);
1903 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1904 /* Flags, Table 5-39 */
1905 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1906 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1907 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
Igor Mammedov1f3aba32016-06-16 14:23:48 +02001908 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001909 }
1910
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001911 /* the memory map is a bit tricky, it contains at least one hole
1912 * from 640k-1M and possibly another one from 3.5G-4G.
1913 */
1914 next_base = 0;
Igor Mammedove5b6d552021-09-24 08:27:44 -04001915 numa_mem_start = table_data->len;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001916
Jingqi Liue77af212021-08-23 09:12:54 +08001917 for (i = 1; i < nb_numa_nodes + 1; ++i) {
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001918 mem_base = next_base;
Jingqi Liue77af212021-08-23 09:12:54 +08001919 mem_len = numa_info[i - 1].node_mem;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001920 next_base = mem_base + mem_len;
1921
Eduardo Habkost49264032017-09-01 10:10:02 +08001922 /* Cut out the 640K hole */
1923 if (mem_base <= HOLE_640K_START &&
1924 next_base > HOLE_640K_START) {
1925 mem_len -= next_base - HOLE_640K_START;
1926 if (mem_len > 0) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001927 build_srat_memory(table_data, mem_base, mem_len, i - 1,
Eduardo Habkost49264032017-09-01 10:10:02 +08001928 MEM_AFFINITY_ENABLED);
1929 }
1930
1931 /* Check for the rare case: 640K < RAM < 1M */
1932 if (next_base <= HOLE_640K_END) {
1933 next_base = HOLE_640K_END;
1934 continue;
1935 }
1936 mem_base = HOLE_640K_END;
1937 mem_len = next_base - HOLE_640K_END;
1938 }
1939
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001940 /* Cut out the ACPI_PCI hole */
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02001941 if (mem_base <= x86ms->below_4g_mem_size &&
1942 next_base > x86ms->below_4g_mem_size) {
1943 mem_len -= next_base - x86ms->below_4g_mem_size;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001944 if (mem_len > 0) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001945 build_srat_memory(table_data, mem_base, mem_len, i - 1,
Shannon Zhao64b83132016-05-12 13:22:28 +01001946 MEM_AFFINITY_ENABLED);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001947 }
Joao Martins4ab4c332022-07-19 18:00:04 +01001948 mem_base = x86ms->above_4g_mem_start;
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02001949 mem_len = next_base - x86ms->below_4g_mem_size;
Dou Liyang6cf6fe32017-12-14 12:08:55 +08001950 next_base = mem_base + mem_len;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001951 }
Dou Liyang16b42262018-07-10 16:58:01 +08001952
1953 if (mem_len > 0) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001954 build_srat_memory(table_data, mem_base, mem_len, i - 1,
Dou Liyang16b42262018-07-10 16:58:01 +08001955 MEM_AFFINITY_ENABLED);
1956 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001957 }
Vishal Vermac3b0cf62020-06-05 18:09:10 -06001958
1959 if (machine->nvdimms_state->is_enabled) {
1960 nvdimm_build_srat(table_data);
1961 }
1962
Yang Zhong11058122021-11-01 12:20:05 -04001963 sgx_epc_build_srat(table_data);
1964
Igor Mammedove5b6d552021-09-24 08:27:44 -04001965 /*
1966 * TODO: this part is not in ACPI spec and current linux kernel boots fine
1967 * without these entries. But I recall there were issues the last time I
1968 * tried to remove it with some ancient guest OS, however I can't remember
1969 * what that was so keep this around for now
1970 */
1971 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
Jingqi Liue77af212021-08-23 09:12:54 +08001972 for (; slots < nb_numa_nodes + 2; slots++) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001973 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001974 }
1975
Ankit Agrawal5deced62024-03-08 14:55:25 +00001976 build_srat_generic_pci_initiator(table_data);
1977
Igor Mammedovdbb6da82018-08-22 11:46:44 +02001978 /*
1979 * Entry is required for Windows to enable memory hotplug in OS
1980 * and for Linux to enable SWIOTLB when booted with less than
1981 * 4G of RAM. Windows works better if the entry sets proximity
1982 * to the highest NUMA node in the machine.
1983 * Memory devices may override proximity set by this entry,
1984 * providing _PXM method if necessary.
1985 */
David Hildenbrand75d5f342023-06-23 14:45:50 +02001986 if (machine->device_memory) {
Igor Mammedove5b6d552021-09-24 08:27:44 -04001987 build_srat_memory(table_data, machine->device_memory->base,
David Hildenbrand75d5f342023-06-23 14:45:50 +02001988 memory_region_size(&machine->device_memory->mr),
1989 nb_numa_nodes - 1,
Igor Mammedovdbb6da82018-08-22 11:46:44 +02001990 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
Igor Mammedovcec65192014-06-02 15:25:28 +02001991 }
1992
Igor Mammedov255bf202021-09-24 08:27:43 -04001993 acpi_table_end(linker, &table);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03001994}
1995
Peter Xud46114f2016-07-14 13:56:14 +08001996/*
Michael Tokarevbad5cfc2023-07-14 14:16:12 +03001997 * Insert DMAR scope for PCI bridges and endpoint devices
Xingang Wang26863362021-07-08 12:55:17 +00001998 */
1999static void
2000insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2001{
Igor Mammedov91a6b972021-09-24 08:27:45 -04002002 const size_t device_scope_size = 6 /* device scope structure */ +
2003 2 /* 1 path entry */;
Xingang Wang26863362021-07-08 12:55:17 +00002004 GArray *scope_blob = opaque;
Xingang Wang26863362021-07-08 12:55:17 +00002005
2006 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2007 /* Dmar Scope Type: 0x02 for PCI Bridge */
2008 build_append_int_noprefix(scope_blob, 0x02, 1);
2009 } else {
2010 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2011 build_append_int_noprefix(scope_blob, 0x01, 1);
2012 }
2013
2014 /* length */
Igor Mammedov91a6b972021-09-24 08:27:45 -04002015 build_append_int_noprefix(scope_blob, device_scope_size, 1);
Xingang Wang26863362021-07-08 12:55:17 +00002016 /* reserved */
2017 build_append_int_noprefix(scope_blob, 0, 2);
2018 /* enumeration_id */
2019 build_append_int_noprefix(scope_blob, 0, 1);
2020 /* bus */
2021 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2022 /* device */
2023 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2024 /* function */
2025 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2026}
2027
2028/* For a given PCI host bridge, walk and insert DMAR scope */
2029static int
2030dmar_host_bridges(Object *obj, void *opaque)
2031{
2032 GArray *scope_blob = opaque;
2033
2034 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2035 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2036
2037 if (bus && !pci_bus_bypass_iommu(bus)) {
Peter Xu2914fc62021-10-28 12:31:26 +08002038 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
Xingang Wang26863362021-07-08 12:55:17 +00002039 }
2040 }
2041
2042 return 0;
2043}
2044
2045/*
Igor Mammedov91a6b972021-09-24 08:27:45 -04002046 * Intel ® Virtualization Technology for Directed I/O
2047 * Architecture Specification. Revision 3.3
2048 * 8.1 DMA Remapping Reporting Structure
Peter Xud46114f2016-07-14 13:56:14 +08002049 */
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002050static void
Marian Postevca602b4582021-01-19 02:32:13 +02002051build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2052 const char *oem_table_id)
Le Tand4eb9112014-08-16 13:55:39 +08002053{
Peter Xud46114f2016-07-14 13:56:14 +08002054 uint8_t dmar_flags = 0;
Igor Mammedov91a6b972021-09-24 08:27:45 -04002055 uint8_t rsvd10[10] = {};
2056 /* Root complex IOAPIC uses one path only */
2057 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2058 2 /* 1 path entry */;
Peter Xud46114f2016-07-14 13:56:14 +08002059 X86IOMMUState *iommu = x86_iommu_get_default();
Prasad Singamsetty37f51382017-11-14 18:13:50 -05002060 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
Xingang Wang26863362021-07-08 12:55:17 +00002061 GArray *scope_blob = g_array_new(false, true, 1);
2062
Igor Mammedov91a6b972021-09-24 08:27:45 -04002063 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2064 .oem_table_id = oem_table_id };
2065
Xingang Wang26863362021-07-08 12:55:17 +00002066 /*
2067 * A PCI bus walk, for each PCI host bridge.
2068 * Insert scope for each PCI bridge and endpoint device which
2069 * is attached to a bus with iommu enabled.
2070 */
2071 object_child_foreach_recursive(object_get_root(),
2072 dmar_host_bridges, scope_blob);
Peter Xud46114f2016-07-14 13:56:14 +08002073
2074 assert(iommu);
Peter Xua924b3d2018-12-20 13:40:36 +08002075 if (x86_iommu_ir_supported(iommu)) {
Peter Xud46114f2016-07-14 13:56:14 +08002076 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2077 }
Le Tand4eb9112014-08-16 13:55:39 +08002078
Igor Mammedov91a6b972021-09-24 08:27:45 -04002079 acpi_table_begin(&table, table_data);
2080 /* Host Address Width */
2081 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2082 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2083 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
Le Tand4eb9112014-08-16 13:55:39 +08002084
Igor Mammedov91a6b972021-09-24 08:27:45 -04002085 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2086 build_append_int_noprefix(table_data, 0, 2); /* Type */
2087 /* Length */
2088 build_append_int_noprefix(table_data,
2089 16 + ioapic_scope_size + scope_blob->len, 2);
2090 /* Flags */
2091 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2092 1);
2093 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2094 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2095 /* Register Base Address */
2096 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
Le Tand4eb9112014-08-16 13:55:39 +08002097
Peter Xucfc13df2016-07-14 13:56:17 +08002098 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2099 * 8.3.1 (version Oct. 2014 or later). */
Igor Mammedov91a6b972021-09-24 08:27:45 -04002100 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2101 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2102 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2103 /* Enumeration ID */
2104 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2105 /* Start Bus Number */
2106 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2107 /* Path, {Device, Function} pair */
2108 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2109 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
Peter Xucfc13df2016-07-14 13:56:17 +08002110
Xingang Wang26863362021-07-08 12:55:17 +00002111 /* Add scope found above */
2112 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2113 g_array_free(scope_blob, true);
2114
Jason Wangbd2baac2016-12-30 18:09:16 +08002115 if (iommu->dt_supported) {
Igor Mammedov91a6b972021-09-24 08:27:45 -04002116 /* 8.5 Root Port ATS Capability Reporting Structure */
2117 build_append_int_noprefix(table_data, 2, 2); /* Type */
2118 build_append_int_noprefix(table_data, 8, 2); /* Length */
2119 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2120 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2121 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
Jason Wangbd2baac2016-12-30 18:09:16 +08002122 }
2123
Igor Mammedov91a6b972021-09-24 08:27:45 -04002124 acpi_table_end(linker, &table);
Le Tand4eb9112014-08-16 13:55:39 +08002125}
Liran Alon14cda352020-03-13 16:50:08 +02002126
2127/*
2128 * Windows ACPI Emulated Devices Table
2129 * (Version 1.0 - April 6, 2009)
2130 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2131 *
2132 * Helpful to speedup Windows guests and ignored by others.
2133 */
2134static void
Marian Postevca602b4582021-01-19 02:32:13 +02002135build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2136 const char *oem_table_id)
Liran Alon14cda352020-03-13 16:50:08 +02002137{
Igor Mammedoveaa50762021-09-24 08:27:46 -04002138 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2139 .oem_table_id = oem_table_id };
Liran Alon14cda352020-03-13 16:50:08 +02002140
Igor Mammedoveaa50762021-09-24 08:27:46 -04002141 acpi_table_begin(&table, table_data);
Liran Alon14cda352020-03-13 16:50:08 +02002142 /*
2143 * Set "ACPI PM timer good" flag.
2144 *
2145 * Tells Windows guests that our ACPI PM timer is reliable in the
2146 * sense that guest can read it only once to obtain a reliable value.
2147 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2148 */
2149 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
Igor Mammedoveaa50762021-09-24 08:27:46 -04002150 acpi_table_end(linker, &table);
Liran Alon14cda352020-03-13 16:50:08 +02002151}
2152
David Kiariefb9f5922016-09-20 18:42:34 +03002153/*
2154 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2155 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2156 */
Singh, Brijeshc0288182018-10-01 19:44:41 +00002157#define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2158
Alex Williamson977aff12019-10-23 16:47:28 -06002159/*
2160 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2161 * necessary for the PCI topology.
2162 */
2163static void
2164insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2165{
2166 GArray *table_data = opaque;
2167 uint32_t entry;
2168
2169 /* "Select" IVHD entry, type 0x2 */
2170 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2171 build_append_int_noprefix(table_data, entry, 4);
2172
2173 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2174 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2175 uint8_t sec = pci_bus_num(sec_bus);
2176 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2177
2178 if (pci_bus_is_express(sec_bus)) {
2179 /*
2180 * Walk the bus if there are subordinates, otherwise use a range
2181 * to cover an entire leaf bus. We could potentially also use a
2182 * range for traversed buses, but we'd need to take care not to
2183 * create both Select and Range entries covering the same device.
2184 * This is easier and potentially more compact.
2185 *
2186 * An example bare metal system seems to use Select entries for
2187 * root ports without a slot (ie. built-ins) and Range entries
2188 * when there is a slot. The same system also only hard-codes
2189 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2190 * making no effort to support nested bridges. We attempt to
2191 * be more thorough here.
2192 */
2193 if (sec == sub) { /* leaf bus */
2194 /* "Start of Range" IVHD entry, type 0x3 */
2195 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2196 build_append_int_noprefix(table_data, entry, 4);
2197 /* "End of Range" IVHD entry, type 0x4 */
2198 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2199 build_append_int_noprefix(table_data, entry, 4);
2200 } else {
2201 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2202 }
2203 } else {
2204 /*
2205 * If the secondary bus is conventional, then we need to create an
2206 * Alias range for everything downstream. The range covers the
2207 * first devfn on the secondary bus to the last devfn on the
2208 * subordinate bus. The alias target depends on legacy versus
2209 * express bridges, just as in pci_device_iommu_address_space().
2210 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2211 */
2212 uint16_t dev_id_a, dev_id_b;
2213
2214 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2215
2216 if (pci_is_express(dev) &&
2217 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2218 dev_id_b = dev_id_a;
2219 } else {
2220 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2221 }
2222
2223 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2224 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2225 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2226
2227 /* "End of Range" IVHD entry, type 0x4 */
2228 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2229 build_append_int_noprefix(table_data, entry, 4);
2230 }
2231 }
2232}
2233
2234/* For all PCI host bridges, walk and insert IVHD entries */
2235static int
2236ivrs_host_bridges(Object *obj, void *opaque)
2237{
2238 GArray *ivhd_blob = opaque;
2239
2240 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2241 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2242
Xingang Wangdec2f562021-07-08 12:55:18 +00002243 if (bus && !pci_bus_bypass_iommu(bus)) {
Peter Xu2914fc62021-10-28 12:31:26 +08002244 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
Alex Williamson977aff12019-10-23 16:47:28 -06002245 }
2246 }
2247
2248 return 0;
2249}
2250
David Kiariefb9f5922016-09-20 18:42:34 +03002251static void
Marian Postevca602b4582021-01-19 02:32:13 +02002252build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2253 const char *oem_table_id)
David Kiariefb9f5922016-09-20 18:42:34 +03002254{
David Kiariefb9f5922016-09-20 18:42:34 +03002255 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
Alex Williamson977aff12019-10-23 16:47:28 -06002256 GArray *ivhd_blob = g_array_new(false, true, 1);
Igor Mammedovb0a45ff2021-09-24 08:27:47 -04002257 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2258 .oem_table_id = oem_table_id };
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002259 uint64_t feature_report;
David Kiariefb9f5922016-09-20 18:42:34 +03002260
Igor Mammedovb0a45ff2021-09-24 08:27:47 -04002261 acpi_table_begin(&table, table_data);
David Kiariefb9f5922016-09-20 18:42:34 +03002262 /* IVinfo - IO virtualization information common to all
2263 * IOMMU units in a system
2264 */
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002265 build_append_int_noprefix(table_data,
2266 (1UL << 0) | /* EFRSup */
2267 (40UL << 8), /* PASize */
2268 4);
David Kiariefb9f5922016-09-20 18:42:34 +03002269 /* reserved */
2270 build_append_int_noprefix(table_data, 0, 8);
2271
Singh, Brijeshc0288182018-10-01 19:44:41 +00002272 /*
Alex Williamson977aff12019-10-23 16:47:28 -06002273 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2274 * complete set of IVHD entries. Do this into a separate blob so that we
2275 * can calculate the total IVRS table length here and then append the new
2276 * blob further below. Fall back to an entry covering all devices, which
2277 * is sufficient when no aliases are present.
2278 */
2279 object_child_foreach_recursive(object_get_root(),
2280 ivrs_host_bridges, ivhd_blob);
2281
2282 if (!ivhd_blob->len) {
2283 /*
2284 * Type 1 device entry reporting all devices
2285 * These are 4-byte device entries currently reporting the range of
2286 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2287 */
2288 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2289 }
2290
Alex Williamson977aff12019-10-23 16:47:28 -06002291 /*
Singh, Brijeshc0288182018-10-01 19:44:41 +00002292 * When interrupt remapping is supported, we add a special IVHD device
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002293 * for type IO-APIC
2294 * Refer to spec - Table 95: IVHD device entry type codes
2295 *
2296 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2297 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
Singh, Brijeshc0288182018-10-01 19:44:41 +00002298 */
Peter Xua924b3d2018-12-20 13:40:36 +08002299 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002300 build_append_int_noprefix(ivhd_blob,
2301 (0x1ull << 56) | /* type IOAPIC */
2302 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2303 0x48, /* special device */
2304 8);
Singh, Brijeshc0288182018-10-01 19:44:41 +00002305 }
Alex Williamson977aff12019-10-23 16:47:28 -06002306
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002307 /* IVHD definition - type 10h */
2308 build_append_int_noprefix(table_data, 0x10, 1);
2309 /* virtualization flags */
2310 build_append_int_noprefix(table_data,
2311 (1UL << 0) | /* HtTunEn */
2312 (1UL << 4) | /* iotblSup */
2313 (1UL << 6) | /* PrefSup */
2314 (1UL << 7), /* PPRSup */
2315 1);
2316
David Kiariefb9f5922016-09-20 18:42:34 +03002317 /* IVHD length */
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002318 build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2);
David Kiariefb9f5922016-09-20 18:42:34 +03002319 /* DeviceID */
Philippe Mathieu-Daudé531f50a2023-03-13 16:30:28 +01002320 build_append_int_noprefix(table_data,
2321 object_property_get_int(OBJECT(&s->pci), "addr",
2322 &error_abort), 2);
David Kiariefb9f5922016-09-20 18:42:34 +03002323 /* Capability offset */
Philippe Mathieu-Daudéae097d82023-03-13 16:30:29 +01002324 build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
David Kiariefb9f5922016-09-20 18:42:34 +03002325 /* IOMMU base address */
2326 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2327 /* PCI Segment Group */
2328 build_append_int_noprefix(table_data, 0, 2);
2329 /* IOMMU info */
2330 build_append_int_noprefix(table_data, 0, 2);
2331 /* IOMMU Feature Reporting */
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002332 feature_report = (48UL << 30) | /* HATS */
2333 (48UL << 28) | /* GATS */
2334 (1UL << 2) | /* GTSup */
2335 (1UL << 6); /* GASup */
2336 if (s->xtsup) {
2337 feature_report |= (1UL << 0); /* XTSup */
2338 }
2339 build_append_int_noprefix(table_data, feature_report, 4);
Alex Williamson977aff12019-10-23 16:47:28 -06002340
2341 /* IVHD entries as found above */
2342 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
David Kiariefb9f5922016-09-20 18:42:34 +03002343
Bui Quang Minh328a11a2024-01-11 22:44:03 +07002344 /* IVHD definition - type 11h */
2345 build_append_int_noprefix(table_data, 0x11, 1);
2346 /* virtualization flags */
2347 build_append_int_noprefix(table_data,
2348 (1UL << 0) | /* HtTunEn */
2349 (1UL << 4), /* iotblSup */
2350 1);
2351
2352 /* IVHD length */
2353 build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2);
2354 /* DeviceID */
2355 build_append_int_noprefix(table_data,
2356 object_property_get_int(OBJECT(&s->pci), "addr",
2357 &error_abort), 2);
2358 /* Capability offset */
2359 build_append_int_noprefix(table_data, s->pci.capab_offset, 2);
2360 /* IOMMU base address */
2361 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2362 /* PCI Segment Group */
2363 build_append_int_noprefix(table_data, 0, 2);
2364 /* IOMMU info */
2365 build_append_int_noprefix(table_data, 0, 2);
2366 /* IOMMU Attributes */
2367 build_append_int_noprefix(table_data, 0, 4);
2368 /* EFR Register Image */
2369 build_append_int_noprefix(table_data,
2370 amdvi_extended_feature_register(s),
2371 8);
2372 /* EFR Register Image 2 */
2373 build_append_int_noprefix(table_data, 0, 8);
2374
2375 /* IVHD entries as found above */
2376 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2377
2378 g_array_free(ivhd_blob, TRUE);
Igor Mammedovb0a45ff2021-09-24 08:27:47 -04002379 acpi_table_end(linker, &table);
David Kiariefb9f5922016-09-20 18:42:34 +03002380}
Le Tand4eb9112014-08-16 13:55:39 +08002381
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002382typedef
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002383struct AcpiBuildState {
2384 /* Copy of table in RAM (for patching). */
Paolo Bonzini339240b2015-03-23 10:24:16 +01002385 MemoryRegion *table_mr;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002386 /* Is table patched? */
2387 uint8_t patched;
Paolo Bonzini339240b2015-03-23 10:24:16 +01002388 MemoryRegion *rsdp_mr;
2389 MemoryRegion *linker_mr;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002390} AcpiBuildState;
2391
2392static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2393{
2394 Object *pci_host;
2395 QObject *o;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002396
Marcel Apfelbaumca6c1852015-06-02 14:22:59 +03002397 pci_host = acpi_get_i386_pci_host();
Julia Suvorovac0e427d2021-07-13 02:42:01 +02002398 if (!pci_host) {
2399 return false;
2400 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002401
2402 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2403 if (!o) {
2404 return false;
2405 }
Wei Yangc3094342019-04-19 08:30:50 +08002406 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +02002407 qobject_unref(o);
Wei Yangc3094342019-04-19 08:30:50 +08002408 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
Igor Mammedovfe4970a2019-04-09 17:00:37 +02002409 return false;
2410 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002411
2412 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2413 assert(o);
Wei Yangc3094342019-04-19 08:30:50 +08002414 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
Marc-André Lureaucb3e7f02018-04-19 17:01:43 +02002415 qobject_unref(o);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002416 return true;
2417}
2418
2419static
Igor Mammedov3d3ebca2016-02-26 14:59:22 +01002420void acpi_build(AcpiBuildTables *tables, MachineState *machine)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002421{
Igor Mammedov3d3ebca2016-02-26 14:59:22 +01002422 PCMachineState *pcms = PC_MACHINE(machine);
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002423 X86MachineState *x86ms = X86_MACHINE(machine);
Jean-Philippe Brucker36efa252021-10-26 19:20:23 +01002424 DeviceState *iommu = pcms->iommu;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002425 GArray *table_offsets;
Philippe Mathieu-Daudéea7a74a2024-02-28 09:30:01 +01002426 unsigned facs, dsdt, rsdt;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002427 AcpiPmInfo pm;
2428 AcpiMiscInfo misc;
2429 AcpiMcfgInfo mcfg;
Julia Suvorovac0e427d2021-07-13 02:42:01 +02002430 Range pci_hole = {}, pci_hole64 = {};
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002431 uint8_t *u;
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002432 GArray *tables_blob = tables->table_data;
Laszlo Ersekae123742016-01-18 15:12:13 +01002433 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
Ben Warrend03637b2017-02-16 15:15:36 -08002434 Object *vmgenid_dev;
Marian Postevca602b4582021-01-19 02:32:13 +02002435 char *oem_id;
2436 char *oem_table_id;
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002437
Like Xu0e11fc62019-05-19 04:54:25 +08002438 acpi_get_pm_info(machine, &pm);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002439 acpi_get_misc_info(&misc);
Markus Armbruster01c97422016-06-15 19:56:31 +02002440 acpi_get_pci_holes(&pci_hole, &pci_hole64);
Laszlo Ersekae123742016-01-18 15:12:13 +01002441 acpi_get_slic_oem(&slic_oem);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002442
Marian Postevca602b4582021-01-19 02:32:13 +02002443 if (slic_oem.id) {
2444 oem_id = slic_oem.id;
2445 } else {
Marian Postevcad07b2282021-02-21 02:17:36 +02002446 oem_id = x86ms->oem_id;
Marian Postevca602b4582021-01-19 02:32:13 +02002447 }
2448
2449 if (slic_oem.table_id) {
2450 oem_table_id = slic_oem.table_id;
2451 } else {
Marian Postevcad07b2282021-02-21 02:17:36 +02002452 oem_table_id = x86ms->oem_table_id;
Marian Postevca602b4582021-01-19 02:32:13 +02002453 }
2454
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002455 table_offsets = g_array_new(false, true /* clear */,
2456 sizeof(uint32_t));
Gonglei8b310fc2014-11-13 10:59:37 +08002457 ACPI_BUILD_DPRINTF("init ACPI tables\n");
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002458
Igor Mammedovad9671b2016-05-19 15:19:26 +02002459 bios_linker_loader_alloc(tables->linker,
2460 ACPI_BUILD_TABLE_FILE, tables_blob,
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002461 64 /* Ensure FACS is aligned */,
2462 false /* high memory */);
2463
2464 /*
2465 * FACS is pointed to by FADT.
2466 * We place it first since it's the only table that has alignment
2467 * requirements.
2468 */
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002469 facs = tables_blob->len;
Wei Yang009180b2019-01-30 11:02:07 +08002470 build_facs(tables_blob);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002471
2472 /* DSDT is pointed to by FADT */
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002473 dsdt = tables_blob->len;
Markus Armbruster01c97422016-06-15 19:56:31 +02002474 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2475 &pci_hole, &pci_hole64, machine);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002476
2477 /* ACPI tables pointed to by RSDT */
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002478 acpi_add_table(table_offsets, tables_blob);
Igor Mammedov937d1b52018-02-28 15:23:51 +01002479 pm.fadt.facs_tbl_offset = &facs;
2480 pm.fadt.dsdt_tbl_offset = &dsdt;
2481 pm.fadt.xdsdt_tbl_offset = &dsdt;
Marian Postevca602b4582021-01-19 02:32:13 +02002482 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002483
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002484 acpi_add_table(table_offsets, tables_blob);
Gerd Hoffmanneb66ffa2020-05-20 15:19:47 +02002485 acpi_build_madt(tables_blob, tables->linker, x86ms,
Bernhard Beschowf4a06e52023-09-08 10:42:27 +02002486 x86ms->oem_id, x86ms->oem_table_id);
Michael S. Tsirkin9ac1c4c2014-04-28 08:15:32 +03002487
Eric DeVolder8486f122022-01-28 15:38:06 -05002488#ifdef CONFIG_ACPI_ERST
2489 {
2490 Object *erst_dev;
2491 erst_dev = find_erst_dev();
2492 if (erst_dev) {
2493 acpi_add_table(table_offsets, tables_blob);
2494 build_erst(tables_blob, tables->linker, erst_dev,
2495 x86ms->oem_id, x86ms->oem_table_id);
2496 }
2497 }
2498#endif
2499
Ben Warrend03637b2017-02-16 15:15:36 -08002500 vmgenid_dev = find_vmgenid_dev();
2501 if (vmgenid_dev) {
2502 acpi_add_table(table_offsets, tables_blob);
2503 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
Marian Postevcad07b2282021-02-21 02:17:36 +02002504 tables->vmgenid, tables->linker, x86ms->oem_id);
Ben Warrend03637b2017-02-16 15:15:36 -08002505 }
2506
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002507 if (misc.has_hpet) {
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002508 acpi_add_table(table_offsets, tables_blob);
Marian Postevcad07b2282021-02-21 02:17:36 +02002509 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2510 x86ms->oem_table_id);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002511 }
Stefan Berger11fb99e2021-06-15 16:21:17 +02002512#ifdef CONFIG_TPM
Stefan Berger5cb18b32015-05-26 16:51:07 -04002513 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
Stefan Berger7e7c1b82020-05-29 15:28:40 -04002514 if (misc.tpm_version == TPM_VERSION_1_2) {
2515 acpi_add_table(table_offsets, tables_blob);
Marian Postevca602b4582021-01-19 02:32:13 +02002516 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
Marian Postevcad07b2282021-02-21 02:17:36 +02002517 x86ms->oem_id, x86ms->oem_table_id);
Stefan Berger7e7c1b82020-05-29 15:28:40 -04002518 } else { /* TPM_VERSION_2_0 */
Igor Mammedov72d97b32015-06-09 05:31:53 +02002519 acpi_add_table(table_offsets, tables_blob);
Marian Postevca602b4582021-01-19 02:32:13 +02002520 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
Marian Postevcad07b2282021-02-21 02:17:36 +02002521 x86ms->oem_id, x86ms->oem_table_id);
Stefan Berger5cb18b32015-05-26 16:51:07 -04002522 }
Stefan Berger711b20b2014-08-11 16:33:36 -04002523 }
Stefan Berger11fb99e2021-06-15 16:21:17 +02002524#endif
Jingqi Liue77af212021-08-23 09:12:54 +08002525 if (machine->numa_state->num_nodes) {
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002526 acpi_add_table(table_offsets, tables_blob);
Igor Mammedov3d3ebca2016-02-26 14:59:22 +01002527 build_srat(tables_blob, tables->linker, machine);
Tao Xu118154b2019-08-09 14:57:23 +08002528 if (machine->numa_state->have_numa_distance) {
He Chen0f203432017-04-27 10:35:58 +08002529 acpi_add_table(table_offsets, tables_blob);
Marian Postevcad07b2282021-02-21 02:17:36 +02002530 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2531 x86ms->oem_table_id);
He Chen0f203432017-04-27 10:35:58 +08002532 }
Liu Jingqie6f123c2019-12-13 09:19:25 +08002533 if (machine->numa_state->hmat_enabled) {
2534 acpi_add_table(table_offsets, tables_blob);
Marian Postevca602b4582021-01-19 02:32:13 +02002535 build_hmat(tables_blob, tables->linker, machine->numa_state,
Marian Postevcad07b2282021-02-21 02:17:36 +02002536 x86ms->oem_id, x86ms->oem_table_id);
Liu Jingqie6f123c2019-12-13 09:19:25 +08002537 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002538 }
2539 if (acpi_get_mcfg(&mcfg)) {
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002540 acpi_add_table(table_offsets, tables_blob);
Marian Postevcad07b2282021-02-21 02:17:36 +02002541 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2542 x86ms->oem_table_id);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002543 }
Jean-Philippe Brucker867e9c92021-10-26 19:20:21 +01002544 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2545 acpi_add_table(table_offsets, tables_blob);
2546 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2547 x86ms->oem_table_id);
2548 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2549 acpi_add_table(table_offsets, tables_blob);
2550 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2551 x86ms->oem_table_id);
Jean-Philippe Brucker36efa252021-10-26 19:20:23 +01002552 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2553 PCIDevice *pdev = PCI_DEVICE(iommu);
2554
2555 acpi_add_table(table_offsets, tables_blob);
2556 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2557 x86ms->oem_id, x86ms->oem_table_id);
Le Tand4eb9112014-08-16 13:55:39 +08002558 }
Eric Augerf6a0d062019-03-08 19:20:53 +01002559 if (machine->nvdimms_state->is_enabled) {
Igor Mammedovad9671b2016-05-19 15:19:26 +02002560 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
Marian Postevca602b4582021-01-19 02:32:13 +02002561 machine->nvdimms_state, machine->ram_slots,
Marian Postevcad07b2282021-02-21 02:17:36 +02002562 x86ms->oem_id, x86ms->oem_table_id);
Xiao Guangrong87252e12015-12-02 15:20:58 +08002563 }
Jonathan Cameron1ebf9002022-06-08 15:54:39 +01002564 if (pcms->cxl_devices_state.is_enabled) {
Jonathan Cameron51359802022-06-08 15:54:34 +01002565 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
Jonathan Cameron1ebf9002022-06-08 15:54:39 +01002566 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
Ben Widawsky3d6a69b2022-04-29 15:40:50 +01002567 }
Xiao Guangrong87252e12015-12-02 15:20:58 +08002568
Liran Alon14cda352020-03-13 16:50:08 +02002569 acpi_add_table(table_offsets, tables_blob);
Marian Postevcad07b2282021-02-21 02:17:36 +02002570 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
Liran Alon14cda352020-03-13 16:50:08 +02002571
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002572 /* Add tables supplied by user (if any) */
2573 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2574 unsigned len = acpi_table_len(u);
2575
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002576 acpi_add_table(table_offsets, tables_blob);
2577 g_array_append_vals(tables_blob, u, len);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002578 }
2579
2580 /* RSDT is pointed to by RSDP */
Igor Mammedov7c2c1fa2015-02-09 10:53:24 +00002581 rsdt = tables_blob->len;
Laszlo Ersekae123742016-01-18 15:12:13 +01002582 build_rsdt(tables_blob, tables->linker, table_offsets,
Marian Postevca602b4582021-01-19 02:32:13 +02002583 oem_id, oem_table_id);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002584
2585 /* RSDP is in FSEG memory, so allocate it separately */
Samuel Ortiza46ce1c2018-12-17 16:34:48 +01002586 {
2587 AcpiRsdpData rsdp_data = {
2588 .revision = 0,
Marian Postevcad07b2282021-02-21 02:17:36 +02002589 .oem_id = x86ms->oem_id,
Samuel Ortiza46ce1c2018-12-17 16:34:48 +01002590 .xsdt_tbl_offset = NULL,
2591 .rsdt_tbl_offset = &rsdt,
2592 };
2593 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
Samuel Ortiza46ce1c2018-12-17 16:34:48 +01002594 }
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002595
Paolo Bonzini07fb6172014-07-28 17:34:15 +02002596 /* We'll expose it all to Guest so we want to reduce
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002597 * chance of size changes.
Paolo Bonzini07fb6172014-07-28 17:34:15 +02002598 *
2599 * We used to align the tables to 4k, but of course this would
2600 * too simple to be enough. 4k turned out to be too small an
2601 * alignment very soon, and in fact it is almost impossible to
2602 * keep the table size stable for all (max_cpus, max_memory_slots)
Philippe Mathieu-Daudéea7a74a2024-02-28 09:30:01 +01002603 * combinations.
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002604 */
Philippe Mathieu-Daudéea7a74a2024-02-28 09:30:01 +01002605 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002606
Igor Mammedov0e9b9ed2016-05-19 15:19:25 +02002607 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002608
2609 /* Cleanup memory that's no longer used. */
2610 g_array_free(table_offsets, true);
Igor Mammedov8cdb99a2021-12-27 14:31:17 -05002611 g_free(slic_oem.id);
2612 g_free(slic_oem.table_id);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002613}
2614
Paolo Bonzini339240b2015-03-23 10:24:16 +01002615static void acpi_ram_update(MemoryRegion *mr, GArray *data)
Michael S. Tsirkin42d85902015-02-15 17:12:11 +01002616{
2617 uint32_t size = acpi_data_len(data);
2618
2619 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
Paolo Bonzini339240b2015-03-23 10:24:16 +01002620 memory_region_ram_resize(mr, size, &error_abort);
Michael S. Tsirkin42d85902015-02-15 17:12:11 +01002621
Paolo Bonzini339240b2015-03-23 10:24:16 +01002622 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2623 memory_region_set_dirty(mr, 0, size);
Michael S. Tsirkin42d85902015-02-15 17:12:11 +01002624}
2625
Gabriel L. Somlo3f8752b2015-11-05 09:32:49 -05002626static void acpi_build_update(void *build_opaque)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002627{
2628 AcpiBuildState *build_state = build_opaque;
2629 AcpiBuildTables tables;
2630
2631 /* No state to update or already patched? Nothing to do. */
2632 if (!build_state || build_state->patched) {
2633 return;
2634 }
2635 build_state->patched = 1;
2636
2637 acpi_build_tables_init(&tables);
2638
Igor Mammedov3d3ebca2016-02-26 14:59:22 +01002639 acpi_build(&tables, MACHINE(qdev_get_machine()));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002640
Paolo Bonzini339240b2015-03-23 10:24:16 +01002641 acpi_ram_update(build_state->table_mr, tables.table_data);
Michael S. Tsirkina1666142014-11-17 07:51:50 +02002642
Philippe Mathieu-Daudée00cb9a2024-02-28 09:55:42 +01002643 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
Michael S. Tsirkina1666142014-11-17 07:51:50 +02002644
Igor Mammedov0e9b9ed2016-05-19 15:19:25 +02002645 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002646 acpi_build_tables_cleanup(&tables, true);
2647}
2648
2649static void acpi_build_reset(void *build_opaque)
2650{
2651 AcpiBuildState *build_state = build_opaque;
2652 build_state->patched = 0;
2653}
2654
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002655static const VMStateDescription vmstate_acpi_build = {
2656 .name = "acpi_build",
2657 .version_id = 1,
2658 .minimum_version_id = 1,
Richard Henderson9231a012023-12-21 14:16:12 +11002659 .fields = (const VMStateField[]) {
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002660 VMSTATE_UINT8(patched, AcpiBuildState),
2661 VMSTATE_END_OF_LIST()
2662 },
2663};
2664
Eduardo Habkostfb306ff2015-12-11 16:42:26 -02002665void acpi_setup(void)
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002666{
Eduardo Habkostfb306ff2015-12-11 16:42:26 -02002667 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002668 X86MachineState *x86ms = X86_MACHINE(pcms);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002669 AcpiBuildTables tables;
2670 AcpiBuildState *build_state;
Ben Warrend03637b2017-02-16 15:15:36 -08002671 Object *vmgenid_dev;
Stefan Berger11fb99e2021-06-15 16:21:17 +02002672#ifdef CONFIG_TPM
Stefan Berger0fe24662019-01-15 02:27:51 +04002673 TPMIf *tpm;
2674 static FwCfgTPMConfig tpm_config;
Stefan Berger11fb99e2021-06-15 16:21:17 +02002675#endif
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002676
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002677 if (!x86ms->fw_cfg) {
Gonglei8b310fc2014-11-13 10:59:37 +08002678 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002679 return;
2680 }
2681
Wei Liu021746c2016-11-01 17:44:16 +00002682 if (!pcms->acpi_build_enabled) {
Gonglei8b310fc2014-11-13 10:59:37 +08002683 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002684 return;
2685 }
2686
Gerd Hoffmann17e89072020-03-20 11:01:36 +01002687 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
Gonglei8b310fc2014-11-13 10:59:37 +08002688 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
Michael S. Tsirkin81adc512013-11-07 14:12:05 +02002689 return;
2690 }
2691
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002692 build_state = g_malloc0(sizeof *build_state);
2693
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002694 acpi_build_tables_init(&tables);
Igor Mammedov3d3ebca2016-02-26 14:59:22 +01002695 acpi_build(&tables, MACHINE(pcms));
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002696
2697 /* Now expose it all to Guest */
Wei Yang82f76c62019-06-10 09:18:30 +08002698 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2699 build_state, tables.table_data,
David Hildenbrand6930ba02021-03-04 11:55:53 +01002700 ACPI_BUILD_TABLE_FILE);
Paolo Bonzini339240b2015-03-23 10:24:16 +01002701 assert(build_state->table_mr != NULL);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002702
Paolo Bonzini339240b2015-03-23 10:24:16 +01002703 build_state->linker_mr =
Wei Yang82f76c62019-06-10 09:18:30 +08002704 acpi_add_rom_blob(acpi_build_update, build_state,
David Hildenbrand6930ba02021-03-04 11:55:53 +01002705 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002706
Stefan Berger11fb99e2021-06-15 16:21:17 +02002707#ifdef CONFIG_TPM
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002708 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
Stefan Berger42a5b302014-10-24 13:21:04 -04002709 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2710
Stefan Berger0fe24662019-01-15 02:27:51 +04002711 tpm = tpm_find();
2712 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2713 tpm_config = (FwCfgTPMConfig) {
2714 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2715 .tpm_version = tpm_get_version(tpm),
Stefan Bergerac6dd312019-01-15 02:27:52 +04002716 .tpmppi_version = TPM_PPI_VERSION_1_30
Stefan Berger0fe24662019-01-15 02:27:51 +04002717 };
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002718 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
Stefan Berger0fe24662019-01-15 02:27:51 +04002719 &tpm_config, sizeof tpm_config);
2720 }
Stefan Berger11fb99e2021-06-15 16:21:17 +02002721#endif
Stefan Berger0fe24662019-01-15 02:27:51 +04002722
Ben Warrend03637b2017-02-16 15:15:36 -08002723 vmgenid_dev = find_vmgenid_dev();
2724 if (vmgenid_dev) {
Paolo Bonzinif0bb2762019-10-22 09:39:50 +02002725 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
Ben Warrend03637b2017-02-16 15:15:36 -08002726 tables.vmgenid);
2727 }
2728
Philippe Mathieu-Daudéaf8348f2024-02-28 09:54:16 +01002729 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2730 build_state, tables.rsdp,
2731 ACPI_BUILD_RSDP_FILE);
Michael S. Tsirkin72c194f2013-07-24 18:56:14 +03002732
2733 qemu_register_reset(acpi_build_reset, build_state);
2734 acpi_build_reset(build_state);
2735 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2736
2737 /* Cleanup tables but don't free the memory: we track it
2738 * in build_state.
2739 */
2740 acpi_build_tables_cleanup(&tables, false);
2741}