ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU SCI/SCIF serial port emulation |
| 3 | * |
| 4 | * Copyright (c) 2007 Magnus Damm |
| 5 | * |
| 6 | * Based on serial.c - QEMU 16450 UART emulation |
| 7 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 8 | * |
| 9 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 10 | * of this software and associated documentation files (the "Software"), to deal |
| 11 | * in the Software without restriction, including without limitation the rights |
| 12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 13 | * copies of the Software, and to permit persons to whom the Software is |
| 14 | * furnished to do so, subject to the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice shall be included in |
| 17 | * all copies or substantial portions of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 25 | * THE SOFTWARE. |
| 26 | */ |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 27 | #include "hw.h" |
| 28 | #include "sh.h" |
| 29 | #include "qemu-char.h" |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 30 | |
| 31 | //#define DEBUG_SERIAL |
| 32 | |
| 33 | #define SH_SERIAL_FLAG_TEND (1 << 0) |
| 34 | #define SH_SERIAL_FLAG_TDE (1 << 1) |
| 35 | #define SH_SERIAL_FLAG_RDF (1 << 2) |
| 36 | #define SH_SERIAL_FLAG_BRK (1 << 3) |
| 37 | #define SH_SERIAL_FLAG_DR (1 << 4) |
| 38 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 39 | #define SH_RX_FIFO_LENGTH (16) |
| 40 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 41 | typedef struct { |
| 42 | uint8_t smr; |
| 43 | uint8_t brr; |
| 44 | uint8_t scr; |
| 45 | uint8_t dr; /* ftdr / tdr */ |
| 46 | uint8_t sr; /* fsr / ssr */ |
| 47 | uint16_t fcr; |
| 48 | uint8_t sptr; |
| 49 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 50 | uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */ |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 51 | uint8_t rx_cnt; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 52 | uint8_t rx_tail; |
| 53 | uint8_t rx_head; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 54 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 55 | int freq; |
| 56 | int feat; |
| 57 | int flags; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 58 | int rtrg; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 59 | |
| 60 | CharDriverState *chr; |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 61 | |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 62 | qemu_irq eri; |
| 63 | qemu_irq rxi; |
| 64 | qemu_irq txi; |
| 65 | qemu_irq tei; |
| 66 | qemu_irq bri; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 67 | } sh_serial_state; |
| 68 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 69 | static void sh_serial_clear_fifo(sh_serial_state * s) |
| 70 | { |
| 71 | memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); |
| 72 | s->rx_cnt = 0; |
| 73 | s->rx_head = 0; |
| 74 | s->rx_tail = 0; |
| 75 | } |
| 76 | |
Aurelien Jarno | b7277ac | 2011-01-19 11:35:02 +0100 | [diff] [blame] | 77 | static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 78 | { |
| 79 | sh_serial_state *s = opaque; |
| 80 | unsigned char ch; |
| 81 | |
| 82 | #ifdef DEBUG_SERIAL |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 83 | printf("sh_serial: write offs=0x%02x val=0x%02x\n", |
| 84 | offs, val); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 85 | #endif |
| 86 | switch(offs) { |
| 87 | case 0x00: /* SMR */ |
| 88 | s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); |
| 89 | return; |
| 90 | case 0x04: /* BRR */ |
| 91 | s->brr = val; |
| 92 | return; |
| 93 | case 0x08: /* SCR */ |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 94 | /* TODO : For SH7751, SCIF mask should be 0xfb. */ |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 95 | s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 96 | if (!(val & (1 << 5))) |
| 97 | s->flags |= SH_SERIAL_FLAG_TEND; |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 98 | if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 99 | qemu_set_irq(s->txi, val & (1 << 7)); |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 100 | } |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 101 | if (!(val & (1 << 6))) { |
| 102 | qemu_set_irq(s->rxi, 0); |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 103 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 104 | return; |
| 105 | case 0x0c: /* FTDR / TDR */ |
| 106 | if (s->chr) { |
| 107 | ch = val; |
| 108 | qemu_chr_write(s->chr, &ch, 1); |
| 109 | } |
| 110 | s->dr = val; |
| 111 | s->flags &= ~SH_SERIAL_FLAG_TDE; |
| 112 | return; |
| 113 | #if 0 |
| 114 | case 0x14: /* FRDR / RDR */ |
| 115 | ret = 0; |
| 116 | break; |
| 117 | #endif |
| 118 | } |
| 119 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
| 120 | switch(offs) { |
| 121 | case 0x10: /* FSR */ |
| 122 | if (!(val & (1 << 6))) |
| 123 | s->flags &= ~SH_SERIAL_FLAG_TEND; |
| 124 | if (!(val & (1 << 5))) |
| 125 | s->flags &= ~SH_SERIAL_FLAG_TDE; |
| 126 | if (!(val & (1 << 4))) |
| 127 | s->flags &= ~SH_SERIAL_FLAG_BRK; |
| 128 | if (!(val & (1 << 1))) |
| 129 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
| 130 | if (!(val & (1 << 0))) |
| 131 | s->flags &= ~SH_SERIAL_FLAG_DR; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 132 | |
| 133 | if (!(val & (1 << 1)) || !(val & (1 << 0))) { |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 134 | if (s->rxi) { |
| 135 | qemu_set_irq(s->rxi, 0); |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 136 | } |
| 137 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 138 | return; |
| 139 | case 0x18: /* FCR */ |
| 140 | s->fcr = val; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 141 | switch ((val >> 6) & 3) { |
| 142 | case 0: |
| 143 | s->rtrg = 1; |
| 144 | break; |
| 145 | case 1: |
| 146 | s->rtrg = 4; |
| 147 | break; |
| 148 | case 2: |
| 149 | s->rtrg = 8; |
| 150 | break; |
| 151 | case 3: |
| 152 | s->rtrg = 14; |
| 153 | break; |
| 154 | } |
| 155 | if (val & (1 << 1)) { |
| 156 | sh_serial_clear_fifo(s); |
| 157 | s->sr &= ~(1 << 1); |
| 158 | } |
| 159 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 160 | return; |
| 161 | case 0x20: /* SPTR */ |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 162 | s->sptr = val & 0xf3; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 163 | return; |
| 164 | case 0x24: /* LSR */ |
| 165 | return; |
| 166 | } |
| 167 | } |
| 168 | else { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 169 | switch(offs) { |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 170 | #if 0 |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 171 | case 0x0c: |
| 172 | ret = s->dr; |
| 173 | break; |
| 174 | case 0x10: |
| 175 | ret = 0; |
| 176 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 177 | #endif |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 178 | case 0x1c: |
| 179 | s->sptr = val & 0x8f; |
| 180 | return; |
| 181 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs); |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 185 | abort(); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 186 | } |
| 187 | |
Aurelien Jarno | b7277ac | 2011-01-19 11:35:02 +0100 | [diff] [blame] | 188 | static uint32_t sh_serial_read(void *opaque, uint32_t offs) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 189 | { |
| 190 | sh_serial_state *s = opaque; |
| 191 | uint32_t ret = ~0; |
| 192 | |
| 193 | #if 0 |
| 194 | switch(offs) { |
| 195 | case 0x00: |
| 196 | ret = s->smr; |
| 197 | break; |
| 198 | case 0x04: |
| 199 | ret = s->brr; |
| 200 | break; |
| 201 | case 0x08: |
| 202 | ret = s->scr; |
| 203 | break; |
| 204 | case 0x14: |
| 205 | ret = 0; |
| 206 | break; |
| 207 | } |
| 208 | #endif |
| 209 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
| 210 | switch(offs) { |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 211 | case 0x00: /* SMR */ |
| 212 | ret = s->smr; |
| 213 | break; |
| 214 | case 0x08: /* SCR */ |
| 215 | ret = s->scr; |
| 216 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 217 | case 0x10: /* FSR */ |
| 218 | ret = 0; |
| 219 | if (s->flags & SH_SERIAL_FLAG_TEND) |
| 220 | ret |= (1 << 6); |
| 221 | if (s->flags & SH_SERIAL_FLAG_TDE) |
| 222 | ret |= (1 << 5); |
| 223 | if (s->flags & SH_SERIAL_FLAG_BRK) |
| 224 | ret |= (1 << 4); |
| 225 | if (s->flags & SH_SERIAL_FLAG_RDF) |
| 226 | ret |= (1 << 1); |
| 227 | if (s->flags & SH_SERIAL_FLAG_DR) |
| 228 | ret |= (1 << 0); |
| 229 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 230 | if (s->scr & (1 << 5)) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 231 | s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; |
| 232 | |
| 233 | break; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 234 | case 0x14: |
| 235 | if (s->rx_cnt > 0) { |
| 236 | ret = s->rx_fifo[s->rx_tail++]; |
| 237 | s->rx_cnt--; |
| 238 | if (s->rx_tail == SH_RX_FIFO_LENGTH) |
| 239 | s->rx_tail = 0; |
| 240 | if (s->rx_cnt < s->rtrg) |
| 241 | s->flags &= ~SH_SERIAL_FLAG_RDF; |
| 242 | } |
| 243 | break; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 244 | #if 0 |
| 245 | case 0x18: |
| 246 | ret = s->fcr; |
| 247 | break; |
| 248 | #endif |
| 249 | case 0x1c: |
| 250 | ret = s->rx_cnt; |
| 251 | break; |
| 252 | case 0x20: |
| 253 | ret = s->sptr; |
| 254 | break; |
| 255 | case 0x24: |
| 256 | ret = 0; |
| 257 | break; |
| 258 | } |
| 259 | } |
| 260 | else { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 261 | switch(offs) { |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 262 | #if 0 |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 263 | case 0x0c: |
| 264 | ret = s->dr; |
| 265 | break; |
| 266 | case 0x10: |
| 267 | ret = 0; |
| 268 | break; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 269 | case 0x14: |
| 270 | ret = s->rx_fifo[0]; |
| 271 | break; |
aurel32 | d1f193b | 2008-12-07 22:46:49 +0000 | [diff] [blame] | 272 | #endif |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 273 | case 0x1c: |
| 274 | ret = s->sptr; |
| 275 | break; |
| 276 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 277 | } |
| 278 | #ifdef DEBUG_SERIAL |
pbrook | 8da3ff1 | 2008-12-01 18:59:50 +0000 | [diff] [blame] | 279 | printf("sh_serial: read offs=0x%02x val=0x%x\n", |
| 280 | offs, ret); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 281 | #endif |
| 282 | |
| 283 | if (ret & ~((1 << 16) - 1)) { |
| 284 | fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs); |
Blue Swirl | 43dc2a6 | 2010-03-18 18:41:57 +0000 | [diff] [blame] | 285 | abort(); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | return ret; |
| 289 | } |
| 290 | |
| 291 | static int sh_serial_can_receive(sh_serial_state *s) |
| 292 | { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 293 | return s->scr & (1 << 4); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 294 | } |
| 295 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 296 | static void sh_serial_receive_break(sh_serial_state *s) |
| 297 | { |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 298 | if (s->feat & SH_SERIAL_FEAT_SCIF) |
| 299 | s->sr |= (1 << 4); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 300 | } |
| 301 | |
| 302 | static int sh_serial_can_receive1(void *opaque) |
| 303 | { |
| 304 | sh_serial_state *s = opaque; |
| 305 | return sh_serial_can_receive(s); |
| 306 | } |
| 307 | |
| 308 | static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) |
| 309 | { |
| 310 | sh_serial_state *s = opaque; |
Aurelien Jarno | b7d2b02 | 2011-01-19 11:38:36 +0100 | [diff] [blame] | 311 | |
| 312 | if (s->feat & SH_SERIAL_FEAT_SCIF) { |
| 313 | int i; |
| 314 | for (i = 0; i < size; i++) { |
| 315 | if (s->rx_cnt < SH_RX_FIFO_LENGTH) { |
| 316 | s->rx_fifo[s->rx_head++] = buf[i]; |
| 317 | if (s->rx_head == SH_RX_FIFO_LENGTH) { |
| 318 | s->rx_head = 0; |
| 319 | } |
| 320 | s->rx_cnt++; |
| 321 | if (s->rx_cnt >= s->rtrg) { |
| 322 | s->flags |= SH_SERIAL_FLAG_RDF; |
| 323 | if (s->scr & (1 << 6) && s->rxi) { |
| 324 | qemu_set_irq(s->rxi, 1); |
| 325 | } |
| 326 | } |
| 327 | } |
| 328 | } |
| 329 | } else { |
| 330 | s->rx_fifo[0] = buf[0]; |
| 331 | } |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | static void sh_serial_event(void *opaque, int event) |
| 335 | { |
| 336 | sh_serial_state *s = opaque; |
| 337 | if (event == CHR_EVENT_BREAK) |
| 338 | sh_serial_receive_break(s); |
| 339 | } |
| 340 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 341 | static CPUReadMemoryFunc * const sh_serial_readfn[] = { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 342 | &sh_serial_read, |
| 343 | &sh_serial_read, |
| 344 | &sh_serial_read, |
| 345 | }; |
| 346 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 347 | static CPUWriteMemoryFunc * const sh_serial_writefn[] = { |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 348 | &sh_serial_write, |
| 349 | &sh_serial_write, |
| 350 | &sh_serial_write, |
| 351 | }; |
| 352 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 353 | void sh_serial_init (target_phys_addr_t base, int feat, |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 354 | uint32_t freq, CharDriverState *chr, |
aurel32 | 4e7ed2d | 2008-11-21 21:06:51 +0000 | [diff] [blame] | 355 | qemu_irq eri_source, |
| 356 | qemu_irq rxi_source, |
| 357 | qemu_irq txi_source, |
| 358 | qemu_irq tei_source, |
| 359 | qemu_irq bri_source) |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 360 | { |
| 361 | sh_serial_state *s; |
| 362 | int s_io_memory; |
| 363 | |
| 364 | s = qemu_mallocz(sizeof(sh_serial_state)); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 365 | |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 366 | s->feat = feat; |
| 367 | s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 368 | s->rtrg = 1; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 369 | |
| 370 | s->smr = 0; |
| 371 | s->brr = 0xff; |
balrog | b7d35e6 | 2007-12-12 00:40:24 +0000 | [diff] [blame] | 372 | s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */ |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 373 | s->sptr = 0; |
| 374 | |
| 375 | if (feat & SH_SERIAL_FEAT_SCIF) { |
| 376 | s->fcr = 0; |
| 377 | } |
| 378 | else { |
| 379 | s->dr = 0xff; |
| 380 | } |
| 381 | |
aurel32 | 63242a0 | 2008-09-15 07:05:18 +0000 | [diff] [blame] | 382 | sh_serial_clear_fifo(s); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 383 | |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 384 | s_io_memory = cpu_register_io_memory(sh_serial_readfn, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 385 | sh_serial_writefn, s, |
| 386 | DEVICE_NATIVE_ENDIAN); |
balrog | 5c16736 | 2008-12-07 19:39:58 +0000 | [diff] [blame] | 387 | cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory); |
| 388 | cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory); |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 389 | |
| 390 | s->chr = chr; |
| 391 | |
| 392 | if (chr) |
| 393 | qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1, |
| 394 | sh_serial_event, s); |
aurel32 | bf5b742 | 2008-05-09 18:46:04 +0000 | [diff] [blame] | 395 | |
| 396 | s->eri = eri_source; |
| 397 | s->rxi = rxi_source; |
| 398 | s->txi = txi_source; |
| 399 | s->tei = tei_source; |
| 400 | s->bri = bri_source; |
ths | 2f062c7 | 2007-09-29 19:43:54 +0000 | [diff] [blame] | 401 | } |