blob: 191f4a60c6f7676e4f77f3c6377225833332f528 [file] [log] [blame]
ths2f062c72007-09-29 19:43:54 +00001/*
2 * QEMU SCI/SCIF serial port emulation
3 *
4 * Copyright (c) 2007 Magnus Damm
5 *
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
pbrook87ecb682007-11-17 17:14:51 +000027#include "hw.h"
28#include "sh.h"
29#include "qemu-char.h"
ths2f062c72007-09-29 19:43:54 +000030
31//#define DEBUG_SERIAL
32
33#define SH_SERIAL_FLAG_TEND (1 << 0)
34#define SH_SERIAL_FLAG_TDE (1 << 1)
35#define SH_SERIAL_FLAG_RDF (1 << 2)
36#define SH_SERIAL_FLAG_BRK (1 << 3)
37#define SH_SERIAL_FLAG_DR (1 << 4)
38
aurel3263242a02008-09-15 07:05:18 +000039#define SH_RX_FIFO_LENGTH (16)
40
ths2f062c72007-09-29 19:43:54 +000041typedef struct {
42 uint8_t smr;
43 uint8_t brr;
44 uint8_t scr;
45 uint8_t dr; /* ftdr / tdr */
46 uint8_t sr; /* fsr / ssr */
47 uint16_t fcr;
48 uint8_t sptr;
49
aurel3263242a02008-09-15 07:05:18 +000050 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
ths2f062c72007-09-29 19:43:54 +000051 uint8_t rx_cnt;
aurel3263242a02008-09-15 07:05:18 +000052 uint8_t rx_tail;
53 uint8_t rx_head;
ths2f062c72007-09-29 19:43:54 +000054
ths2f062c72007-09-29 19:43:54 +000055 int freq;
56 int feat;
57 int flags;
aurel3263242a02008-09-15 07:05:18 +000058 int rtrg;
ths2f062c72007-09-29 19:43:54 +000059
60 CharDriverState *chr;
aurel32bf5b7422008-05-09 18:46:04 +000061
aurel324e7ed2d2008-11-21 21:06:51 +000062 qemu_irq eri;
63 qemu_irq rxi;
64 qemu_irq txi;
65 qemu_irq tei;
66 qemu_irq bri;
ths2f062c72007-09-29 19:43:54 +000067} sh_serial_state;
68
aurel3263242a02008-09-15 07:05:18 +000069static void sh_serial_clear_fifo(sh_serial_state * s)
70{
71 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
72 s->rx_cnt = 0;
73 s->rx_head = 0;
74 s->rx_tail = 0;
75}
76
Aurelien Jarnob7277ac2011-01-19 11:35:02 +010077static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
ths2f062c72007-09-29 19:43:54 +000078{
79 sh_serial_state *s = opaque;
80 unsigned char ch;
81
82#ifdef DEBUG_SERIAL
pbrook8da3ff12008-12-01 18:59:50 +000083 printf("sh_serial: write offs=0x%02x val=0x%02x\n",
84 offs, val);
ths2f062c72007-09-29 19:43:54 +000085#endif
86 switch(offs) {
87 case 0x00: /* SMR */
88 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
89 return;
90 case 0x04: /* BRR */
91 s->brr = val;
92 return;
93 case 0x08: /* SCR */
aurel3263242a02008-09-15 07:05:18 +000094 /* TODO : For SH7751, SCIF mask should be 0xfb. */
aurel32bf5b7422008-05-09 18:46:04 +000095 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
ths2f062c72007-09-29 19:43:54 +000096 if (!(val & (1 << 5)))
97 s->flags |= SH_SERIAL_FLAG_TEND;
aurel32bf5b7422008-05-09 18:46:04 +000098 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
aurel324e7ed2d2008-11-21 21:06:51 +000099 qemu_set_irq(s->txi, val & (1 << 7));
aurel32bf5b7422008-05-09 18:46:04 +0000100 }
aurel324e7ed2d2008-11-21 21:06:51 +0000101 if (!(val & (1 << 6))) {
102 qemu_set_irq(s->rxi, 0);
aurel3263242a02008-09-15 07:05:18 +0000103 }
ths2f062c72007-09-29 19:43:54 +0000104 return;
105 case 0x0c: /* FTDR / TDR */
106 if (s->chr) {
107 ch = val;
108 qemu_chr_write(s->chr, &ch, 1);
109 }
110 s->dr = val;
111 s->flags &= ~SH_SERIAL_FLAG_TDE;
112 return;
113#if 0
114 case 0x14: /* FRDR / RDR */
115 ret = 0;
116 break;
117#endif
118 }
119 if (s->feat & SH_SERIAL_FEAT_SCIF) {
120 switch(offs) {
121 case 0x10: /* FSR */
122 if (!(val & (1 << 6)))
123 s->flags &= ~SH_SERIAL_FLAG_TEND;
124 if (!(val & (1 << 5)))
125 s->flags &= ~SH_SERIAL_FLAG_TDE;
126 if (!(val & (1 << 4)))
127 s->flags &= ~SH_SERIAL_FLAG_BRK;
128 if (!(val & (1 << 1)))
129 s->flags &= ~SH_SERIAL_FLAG_RDF;
130 if (!(val & (1 << 0)))
131 s->flags &= ~SH_SERIAL_FLAG_DR;
aurel3263242a02008-09-15 07:05:18 +0000132
133 if (!(val & (1 << 1)) || !(val & (1 << 0))) {
aurel324e7ed2d2008-11-21 21:06:51 +0000134 if (s->rxi) {
135 qemu_set_irq(s->rxi, 0);
aurel3263242a02008-09-15 07:05:18 +0000136 }
137 }
ths2f062c72007-09-29 19:43:54 +0000138 return;
139 case 0x18: /* FCR */
140 s->fcr = val;
aurel3263242a02008-09-15 07:05:18 +0000141 switch ((val >> 6) & 3) {
142 case 0:
143 s->rtrg = 1;
144 break;
145 case 1:
146 s->rtrg = 4;
147 break;
148 case 2:
149 s->rtrg = 8;
150 break;
151 case 3:
152 s->rtrg = 14;
153 break;
154 }
155 if (val & (1 << 1)) {
156 sh_serial_clear_fifo(s);
157 s->sr &= ~(1 << 1);
158 }
159
ths2f062c72007-09-29 19:43:54 +0000160 return;
161 case 0x20: /* SPTR */
aurel3263242a02008-09-15 07:05:18 +0000162 s->sptr = val & 0xf3;
ths2f062c72007-09-29 19:43:54 +0000163 return;
164 case 0x24: /* LSR */
165 return;
166 }
167 }
168 else {
ths2f062c72007-09-29 19:43:54 +0000169 switch(offs) {
aurel32d1f193b2008-12-07 22:46:49 +0000170#if 0
ths2f062c72007-09-29 19:43:54 +0000171 case 0x0c:
172 ret = s->dr;
173 break;
174 case 0x10:
175 ret = 0;
176 break;
ths2f062c72007-09-29 19:43:54 +0000177#endif
aurel32d1f193b2008-12-07 22:46:49 +0000178 case 0x1c:
179 s->sptr = val & 0x8f;
180 return;
181 }
ths2f062c72007-09-29 19:43:54 +0000182 }
183
184 fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
Blue Swirl43dc2a62010-03-18 18:41:57 +0000185 abort();
ths2f062c72007-09-29 19:43:54 +0000186}
187
Aurelien Jarnob7277ac2011-01-19 11:35:02 +0100188static uint32_t sh_serial_read(void *opaque, uint32_t offs)
ths2f062c72007-09-29 19:43:54 +0000189{
190 sh_serial_state *s = opaque;
191 uint32_t ret = ~0;
192
193#if 0
194 switch(offs) {
195 case 0x00:
196 ret = s->smr;
197 break;
198 case 0x04:
199 ret = s->brr;
200 break;
201 case 0x08:
202 ret = s->scr;
203 break;
204 case 0x14:
205 ret = 0;
206 break;
207 }
208#endif
209 if (s->feat & SH_SERIAL_FEAT_SCIF) {
210 switch(offs) {
aurel32bf5b7422008-05-09 18:46:04 +0000211 case 0x00: /* SMR */
212 ret = s->smr;
213 break;
214 case 0x08: /* SCR */
215 ret = s->scr;
216 break;
ths2f062c72007-09-29 19:43:54 +0000217 case 0x10: /* FSR */
218 ret = 0;
219 if (s->flags & SH_SERIAL_FLAG_TEND)
220 ret |= (1 << 6);
221 if (s->flags & SH_SERIAL_FLAG_TDE)
222 ret |= (1 << 5);
223 if (s->flags & SH_SERIAL_FLAG_BRK)
224 ret |= (1 << 4);
225 if (s->flags & SH_SERIAL_FLAG_RDF)
226 ret |= (1 << 1);
227 if (s->flags & SH_SERIAL_FLAG_DR)
228 ret |= (1 << 0);
229
aurel3263242a02008-09-15 07:05:18 +0000230 if (s->scr & (1 << 5))
ths2f062c72007-09-29 19:43:54 +0000231 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
232
233 break;
aurel3263242a02008-09-15 07:05:18 +0000234 case 0x14:
235 if (s->rx_cnt > 0) {
236 ret = s->rx_fifo[s->rx_tail++];
237 s->rx_cnt--;
238 if (s->rx_tail == SH_RX_FIFO_LENGTH)
239 s->rx_tail = 0;
240 if (s->rx_cnt < s->rtrg)
241 s->flags &= ~SH_SERIAL_FLAG_RDF;
242 }
243 break;
ths2f062c72007-09-29 19:43:54 +0000244#if 0
245 case 0x18:
246 ret = s->fcr;
247 break;
248#endif
249 case 0x1c:
250 ret = s->rx_cnt;
251 break;
252 case 0x20:
253 ret = s->sptr;
254 break;
255 case 0x24:
256 ret = 0;
257 break;
258 }
259 }
260 else {
ths2f062c72007-09-29 19:43:54 +0000261 switch(offs) {
aurel32d1f193b2008-12-07 22:46:49 +0000262#if 0
ths2f062c72007-09-29 19:43:54 +0000263 case 0x0c:
264 ret = s->dr;
265 break;
266 case 0x10:
267 ret = 0;
268 break;
aurel3263242a02008-09-15 07:05:18 +0000269 case 0x14:
270 ret = s->rx_fifo[0];
271 break;
aurel32d1f193b2008-12-07 22:46:49 +0000272#endif
ths2f062c72007-09-29 19:43:54 +0000273 case 0x1c:
274 ret = s->sptr;
275 break;
276 }
ths2f062c72007-09-29 19:43:54 +0000277 }
278#ifdef DEBUG_SERIAL
pbrook8da3ff12008-12-01 18:59:50 +0000279 printf("sh_serial: read offs=0x%02x val=0x%x\n",
280 offs, ret);
ths2f062c72007-09-29 19:43:54 +0000281#endif
282
283 if (ret & ~((1 << 16) - 1)) {
284 fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
Blue Swirl43dc2a62010-03-18 18:41:57 +0000285 abort();
ths2f062c72007-09-29 19:43:54 +0000286 }
287
288 return ret;
289}
290
291static int sh_serial_can_receive(sh_serial_state *s)
292{
aurel3263242a02008-09-15 07:05:18 +0000293 return s->scr & (1 << 4);
ths2f062c72007-09-29 19:43:54 +0000294}
295
ths2f062c72007-09-29 19:43:54 +0000296static void sh_serial_receive_break(sh_serial_state *s)
297{
aurel3263242a02008-09-15 07:05:18 +0000298 if (s->feat & SH_SERIAL_FEAT_SCIF)
299 s->sr |= (1 << 4);
ths2f062c72007-09-29 19:43:54 +0000300}
301
302static int sh_serial_can_receive1(void *opaque)
303{
304 sh_serial_state *s = opaque;
305 return sh_serial_can_receive(s);
306}
307
308static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
309{
310 sh_serial_state *s = opaque;
Aurelien Jarnob7d2b022011-01-19 11:38:36 +0100311
312 if (s->feat & SH_SERIAL_FEAT_SCIF) {
313 int i;
314 for (i = 0; i < size; i++) {
315 if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
316 s->rx_fifo[s->rx_head++] = buf[i];
317 if (s->rx_head == SH_RX_FIFO_LENGTH) {
318 s->rx_head = 0;
319 }
320 s->rx_cnt++;
321 if (s->rx_cnt >= s->rtrg) {
322 s->flags |= SH_SERIAL_FLAG_RDF;
323 if (s->scr & (1 << 6) && s->rxi) {
324 qemu_set_irq(s->rxi, 1);
325 }
326 }
327 }
328 }
329 } else {
330 s->rx_fifo[0] = buf[0];
331 }
ths2f062c72007-09-29 19:43:54 +0000332}
333
334static void sh_serial_event(void *opaque, int event)
335{
336 sh_serial_state *s = opaque;
337 if (event == CHR_EVENT_BREAK)
338 sh_serial_receive_break(s);
339}
340
Blue Swirld60efc62009-08-25 18:29:31 +0000341static CPUReadMemoryFunc * const sh_serial_readfn[] = {
ths2f062c72007-09-29 19:43:54 +0000342 &sh_serial_read,
343 &sh_serial_read,
344 &sh_serial_read,
345};
346
Blue Swirld60efc62009-08-25 18:29:31 +0000347static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
ths2f062c72007-09-29 19:43:54 +0000348 &sh_serial_write,
349 &sh_serial_write,
350 &sh_serial_write,
351};
352
Anthony Liguoric227f092009-10-01 16:12:16 -0500353void sh_serial_init (target_phys_addr_t base, int feat,
aurel32bf5b7422008-05-09 18:46:04 +0000354 uint32_t freq, CharDriverState *chr,
aurel324e7ed2d2008-11-21 21:06:51 +0000355 qemu_irq eri_source,
356 qemu_irq rxi_source,
357 qemu_irq txi_source,
358 qemu_irq tei_source,
359 qemu_irq bri_source)
ths2f062c72007-09-29 19:43:54 +0000360{
361 sh_serial_state *s;
362 int s_io_memory;
363
364 s = qemu_mallocz(sizeof(sh_serial_state));
ths2f062c72007-09-29 19:43:54 +0000365
ths2f062c72007-09-29 19:43:54 +0000366 s->feat = feat;
367 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
aurel3263242a02008-09-15 07:05:18 +0000368 s->rtrg = 1;
ths2f062c72007-09-29 19:43:54 +0000369
370 s->smr = 0;
371 s->brr = 0xff;
balrogb7d35e62007-12-12 00:40:24 +0000372 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
ths2f062c72007-09-29 19:43:54 +0000373 s->sptr = 0;
374
375 if (feat & SH_SERIAL_FEAT_SCIF) {
376 s->fcr = 0;
377 }
378 else {
379 s->dr = 0xff;
380 }
381
aurel3263242a02008-09-15 07:05:18 +0000382 sh_serial_clear_fifo(s);
ths2f062c72007-09-29 19:43:54 +0000383
Avi Kivity1eed09c2009-06-14 11:38:51 +0300384 s_io_memory = cpu_register_io_memory(sh_serial_readfn,
Alexander Graf2507c122010-12-08 12:05:37 +0100385 sh_serial_writefn, s,
386 DEVICE_NATIVE_ENDIAN);
balrog5c167362008-12-07 19:39:58 +0000387 cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
388 cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
ths2f062c72007-09-29 19:43:54 +0000389
390 s->chr = chr;
391
392 if (chr)
393 qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
394 sh_serial_event, s);
aurel32bf5b7422008-05-09 18:46:04 +0000395
396 s->eri = eri_source;
397 s->rxi = rxi_source;
398 s->txi = txi_source;
399 s->tei = tei_source;
400 s->bri = bri_source;
ths2f062c72007-09-29 19:43:54 +0000401}