blob: f75951b3ea4779e0805536e9084b0678d3654960 [file] [log] [blame]
Juan Quintela823e6752009-08-28 15:28:13 +02001/*
2 * QEMU PIIX4 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "hw.h"
26#include "pc.h"
27#include "pci.h"
28#include "isa.h"
29#include "sysbus.h"
30
31PCIDevice *piix4_dev;
32
33static void piix4_reset(void *opaque)
34{
35 PCIDevice *d = opaque;
36 uint8_t *pci_conf = d->config;
37
38 pci_conf[0x04] = 0x07; // master, memory and I/O
39 pci_conf[0x05] = 0x00;
40 pci_conf[0x06] = 0x00;
41 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
42 pci_conf[0x4c] = 0x4d;
43 pci_conf[0x4e] = 0x03;
44 pci_conf[0x4f] = 0x00;
45 pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
46 pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
47 pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
48 pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
49 pci_conf[0x69] = 0x02;
50 pci_conf[0x70] = 0x80;
51 pci_conf[0x76] = 0x0c;
52 pci_conf[0x77] = 0x0c;
53 pci_conf[0x78] = 0x02;
54 pci_conf[0x79] = 0x00;
55 pci_conf[0x80] = 0x00;
56 pci_conf[0x82] = 0x00;
57 pci_conf[0xa0] = 0x08;
58 pci_conf[0xa2] = 0x00;
59 pci_conf[0xa3] = 0x00;
60 pci_conf[0xa4] = 0x00;
61 pci_conf[0xa5] = 0x00;
62 pci_conf[0xa6] = 0x00;
63 pci_conf[0xa7] = 0x00;
64 pci_conf[0xa8] = 0x0f;
65 pci_conf[0xaa] = 0x00;
66 pci_conf[0xab] = 0x00;
67 pci_conf[0xac] = 0x00;
68 pci_conf[0xae] = 0x00;
69}
70
71static void piix_save(QEMUFile* f, void *opaque)
72{
73 PCIDevice *d = opaque;
74 pci_device_save(d, f);
75}
76
77static int piix_load(QEMUFile* f, void *opaque, int version_id)
78{
79 PCIDevice *d = opaque;
80 if (version_id != 2)
81 return -EINVAL;
82 return pci_device_load(d, f);
83}
84
85static int piix4_initfn(PCIDevice *d)
86{
87 uint8_t *pci_conf;
88
Stefan Weilae027ad2009-08-28 19:37:00 +020089 isa_bus_new(&d->qdev);
Juan Quintela823e6752009-08-28 15:28:13 +020090 register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
91
92 pci_conf = d->config;
93 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
94 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
95 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
96 pci_conf[PCI_HEADER_TYPE] =
97 PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
98
99 piix4_dev = d;
Juan Quintela823e6752009-08-28 15:28:13 +0200100 qemu_register_reset(piix4_reset, d);
101 return 0;
102}
103
104int piix4_init(PCIBus *bus, int devfn)
105{
106 PCIDevice *d;
107
108 d = pci_create_simple(bus, devfn, "PIIX4");
109 return d->devfn;
110}
111
112static PCIDeviceInfo piix4_info[] = {
113 {
114 .qdev.name = "PIIX4",
115 .qdev.desc = "ISA bridge",
116 .qdev.size = sizeof(PCIDevice),
117 .qdev.no_user = 1,
118 .init = piix4_initfn,
119 },{
120 /* end of list */
121 }
122};
123
124static void piix4_register(void)
125{
126 pci_qdev_register_many(piix4_info);
127}
128device_init(piix4_register);