Google Git
Sign in
qemu / qemu / 3f879f2f319379daeb65faa3677191ba4240b45c / . / hw / tricore / tc27x_soc.c
blob: ecd92717b50f38f6418269265f7ca905cd89d8a8 [file] [log] [blame]
Andreas Konopik34602f92020-11-09 17:50:55 +0100[diff] [blame]1/*
2 * Infineon tc27x SoC System emulation.
3 *
4 * Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
5 * Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "hw/sysbus.h"
Andreas Konopik34602f92020-11-09 17:50:55 +0100[diff] [blame]24#include "hw/loader.h"
25#include "qemu/units.h"
26#include "hw/misc/unimp.h"
Andreas Konopik34602f92020-11-09 17:50:55 +0100[diff] [blame]27
28#include "hw/tricore/tc27x_soc.h"
29#include "hw/tricore/triboard.h"
30
31const MemmapEntry tc27x_soc_memmap[] = {
32 [TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
33 [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
34 [TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
35 [TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
36 [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
37 [TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
38 [TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
39 [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
40 [TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
41 [TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
42 [TC27XD_PCACHE1] = { 0x60108000, 16 * KiB },
43 [TC27XD_PTAG1] = { 0x601C0000, 0x1800 },
44 [TC27XD_DSPR0] = { 0x70000000, 112 * KiB },
45 [TC27XD_PSPR0] = { 0x70100000, 24 * KiB },
46 [TC27XD_PCACHE0] = { 0x70106000, 8 * KiB },
47 [TC27XD_PTAG0] = { 0x701C0000, 0xC00 },
48 [TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB },
49 [TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB },
50 [TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB },
51 [TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB },
52 [TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB },
53 [TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB },
54 [TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 },
55 [TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 },
56 [TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB },
57 [TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB },
58 [TC27XD_OLDA_U] = { 0xAFE70000, 0x0 },
59 [TC27XD_BROM_U] = { 0xAFFF8000, 0x0 },
60 [TC27XD_LMURAM_U] = { 0xB0000000, 0x0 },
61 [TC27XD_EMEM_U] = { 0xBF000000, 0x0 },
62 [TC27XD_PSPRX] = { 0xC0000000, 0x0 },
63 [TC27XD_DSPRX] = { 0xD0000000, 0x0 },
64};
65
66/*
67 * Initialize the auxiliary ROM region @mr and map it into
68 * the memory map at @base.
69 */
70static void make_rom(MemoryRegion *mr, const char *name,
71 hwaddr base, hwaddr size)
72{
73 memory_region_init_rom(mr, NULL, name, size, &error_fatal);
74 memory_region_add_subregion(get_system_memory(), base, mr);
75}
76
77/*
78 * Initialize the auxiliary RAM region @mr and map it into
79 * the memory map at @base.
80 */
81static void make_ram(MemoryRegion *mr, const char *name,
82 hwaddr base, hwaddr size)
83{
84 memory_region_init_ram(mr, NULL, name, size, &error_fatal);
85 memory_region_add_subregion(get_system_memory(), base, mr);
86}
87
88/*
89 * Create an alias of an entire original MemoryRegion @orig
90 * located at @base in the memory map.
91 */
92static void make_alias(MemoryRegion *mr, const char *name,
93 MemoryRegion *orig, hwaddr base)
94{
95 memory_region_init_alias(mr, NULL, name, orig, 0,
96 memory_region_size(orig));
97 memory_region_add_subregion(get_system_memory(), base, mr);
98}
99
100static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc)
101{
102 TC27XSoCState *s = TC27X_SOC(dev_soc);
103 TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
104
105 make_ram(&s->cpu0mem.dspr, "CPU0.DSPR",
106 sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size);
107 make_ram(&s->cpu0mem.pspr, "CPU0.PSPR",
108 sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size);
109 make_ram(&s->cpu1mem.dspr, "CPU1.DSPR",
110 sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size);
111 make_ram(&s->cpu1mem.pspr, "CPU1.PSPR",
112 sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size);
113 make_ram(&s->cpu2mem.dspr, "CPU2.DSPR",
114 sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size);
115 make_ram(&s->cpu2mem.pspr, "CPU2.PSPR",
116 sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size);
117
118 /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
119 make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE",
120 sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size);
121 make_ram(&s->cpu2mem.dtag, "CPU2.DTAG",
122 sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size);
123 make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE",
124 sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size);
125 make_ram(&s->cpu2mem.ptag, "CPU2.PTAG",
126 sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size);
127
128 make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE",
129 sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size);
130 make_ram(&s->cpu1mem.dtag, "CPU1.DTAG",
131 sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size);
132 make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE",
133 sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size);
134 make_ram(&s->cpu1mem.ptag, "CPU1.PTAG",
135 sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size);
136
137 make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE",
138 sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size);
139 make_ram(&s->cpu0mem.ptag, "CPU0.PTAG",
140 sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size);
141
142 /*
143 * TriCore QEMU executes CPU0 only, thus it is sufficient to map
144 * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
145 */
146 make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
147 sc->memmap[TC27XD_PSPRX].base);
148 make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
149 sc->memmap[TC27XD_DSPRX].base);
150
151 make_ram(&s->flashmem.pflash0_c, "PF0",
152 sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size);
153 make_ram(&s->flashmem.pflash1_c, "PF1",
154 sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size);
155 make_ram(&s->flashmem.dflash0, "DF0",
156 sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size);
157 make_ram(&s->flashmem.dflash1, "DF1",
158 sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size);
159 make_ram(&s->flashmem.olda_c, "OLDA",
160 sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size);
161 make_rom(&s->flashmem.brom_c, "BROM",
162 sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size);
163 make_ram(&s->flashmem.lmuram_c, "LMURAM",
164 sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size);
165 make_ram(&s->flashmem.emem_c, "EMEM",
166 sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size);
167
168 make_alias(&s->flashmem.pflash0_u, "PF0.U", &s->flashmem.pflash0_c,
169 sc->memmap[TC27XD_PFLASH0_U].base);
170 make_alias(&s->flashmem.pflash1_u, "PF1.U", &s->flashmem.pflash1_c,
171 sc->memmap[TC27XD_PFLASH1_U].base);
172 make_alias(&s->flashmem.olda_u, "OLDA.U", &s->flashmem.olda_c,
173 sc->memmap[TC27XD_OLDA_U].base);
174 make_alias(&s->flashmem.brom_u, "BROM.U", &s->flashmem.brom_c,
175 sc->memmap[TC27XD_BROM_U].base);
176 make_alias(&s->flashmem.lmuram_u, "LMURAM.U", &s->flashmem.lmuram_c,
177 sc->memmap[TC27XD_LMURAM_U].base);
178 make_alias(&s->flashmem.emem_u, "EMEM.U", &s->flashmem.emem_c,
179 sc->memmap[TC27XD_EMEM_U].base);
180}
181
182static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp)
183{
184 TC27XSoCState *s = TC27X_SOC(dev_soc);
185 Error *err = NULL;
186
187 qdev_realize(DEVICE(&s->cpu), NULL, &err);
188 if (err) {
189 error_propagate(errp, err);
190 return;
191 }
192
193 tc27x_soc_init_memory_mapping(dev_soc);
194}
195
196static void tc27x_soc_init(Object *obj)
197{
198 TC27XSoCState *s = TC27X_SOC(obj);
199 TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
200
201 object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type);
202}
203
204static Property tc27x_soc_properties[] = {
205 DEFINE_PROP_END_OF_LIST(),
206};
207
208static void tc27x_soc_class_init(ObjectClass *klass, void *data)
209{
210 DeviceClass *dc = DEVICE_CLASS(klass);
211
212 dc->realize = tc27x_soc_realize;
213 device_class_set_props(dc, tc27x_soc_properties);
214}
215
216static void tc277d_soc_class_init(ObjectClass *oc, void *data)
217{
218 TC27XSoCClass *sc = TC27X_SOC_CLASS(oc);
219
220 sc->name = "tc277d-soc";
221 sc->cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
222 sc->memmap = tc27x_soc_memmap;
223 sc->num_cpus = 1;
224}
225
226static const TypeInfo tc27x_soc_types[] = {
227 {
228 .name = "tc277d-soc",
229 .parent = TYPE_TC27X_SOC,
230 .class_init = tc277d_soc_class_init,
231 }, {
232 .name = TYPE_TC27X_SOC,
233 .parent = TYPE_SYS_BUS_DEVICE,
234 .instance_size = sizeof(TC27XSoCState),
235 .instance_init = tc27x_soc_init,
236 .class_size = sizeof(TC27XSoCClass),
237 .class_init = tc27x_soc_class_init,
238 .abstract = true,
239 },
240};
241
242DEFINE_TYPES(tc27x_soc_types)