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Max Filippova2e67072014-02-10 20:20:52 +04001#include "macros.inc"
Max Filippov7d890b42011-09-06 03:55:57 +04002
Max Filippov72b3b8f2016-09-05 20:55:13 -07003#define CCOUNT_SHIFT 4
4#define WAIT_LOOPS 20
Max Filippov02a5a4a2019-02-18 06:55:15 -08005#define level1 kernel
6#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
Max Filippov72b3b8f2016-09-05 20:55:13 -07007
8.macro make_ccount_delta target, delta
9 rsr \delta, ccount
10 rsr \target, ccount
11 sub \delta, \target, \delta
12 slli \delta, \delta, CCOUNT_SHIFT
13 add \target, \target, \delta
14.endm
15
Max Filippov7d890b42011-09-06 03:55:57 +040016test_suite timer
17
Max Filippov02a5a4a2019-02-18 06:55:15 -080018#if XCHAL_HAVE_CCOUNT
19
Max Filippov7d890b42011-09-06 03:55:57 +040020test ccount
21 rsr a3, ccount
22 rsr a4, ccount
Max Filippov72b3b8f2016-09-05 20:55:13 -070023 assert ne, a3, a4
Max Filippov7d890b42011-09-06 03:55:57 +040024test_end
25
Max Filippov0a362d02017-01-15 08:42:31 -080026test ccount_write
27 rsr a3, ccount
28 rsr a4, ccount
29 sub a4, a4, a3
30 movi a2, 0x12345678
31 wsr a2, ccount
32 esync
33 rsr a3, ccount
34 sub a3, a3, a2
35 slli a4, a4, 2
36 assert ltu, a3, a4
37test_end
38
Max Filippov02a5a4a2019-02-18 06:55:15 -080039#if XCHAL_NUM_TIMERS
40
Max Filippov4be4c5b2022-04-27 10:06:00 -070041#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
42#define TIMER0_VECTOR kernel
43#else
44#define TIMER0_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT))
45#endif
46
47#if XCHAL_NUM_TIMERS > 1
48#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
49#define TIMER1_VECTOR kernel
50#else
51#define TIMER1_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT))
52#endif
53#endif
54
55#if XCHAL_NUM_TIMERS > 2
56#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
57#define TIMER2_VECTOR kernel
58#else
59#define TIMER2_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT))
60#endif
61#endif
62
Max Filippov0a362d02017-01-15 08:42:31 -080063test ccount_update_deadline
64 movi a2, 0
65 wsr a2, intenable
66 rsr a2, interrupt
67 wsr a2, intclear
68 movi a2, 0
Max Filippov02a5a4a2019-02-18 06:55:15 -080069#if XCHAL_NUM_TIMERS > 1
Max Filippov0a362d02017-01-15 08:42:31 -080070 wsr a2, ccompare1
Max Filippov02a5a4a2019-02-18 06:55:15 -080071#endif
72#if XCHAL_NUM_TIMERS > 2
Max Filippov0a362d02017-01-15 08:42:31 -080073 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -080074#endif
Max Filippov0a362d02017-01-15 08:42:31 -080075 movi a2, 0x12345678
76 wsr a2, ccompare0
77 rsr a3, interrupt
78 assert eqi, a3, 0
79 movi a2, 0x12345677
80 wsr a2, ccount
81 esync
82 nop
83 rsr a2, interrupt
84 movi a3, 1 << XCHAL_TIMER0_INTERRUPT
85 assert eq, a2, a3
86test_end
87
Max Filippov7d890b42011-09-06 03:55:57 +040088test ccompare
89 movi a2, 0
90 wsr a2, intenable
91 rsr a2, interrupt
92 wsr a2, intclear
Max Filippov890c6332011-10-10 06:25:04 +040093 movi a2, 0
Max Filippov02a5a4a2019-02-18 06:55:15 -080094#if XCHAL_NUM_TIMERS > 1
Max Filippov7d890b42011-09-06 03:55:57 +040095 wsr a2, ccompare1
Max Filippov02a5a4a2019-02-18 06:55:15 -080096#endif
97#if XCHAL_NUM_TIMERS > 2
Max Filippov7d890b42011-09-06 03:55:57 +040098 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -080099#endif
Max Filippov7d890b42011-09-06 03:55:57 +0400100
Max Filippov72b3b8f2016-09-05 20:55:13 -0700101 make_ccount_delta a2, a15
Max Filippov7d890b42011-09-06 03:55:57 +0400102 wsr a2, ccompare0
Max Filippov7d890b42011-09-06 03:55:57 +04001031:
Max Filippov72b3b8f2016-09-05 20:55:13 -0700104 rsr a3, interrupt
105 rsr a4, ccount
106 rsr a5, interrupt
107 sub a4, a4, a2
108 bgez a4, 2f
109 assert eqi, a3, 0
110 j 1b
Max Filippov7d890b42011-09-06 03:55:57 +04001112:
Max Filippov72b3b8f2016-09-05 20:55:13 -0700112 assert nei, a5, 0
Max Filippov7d890b42011-09-06 03:55:57 +0400113test_end
114
115test ccompare0_interrupt
Max Filippov4be4c5b2022-04-27 10:06:00 -0700116 set_vector TIMER0_VECTOR, 2f
Max Filippov7d890b42011-09-06 03:55:57 +0400117 movi a2, 0
118 wsr a2, intenable
119 rsr a2, interrupt
120 wsr a2, intclear
Max Filippov890c6332011-10-10 06:25:04 +0400121 movi a2, 0
Max Filippov02a5a4a2019-02-18 06:55:15 -0800122#if XCHAL_NUM_TIMERS > 1
Max Filippov7d890b42011-09-06 03:55:57 +0400123 wsr a2, ccompare1
Max Filippov02a5a4a2019-02-18 06:55:15 -0800124#endif
125#if XCHAL_NUM_TIMERS > 2
Max Filippov7d890b42011-09-06 03:55:57 +0400126 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -0800127#endif
Max Filippov7d890b42011-09-06 03:55:57 +0400128
Max Filippov72b3b8f2016-09-05 20:55:13 -0700129 movi a3, WAIT_LOOPS
130 make_ccount_delta a2, a15
Max Filippov7d890b42011-09-06 03:55:57 +0400131 wsr a2, ccompare0
132 rsync
133 rsr a2, interrupt
134 assert eqi, a2, 0
135
Max Filippov4f89b412017-01-14 19:58:55 -0800136 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
Max Filippov7d890b42011-09-06 03:55:57 +0400137 wsr a2, intenable
138 rsil a2, 0
Max Filippov7d890b42011-09-06 03:55:57 +04001391:
Max Filippove120c832022-04-25 18:12:53 -0700140 addi a3, a3, -1
141 bnez a3, 1b
Max Filippov7d890b42011-09-06 03:55:57 +0400142 test_fail
1432:
Max Filippov4be4c5b2022-04-27 10:06:00 -0700144#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
Max Filippov7d890b42011-09-06 03:55:57 +0400145 rsr a2, exccause
146 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
Max Filippov02a5a4a2019-02-18 06:55:15 -0800147#endif
Max Filippov4be4c5b2022-04-27 10:06:00 -0700148test_end
Max Filippov02a5a4a2019-02-18 06:55:15 -0800149
150#if XCHAL_NUM_TIMERS > 1
Max Filippov7d890b42011-09-06 03:55:57 +0400151
152test ccompare1_interrupt
Max Filippov4be4c5b2022-04-27 10:06:00 -0700153 set_vector TIMER1_VECTOR, 2f
Max Filippov7d890b42011-09-06 03:55:57 +0400154 movi a2, 0
155 wsr a2, intenable
156 rsr a2, interrupt
157 wsr a2, intclear
Max Filippov890c6332011-10-10 06:25:04 +0400158 movi a2, 0
Max Filippov7d890b42011-09-06 03:55:57 +0400159 wsr a2, ccompare0
Max Filippov02a5a4a2019-02-18 06:55:15 -0800160#if XCHAL_NUM_TIMERS > 2
Max Filippov7d890b42011-09-06 03:55:57 +0400161 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -0800162#endif
Max Filippov7d890b42011-09-06 03:55:57 +0400163
Max Filippov72b3b8f2016-09-05 20:55:13 -0700164 movi a3, WAIT_LOOPS
165 make_ccount_delta a2, a15
Max Filippov7d890b42011-09-06 03:55:57 +0400166 wsr a2, ccompare1
167 rsync
168 rsr a2, interrupt
169 assert eqi, a2, 0
Max Filippov4f89b412017-01-14 19:58:55 -0800170 movi a2, 1 << XCHAL_TIMER1_INTERRUPT
Max Filippov7d890b42011-09-06 03:55:57 +0400171 wsr a2, intenable
Max Filippov02a5a4a2019-02-18 06:55:15 -0800172 rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
Max Filippov7d890b42011-09-06 03:55:57 +04001731:
Max Filippove120c832022-04-25 18:12:53 -0700174 addi a3, a3, -1
175 bnez a3, 1b
Max Filippov7d890b42011-09-06 03:55:57 +0400176 test_fail
1772:
Max Filippov4be4c5b2022-04-27 10:06:00 -0700178#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
179 rsr a2, exccause
180 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
181#endif
Max Filippov7d890b42011-09-06 03:55:57 +0400182test_end
183
Max Filippov02a5a4a2019-02-18 06:55:15 -0800184#endif
185#if XCHAL_NUM_TIMERS > 2
186
Max Filippov7d890b42011-09-06 03:55:57 +0400187test ccompare2_interrupt
Max Filippov4be4c5b2022-04-27 10:06:00 -0700188 set_vector TIMER2_VECTOR, 2f
Max Filippov7d890b42011-09-06 03:55:57 +0400189 movi a2, 0
190 wsr a2, intenable
191 rsr a2, interrupt
192 wsr a2, intclear
Max Filippov890c6332011-10-10 06:25:04 +0400193 movi a2, 0
Max Filippov7d890b42011-09-06 03:55:57 +0400194 wsr a2, ccompare0
195 wsr a2, ccompare1
196
Max Filippov72b3b8f2016-09-05 20:55:13 -0700197 movi a3, WAIT_LOOPS
198 make_ccount_delta a2, a15
Max Filippov7d890b42011-09-06 03:55:57 +0400199 wsr a2, ccompare2
200 rsync
201 rsr a2, interrupt
202 assert eqi, a2, 0
Max Filippov4f89b412017-01-14 19:58:55 -0800203 movi a2, 1 << XCHAL_TIMER2_INTERRUPT
Max Filippov7d890b42011-09-06 03:55:57 +0400204 wsr a2, intenable
Max Filippov02a5a4a2019-02-18 06:55:15 -0800205 rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
Max Filippov7d890b42011-09-06 03:55:57 +04002061:
Max Filippove120c832022-04-25 18:12:53 -0700207 addi a3, a3, -1
208 bnez a3, 1b
Max Filippov7d890b42011-09-06 03:55:57 +0400209 test_fail
2102:
Max Filippov4be4c5b2022-04-27 10:06:00 -0700211#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
212 rsr a2, exccause
213 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
214#endif
Max Filippov7d890b42011-09-06 03:55:57 +0400215test_end
216
Max Filippov02a5a4a2019-02-18 06:55:15 -0800217#endif
218
Max Filippov890c6332011-10-10 06:25:04 +0400219test ccompare_interrupt_masked
Max Filippov4be4c5b2022-04-27 10:06:00 -0700220 set_vector TIMER0_VECTOR, 2f
Max Filippov890c6332011-10-10 06:25:04 +0400221 movi a2, 0
222 wsr a2, intenable
223 rsr a2, interrupt
224 wsr a2, intclear
225 movi a2, 0
Max Filippov02a5a4a2019-02-18 06:55:15 -0800226#if XCHAL_NUM_TIMERS > 2
Max Filippov890c6332011-10-10 06:25:04 +0400227 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -0800228#endif
Max Filippov890c6332011-10-10 06:25:04 +0400229
Max Filippove120c832022-04-25 18:12:53 -0700230 movi a3, WAIT_LOOPS
Max Filippov72b3b8f2016-09-05 20:55:13 -0700231 make_ccount_delta a2, a15
Max Filippov02a5a4a2019-02-18 06:55:15 -0800232#if XCHAL_NUM_TIMERS > 1
Max Filippov890c6332011-10-10 06:25:04 +0400233 wsr a2, ccompare1
Max Filippov02a5a4a2019-02-18 06:55:15 -0800234#endif
Max Filippov72b3b8f2016-09-05 20:55:13 -0700235 add a2, a2, a15
Max Filippov890c6332011-10-10 06:25:04 +0400236 wsr a2, ccompare0
237 rsync
238 rsr a2, interrupt
239 assert eqi, a2, 0
240
Max Filippov4f89b412017-01-14 19:58:55 -0800241 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
Max Filippov890c6332011-10-10 06:25:04 +0400242 wsr a2, intenable
243 rsil a2, 0
Max Filippov890c6332011-10-10 06:25:04 +04002441:
Max Filippove120c832022-04-25 18:12:53 -0700245 addi a3, a3, -1
246 bnez a3, 1b
247
Max Filippov890c6332011-10-10 06:25:04 +0400248 test_fail
2492:
Max Filippov4be4c5b2022-04-27 10:06:00 -0700250#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
Max Filippov890c6332011-10-10 06:25:04 +0400251 rsr a2, exccause
252 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
Max Filippov4be4c5b2022-04-27 10:06:00 -0700253#endif
Max Filippov890c6332011-10-10 06:25:04 +0400254test_end
255
256test ccompare_interrupt_masked_waiti
Max Filippov4be4c5b2022-04-27 10:06:00 -0700257 set_vector TIMER0_VECTOR, 2f
Max Filippov890c6332011-10-10 06:25:04 +0400258 movi a2, 0
259 wsr a2, intenable
260 rsr a2, interrupt
261 wsr a2, intclear
262 movi a2, 0
Max Filippov02a5a4a2019-02-18 06:55:15 -0800263#if XCHAL_NUM_TIMERS > 2
Max Filippov890c6332011-10-10 06:25:04 +0400264 wsr a2, ccompare2
Max Filippov02a5a4a2019-02-18 06:55:15 -0800265#endif
Max Filippov890c6332011-10-10 06:25:04 +0400266
Max Filippov72b3b8f2016-09-05 20:55:13 -0700267 make_ccount_delta a2, a15
Max Filippov02a5a4a2019-02-18 06:55:15 -0800268#if XCHAL_NUM_TIMERS > 1
Max Filippov890c6332011-10-10 06:25:04 +0400269 wsr a2, ccompare1
Max Filippov02a5a4a2019-02-18 06:55:15 -0800270#endif
Max Filippov72b3b8f2016-09-05 20:55:13 -0700271 add a2, a2, a15
Max Filippov890c6332011-10-10 06:25:04 +0400272 wsr a2, ccompare0
273 rsync
274 rsr a2, interrupt
275 assert eqi, a2, 0
276
Max Filippov4f89b412017-01-14 19:58:55 -0800277 movi a2, 1 << XCHAL_TIMER0_INTERRUPT
Max Filippov890c6332011-10-10 06:25:04 +0400278 wsr a2, intenable
279 waiti 0
280 test_fail
2812:
Max Filippov4be4c5b2022-04-27 10:06:00 -0700282#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
Max Filippov890c6332011-10-10 06:25:04 +0400283 rsr a2, exccause
284 assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
Max Filippov4be4c5b2022-04-27 10:06:00 -0700285#endif
Max Filippov890c6332011-10-10 06:25:04 +0400286test_end
287
Max Filippov02a5a4a2019-02-18 06:55:15 -0800288#endif
289#endif
290
Max Filippov7d890b42011-09-06 03:55:57 +0400291test_suite_end