Alexander Graf | f570c61 | 2013-09-03 20:12:03 +0100 | [diff] [blame] | 1 | #ifndef TARGET_ARM_TRANSLATE_H |
| 2 | #define TARGET_ARM_TRANSLATE_H |
| 3 | |
| 4 | /* internal defines */ |
| 5 | typedef struct DisasContext { |
| 6 | target_ulong pc; |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 7 | uint32_t insn; |
Alexander Graf | f570c61 | 2013-09-03 20:12:03 +0100 | [diff] [blame] | 8 | int is_jmp; |
| 9 | /* Nonzero if this instruction has been conditionally skipped. */ |
| 10 | int condjmp; |
| 11 | /* The label that will be jumped to when the instruction is skipped. */ |
| 12 | int condlabel; |
| 13 | /* Thumb-2 conditional execution bits. */ |
| 14 | int condexec_mask; |
| 15 | int condexec_cond; |
| 16 | struct TranslationBlock *tb; |
| 17 | int singlestep_enabled; |
| 18 | int thumb; |
| 19 | int bswap_code; |
| 20 | #if !defined(CONFIG_USER_ONLY) |
| 21 | int user; |
| 22 | #endif |
Peter Maydell | c1e3781 | 2015-02-05 13:37:23 +0000 | [diff] [blame] | 23 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ |
Sergey Fedorov | 3f342b9 | 2014-12-11 12:07:48 +0000 | [diff] [blame] | 24 | bool ns; /* Use non-secure CPREG bank on access */ |
Peter Maydell | 8c6afa6 | 2014-04-15 19:18:39 +0100 | [diff] [blame] | 25 | bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ |
| 26 | bool vfp_enabled; /* FP enabled via FPSCR.EN */ |
Alexander Graf | f570c61 | 2013-09-03 20:12:03 +0100 | [diff] [blame] | 27 | int vec_len; |
| 28 | int vec_stride; |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 29 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI |
| 30 | * so that top level loop can generate correct syndrome information. |
| 31 | */ |
| 32 | uint32_t svc_imm; |
Alexander Graf | 3926cc8 | 2013-09-03 20:12:09 +0100 | [diff] [blame] | 33 | int aarch64; |
Greg Bellows | dcbff19 | 2014-10-24 12:19:14 +0100 | [diff] [blame] | 34 | int current_el; |
Peter Maydell | 60322b3 | 2014-01-04 22:15:44 +0000 | [diff] [blame] | 35 | GHashTable *cp_regs; |
Peter Maydell | a984e42 | 2014-03-17 16:31:47 +0000 | [diff] [blame] | 36 | uint64_t features; /* CPU features bits */ |
Peter Maydell | 90e4963 | 2014-04-15 19:18:40 +0100 | [diff] [blame] | 37 | /* Because unallocated encodings generate different exception syndrome |
| 38 | * information from traps due to FP being disabled, we can't do a single |
| 39 | * "is fp access disabled" check at a high level in the decode tree. |
| 40 | * To help in catching bugs where the access check was forgotten in some |
| 41 | * code path, we set this flag when the access check is done, and assert |
| 42 | * that it is set at the point where we actually touch the FP regs. |
| 43 | */ |
| 44 | bool fp_access_checked; |
Peter Maydell | 7ea47fe | 2014-08-19 18:56:26 +0100 | [diff] [blame] | 45 | /* ARMv8 single-step state (this is distinct from the QEMU gdbstub |
| 46 | * single-step support). |
| 47 | */ |
| 48 | bool ss_active; |
| 49 | bool pstate_ss; |
| 50 | /* True if the insn just emitted was a load-exclusive instruction |
| 51 | * (necessary for syndrome information for single step exceptions), |
| 52 | * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. |
| 53 | */ |
| 54 | bool is_ldex; |
| 55 | /* True if a single-step exception will be taken to the current EL */ |
| 56 | bool ss_same_el; |
Peter Maydell | c0f4af1 | 2014-09-29 18:48:48 +0100 | [diff] [blame] | 57 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |
| 58 | int c15_cpar; |
Alexander Graf | 11e169d | 2013-12-17 19:42:32 +0000 | [diff] [blame] | 59 | #define TMP_A64_MAX 16 |
| 60 | int tmp_a64_count; |
| 61 | TCGv_i64 tmp_a64[TMP_A64_MAX]; |
Alexander Graf | f570c61 | 2013-09-03 20:12:03 +0100 | [diff] [blame] | 62 | } DisasContext; |
| 63 | |
Alexander Graf | 3407ad0 | 2013-09-03 20:12:04 +0100 | [diff] [blame] | 64 | extern TCGv_ptr cpu_env; |
| 65 | |
Peter Maydell | a984e42 | 2014-03-17 16:31:47 +0000 | [diff] [blame] | 66 | static inline int arm_dc_feature(DisasContext *dc, int feature) |
| 67 | { |
| 68 | return (dc->features & (1ULL << feature)) != 0; |
| 69 | } |
| 70 | |
Edgar E. Iglesias | 9d4c4e8 | 2014-05-27 17:09:50 +0100 | [diff] [blame] | 71 | static inline int get_mem_index(DisasContext *s) |
| 72 | { |
Peter Maydell | c1e3781 | 2015-02-05 13:37:23 +0000 | [diff] [blame] | 73 | return s->mmu_idx; |
Edgar E. Iglesias | 9d4c4e8 | 2014-05-27 17:09:50 +0100 | [diff] [blame] | 74 | } |
| 75 | |
Peter Maydell | 40f860c | 2013-12-17 19:42:31 +0000 | [diff] [blame] | 76 | /* target-specific extra values for is_jmp */ |
| 77 | /* These instructions trap after executing, so the A32/T32 decoder must |
| 78 | * defer them until after the conditional execution state has been updated. |
| 79 | * WFI also needs special handling when single-stepping. |
| 80 | */ |
| 81 | #define DISAS_WFI 4 |
| 82 | #define DISAS_SWI 5 |
| 83 | /* For instructions which unconditionally cause an exception we can skip |
| 84 | * emitting unreachable code at the end of the TB in the A64 decoder |
| 85 | */ |
| 86 | #define DISAS_EXC 6 |
Peter Maydell | 72c1d3a | 2014-03-10 14:56:30 +0000 | [diff] [blame] | 87 | /* WFE */ |
| 88 | #define DISAS_WFE 7 |
Peter Maydell | 37e6456 | 2014-10-24 12:19:13 +0100 | [diff] [blame] | 89 | #define DISAS_HVC 8 |
| 90 | #define DISAS_SMC 9 |
Peter Maydell | 40f860c | 2013-12-17 19:42:31 +0000 | [diff] [blame] | 91 | |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 92 | #ifdef TARGET_AARCH64 |
| 93 | void a64_translate_init(void); |
Peter Maydell | 40f860c | 2013-12-17 19:42:31 +0000 | [diff] [blame] | 94 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
| 95 | TranslationBlock *tb, |
| 96 | bool search_pc); |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 97 | void gen_a64_set_pc_im(uint64_t val); |
Peter Maydell | 1773111 | 2014-04-15 19:19:15 +0100 | [diff] [blame] | 98 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
| 99 | fprintf_function cpu_fprintf, int flags); |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 100 | #else |
| 101 | static inline void a64_translate_init(void) |
| 102 | { |
| 103 | } |
| 104 | |
Peter Maydell | 40f860c | 2013-12-17 19:42:31 +0000 | [diff] [blame] | 105 | static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
| 106 | TranslationBlock *tb, |
| 107 | bool search_pc) |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 108 | { |
| 109 | } |
| 110 | |
| 111 | static inline void gen_a64_set_pc_im(uint64_t val) |
| 112 | { |
| 113 | } |
Peter Maydell | 1773111 | 2014-04-15 19:19:15 +0100 | [diff] [blame] | 114 | |
| 115 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
| 116 | fprintf_function cpu_fprintf, |
| 117 | int flags) |
| 118 | { |
| 119 | } |
Alexander Graf | 14ade10 | 2013-09-03 20:12:10 +0100 | [diff] [blame] | 120 | #endif |
| 121 | |
Alexander Graf | 39fb730 | 2013-12-17 19:42:33 +0000 | [diff] [blame] | 122 | void arm_gen_test_cc(int cc, int label); |
| 123 | |
Alexander Graf | f570c61 | 2013-09-03 20:12:03 +0100 | [diff] [blame] | 124 | #endif /* TARGET_ARM_TRANSLATE_H */ |