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Alexander Graff570c612013-09-03 20:12:03 +01001#ifndef TARGET_ARM_TRANSLATE_H
2#define TARGET_ARM_TRANSLATE_H
3
4/* internal defines */
5typedef struct DisasContext {
6 target_ulong pc;
Alexander Graf14ade102013-09-03 20:12:10 +01007 uint32_t insn;
Alexander Graff570c612013-09-03 20:12:03 +01008 int is_jmp;
9 /* Nonzero if this instruction has been conditionally skipped. */
10 int condjmp;
11 /* The label that will be jumped to when the instruction is skipped. */
12 int condlabel;
13 /* Thumb-2 conditional execution bits. */
14 int condexec_mask;
15 int condexec_cond;
16 struct TranslationBlock *tb;
17 int singlestep_enabled;
18 int thumb;
19 int bswap_code;
20#if !defined(CONFIG_USER_ONLY)
21 int user;
22#endif
Peter Maydellc1e37812015-02-05 13:37:23 +000023 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
Sergey Fedorov3f342b92014-12-11 12:07:48 +000024 bool ns; /* Use non-secure CPREG bank on access */
Peter Maydell8c6afa62014-04-15 19:18:39 +010025 bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
26 bool vfp_enabled; /* FP enabled via FPSCR.EN */
Alexander Graff570c612013-09-03 20:12:03 +010027 int vec_len;
28 int vec_stride;
Peter Maydelld4a2dc62014-04-15 19:18:38 +010029 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
30 * so that top level loop can generate correct syndrome information.
31 */
32 uint32_t svc_imm;
Alexander Graf3926cc82013-09-03 20:12:09 +010033 int aarch64;
Greg Bellowsdcbff192014-10-24 12:19:14 +010034 int current_el;
Peter Maydell60322b32014-01-04 22:15:44 +000035 GHashTable *cp_regs;
Peter Maydella984e422014-03-17 16:31:47 +000036 uint64_t features; /* CPU features bits */
Peter Maydell90e49632014-04-15 19:18:40 +010037 /* Because unallocated encodings generate different exception syndrome
38 * information from traps due to FP being disabled, we can't do a single
39 * "is fp access disabled" check at a high level in the decode tree.
40 * To help in catching bugs where the access check was forgotten in some
41 * code path, we set this flag when the access check is done, and assert
42 * that it is set at the point where we actually touch the FP regs.
43 */
44 bool fp_access_checked;
Peter Maydell7ea47fe2014-08-19 18:56:26 +010045 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
46 * single-step support).
47 */
48 bool ss_active;
49 bool pstate_ss;
50 /* True if the insn just emitted was a load-exclusive instruction
51 * (necessary for syndrome information for single step exceptions),
52 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
53 */
54 bool is_ldex;
55 /* True if a single-step exception will be taken to the current EL */
56 bool ss_same_el;
Peter Maydellc0f4af12014-09-29 18:48:48 +010057 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
58 int c15_cpar;
Alexander Graf11e169d2013-12-17 19:42:32 +000059#define TMP_A64_MAX 16
60 int tmp_a64_count;
61 TCGv_i64 tmp_a64[TMP_A64_MAX];
Alexander Graff570c612013-09-03 20:12:03 +010062} DisasContext;
63
Alexander Graf3407ad02013-09-03 20:12:04 +010064extern TCGv_ptr cpu_env;
65
Peter Maydella984e422014-03-17 16:31:47 +000066static inline int arm_dc_feature(DisasContext *dc, int feature)
67{
68 return (dc->features & (1ULL << feature)) != 0;
69}
70
Edgar E. Iglesias9d4c4e82014-05-27 17:09:50 +010071static inline int get_mem_index(DisasContext *s)
72{
Peter Maydellc1e37812015-02-05 13:37:23 +000073 return s->mmu_idx;
Edgar E. Iglesias9d4c4e82014-05-27 17:09:50 +010074}
75
Peter Maydell40f860c2013-12-17 19:42:31 +000076/* target-specific extra values for is_jmp */
77/* These instructions trap after executing, so the A32/T32 decoder must
78 * defer them until after the conditional execution state has been updated.
79 * WFI also needs special handling when single-stepping.
80 */
81#define DISAS_WFI 4
82#define DISAS_SWI 5
83/* For instructions which unconditionally cause an exception we can skip
84 * emitting unreachable code at the end of the TB in the A64 decoder
85 */
86#define DISAS_EXC 6
Peter Maydell72c1d3a2014-03-10 14:56:30 +000087/* WFE */
88#define DISAS_WFE 7
Peter Maydell37e64562014-10-24 12:19:13 +010089#define DISAS_HVC 8
90#define DISAS_SMC 9
Peter Maydell40f860c2013-12-17 19:42:31 +000091
Alexander Graf14ade102013-09-03 20:12:10 +010092#ifdef TARGET_AARCH64
93void a64_translate_init(void);
Peter Maydell40f860c2013-12-17 19:42:31 +000094void gen_intermediate_code_internal_a64(ARMCPU *cpu,
95 TranslationBlock *tb,
96 bool search_pc);
Alexander Graf14ade102013-09-03 20:12:10 +010097void gen_a64_set_pc_im(uint64_t val);
Peter Maydell17731112014-04-15 19:19:15 +010098void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
99 fprintf_function cpu_fprintf, int flags);
Alexander Graf14ade102013-09-03 20:12:10 +0100100#else
101static inline void a64_translate_init(void)
102{
103}
104
Peter Maydell40f860c2013-12-17 19:42:31 +0000105static inline void gen_intermediate_code_internal_a64(ARMCPU *cpu,
106 TranslationBlock *tb,
107 bool search_pc)
Alexander Graf14ade102013-09-03 20:12:10 +0100108{
109}
110
111static inline void gen_a64_set_pc_im(uint64_t val)
112{
113}
Peter Maydell17731112014-04-15 19:19:15 +0100114
115static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
116 fprintf_function cpu_fprintf,
117 int flags)
118{
119}
Alexander Graf14ade102013-09-03 20:12:10 +0100120#endif
121
Alexander Graf39fb7302013-12-17 19:42:33 +0000122void arm_gen_test_cc(int cc, int label);
123
Alexander Graff570c612013-09-03 20:12:03 +0100124#endif /* TARGET_ARM_TRANSLATE_H */