blob: 55a780c7b5e96972a5e25ecc3832ab0336264490 [file] [log] [blame]
Jia Liub6a71ef2012-07-20 15:50:41 +08001/*
2 * OpenRISC interrupt helper routines
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "cpu.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070022#include "exec/helper-proto.h"
Jia Liub6a71ef2012-07-20 15:50:41 +080023
24void HELPER(rfe)(CPUOpenRISCState *env)
25{
Andreas Färberdd51dc52013-01-17 17:30:08 +010026 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
Andreas Färber259186a2013-01-17 18:51:17 +010027 CPUState *cs = CPU(cpu);
Jia Liub6a71ef2012-07-20 15:50:41 +080028#ifndef CONFIG_USER_ONLY
29 int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
30 (cpu->env.esr & (SR_SM | SR_IME | SR_DME));
31#endif
32 cpu->env.pc = cpu->env.epcr;
33 cpu->env.npc = cpu->env.epcr;
34 cpu->env.sr = cpu->env.esr;
35
36#ifndef CONFIG_USER_ONLY
37 if (cpu->env.sr & SR_DME) {
38 cpu->env.tlb->cpu_openrisc_map_address_data =
39 &cpu_openrisc_get_phys_data;
40 } else {
41 cpu->env.tlb->cpu_openrisc_map_address_data =
42 &cpu_openrisc_get_phys_nommu;
43 }
44
45 if (cpu->env.sr & SR_IME) {
46 cpu->env.tlb->cpu_openrisc_map_address_code =
47 &cpu_openrisc_get_phys_code;
48 } else {
49 cpu->env.tlb->cpu_openrisc_map_address_code =
50 &cpu_openrisc_get_phys_nommu;
51 }
52
53 if (need_flush_tlb) {
Andreas Färber00c8cb02013-09-04 02:19:44 +020054 tlb_flush(cs, 1);
Jia Liub6a71ef2012-07-20 15:50:41 +080055 }
56#endif
Andreas Färber259186a2013-01-17 18:51:17 +010057 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
Jia Liub6a71ef2012-07-20 15:50:41 +080058}