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ths83fa1012007-10-08 13:26:33 +00001/*
edgar_igle62b5b12008-03-14 01:04:24 +00002 * QEMU ETRAX Timers
ths83fa1012007-10-08 13:26:33 +00003 *
4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020024
Peter Maydell282bc812016-01-26 18:17:18 +000025#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010026#include "hw/sysbus.h"
Markus Armbruster71e8a912019-08-12 07:23:38 +020027#include "sysemu/reset.h"
Markus Armbruster54d31232019-08-12 07:23:59 +020028#include "sysemu/runstate.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020029#include "qemu/module.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010030#include "qemu/timer.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020031#include "hw/irq.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010032#include "hw/ptimer.h"
ths83fa1012007-10-08 13:26:33 +000033
edgar_iglbbaf29c2008-03-01 17:25:33 +000034#define D(x)
35
edgar_iglca87d032008-03-14 01:50:49 +000036#define RW_TMR0_DIV 0x00
37#define R_TMR0_DATA 0x04
38#define RW_TMR0_CTRL 0x08
39#define RW_TMR1_DIV 0x10
40#define R_TMR1_DATA 0x14
41#define RW_TMR1_CTRL 0x18
42#define R_TIME 0x38
43#define RW_WD_CTRL 0x40
edgar_igl54397792008-05-27 21:04:41 +000044#define R_WD_STAT 0x44
edgar_iglca87d032008-03-14 01:50:49 +000045#define RW_INTR_MASK 0x48
46#define RW_ACK_INTR 0x4c
47#define R_INTR 0x50
48#define R_MASKED_INTR 0x54
ths83fa1012007-10-08 13:26:33 +000049
Andreas Färber5880ce52013-07-27 14:34:22 +020050#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
51#define ETRAX_TIMER(obj) \
52 OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
53
Andreas Färber3c9a8a82013-07-27 14:30:31 +020054typedef struct ETRAXTimerState {
Andreas Färber5880ce52013-07-27 14:34:22 +020055 SysBusDevice parent_obj;
56
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +020057 MemoryRegion mmio;
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +020058 qemu_irq irq;
59 qemu_irq nmi;
edgar_iglca87d032008-03-14 01:50:49 +000060
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020061 ptimer_state *ptimer_t0;
62 ptimer_state *ptimer_t1;
63 ptimer_state *ptimer_wd;
edgar_igle62b5b12008-03-14 01:04:24 +000064
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020065 int wd_hits;
edgar_igl5ef98b42008-06-09 23:33:30 +000066
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020067 /* Control registers. */
68 uint32_t rw_tmr0_div;
69 uint32_t r_tmr0_data;
70 uint32_t rw_tmr0_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000071
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020072 uint32_t rw_tmr1_div;
73 uint32_t r_tmr1_data;
74 uint32_t rw_tmr1_ctrl;
edgar_igl60237222008-05-02 22:32:02 +000075
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020076 uint32_t rw_wd_ctrl;
edgar_igl54397792008-05-27 21:04:41 +000077
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020078 uint32_t rw_intr_mask;
79 uint32_t rw_ack_intr;
80 uint32_t r_intr;
81 uint32_t r_masked_intr;
Andreas Färber3c9a8a82013-07-27 14:30:31 +020082} ETRAXTimerState;
ths83fa1012007-10-08 13:26:33 +000083
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +020084static uint64_t
Avi Kivitya8170e52012-10-23 12:30:10 +020085timer_read(void *opaque, hwaddr addr, unsigned int size)
ths83fa1012007-10-08 13:26:33 +000086{
Andreas Färber3c9a8a82013-07-27 14:30:31 +020087 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020088 uint32_t r = 0;
ths83fa1012007-10-08 13:26:33 +000089
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020090 switch (addr) {
91 case R_TMR0_DATA:
92 r = ptimer_get_count(t->ptimer_t0);
93 break;
94 case R_TMR1_DATA:
95 r = ptimer_get_count(t->ptimer_t1);
96 break;
97 case R_TIME:
Alex Blighbc72ad62013-08-21 16:03:08 +010098 r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +020099 break;
100 case RW_INTR_MASK:
101 r = t->rw_intr_mask;
102 break;
103 case R_MASKED_INTR:
104 r = t->r_intr & t->rw_intr_mask;
105 break;
106 default:
107 D(printf ("%s %x\n", __func__, addr));
108 break;
109 }
110 return r;
ths83fa1012007-10-08 13:26:33 +0000111}
112
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200113static void update_ctrl(ETRAXTimerState *t, int tnum)
ths83fa1012007-10-08 13:26:33 +0000114{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200115 unsigned int op;
116 unsigned int freq;
117 unsigned int freq_hz;
118 unsigned int div;
119 uint32_t ctrl;
edgar_igl5ef98b42008-06-09 23:33:30 +0000120
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200121 ptimer_state *timer;
ths83fa1012007-10-08 13:26:33 +0000122
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200123 if (tnum == 0) {
124 ctrl = t->rw_tmr0_ctrl;
125 div = t->rw_tmr0_div;
126 timer = t->ptimer_t0;
127 } else {
128 ctrl = t->rw_tmr1_ctrl;
129 div = t->rw_tmr1_div;
130 timer = t->ptimer_t1;
131 }
edgar_igl54397792008-05-27 21:04:41 +0000132
133
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200134 op = ctrl & 3;
135 freq = ctrl >> 2;
136 freq_hz = 32000000;
ths83fa1012007-10-08 13:26:33 +0000137
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200138 switch (freq)
139 {
140 case 0:
141 case 1:
142 D(printf ("extern or disabled timer clock?\n"));
143 break;
144 case 4: freq_hz = 29493000; break;
145 case 5: freq_hz = 32000000; break;
146 case 6: freq_hz = 32768000; break;
147 case 7: freq_hz = 100000000; break;
148 default:
149 abort();
150 break;
151 }
ths83fa1012007-10-08 13:26:33 +0000152
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200153 D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
Peter Maydell2cb42c92019-10-22 16:50:36 +0100154 ptimer_transaction_begin(timer);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200155 ptimer_set_freq(timer, freq_hz);
156 ptimer_set_limit(timer, div, 0);
ths83fa1012007-10-08 13:26:33 +0000157
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200158 switch (op)
159 {
160 case 0:
161 /* Load. */
162 ptimer_set_limit(timer, div, 1);
163 break;
164 case 1:
165 /* Hold. */
166 ptimer_stop(timer);
167 break;
168 case 2:
169 /* Run. */
170 ptimer_run(timer, 0);
171 break;
172 default:
173 abort();
174 break;
175 }
Peter Maydell2cb42c92019-10-22 16:50:36 +0100176 ptimer_transaction_commit(timer);
ths83fa1012007-10-08 13:26:33 +0000177}
178
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200179static void timer_update_irq(ETRAXTimerState *t)
ths83fa1012007-10-08 13:26:33 +0000180{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200181 t->r_intr &= ~(t->rw_ack_intr);
182 t->r_masked_intr = t->r_intr & t->rw_intr_mask;
edgar_igl60237222008-05-02 22:32:02 +0000183
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200184 D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200185 qemu_set_irq(t->irq, !!t->r_masked_intr);
ths83fa1012007-10-08 13:26:33 +0000186}
187
edgar_igl54397792008-05-27 21:04:41 +0000188static void timer0_hit(void *opaque)
edgar_igl60237222008-05-02 22:32:02 +0000189{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200190 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200191 t->r_intr |= 1;
192 timer_update_irq(t);
edgar_igl60237222008-05-02 22:32:02 +0000193}
194
edgar_igl54397792008-05-27 21:04:41 +0000195static void timer1_hit(void *opaque)
196{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200197 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200198 t->r_intr |= 2;
199 timer_update_irq(t);
edgar_igl54397792008-05-27 21:04:41 +0000200}
201
202static void watchdog_hit(void *opaque)
203{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200204 ETRAXTimerState *t = opaque;
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200205 if (t->wd_hits == 0) {
206 /* real hw gives a single tick before reseting but we are
207 a bit friendlier to compensate for our slower execution. */
208 ptimer_set_count(t->ptimer_wd, 10);
209 ptimer_run(t->ptimer_wd, 1);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200210 qemu_irq_raise(t->nmi);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200211 }
212 else
Eric Blakecf83f142017-05-15 16:41:13 -0500213 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
edgar_igl5ef98b42008-06-09 23:33:30 +0000214
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200215 t->wd_hits++;
edgar_igl54397792008-05-27 21:04:41 +0000216}
217
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200218static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
edgar_igl54397792008-05-27 21:04:41 +0000219{
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200220 unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
221 unsigned int wd_key = t->rw_wd_ctrl >> 9;
222 unsigned int wd_cnt = t->rw_wd_ctrl & 511;
223 unsigned int new_key = value >> 9 & ((1 << 7) - 1);
224 unsigned int new_cmd = (value >> 8) & 1;
edgar_igl54397792008-05-27 21:04:41 +0000225
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200226 /* If the watchdog is enabled, they written key must match the
227 complement of the previous. */
228 wd_key = ~wd_key & ((1 << 7) - 1);
edgar_igl54397792008-05-27 21:04:41 +0000229
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200230 if (wd_en && wd_key != new_key)
231 return;
edgar_igl54397792008-05-27 21:04:41 +0000232
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200233 D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
234 wd_en, new_key, wd_key, new_cmd, wd_cnt));
edgar_igl54397792008-05-27 21:04:41 +0000235
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200236 if (t->wd_hits)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200237 qemu_irq_lower(t->nmi);
edgar_igl5ef98b42008-06-09 23:33:30 +0000238
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200239 t->wd_hits = 0;
edgar_igl5ef98b42008-06-09 23:33:30 +0000240
Peter Maydell2cb42c92019-10-22 16:50:36 +0100241 ptimer_transaction_begin(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200242 ptimer_set_freq(t->ptimer_wd, 760);
243 if (wd_cnt == 0)
244 wd_cnt = 256;
245 ptimer_set_count(t->ptimer_wd, wd_cnt);
246 if (new_cmd)
247 ptimer_run(t->ptimer_wd, 1);
248 else
249 ptimer_stop(t->ptimer_wd);
edgar_igl54397792008-05-27 21:04:41 +0000250
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200251 t->rw_wd_ctrl = value;
Peter Maydell2cb42c92019-10-22 16:50:36 +0100252 ptimer_transaction_commit(t->ptimer_wd);
edgar_igl54397792008-05-27 21:04:41 +0000253}
254
ths83fa1012007-10-08 13:26:33 +0000255static void
Avi Kivitya8170e52012-10-23 12:30:10 +0200256timer_write(void *opaque, hwaddr addr,
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200257 uint64_t val64, unsigned int size)
ths83fa1012007-10-08 13:26:33 +0000258{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200259 ETRAXTimerState *t = opaque;
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200260 uint32_t value = val64;
edgar_iglbbaf29c2008-03-01 17:25:33 +0000261
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200262 switch (addr)
263 {
264 case RW_TMR0_DIV:
265 t->rw_tmr0_div = value;
266 break;
267 case RW_TMR0_CTRL:
268 D(printf ("RW_TMR0_CTRL=%x\n", value));
269 t->rw_tmr0_ctrl = value;
270 update_ctrl(t, 0);
271 break;
272 case RW_TMR1_DIV:
273 t->rw_tmr1_div = value;
274 break;
275 case RW_TMR1_CTRL:
276 D(printf ("RW_TMR1_CTRL=%x\n", value));
277 t->rw_tmr1_ctrl = value;
278 update_ctrl(t, 1);
279 break;
280 case RW_INTR_MASK:
281 D(printf ("RW_INTR_MASK=%x\n", value));
282 t->rw_intr_mask = value;
283 timer_update_irq(t);
284 break;
285 case RW_WD_CTRL:
286 timer_watchdog_update(t, value);
287 break;
288 case RW_ACK_INTR:
289 t->rw_ack_intr = value;
290 timer_update_irq(t);
291 t->rw_ack_intr = 0;
292 break;
293 default:
294 printf ("%s " TARGET_FMT_plx " %x\n",
295 __func__, addr, value);
296 break;
297 }
ths83fa1012007-10-08 13:26:33 +0000298}
299
Edgar E. Iglesiasb8e5da22011-08-11 13:47:46 +0200300static const MemoryRegionOps timer_ops = {
301 .read = timer_read,
302 .write = timer_write,
303 .endianness = DEVICE_LITTLE_ENDIAN,
304 .valid = {
305 .min_access_size = 4,
306 .max_access_size = 4
307 }
ths83fa1012007-10-08 13:26:33 +0000308};
309
edgar_igl54397792008-05-27 21:04:41 +0000310static void etraxfs_timer_reset(void *opaque)
311{
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200312 ETRAXTimerState *t = opaque;
edgar_igl54397792008-05-27 21:04:41 +0000313
Peter Maydell2cb42c92019-10-22 16:50:36 +0100314 ptimer_transaction_begin(t->ptimer_t0);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200315 ptimer_stop(t->ptimer_t0);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100316 ptimer_transaction_commit(t->ptimer_t0);
317 ptimer_transaction_begin(t->ptimer_t1);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200318 ptimer_stop(t->ptimer_t1);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100319 ptimer_transaction_commit(t->ptimer_t1);
320 ptimer_transaction_begin(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200321 ptimer_stop(t->ptimer_wd);
Peter Maydell2cb42c92019-10-22 16:50:36 +0100322 ptimer_transaction_commit(t->ptimer_wd);
Edgar E. Iglesias84ceea52009-05-16 01:46:26 +0200323 t->rw_wd_ctrl = 0;
324 t->r_intr = 0;
325 t->rw_intr_mask = 0;
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200326 qemu_irq_lower(t->irq);
edgar_igl54397792008-05-27 21:04:41 +0000327}
328
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000329static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
ths83fa1012007-10-08 13:26:33 +0000330{
Andreas Färber5880ce52013-07-27 14:34:22 +0200331 ETRAXTimerState *t = ETRAX_TIMER(dev);
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000332 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ths83fa1012007-10-08 13:26:33 +0000333
Peter Maydell2cb42c92019-10-22 16:50:36 +0100334 t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
335 t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
336 t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200337
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000338 sysbus_init_irq(sbd, &t->irq);
339 sysbus_init_irq(sbd, &t->nmi);
ths83fa1012007-10-08 13:26:33 +0000340
Paolo Bonzini853dca12013-06-06 21:25:08 -0400341 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
342 "etraxfs-timer", 0x5c);
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000343 sysbus_init_mmio(sbd, &t->mmio);
Jan Kiszkaa08d4362009-06-27 09:25:07 +0200344 qemu_register_reset(etraxfs_timer_reset, t);
ths83fa1012007-10-08 13:26:33 +0000345}
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200346
Anthony Liguori999e12b2012-01-24 13:12:29 -0600347static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
348{
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000349 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600350
Mao Zhongyi34a598f2018-12-13 13:48:00 +0000351 dc->realize = etraxfs_timer_realize;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600352}
353
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100354static const TypeInfo etraxfs_timer_info = {
Andreas Färber5880ce52013-07-27 14:34:22 +0200355 .name = TYPE_ETRAX_FS_TIMER,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600356 .parent = TYPE_SYS_BUS_DEVICE,
Andreas Färber3c9a8a82013-07-27 14:30:31 +0200357 .instance_size = sizeof(ETRAXTimerState),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600358 .class_init = etraxfs_timer_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600359};
360
Andreas Färber83f7d432012-02-09 15:20:55 +0100361static void etraxfs_timer_register_types(void)
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200362{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600363 type_register_static(&etraxfs_timer_info);
Edgar E. Iglesias3b1fd902009-05-16 02:08:16 +0200364}
365
Andreas Färber83f7d432012-02-09 15:20:55 +0100366type_init(etraxfs_timer_register_types)