ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 1 | Unsolved issues/bugs in the mips/mipsel backend |
| 2 | ----------------------------------------------- |
| 3 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 4 | General |
| 5 | ------- |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 6 | - Unimplemented ASEs: |
ths | d0f4807 | 2007-10-13 19:00:52 +0000 | [diff] [blame] | 7 | - MDMX |
| 8 | - SmartMIPS |
| 9 | - DSP r1 |
| 10 | - DSP r2 |
| 11 | - MT ASE only partially implemented and not functional |
| 12 | - Shadow register support only partially implemented, |
| 13 | lacks set switching on interrupt/exception. |
| 14 | - 34K ITC not implemented. |
| 15 | - A general lack of documentation, especially for technical internals. |
| 16 | Existing documentation is x86-centric. |
| 17 | - Reverse endianness bit not implemented |
| 18 | - The TLB emulation is very inefficient: |
| 19 | Qemu's softmmu implements a x86-style MMU, with separate entries |
| 20 | for read/write/execute, a TLB index which is just a modulo of the |
| 21 | virtual address, and a set of TLBs for each user/kernel/supervisor |
| 22 | MMU mode. |
| 23 | MIPS has a single entry for read/write/execute and only one MMU mode. |
| 24 | But it is fully associative with randomized entry indices, and uses |
| 25 | up to 256 ASID tags as additional matching criterion (which roughly |
| 26 | equates to 256 MMU modes). It also has a global flag which causes |
| 27 | entries to match regardless of ASID. |
| 28 | To cope with these differences, Qemu currently flushes the TLB at |
| 29 | each ASID change. Using the MMU modes to implement ASIDs hinges on |
| 30 | implementing the global bit efficiently. |
ths | bec19c0 | 2008-05-07 15:39:12 +0000 | [diff] [blame] | 31 | - save/restore of the CPU state is not implemented (see machine.c). |
ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 32 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 33 | MIPS64 |
| 34 | ------ |
ths | 540635b | 2007-09-30 01:58:33 +0000 | [diff] [blame] | 35 | - Userland emulation (both n32 and n64) not functional. |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 36 | |
| 37 | "Generic" 4Kc system emulation |
| 38 | ------------------------------ |
ths | ebbd0ff | 2008-06-24 22:04:41 +0000 | [diff] [blame] | 39 | - Doesn't correspond to any real hardware. Should be removed some day, |
| 40 | U-Boot is the last remaining user. |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 41 | |
ths | 509b8ab | 2007-04-28 21:44:04 +0000 | [diff] [blame] | 42 | PICA 61 system emulation |
| 43 | ------------------------ |
| 44 | - No framebuffer support yet. |
| 45 | |
ths | 15dcf5a | 2007-01-19 17:56:23 +0000 | [diff] [blame] | 46 | MALTA system emulation |
| 47 | ---------------------- |
ths | 2c52c81 | 2007-01-17 20:03:15 +0000 | [diff] [blame] | 48 | - We fake firmware support instead of doing the real thing |
ths | ebbd0ff | 2008-06-24 22:04:41 +0000 | [diff] [blame] | 49 | - Real firmware (YAMON) falls over when trying to init RAM, presumably |
| 50 | due to lacking system controller emulation. |
ths | 0300e3f | 2007-12-17 03:53:42 +0000 | [diff] [blame] | 51 | - Bonito system controller not implemented |
| 52 | - MSC1 system controller not implemented |