bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 1 | /* |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 2 | * QEMU ESP/NCR53C9x emulation |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 3 | * |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | #include "vl.h" |
| 25 | |
| 26 | /* debug ESP card */ |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 27 | //#define DEBUG_ESP |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 28 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 29 | /* |
| 30 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also |
| 31 | * produced as NCR89C100. See |
| 32 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
| 33 | * and |
| 34 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt |
| 35 | */ |
| 36 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 37 | #ifdef DEBUG_ESP |
| 38 | #define DPRINTF(fmt, args...) \ |
| 39 | do { printf("ESP: " fmt , ##args); } while (0) |
| 40 | #else |
| 41 | #define DPRINTF(fmt, args...) |
| 42 | #endif |
| 43 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 44 | #define ESP_MAXREG 0x3f |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 45 | #define TI_BUFSZ 32 |
ths | fa1fb14 | 2006-12-24 17:12:43 +0000 | [diff] [blame] | 46 | /* The HBA is ID 7, so for simplicitly limit to 7 devices. */ |
| 47 | #define ESP_MAX_DEVS 7 |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 48 | |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 49 | typedef struct ESPState ESPState; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 50 | |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 51 | struct ESPState { |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 52 | BlockDriverState **bd; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 53 | uint8_t rregs[ESP_MAXREG]; |
| 54 | uint8_t wregs[ESP_MAXREG]; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 55 | int32_t ti_size; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 56 | uint32_t ti_rptr, ti_wptr; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 57 | uint8_t ti_buf[TI_BUFSZ]; |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 58 | int sense; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 59 | int dma; |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 60 | SCSIDevice *scsi_dev[MAX_DISKS]; |
| 61 | SCSIDevice *current_dev; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 62 | uint8_t cmdbuf[TI_BUFSZ]; |
| 63 | int cmdlen; |
| 64 | int do_cmd; |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 65 | |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 66 | /* The amount of data left in the current DMA transfer. */ |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 67 | uint32_t dma_left; |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 68 | /* The size of the current DMA transfer. Zero if no transfer is in |
| 69 | progress. */ |
| 70 | uint32_t dma_counter; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 71 | uint8_t *async_buf; |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 72 | uint32_t async_len; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 73 | void *dma_opaque; |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 74 | }; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 75 | |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 76 | #define STAT_DO 0x00 |
| 77 | #define STAT_DI 0x01 |
| 78 | #define STAT_CD 0x02 |
| 79 | #define STAT_ST 0x03 |
| 80 | #define STAT_MI 0x06 |
| 81 | #define STAT_MO 0x07 |
| 82 | |
| 83 | #define STAT_TC 0x10 |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 84 | #define STAT_PE 0x20 |
| 85 | #define STAT_GE 0x40 |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 86 | #define STAT_IN 0x80 |
| 87 | |
| 88 | #define INTR_FC 0x08 |
| 89 | #define INTR_BS 0x10 |
| 90 | #define INTR_DC 0x20 |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 91 | #define INTR_RST 0x80 |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 92 | |
| 93 | #define SEQ_0 0x0 |
| 94 | #define SEQ_CD 0x4 |
| 95 | |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 96 | static int get_cmd(ESPState *s, uint8_t *buf) |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 97 | { |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 98 | uint32_t dmalen; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 99 | int target; |
| 100 | |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 101 | dmalen = s->rregs[0] | (s->rregs[1] << 8); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 102 | target = s->wregs[4] & 7; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 103 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 104 | if (s->dma) { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 105 | espdma_memory_read(s->dma_opaque, buf, dmalen); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 106 | } else { |
| 107 | buf[0] = 0; |
| 108 | memcpy(&buf[1], s->ti_buf, dmalen); |
| 109 | dmalen++; |
| 110 | } |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 111 | |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 112 | s->ti_size = 0; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 113 | s->ti_rptr = 0; |
| 114 | s->ti_wptr = 0; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 115 | |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 116 | if (s->current_dev) { |
| 117 | /* Started a new command before the old one finished. Cancel it. */ |
| 118 | scsi_cancel_io(s->current_dev, 0); |
| 119 | s->async_len = 0; |
| 120 | } |
| 121 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 122 | if (target >= MAX_DISKS || !s->scsi_dev[target]) { |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 123 | // No such drive |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 124 | s->rregs[4] = STAT_IN; |
| 125 | s->rregs[5] = INTR_DC; |
| 126 | s->rregs[6] = SEQ_0; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 127 | espdma_raise_irq(s->dma_opaque); |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 128 | return 0; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 129 | } |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 130 | s->current_dev = s->scsi_dev[target]; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 131 | return dmalen; |
| 132 | } |
| 133 | |
| 134 | static void do_cmd(ESPState *s, uint8_t *buf) |
| 135 | { |
| 136 | int32_t datalen; |
| 137 | int lun; |
| 138 | |
| 139 | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
| 140 | lun = buf[0] & 7; |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 141 | datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun); |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 142 | s->ti_size = datalen; |
| 143 | if (datalen != 0) { |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 144 | s->rregs[4] = STAT_IN | STAT_TC; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 145 | s->dma_left = 0; |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 146 | s->dma_counter = 0; |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 147 | if (datalen > 0) { |
| 148 | s->rregs[4] |= STAT_DI; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 149 | scsi_read_data(s->current_dev, 0); |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 150 | } else { |
| 151 | s->rregs[4] |= STAT_DO; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 152 | scsi_write_data(s->current_dev, 0); |
bellard | b9788fc | 2005-12-05 20:30:36 +0000 | [diff] [blame] | 153 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 154 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 155 | s->rregs[5] = INTR_BS | INTR_FC; |
| 156 | s->rregs[6] = SEQ_CD; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 157 | espdma_raise_irq(s->dma_opaque); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 158 | } |
| 159 | |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 160 | static void handle_satn(ESPState *s) |
| 161 | { |
| 162 | uint8_t buf[32]; |
| 163 | int len; |
| 164 | |
| 165 | len = get_cmd(s, buf); |
| 166 | if (len) |
| 167 | do_cmd(s, buf); |
| 168 | } |
| 169 | |
| 170 | static void handle_satn_stop(ESPState *s) |
| 171 | { |
| 172 | s->cmdlen = get_cmd(s, s->cmdbuf); |
| 173 | if (s->cmdlen) { |
| 174 | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); |
| 175 | s->do_cmd = 1; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 176 | s->rregs[4] = STAT_IN | STAT_TC | STAT_CD; |
| 177 | s->rregs[5] = INTR_BS | INTR_FC; |
| 178 | s->rregs[6] = SEQ_CD; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 179 | espdma_raise_irq(s->dma_opaque); |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 180 | } |
| 181 | } |
| 182 | |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 183 | static void write_response(ESPState *s) |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 184 | { |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 185 | DPRINTF("Transfer status (sense=%d)\n", s->sense); |
| 186 | s->ti_buf[0] = s->sense; |
| 187 | s->ti_buf[1] = 0; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 188 | if (s->dma) { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 189 | espdma_memory_write(s->dma_opaque, s->ti_buf, 2); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 190 | s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; |
| 191 | s->rregs[5] = INTR_BS | INTR_FC; |
| 192 | s->rregs[6] = SEQ_CD; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 193 | } else { |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 194 | s->ti_size = 2; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 195 | s->ti_rptr = 0; |
| 196 | s->ti_wptr = 0; |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 197 | s->rregs[7] = 2; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 198 | } |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 199 | espdma_raise_irq(s->dma_opaque); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 200 | } |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 201 | |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 202 | static void esp_dma_done(ESPState *s) |
| 203 | { |
| 204 | s->rregs[4] |= STAT_IN | STAT_TC; |
| 205 | s->rregs[5] = INTR_BS; |
| 206 | s->rregs[6] = 0; |
| 207 | s->rregs[7] = 0; |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 208 | s->rregs[0] = 0; |
| 209 | s->rregs[1] = 0; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 210 | espdma_raise_irq(s->dma_opaque); |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 211 | } |
| 212 | |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 213 | static void esp_do_dma(ESPState *s) |
| 214 | { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 215 | uint32_t len; |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 216 | int to_device; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 217 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 218 | to_device = (s->ti_size < 0); |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 219 | len = s->dma_left; |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 220 | if (s->do_cmd) { |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 221 | DPRINTF("command len %d + %d\n", s->cmdlen, len); |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 222 | espdma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 223 | s->ti_size = 0; |
| 224 | s->cmdlen = 0; |
| 225 | s->do_cmd = 0; |
| 226 | do_cmd(s, s->cmdbuf); |
| 227 | return; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 228 | } |
| 229 | if (s->async_len == 0) { |
| 230 | /* Defer until data is available. */ |
| 231 | return; |
| 232 | } |
| 233 | if (len > s->async_len) { |
| 234 | len = s->async_len; |
| 235 | } |
| 236 | if (to_device) { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 237 | espdma_memory_read(s->dma_opaque, s->async_buf, len); |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 238 | } else { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 239 | espdma_memory_write(s->dma_opaque, s->async_buf, len); |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 240 | } |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 241 | s->dma_left -= len; |
| 242 | s->async_buf += len; |
| 243 | s->async_len -= len; |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 244 | if (to_device) |
| 245 | s->ti_size += len; |
| 246 | else |
| 247 | s->ti_size -= len; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 248 | if (s->async_len == 0) { |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 249 | if (to_device) { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 250 | // ti_size is negative |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 251 | scsi_write_data(s->current_dev, 0); |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 252 | } else { |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 253 | scsi_read_data(s->current_dev, 0); |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 254 | /* If there is still data to be read from the device then |
| 255 | complete the DMA operation immeriately. Otherwise defer |
| 256 | until the scsi layer has completed. */ |
| 257 | if (s->dma_left == 0 && s->ti_size > 0) { |
| 258 | esp_dma_done(s); |
| 259 | } |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 260 | } |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 261 | } else { |
| 262 | /* Partially filled a scsi buffer. Complete immediately. */ |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 263 | esp_dma_done(s); |
| 264 | } |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 265 | } |
| 266 | |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 267 | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
| 268 | uint32_t arg) |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 269 | { |
| 270 | ESPState *s = (ESPState *)opaque; |
| 271 | |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 272 | if (reason == SCSI_REASON_DONE) { |
| 273 | DPRINTF("SCSI Command complete\n"); |
| 274 | if (s->ti_size != 0) |
| 275 | DPRINTF("SCSI command completed unexpectedly\n"); |
| 276 | s->ti_size = 0; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 277 | s->dma_left = 0; |
| 278 | s->async_len = 0; |
| 279 | if (arg) |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 280 | DPRINTF("Command failed\n"); |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 281 | s->sense = arg; |
| 282 | s->rregs[4] = STAT_ST; |
| 283 | esp_dma_done(s); |
| 284 | s->current_dev = NULL; |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 285 | } else { |
| 286 | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size); |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 287 | s->async_len = arg; |
| 288 | s->async_buf = scsi_get_buf(s->current_dev, 0); |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 289 | if (s->dma_left) { |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 290 | esp_do_dma(s); |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 291 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
| 292 | /* If this was the last part of a DMA transfer then the |
| 293 | completion interrupt is deferred to here. */ |
| 294 | esp_dma_done(s); |
| 295 | } |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 296 | } |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 297 | } |
| 298 | |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 299 | static void handle_ti(ESPState *s) |
| 300 | { |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 301 | uint32_t dmalen, minlen; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 302 | |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 303 | dmalen = s->rregs[0] | (s->rregs[1] << 8); |
pbrook | db59203 | 2006-05-21 12:46:31 +0000 | [diff] [blame] | 304 | if (dmalen==0) { |
| 305 | dmalen=0x10000; |
| 306 | } |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 307 | s->dma_counter = dmalen; |
pbrook | db59203 | 2006-05-21 12:46:31 +0000 | [diff] [blame] | 308 | |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 309 | if (s->do_cmd) |
| 310 | minlen = (dmalen < 32) ? dmalen : 32; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 311 | else if (s->ti_size < 0) |
| 312 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 313 | else |
| 314 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
pbrook | db59203 | 2006-05-21 12:46:31 +0000 | [diff] [blame] | 315 | DPRINTF("Transfer Information len %d\n", minlen); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 316 | if (s->dma) { |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 317 | s->dma_left = minlen; |
| 318 | s->rregs[4] &= ~STAT_TC; |
| 319 | esp_do_dma(s); |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 320 | } else if (s->do_cmd) { |
| 321 | DPRINTF("command len %d\n", s->cmdlen); |
| 322 | s->ti_size = 0; |
| 323 | s->cmdlen = 0; |
| 324 | s->do_cmd = 0; |
| 325 | do_cmd(s, s->cmdbuf); |
| 326 | return; |
| 327 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 328 | } |
| 329 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 330 | void esp_reset(void *opaque) |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 331 | { |
| 332 | ESPState *s = opaque; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 333 | |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 334 | memset(s->rregs, 0, ESP_MAXREG); |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 335 | memset(s->wregs, 0, ESP_MAXREG); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 336 | s->rregs[0x0e] = 0x4; // Indicate fas100a |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 337 | s->ti_size = 0; |
| 338 | s->ti_rptr = 0; |
| 339 | s->ti_wptr = 0; |
pbrook | 4e9aec7 | 2006-03-11 16:29:14 +0000 | [diff] [blame] | 340 | s->dma = 0; |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 341 | s->do_cmd = 0; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
| 345 | { |
| 346 | ESPState *s = opaque; |
| 347 | uint32_t saddr; |
| 348 | |
| 349 | saddr = (addr & ESP_MAXREG) >> 2; |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 350 | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 351 | switch (saddr) { |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 352 | case 2: |
| 353 | // FIFO |
| 354 | if (s->ti_size > 0) { |
| 355 | s->ti_size--; |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 356 | if ((s->rregs[4] & 6) == 0) { |
| 357 | /* Data in/out. */ |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 358 | fprintf(stderr, "esp: PIO data read not implemented\n"); |
| 359 | s->rregs[2] = 0; |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 360 | } else { |
| 361 | s->rregs[2] = s->ti_buf[s->ti_rptr++]; |
| 362 | } |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 363 | espdma_raise_irq(s->dma_opaque); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 364 | } |
| 365 | if (s->ti_size == 0) { |
| 366 | s->ti_rptr = 0; |
| 367 | s->ti_wptr = 0; |
| 368 | } |
| 369 | break; |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 370 | case 5: |
| 371 | // interrupt |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 372 | // Clear interrupt/error status bits |
| 373 | s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 374 | espdma_clear_irq(s->dma_opaque); |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 375 | break; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 376 | default: |
| 377 | break; |
| 378 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 379 | return s->rregs[saddr]; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 380 | } |
| 381 | |
| 382 | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 383 | { |
| 384 | ESPState *s = opaque; |
| 385 | uint32_t saddr; |
| 386 | |
| 387 | saddr = (addr & ESP_MAXREG) >> 2; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 388 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 389 | switch (saddr) { |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 390 | case 0: |
| 391 | case 1: |
pbrook | 4d611c9 | 2006-08-12 01:04:27 +0000 | [diff] [blame] | 392 | s->rregs[4] &= ~STAT_TC; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 393 | break; |
| 394 | case 2: |
| 395 | // FIFO |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 396 | if (s->do_cmd) { |
| 397 | s->cmdbuf[s->cmdlen++] = val & 0xff; |
| 398 | } else if ((s->rregs[4] & 6) == 0) { |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 399 | uint8_t buf; |
| 400 | buf = val & 0xff; |
| 401 | s->ti_size--; |
pbrook | a917d38 | 2006-08-29 04:52:16 +0000 | [diff] [blame] | 402 | fprintf(stderr, "esp: PIO data write not implemented\n"); |
pbrook | 2e5d83b | 2006-05-25 23:58:51 +0000 | [diff] [blame] | 403 | } else { |
| 404 | s->ti_size++; |
| 405 | s->ti_buf[s->ti_wptr++] = val & 0xff; |
| 406 | } |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 407 | break; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 408 | case 3: |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 409 | s->rregs[saddr] = val; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 410 | // Command |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 411 | if (val & 0x80) { |
| 412 | s->dma = 1; |
pbrook | 6787f5f | 2006-09-17 03:20:58 +0000 | [diff] [blame] | 413 | /* Reload DMA counter. */ |
| 414 | s->rregs[0] = s->wregs[0]; |
| 415 | s->rregs[1] = s->wregs[1]; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 416 | } else { |
| 417 | s->dma = 0; |
| 418 | } |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 419 | switch(val & 0x7f) { |
| 420 | case 0: |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 421 | DPRINTF("NOP (%2.2x)\n", val); |
| 422 | break; |
| 423 | case 1: |
| 424 | DPRINTF("Flush FIFO (%2.2x)\n", val); |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 425 | //s->ti_size = 0; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 426 | s->rregs[5] = INTR_FC; |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 427 | s->rregs[6] = 0; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 428 | break; |
| 429 | case 2: |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 430 | DPRINTF("Chip reset (%2.2x)\n", val); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 431 | esp_reset(s); |
| 432 | break; |
| 433 | case 3: |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 434 | DPRINTF("Bus reset (%2.2x)\n", val); |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 435 | s->rregs[5] = INTR_RST; |
| 436 | if (!(s->wregs[8] & 0x40)) { |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 437 | espdma_raise_irq(s->dma_opaque); |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 438 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 439 | break; |
| 440 | case 0x10: |
| 441 | handle_ti(s); |
| 442 | break; |
| 443 | case 0x11: |
| 444 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 445 | write_response(s); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 446 | break; |
| 447 | case 0x12: |
| 448 | DPRINTF("Message Accepted (%2.2x)\n", val); |
pbrook | 0fc5c15 | 2006-05-26 21:53:41 +0000 | [diff] [blame] | 449 | write_response(s); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 450 | s->rregs[5] = INTR_DC; |
| 451 | s->rregs[6] = 0; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 452 | break; |
| 453 | case 0x1a: |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 454 | DPRINTF("Set ATN (%2.2x)\n", val); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 455 | break; |
| 456 | case 0x42: |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 457 | DPRINTF("Set ATN (%2.2x)\n", val); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 458 | handle_satn(s); |
| 459 | break; |
| 460 | case 0x43: |
| 461 | DPRINTF("Set ATN & stop (%2.2x)\n", val); |
pbrook | 9f149aa | 2006-06-03 14:19:19 +0000 | [diff] [blame] | 462 | handle_satn_stop(s); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 463 | break; |
| 464 | default: |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 465 | DPRINTF("Unhandled ESP command (%2.2x)\n", val); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 466 | break; |
| 467 | } |
| 468 | break; |
| 469 | case 4 ... 7: |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 470 | break; |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 471 | case 8: |
| 472 | s->rregs[saddr] = val; |
| 473 | break; |
| 474 | case 9 ... 10: |
| 475 | break; |
bellard | 9e61bde | 2005-11-11 00:24:58 +0000 | [diff] [blame] | 476 | case 11: |
| 477 | s->rregs[saddr] = val & 0x15; |
| 478 | break; |
| 479 | case 12 ... 15: |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 480 | s->rregs[saddr] = val; |
| 481 | break; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 482 | default: |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 483 | break; |
| 484 | } |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 485 | s->wregs[saddr] = val; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | static CPUReadMemoryFunc *esp_mem_read[3] = { |
| 489 | esp_mem_readb, |
| 490 | esp_mem_readb, |
| 491 | esp_mem_readb, |
| 492 | }; |
| 493 | |
| 494 | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
| 495 | esp_mem_writeb, |
| 496 | esp_mem_writeb, |
| 497 | esp_mem_writeb, |
| 498 | }; |
| 499 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 500 | static void esp_save(QEMUFile *f, void *opaque) |
| 501 | { |
| 502 | ESPState *s = opaque; |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 503 | |
| 504 | qemu_put_buffer(f, s->rregs, ESP_MAXREG); |
| 505 | qemu_put_buffer(f, s->wregs, ESP_MAXREG); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 506 | qemu_put_be32s(f, &s->ti_size); |
| 507 | qemu_put_be32s(f, &s->ti_rptr); |
| 508 | qemu_put_be32s(f, &s->ti_wptr); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 509 | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
| 510 | qemu_put_be32s(f, &s->dma); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
| 514 | { |
| 515 | ESPState *s = opaque; |
| 516 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 517 | if (version_id != 2) |
| 518 | return -EINVAL; // Cannot emulate 1 |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 519 | |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 520 | qemu_get_buffer(f, s->rregs, ESP_MAXREG); |
| 521 | qemu_get_buffer(f, s->wregs, ESP_MAXREG); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 522 | qemu_get_be32s(f, &s->ti_size); |
| 523 | qemu_get_be32s(f, &s->ti_rptr); |
| 524 | qemu_get_be32s(f, &s->ti_wptr); |
bellard | 4f6200f | 2005-10-30 17:24:05 +0000 | [diff] [blame] | 525 | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
| 526 | qemu_get_be32s(f, &s->dma); |
bellard | 2f275b8 | 2005-04-06 20:31:50 +0000 | [diff] [blame] | 527 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 528 | return 0; |
| 529 | } |
| 530 | |
ths | fa1fb14 | 2006-12-24 17:12:43 +0000 | [diff] [blame] | 531 | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
| 532 | { |
| 533 | ESPState *s = (ESPState *)opaque; |
| 534 | |
| 535 | if (id < 0) { |
| 536 | for (id = 0; id < ESP_MAX_DEVS; id++) { |
| 537 | if (s->scsi_dev[id] == NULL) |
| 538 | break; |
| 539 | } |
| 540 | } |
| 541 | if (id >= ESP_MAX_DEVS) { |
| 542 | DPRINTF("Bad Device ID %d\n", id); |
| 543 | return; |
| 544 | } |
| 545 | if (s->scsi_dev[id]) { |
| 546 | DPRINTF("Destroying device %d\n", id); |
| 547 | scsi_disk_destroy(s->scsi_dev[id]); |
| 548 | } |
| 549 | DPRINTF("Attaching block device %d\n", id); |
| 550 | /* Command queueing is not implemented. */ |
| 551 | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s); |
| 552 | } |
| 553 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 554 | void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque) |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 555 | { |
| 556 | ESPState *s; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 557 | int esp_io_memory; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 558 | |
| 559 | s = qemu_mallocz(sizeof(ESPState)); |
| 560 | if (!s) |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 561 | return NULL; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 562 | |
| 563 | s->bd = bd; |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 564 | s->dma_opaque = dma_opaque; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 565 | |
| 566 | esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s); |
| 567 | cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory); |
| 568 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 569 | esp_reset(s); |
| 570 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 571 | register_savevm("esp", espaddr, 2, esp_save, esp_load, s); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 572 | qemu_register_reset(esp_reset, s); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 573 | |
bellard | 67e999b | 2006-09-03 16:09:07 +0000 | [diff] [blame] | 574 | return s; |
| 575 | } |