| Stefano Garzarella | d0fb965 | 2021-05-17 17:16:58 +0200 | [diff] [blame] | 1 | # See docs/devel/tracing.rst for syntax documentation. |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 2 | |
| Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 3 | # slavio_timer.c |
| Vladimir Sementsov-Ogievskiy | 8908eb1 | 2017-07-31 19:01:35 +0300 | [diff] [blame] | 4 | slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit 0x%"PRIx64" count 0x%x0x%08x" |
| 5 | slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count 0x%x0x%08x" |
| 6 | slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address 0x%"PRIx64 |
| 7 | slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read 0x%"PRIx64" = 0x%08x" |
| 8 | slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write 0x%"PRIx64" = 0x%08x" |
| 9 | slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to 0x%016"PRIx64 |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 10 | slavio_timer_mem_writel_counter_invalid(void) "not user timer" |
| 11 | slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" |
| 12 | slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" |
| 13 | slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" |
| 14 | slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" |
| 15 | slavio_timer_mem_writel_mode_invalid(void) "not system timer" |
| Vladimir Sementsov-Ogievskiy | 8908eb1 | 2017-07-31 19:01:35 +0300 | [diff] [blame] | 16 | slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address 0x%"PRIx64 |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 17 | |
| Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 18 | # grlib_gptimer.c |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 19 | grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" |
| 20 | grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" |
| 21 | grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x" |
| Philippe Mathieu-Daudé | 8e071cd | 2020-03-31 11:38:01 +0200 | [diff] [blame] | 22 | grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq:%uHz" |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 23 | grlib_gptimer_hit(int id) "timer:%d HIT" |
| 24 | grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" |
| 25 | grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" |
| 26 | |
| Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 27 | # aspeed_timer.c |
| Daniel P. Berrange | c3e203f | 2016-06-16 09:40:05 +0100 | [diff] [blame] | 28 | aspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| 29 | aspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| 30 | aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| 31 | aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| 32 | aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 |
| 33 | aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32 |
| 34 | aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64 |
| Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame] | 35 | |
| Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 36 | # armv7m_systick.c |
| Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame] | 37 | systick_reload(void) "systick reload" |
| Samuel Tardieu | 7c8faaf | 2024-01-09 19:45:08 +0100 | [diff] [blame] | 38 | systick_timer_tick(void) "systick tick" |
| Peter Maydell | ff68dac | 2017-02-20 15:36:03 +0000 | [diff] [blame] | 39 | systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| 40 | systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| Peter Maydell | 5dd85b4 | 2017-07-17 13:36:08 +0100 | [diff] [blame] | 41 | |
| Markus Armbruster | dec9776 | 2019-03-14 19:09:29 +0100 | [diff] [blame] | 42 | # cmsdk-apb-timer.c |
| Peter Maydell | 5dd85b4 | 2017-07-17 13:36:08 +0100 | [diff] [blame] | 43 | cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 44 | cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 45 | cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" |
| Alistair Francis | 246003c | 2018-03-02 10:45:34 +0000 | [diff] [blame] | 46 | |
| Markus Armbruster | dec9776 | 2019-03-14 19:09:29 +0100 | [diff] [blame] | 47 | # cmsdk-apb-dualtimer.c |
| Peter Maydell | 4f4c620 | 2018-08-24 13:17:41 +0100 | [diff] [blame] | 48 | cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 49 | cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 50 | cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset" |
| 51 | |
| Havard Skinnemoen | 85fdd74 | 2020-09-10 22:20:50 -0700 | [diff] [blame] | 52 | # npcm7xx_timer.c |
| 53 | npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| 54 | npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| 55 | npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d" |
| 56 | |
| Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 57 | # nrf51_timer.c |
| Philippe Mathieu-Daudé | 27d6dea | 2020-05-04 09:28:21 +0200 | [diff] [blame] | 58 | nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| 59 | nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| Philippe Mathieu-Daudé | 602ab78 | 2020-05-04 09:28:22 +0200 | [diff] [blame] | 60 | nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32 |
| Steffen Görtz | c5a4829 | 2019-01-07 15:23:47 +0000 | [diff] [blame] | 61 | |
| Philippe Mathieu-Daudé | d05be88 | 2019-10-20 01:47:02 +0200 | [diff] [blame] | 62 | # bcm2835_systmr.c |
| Philippe Mathieu-Daudé | be95dff | 2020-10-10 22:37:08 +0200 | [diff] [blame] | 63 | bcm2835_systmr_timer_expired(unsigned id) "timer #%u expired" |
| 64 | bcm2835_systmr_irq_ack(unsigned id) "timer #%u acked" |
| Philippe Mathieu-Daudé | d05be88 | 2019-10-20 01:47:02 +0200 | [diff] [blame] | 65 | bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| Philippe Mathieu-Daudé | be95dff | 2020-10-10 22:37:08 +0200 | [diff] [blame] | 66 | bcm2835_systmr_write(uint64_t offset, uint32_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx32 |
| 67 | bcm2835_systmr_run(unsigned id, uint64_t delay_us) "timer #%u expiring in %"PRIu64" us" |
| Michael Rolnik | 8ff47bc | 2020-01-24 01:51:18 +0100 | [diff] [blame] | 68 | |
| 69 | # avr_timer16.c |
| 70 | avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u" |
| 71 | avr_timer16_read_ifr(uint8_t value) "timer16 read addr:ifr value:%u" |
| 72 | avr_timer16_read_imsk(uint8_t value) "timer16 read addr:imsk value:%u" |
| 73 | avr_timer16_write(uint8_t addr, uint8_t value) "timer16 write addr:%u value:%u" |
| Michael Rolnik | 8ff47bc | 2020-01-24 01:51:18 +0100 | [diff] [blame] | 74 | avr_timer16_write_imsk(uint8_t value) "timer16 write addr:imsk value:%u" |
| 75 | avr_timer16_interrupt_count(uint8_t cnt) "count: %u" |
| 76 | avr_timer16_interrupt_overflow(const char *reason) "overflow: %s" |
| 77 | avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from now" |
| 78 | avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)" |
| Peter Maydell | 0d10df3 | 2021-02-19 14:45:44 +0000 | [diff] [blame] | 79 | |
| 80 | # sse_counter.c |
| 81 | sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 82 | sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control framen write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 83 | sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 84 | sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 85 | sse_counter_reset(void) "SSE system counter: reset" |
| Peter Maydell | 0b8ceee | 2021-02-19 14:45:45 +0000 | [diff] [blame] | 86 | |
| 87 | # sse_timer.c |
| 88 | sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 89 | sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| 90 | sse_timer_reset(void) "SSE system timer: reset" |
| Alistair Francis | 5bf6f1a | 2021-09-09 13:55:02 +1000 | [diff] [blame] | 91 | |
| 92 | # sifive_pwm.c |
| 93 | sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setting alarm to: 0x%" PRIx64 ", now: 0x%" PRIx64 |
| 94 | sifive_pwm_interrupt(int num) "Interrupt %d" |
| 95 | sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64 |
| 96 | sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address: 0x%" PRIx64 |
| BALATON Zoltan | ad52cfc | 2021-10-29 23:02:09 +0200 | [diff] [blame] | 97 | |
| 98 | # sh_timer.c |
| 99 | sh_timer_start_stop(int enable, int current) "%d (%d)" |
| 100 | sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64 |
| 101 | sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 |
| Daniel Hoffman | c0d0b71 | 2023-11-18 15:11:29 -0800 | [diff] [blame] | 102 | |
| 103 | # hpet.c |
| 104 | hpet_timer_id_out_of_range(uint8_t timer_id) "timer id out of range: 0x%" PRIx8 |
| 105 | hpet_invalid_hpet_cfg(uint8_t reg_off) "invalid HPET_CFG + %u" PRIx8 |
| 106 | hpet_ram_read(uint64_t addr) "enter hpet_ram_readl at 0x%" PRIx64 |
| 107 | hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0x%" PRIx64 |
| 108 | hpet_ram_read_invalid(void) "invalid hpet_ram_readl" |
| 109 | hpet_ram_write(uint64_t addr, uint64_t value) "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64 |
| 110 | hpet_ram_write_timer_id(uint64_t timer_id) "hpet_ram_writel timer_id = 0x%" PRIx64 |
| Paolo Bonzini | c236656 | 2024-07-10 09:58:01 +0200 | [diff] [blame] | 111 | hpet_ram_write_tn_cfg(uint8_t reg_off) "hpet_ram_writel HPET_TN_CFG + %" PRIu8 |
| Daniel Hoffman | c0d0b71 | 2023-11-18 15:11:29 -0800 | [diff] [blame] | 112 | hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8 |
| Paolo Bonzini | 9eb7fad | 2024-07-10 10:53:05 +0200 | [diff] [blame] | 113 | hpet_ram_write_invalid_tn_cmp(void) "invalid HPET_TN_CMP + 4 write" |
| Daniel Hoffman | c0d0b71 | 2023-11-18 15:11:29 -0800 | [diff] [blame] | 114 | hpet_ram_write_invalid(void) "invalid hpet_ram_writel" |
| 115 | hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!" |
| 116 | hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter) "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64 |
