bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 1 | /* |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 2 | * QEMU PowerMac CUDA device support |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 4 | * Copyright (c) 2004-2007 Fabrice Bellard |
| 5 | * Copyright (c) 2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6 | * |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 25 | #include "hw.h" |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 26 | #include "ppc_mac.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 27 | #include "qemu-timer.h" |
| 28 | #include "sysemu.h" |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 29 | |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 30 | /* XXX: implement all timer modes */ |
| 31 | |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 32 | /* debug CUDA */ |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 33 | //#define DEBUG_CUDA |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 34 | |
| 35 | /* debug CUDA packets */ |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 36 | //#define DEBUG_CUDA_PACKET |
| 37 | |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 38 | #ifdef DEBUG_CUDA |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 39 | #define CUDA_DPRINTF(fmt, ...) \ |
| 40 | do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0) |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 41 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 42 | #define CUDA_DPRINTF(fmt, ...) |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 43 | #endif |
| 44 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 45 | /* Bits in B data register: all active low */ |
| 46 | #define TREQ 0x08 /* Transfer request (input) */ |
| 47 | #define TACK 0x10 /* Transfer acknowledge (output) */ |
| 48 | #define TIP 0x20 /* Transfer in progress (output) */ |
| 49 | |
| 50 | /* Bits in ACR */ |
| 51 | #define SR_CTRL 0x1c /* Shift register control bits */ |
| 52 | #define SR_EXT 0x0c /* Shift on external clock */ |
| 53 | #define SR_OUT 0x10 /* Shift out if 1 */ |
| 54 | |
| 55 | /* Bits in IFR and IER */ |
| 56 | #define IER_SET 0x80 /* set bits in IER */ |
| 57 | #define IER_CLR 0 /* clear bits in IER */ |
| 58 | #define SR_INT 0x04 /* Shift register full/empty */ |
| 59 | #define T1_INT 0x40 /* Timer 1 interrupt */ |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 60 | #define T2_INT 0x20 /* Timer 2 interrupt */ |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 61 | |
| 62 | /* Bits in ACR */ |
| 63 | #define T1MODE 0xc0 /* Timer 1 mode */ |
| 64 | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
| 65 | |
| 66 | /* commands (1st byte) */ |
| 67 | #define ADB_PACKET 0 |
| 68 | #define CUDA_PACKET 1 |
| 69 | #define ERROR_PACKET 2 |
| 70 | #define TIMER_PACKET 3 |
| 71 | #define POWER_PACKET 4 |
| 72 | #define MACIIC_PACKET 5 |
| 73 | #define PMU_PACKET 6 |
| 74 | |
| 75 | |
| 76 | /* CUDA commands (2nd byte) */ |
| 77 | #define CUDA_WARM_START 0x0 |
| 78 | #define CUDA_AUTOPOLL 0x1 |
| 79 | #define CUDA_GET_6805_ADDR 0x2 |
| 80 | #define CUDA_GET_TIME 0x3 |
| 81 | #define CUDA_GET_PRAM 0x7 |
| 82 | #define CUDA_SET_6805_ADDR 0x8 |
| 83 | #define CUDA_SET_TIME 0x9 |
| 84 | #define CUDA_POWERDOWN 0xa |
| 85 | #define CUDA_POWERUP_TIME 0xb |
| 86 | #define CUDA_SET_PRAM 0xc |
| 87 | #define CUDA_MS_RESET 0xd |
| 88 | #define CUDA_SEND_DFAC 0xe |
| 89 | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
| 90 | #define CUDA_RESET_SYSTEM 0x11 |
| 91 | #define CUDA_SET_IPL 0x12 |
| 92 | #define CUDA_FILE_SERVER_FLAG 0x13 |
| 93 | #define CUDA_SET_AUTO_RATE 0x14 |
| 94 | #define CUDA_GET_AUTO_RATE 0x16 |
| 95 | #define CUDA_SET_DEVICE_LIST 0x19 |
| 96 | #define CUDA_GET_DEVICE_LIST 0x1a |
| 97 | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
| 98 | #define CUDA_SET_POWER_MESSAGES 0x21 |
| 99 | #define CUDA_GET_SET_IIC 0x22 |
| 100 | #define CUDA_WAKEUP 0x23 |
| 101 | #define CUDA_TIMER_TICKLE 0x24 |
| 102 | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
| 103 | |
| 104 | #define CUDA_TIMER_FREQ (4700000 / 6) |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 105 | #define CUDA_ADB_POLL_FREQ 50 |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 106 | |
bellard | d7ce296 | 2005-02-09 00:07:08 +0000 | [diff] [blame] | 107 | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */ |
| 108 | #define RTC_OFFSET 2082844800 |
| 109 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 110 | typedef struct CUDATimer { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 111 | int index; |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 112 | uint16_t latch; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 113 | uint16_t counter_value; /* counter value at load time */ |
| 114 | int64_t load_time; |
| 115 | int64_t next_irq_time; |
| 116 | QEMUTimer *timer; |
| 117 | } CUDATimer; |
| 118 | |
| 119 | typedef struct CUDAState { |
| 120 | /* cuda registers */ |
| 121 | uint8_t b; /* B-side data */ |
| 122 | uint8_t a; /* A-side data */ |
| 123 | uint8_t dirb; /* B-side direction (1=output) */ |
| 124 | uint8_t dira; /* A-side direction (1=output) */ |
| 125 | uint8_t sr; /* Shift register */ |
| 126 | uint8_t acr; /* Auxiliary control register */ |
| 127 | uint8_t pcr; /* Peripheral control register */ |
| 128 | uint8_t ifr; /* Interrupt flag register */ |
| 129 | uint8_t ier; /* Interrupt enable register */ |
| 130 | uint8_t anh; /* A-side data, no handshake */ |
| 131 | |
| 132 | CUDATimer timers[2]; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 133 | |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 134 | uint32_t tick_offset; |
| 135 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 136 | uint8_t last_b; /* last value of B register */ |
| 137 | uint8_t last_acr; /* last value of B register */ |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 138 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 139 | int data_in_size; |
| 140 | int data_in_index; |
| 141 | int data_out_index; |
| 142 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 143 | qemu_irq irq; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 144 | uint8_t autopoll; |
| 145 | uint8_t data_in[128]; |
| 146 | uint8_t data_out[16]; |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 147 | QEMUTimer *adb_poll_timer; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 148 | } CUDAState; |
| 149 | |
| 150 | static CUDAState cuda_state; |
| 151 | ADBBusState adb_bus; |
| 152 | |
| 153 | static void cuda_update(CUDAState *s); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 154 | static void cuda_receive_packet_from_host(CUDAState *s, |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 155 | const uint8_t *data, int len); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 156 | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 157 | int64_t current_time); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 158 | |
| 159 | static void cuda_update_irq(CUDAState *s) |
| 160 | { |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 161 | if (s->ifr & s->ier & (SR_INT | T1_INT)) { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 162 | qemu_irq_raise(s->irq); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 163 | } else { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 164 | qemu_irq_lower(s->irq); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 165 | } |
| 166 | } |
| 167 | |
| 168 | static unsigned int get_counter(CUDATimer *s) |
| 169 | { |
| 170 | int64_t d; |
| 171 | unsigned int counter; |
| 172 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 173 | d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 174 | CUDA_TIMER_FREQ, get_ticks_per_sec()); |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 175 | if (s->index == 0) { |
| 176 | /* the timer goes down from latch to -1 (period of latch + 2) */ |
| 177 | if (d <= (s->counter_value + 1)) { |
| 178 | counter = (s->counter_value - d) & 0xffff; |
| 179 | } else { |
| 180 | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 181 | counter = (s->latch - counter) & 0xffff; |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 182 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 183 | } else { |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 184 | counter = (s->counter_value - d) & 0xffff; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 185 | } |
| 186 | return counter; |
| 187 | } |
| 188 | |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 189 | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 190 | { |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 191 | CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val); |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 192 | ti->load_time = qemu_get_clock(vm_clock); |
| 193 | ti->counter_value = val; |
| 194 | cuda_timer_update(s, ti, ti->load_time); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 195 | } |
| 196 | |
| 197 | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) |
| 198 | { |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 199 | int64_t d, next_time; |
| 200 | unsigned int counter; |
| 201 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 202 | /* current counter value */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 203 | d = muldiv64(current_time - s->load_time, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 204 | CUDA_TIMER_FREQ, get_ticks_per_sec()); |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 205 | /* the timer goes down from latch to -1 (period of latch + 2) */ |
| 206 | if (d <= (s->counter_value + 1)) { |
| 207 | counter = (s->counter_value - d) & 0xffff; |
| 208 | } else { |
| 209 | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 210 | counter = (s->latch - counter) & 0xffff; |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 211 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 212 | |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 213 | /* Note: we consider the irq is raised on 0 */ |
| 214 | if (counter == 0xffff) { |
| 215 | next_time = d + s->latch + 1; |
| 216 | } else if (counter == 0) { |
| 217 | next_time = d + s->latch + 2; |
| 218 | } else { |
| 219 | next_time = d + counter; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 220 | } |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 221 | CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
| 222 | s->latch, d, next_time - d); |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 223 | next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) + |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 224 | s->load_time; |
| 225 | if (next_time <= current_time) |
| 226 | next_time = current_time + 1; |
| 227 | return next_time; |
| 228 | } |
| 229 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 230 | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 231 | int64_t current_time) |
| 232 | { |
| 233 | if (!ti->timer) |
| 234 | return; |
| 235 | if ((s->acr & T1MODE) != T1MODE_CONT) { |
| 236 | qemu_del_timer(ti->timer); |
| 237 | } else { |
| 238 | ti->next_irq_time = get_next_irq_time(ti, current_time); |
| 239 | qemu_mod_timer(ti->timer, ti->next_irq_time); |
| 240 | } |
| 241 | } |
| 242 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 243 | static void cuda_timer1(void *opaque) |
| 244 | { |
| 245 | CUDAState *s = opaque; |
| 246 | CUDATimer *ti = &s->timers[0]; |
| 247 | |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 248 | cuda_timer_update(s, ti, ti->next_irq_time); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 249 | s->ifr |= T1_INT; |
| 250 | cuda_update_irq(s); |
| 251 | } |
| 252 | |
| 253 | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
| 254 | { |
| 255 | CUDAState *s = opaque; |
| 256 | uint32_t val; |
| 257 | |
| 258 | addr = (addr >> 9) & 0xf; |
| 259 | switch(addr) { |
| 260 | case 0: |
| 261 | val = s->b; |
| 262 | break; |
| 263 | case 1: |
| 264 | val = s->a; |
| 265 | break; |
| 266 | case 2: |
| 267 | val = s->dirb; |
| 268 | break; |
| 269 | case 3: |
| 270 | val = s->dira; |
| 271 | break; |
| 272 | case 4: |
| 273 | val = get_counter(&s->timers[0]) & 0xff; |
| 274 | s->ifr &= ~T1_INT; |
| 275 | cuda_update_irq(s); |
| 276 | break; |
| 277 | case 5: |
| 278 | val = get_counter(&s->timers[0]) >> 8; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 279 | cuda_update_irq(s); |
| 280 | break; |
| 281 | case 6: |
| 282 | val = s->timers[0].latch & 0xff; |
| 283 | break; |
| 284 | case 7: |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 285 | /* XXX: check this */ |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 286 | val = (s->timers[0].latch >> 8) & 0xff; |
| 287 | break; |
| 288 | case 8: |
| 289 | val = get_counter(&s->timers[1]) & 0xff; |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 290 | s->ifr &= ~T2_INT; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 291 | break; |
| 292 | case 9: |
| 293 | val = get_counter(&s->timers[1]) >> 8; |
| 294 | break; |
| 295 | case 10: |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 296 | val = s->sr; |
| 297 | s->ifr &= ~SR_INT; |
| 298 | cuda_update_irq(s); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 299 | break; |
| 300 | case 11: |
| 301 | val = s->acr; |
| 302 | break; |
| 303 | case 12: |
| 304 | val = s->pcr; |
| 305 | break; |
| 306 | case 13: |
| 307 | val = s->ifr; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 308 | if (s->ifr & s->ier) |
bellard | b7c7b18 | 2005-07-23 14:01:47 +0000 | [diff] [blame] | 309 | val |= 0x80; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 310 | break; |
| 311 | case 14: |
bellard | b7c7b18 | 2005-07-23 14:01:47 +0000 | [diff] [blame] | 312 | val = s->ier | 0x80; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 313 | break; |
| 314 | default: |
| 315 | case 15: |
| 316 | val = s->anh; |
| 317 | break; |
| 318 | } |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 319 | if (addr != 13 || val != 0) |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 320 | CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 321 | return val; |
| 322 | } |
| 323 | |
| 324 | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 325 | { |
| 326 | CUDAState *s = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 327 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 328 | addr = (addr >> 9) & 0xf; |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 329 | CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 330 | |
| 331 | switch(addr) { |
| 332 | case 0: |
| 333 | s->b = val; |
| 334 | cuda_update(s); |
| 335 | break; |
| 336 | case 1: |
| 337 | s->a = val; |
| 338 | break; |
| 339 | case 2: |
| 340 | s->dirb = val; |
| 341 | break; |
| 342 | case 3: |
| 343 | s->dira = val; |
| 344 | break; |
| 345 | case 4: |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 346 | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
| 347 | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 348 | break; |
| 349 | case 5: |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 350 | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
| 351 | s->ifr &= ~T1_INT; |
| 352 | set_counter(s, &s->timers[0], s->timers[0].latch); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 353 | break; |
| 354 | case 6: |
| 355 | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 356 | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 357 | break; |
| 358 | case 7: |
| 359 | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 360 | s->ifr &= ~T1_INT; |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 361 | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 362 | break; |
| 363 | case 8: |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 364 | s->timers[1].latch = val; |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 365 | set_counter(s, &s->timers[1], val); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 366 | break; |
| 367 | case 9: |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 368 | set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 369 | break; |
| 370 | case 10: |
| 371 | s->sr = val; |
| 372 | break; |
| 373 | case 11: |
| 374 | s->acr = val; |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 375 | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock)); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 376 | cuda_update(s); |
| 377 | break; |
| 378 | case 12: |
| 379 | s->pcr = val; |
| 380 | break; |
| 381 | case 13: |
| 382 | /* reset bits */ |
| 383 | s->ifr &= ~val; |
| 384 | cuda_update_irq(s); |
| 385 | break; |
| 386 | case 14: |
| 387 | if (val & IER_SET) { |
| 388 | /* set bits */ |
| 389 | s->ier |= val & 0x7f; |
| 390 | } else { |
| 391 | /* reset bits */ |
| 392 | s->ier &= ~val; |
| 393 | } |
| 394 | cuda_update_irq(s); |
| 395 | break; |
| 396 | default: |
| 397 | case 15: |
| 398 | s->anh = val; |
| 399 | break; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | /* NOTE: TIP and TREQ are negated */ |
| 404 | static void cuda_update(CUDAState *s) |
| 405 | { |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 406 | int packet_received, len; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 407 | |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 408 | packet_received = 0; |
| 409 | if (!(s->b & TIP)) { |
| 410 | /* transfer requested from host */ |
| 411 | |
| 412 | if (s->acr & SR_OUT) { |
| 413 | /* data output */ |
| 414 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
| 415 | if (s->data_out_index < sizeof(s->data_out)) { |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 416 | CUDA_DPRINTF("send: %02x\n", s->sr); |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 417 | s->data_out[s->data_out_index++] = s->sr; |
| 418 | s->ifr |= SR_INT; |
| 419 | cuda_update_irq(s); |
| 420 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 421 | } |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 422 | } else { |
| 423 | if (s->data_in_index < s->data_in_size) { |
| 424 | /* data input */ |
| 425 | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) { |
| 426 | s->sr = s->data_in[s->data_in_index++]; |
blueswir1 | ea026b2 | 2008-12-24 09:38:16 +0000 | [diff] [blame] | 427 | CUDA_DPRINTF("recv: %02x\n", s->sr); |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 428 | /* indicate end of transfer */ |
| 429 | if (s->data_in_index >= s->data_in_size) { |
| 430 | s->b = (s->b | TREQ); |
| 431 | } |
| 432 | s->ifr |= SR_INT; |
| 433 | cuda_update_irq(s); |
| 434 | } |
| 435 | } |
| 436 | } |
| 437 | } else { |
| 438 | /* no transfer requested: handle sync case */ |
| 439 | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) { |
| 440 | /* update TREQ state each time TACK change state */ |
| 441 | if (s->b & TACK) |
| 442 | s->b = (s->b | TREQ); |
| 443 | else |
| 444 | s->b = (s->b & ~TREQ); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 445 | s->ifr |= SR_INT; |
| 446 | cuda_update_irq(s); |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 447 | } else { |
| 448 | if (!(s->last_b & TIP)) { |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 449 | /* handle end of host to cuda transfer */ |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 450 | packet_received = (s->data_out_index > 0); |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 451 | /* always an IRQ at the end of transfer */ |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 452 | s->ifr |= SR_INT; |
| 453 | cuda_update_irq(s); |
| 454 | } |
| 455 | /* signal if there is data to read */ |
| 456 | if (s->data_in_index < s->data_in_size) { |
| 457 | s->b = (s->b & ~TREQ); |
| 458 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 459 | } |
| 460 | } |
| 461 | |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 462 | s->last_acr = s->acr; |
| 463 | s->last_b = s->b; |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 464 | |
| 465 | /* NOTE: cuda_receive_packet_from_host() can call cuda_update() |
| 466 | recursively */ |
| 467 | if (packet_received) { |
| 468 | len = s->data_out_index; |
| 469 | s->data_out_index = 0; |
| 470 | cuda_receive_packet_from_host(s, s->data_out, len); |
| 471 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 472 | } |
| 473 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 474 | static void cuda_send_packet_to_host(CUDAState *s, |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 475 | const uint8_t *data, int len) |
| 476 | { |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 477 | #ifdef DEBUG_CUDA_PACKET |
| 478 | { |
| 479 | int i; |
| 480 | printf("cuda_send_packet_to_host:\n"); |
| 481 | for(i = 0; i < len; i++) |
| 482 | printf(" %02x", data[i]); |
| 483 | printf("\n"); |
| 484 | } |
| 485 | #endif |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 486 | memcpy(s->data_in, data, len); |
| 487 | s->data_in_size = len; |
| 488 | s->data_in_index = 0; |
| 489 | cuda_update(s); |
| 490 | s->ifr |= SR_INT; |
| 491 | cuda_update_irq(s); |
| 492 | } |
| 493 | |
bellard | 7db4eea | 2004-07-06 20:57:47 +0000 | [diff] [blame] | 494 | static void cuda_adb_poll(void *opaque) |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 495 | { |
| 496 | CUDAState *s = opaque; |
| 497 | uint8_t obuf[ADB_MAX_OUT_LEN + 2]; |
| 498 | int olen; |
| 499 | |
| 500 | olen = adb_poll(&adb_bus, obuf + 2); |
| 501 | if (olen > 0) { |
| 502 | obuf[0] = ADB_PACKET; |
| 503 | obuf[1] = 0x40; /* polled data */ |
| 504 | cuda_send_packet_to_host(s, obuf, olen + 2); |
| 505 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 506 | qemu_mod_timer(s->adb_poll_timer, |
| 507 | qemu_get_clock(vm_clock) + |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 508 | (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 509 | } |
| 510 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 511 | static void cuda_receive_packet(CUDAState *s, |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 512 | const uint8_t *data, int len) |
| 513 | { |
| 514 | uint8_t obuf[16]; |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 515 | int autopoll; |
| 516 | uint32_t ti; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 517 | |
| 518 | switch(data[0]) { |
| 519 | case CUDA_AUTOPOLL: |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 520 | autopoll = (data[1] != 0); |
| 521 | if (autopoll != s->autopoll) { |
| 522 | s->autopoll = autopoll; |
| 523 | if (autopoll) { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 524 | qemu_mod_timer(s->adb_poll_timer, |
| 525 | qemu_get_clock(vm_clock) + |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 526 | (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 527 | } else { |
| 528 | qemu_del_timer(s->adb_poll_timer); |
| 529 | } |
| 530 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 531 | obuf[0] = CUDA_PACKET; |
| 532 | obuf[1] = data[1]; |
| 533 | cuda_send_packet_to_host(s, obuf, 2); |
| 534 | break; |
bellard | dccfafc | 2005-04-23 18:16:54 +0000 | [diff] [blame] | 535 | case CUDA_SET_TIME: |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 536 | ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 537 | s->tick_offset = ti - (qemu_get_clock(vm_clock) / get_ticks_per_sec()); |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 538 | obuf[0] = CUDA_PACKET; |
| 539 | obuf[1] = 0; |
| 540 | obuf[2] = 0; |
| 541 | cuda_send_packet_to_host(s, obuf, 3); |
| 542 | break; |
| 543 | case CUDA_GET_TIME: |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 544 | ti = s->tick_offset + (qemu_get_clock(vm_clock) / get_ticks_per_sec()); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 545 | obuf[0] = CUDA_PACKET; |
| 546 | obuf[1] = 0; |
| 547 | obuf[2] = 0; |
| 548 | obuf[3] = ti >> 24; |
| 549 | obuf[4] = ti >> 16; |
| 550 | obuf[5] = ti >> 8; |
| 551 | obuf[6] = ti; |
| 552 | cuda_send_packet_to_host(s, obuf, 7); |
| 553 | break; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 554 | case CUDA_FILE_SERVER_FLAG: |
| 555 | case CUDA_SET_DEVICE_LIST: |
| 556 | case CUDA_SET_AUTO_RATE: |
| 557 | case CUDA_SET_POWER_MESSAGES: |
| 558 | obuf[0] = CUDA_PACKET; |
| 559 | obuf[1] = 0; |
| 560 | cuda_send_packet_to_host(s, obuf, 2); |
| 561 | break; |
bellard | d7ce296 | 2005-02-09 00:07:08 +0000 | [diff] [blame] | 562 | case CUDA_POWERDOWN: |
| 563 | obuf[0] = CUDA_PACKET; |
| 564 | obuf[1] = 0; |
| 565 | cuda_send_packet_to_host(s, obuf, 2); |
aurel32 | c76ee25 | 2009-01-15 18:57:25 +0000 | [diff] [blame] | 566 | qemu_system_shutdown_request(); |
| 567 | break; |
j_mayer | 0686970 | 2007-09-19 04:46:57 +0000 | [diff] [blame] | 568 | case CUDA_RESET_SYSTEM: |
| 569 | obuf[0] = CUDA_PACKET; |
| 570 | obuf[1] = 0; |
| 571 | cuda_send_packet_to_host(s, obuf, 2); |
| 572 | qemu_system_reset_request(); |
| 573 | break; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 574 | default: |
| 575 | break; |
| 576 | } |
| 577 | } |
| 578 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 579 | static void cuda_receive_packet_from_host(CUDAState *s, |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 580 | const uint8_t *data, int len) |
| 581 | { |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 582 | #ifdef DEBUG_CUDA_PACKET |
| 583 | { |
| 584 | int i; |
bellard | cadae95 | 2005-06-05 15:24:23 +0000 | [diff] [blame] | 585 | printf("cuda_receive_packet_from_host:\n"); |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 586 | for(i = 0; i < len; i++) |
| 587 | printf(" %02x", data[i]); |
| 588 | printf("\n"); |
| 589 | } |
| 590 | #endif |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 591 | switch(data[0]) { |
| 592 | case ADB_PACKET: |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 593 | { |
| 594 | uint8_t obuf[ADB_MAX_OUT_LEN + 2]; |
| 595 | int olen; |
| 596 | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
bellard | 38f0b14 | 2004-07-12 20:16:00 +0000 | [diff] [blame] | 597 | if (olen > 0) { |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 598 | obuf[0] = ADB_PACKET; |
| 599 | obuf[1] = 0x00; |
| 600 | } else { |
bellard | 38f0b14 | 2004-07-12 20:16:00 +0000 | [diff] [blame] | 601 | /* error */ |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 602 | obuf[0] = ADB_PACKET; |
bellard | 38f0b14 | 2004-07-12 20:16:00 +0000 | [diff] [blame] | 603 | obuf[1] = -olen; |
| 604 | olen = 0; |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 605 | } |
| 606 | cuda_send_packet_to_host(s, obuf, olen + 2); |
| 607 | } |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 608 | break; |
| 609 | case CUDA_PACKET: |
| 610 | cuda_receive_packet(s, data + 1, len - 1); |
| 611 | break; |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 616 | { |
| 617 | } |
| 618 | |
| 619 | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 620 | { |
| 621 | } |
| 622 | |
| 623 | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
| 624 | { |
| 625 | return 0; |
| 626 | } |
| 627 | |
| 628 | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
| 629 | { |
| 630 | return 0; |
| 631 | } |
| 632 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 633 | static CPUWriteMemoryFunc * const cuda_write[] = { |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 634 | &cuda_writeb, |
| 635 | &cuda_writew, |
| 636 | &cuda_writel, |
| 637 | }; |
| 638 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 639 | static CPUReadMemoryFunc * const cuda_read[] = { |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 640 | &cuda_readb, |
| 641 | &cuda_readw, |
| 642 | &cuda_readl, |
| 643 | }; |
| 644 | |
blueswir1 | 9b64997 | 2008-12-30 19:01:19 +0000 | [diff] [blame] | 645 | static void cuda_save_timer(QEMUFile *f, CUDATimer *s) |
| 646 | { |
| 647 | qemu_put_be16s(f, &s->latch); |
| 648 | qemu_put_be16s(f, &s->counter_value); |
| 649 | qemu_put_sbe64s(f, &s->load_time); |
| 650 | qemu_put_sbe64s(f, &s->next_irq_time); |
| 651 | if (s->timer) |
| 652 | qemu_put_timer(f, s->timer); |
| 653 | } |
| 654 | |
| 655 | static void cuda_save(QEMUFile *f, void *opaque) |
| 656 | { |
| 657 | CUDAState *s = (CUDAState *)opaque; |
| 658 | |
| 659 | qemu_put_ubyte(f, s->b); |
| 660 | qemu_put_ubyte(f, s->a); |
| 661 | qemu_put_ubyte(f, s->dirb); |
| 662 | qemu_put_ubyte(f, s->dira); |
| 663 | qemu_put_ubyte(f, s->sr); |
| 664 | qemu_put_ubyte(f, s->acr); |
| 665 | qemu_put_ubyte(f, s->pcr); |
| 666 | qemu_put_ubyte(f, s->ifr); |
| 667 | qemu_put_ubyte(f, s->ier); |
| 668 | qemu_put_ubyte(f, s->anh); |
| 669 | qemu_put_sbe32s(f, &s->data_in_size); |
| 670 | qemu_put_sbe32s(f, &s->data_in_index); |
| 671 | qemu_put_sbe32s(f, &s->data_out_index); |
| 672 | qemu_put_ubyte(f, s->autopoll); |
| 673 | qemu_put_buffer(f, s->data_in, sizeof(s->data_in)); |
| 674 | qemu_put_buffer(f, s->data_out, sizeof(s->data_out)); |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 675 | qemu_put_be32s(f, &s->tick_offset); |
blueswir1 | 9b64997 | 2008-12-30 19:01:19 +0000 | [diff] [blame] | 676 | cuda_save_timer(f, &s->timers[0]); |
| 677 | cuda_save_timer(f, &s->timers[1]); |
| 678 | } |
| 679 | |
| 680 | static void cuda_load_timer(QEMUFile *f, CUDATimer *s) |
| 681 | { |
| 682 | qemu_get_be16s(f, &s->latch); |
| 683 | qemu_get_be16s(f, &s->counter_value); |
| 684 | qemu_get_sbe64s(f, &s->load_time); |
| 685 | qemu_get_sbe64s(f, &s->next_irq_time); |
| 686 | if (s->timer) |
| 687 | qemu_get_timer(f, s->timer); |
| 688 | } |
| 689 | |
| 690 | static int cuda_load(QEMUFile *f, void *opaque, int version_id) |
| 691 | { |
| 692 | CUDAState *s = (CUDAState *)opaque; |
| 693 | |
| 694 | if (version_id != 1) |
| 695 | return -EINVAL; |
| 696 | |
| 697 | s->b = qemu_get_ubyte(f); |
| 698 | s->a = qemu_get_ubyte(f); |
| 699 | s->dirb = qemu_get_ubyte(f); |
| 700 | s->dira = qemu_get_ubyte(f); |
| 701 | s->sr = qemu_get_ubyte(f); |
| 702 | s->acr = qemu_get_ubyte(f); |
| 703 | s->pcr = qemu_get_ubyte(f); |
| 704 | s->ifr = qemu_get_ubyte(f); |
| 705 | s->ier = qemu_get_ubyte(f); |
| 706 | s->anh = qemu_get_ubyte(f); |
| 707 | qemu_get_sbe32s(f, &s->data_in_size); |
| 708 | qemu_get_sbe32s(f, &s->data_in_index); |
| 709 | qemu_get_sbe32s(f, &s->data_out_index); |
| 710 | s->autopoll = qemu_get_ubyte(f); |
| 711 | qemu_get_buffer(f, s->data_in, sizeof(s->data_in)); |
| 712 | qemu_get_buffer(f, s->data_out, sizeof(s->data_out)); |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 713 | qemu_get_be32s(f, &s->tick_offset); |
blueswir1 | 9b64997 | 2008-12-30 19:01:19 +0000 | [diff] [blame] | 714 | cuda_load_timer(f, &s->timers[0]); |
| 715 | cuda_load_timer(f, &s->timers[1]); |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
blueswir1 | 6e6b736 | 2008-12-28 18:27:10 +0000 | [diff] [blame] | 720 | static void cuda_reset(void *opaque) |
| 721 | { |
| 722 | CUDAState *s = opaque; |
| 723 | |
| 724 | s->b = 0; |
| 725 | s->a = 0; |
| 726 | s->dirb = 0; |
| 727 | s->dira = 0; |
| 728 | s->sr = 0; |
| 729 | s->acr = 0; |
| 730 | s->pcr = 0; |
| 731 | s->ifr = 0; |
| 732 | s->ier = 0; |
| 733 | // s->ier = T1_INT | SR_INT; |
| 734 | s->anh = 0; |
| 735 | s->data_in_size = 0; |
| 736 | s->data_in_index = 0; |
| 737 | s->data_out_index = 0; |
| 738 | s->autopoll = 0; |
| 739 | |
| 740 | s->timers[0].latch = 0xffff; |
| 741 | set_counter(s, &s->timers[0], 0xffff); |
| 742 | |
| 743 | s->timers[1].latch = 0; |
| 744 | set_counter(s, &s->timers[1], 0xffff); |
| 745 | } |
| 746 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 747 | void cuda_init (int *cuda_mem_index, qemu_irq irq) |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 748 | { |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 749 | struct tm tm; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 750 | CUDAState *s = &cuda_state; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 751 | |
bellard | 819e712 | 2004-06-21 16:47:13 +0000 | [diff] [blame] | 752 | s->irq = irq; |
| 753 | |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 754 | s->timers[0].index = 0; |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 755 | s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s); |
bellard | 61271e5 | 2005-07-07 21:45:18 +0000 | [diff] [blame] | 756 | |
| 757 | s->timers[1].index = 1; |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 758 | |
aurel32 | 9c554c1 | 2009-01-18 12:16:26 +0000 | [diff] [blame] | 759 | qemu_get_timedate(&tm, 0); |
| 760 | s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; |
aurel32 | 5703c17 | 2009-01-15 18:57:15 +0000 | [diff] [blame] | 761 | |
bellard | e2733d2 | 2004-06-21 22:46:10 +0000 | [diff] [blame] | 762 | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 763 | *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s); |
blueswir1 | 9b64997 | 2008-12-30 19:01:19 +0000 | [diff] [blame] | 764 | register_savevm("cuda", -1, 1, cuda_save, cuda_load, s); |
Jan Kiszka | a08d436 | 2009-06-27 09:25:07 +0200 | [diff] [blame] | 765 | qemu_register_reset(cuda_reset, s); |
blueswir1 | 6e6b736 | 2008-12-28 18:27:10 +0000 | [diff] [blame] | 766 | cuda_reset(s); |
bellard | 267002c | 2004-06-03 18:46:20 +0000 | [diff] [blame] | 767 | } |