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Bharata B Rao3b542542016-06-10 06:29:01 +05301/*
2 * sPAPR CPU core device.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9#ifndef HW_SPAPR_CPU_CORE_H
10#define HW_SPAPR_CPU_CORE_H
11
Bharata B Rao3b542542016-06-10 06:29:01 +053012#include "hw/cpu/core.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020013#include "hw/qdev-core.h"
Thomas Huthfcf5ef22016-10-11 08:56:52 +020014#include "target/ppc/cpu-qom.h"
David Gibson84369f62018-05-01 16:22:49 +100015#include "target/ppc/cpu.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040016#include "qom/object.h"
Bharata B Rao3b542542016-06-10 06:29:01 +053017
18#define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
Eduardo Habkostc821774a2020-08-31 17:07:37 -040019OBJECT_DECLARE_TYPE(SpaprCpuCore, SpaprCpuCoreClass,
Eduardo Habkost30b57072020-09-16 14:25:17 -040020 SPAPR_CPU_CORE)
Bharata B Rao3b542542016-06-10 06:29:01 +053021
Igor Mammedov44cd95e2017-10-09 21:51:00 +020022#define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
23
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040024struct SpaprCpuCore {
Bharata B Rao3b542542016-06-10 06:29:01 +053025 /*< private >*/
26 CPUCore parent_obj;
27
28 /*< public >*/
Greg Kurz94ad93b2017-11-20 10:19:54 +010029 PowerPCCPU **threads;
Igor Mammedov0b8497f2017-05-10 13:29:46 +020030 int node_id;
David Gibsonce2918c2019-03-06 15:35:37 +110031 bool pre_3_0_migration; /* older machine don't know about SpaprCpuState */
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040032};
Bharata B Rao3b542542016-06-10 06:29:01 +053033
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040034struct SpaprCpuCoreClass {
Bharata B Rao7ebaf792016-09-12 13:27:20 +053035 DeviceClass parent_class;
Igor Mammedovb51d3c82017-10-09 21:51:01 +020036 const char *cpu_type;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040037};
Bharata B Rao7ebaf792016-09-12 13:27:20 +053038
Igor Mammedov2e9c10e2017-10-09 21:51:05 +020039const char *spapr_get_cpu_core_type(const char *cpu_type);
Alexey Kardashevskiy395a20d2020-03-10 16:07:31 +110040void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
41 target_ulong r1, target_ulong r3,
42 target_ulong r4);
David Gibson84369f62018-05-01 16:22:49 +100043
David Gibsonce2918c2019-03-06 15:35:37 +110044typedef struct SpaprCpuState {
David Gibson7388efa2018-06-13 16:22:18 +100045 uint64_t vpa_addr;
46 uint64_t slb_shadow_addr, slb_shadow_size;
47 uint64_t dtl_addr, dtl_size;
Nicholas Piggin3a6e6222019-07-18 13:42:12 +100048 bool prod; /* not migrated, only used to improve dispatch latencies */
Cédric Le Goatera28b9a52019-01-17 08:53:26 +010049 struct ICPState *icp;
50 struct XiveTCTX *tctx;
David Gibsonce2918c2019-03-06 15:35:37 +110051} SpaprCpuState;
David Gibson7388efa2018-06-13 16:22:18 +100052
David Gibsonce2918c2019-03-06 15:35:37 +110053static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
David Gibson7388efa2018-06-13 16:22:18 +100054{
David Gibsonce2918c2019-03-06 15:35:37 +110055 return (SpaprCpuState *)cpu->machine_data;
David Gibson7388efa2018-06-13 16:22:18 +100056}
57
Bharata B Rao3b542542016-06-10 06:29:01 +053058#endif