bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1 | /* |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 2 | * QEMU generic PowerPC hardware System Emulator |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 24 | #include "hw/hw.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 25 | #include "hw/ppc/ppc.h" |
Andreas Färber | 2b92757 | 2013-06-16 17:04:21 +0200 | [diff] [blame] | 26 | #include "hw/ppc/ppc_e500.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 27 | #include "qemu/timer.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 28 | #include "sysemu/sysemu.h" |
Alexey Kardashevskiy | 0ce470c | 2014-02-02 01:45:51 +1100 | [diff] [blame] | 29 | #include "sysemu/cpus.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 30 | #include "hw/timer/m48t59.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 31 | #include "qemu/log.h" |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 32 | #include "qemu/error-report.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 33 | #include "hw/loader.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 34 | #include "sysemu/kvm.h" |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 35 | #include "kvm_ppc.h" |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 36 | #include "trace.h" |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 37 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 38 | //#define PPC_DEBUG_IRQ |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 39 | //#define PPC_DEBUG_TB |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 40 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 41 | #ifdef PPC_DEBUG_IRQ |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 42 | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 43 | #else |
| 44 | # define LOG_IRQ(...) do { } while (0) |
| 45 | #endif |
| 46 | |
| 47 | |
| 48 | #ifdef PPC_DEBUG_TB |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 49 | # define LOG_TB(...) qemu_log(__VA_ARGS__) |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 50 | #else |
| 51 | # define LOG_TB(...) do { } while (0) |
| 52 | #endif |
| 53 | |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 54 | #define NSEC_PER_SEC 1000000000LL |
| 55 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 56 | static void cpu_ppc_tb_stop (CPUPPCState *env); |
| 57 | static void cpu_ppc_tb_start (CPUPPCState *env); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 58 | |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 59 | void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 60 | { |
Andreas Färber | d8ed887 | 2013-01-17 22:30:20 +0100 | [diff] [blame] | 61 | CPUState *cs = CPU(cpu); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 62 | CPUPPCState *env = &cpu->env; |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 63 | unsigned int old_pending = env->pending_interrupts; |
| 64 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 65 | if (level) { |
| 66 | env->pending_interrupts |= 1 << n_IRQ; |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 67 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 68 | } else { |
| 69 | env->pending_interrupts &= ~(1 << n_IRQ); |
Andreas Färber | d8ed887 | 2013-01-17 22:30:20 +0100 | [diff] [blame] | 70 | if (env->pending_interrupts == 0) { |
| 71 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 72 | } |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 73 | } |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 74 | |
| 75 | if (old_pending != env->pending_interrupts) { |
| 76 | #ifdef CONFIG_KVM |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 77 | kvmppc_set_interrupt(cpu, n_IRQ, level); |
Alexander Graf | fc87e18 | 2010-08-30 13:49:15 +0200 | [diff] [blame] | 78 | #endif |
| 79 | } |
| 80 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 81 | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 82 | "req %08x\n", __func__, env, n_IRQ, level, |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 83 | env->pending_interrupts, CPU(cpu)->interrupt_request); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 84 | } |
| 85 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 86 | /* PowerPC 6xx / 7xx internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 87 | static void ppc6xx_set_irq(void *opaque, int pin, int level) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 88 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 89 | PowerPCCPU *cpu = opaque; |
| 90 | CPUPPCState *env = &cpu->env; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 91 | int cur_level; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 92 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 93 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 94 | env, pin, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 95 | cur_level = (env->irq_input_state >> pin) & 1; |
| 96 | /* Don't generate spurious events */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 97 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 98 | CPUState *cs = CPU(cpu); |
| 99 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 100 | switch (pin) { |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 101 | case PPC6xx_INPUT_TBEN: |
| 102 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 103 | LOG_IRQ("%s: %s the time base\n", |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 104 | __func__, level ? "start" : "stop"); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 105 | if (level) { |
| 106 | cpu_ppc_tb_start(env); |
| 107 | } else { |
| 108 | cpu_ppc_tb_stop(env); |
| 109 | } |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 110 | case PPC6xx_INPUT_INT: |
| 111 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 112 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 113 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 114 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 115 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 116 | case PPC6xx_INPUT_SMI: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 117 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 118 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 119 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 120 | ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 121 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 122 | case PPC6xx_INPUT_MCP: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 123 | /* Negative edge sensitive */ |
| 124 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 125 | * 603/604/740/750: check HID0[EMCP] |
| 126 | */ |
| 127 | if (cur_level == 1 && level == 0) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 128 | LOG_IRQ("%s: raise machine check state\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 129 | __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 130 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 131 | } |
| 132 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 133 | case PPC6xx_INPUT_CKSTP_IN: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 134 | /* Level sensitive - active low */ |
| 135 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
j_mayer | e63ecc6 | 2007-10-14 08:48:23 +0000 | [diff] [blame] | 136 | /* XXX: Note that the only way to restart the CPU is to reset it */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 137 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 138 | LOG_IRQ("%s: stop the CPU\n", __func__); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 139 | cs->halted = 1; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 140 | } |
| 141 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 142 | case PPC6xx_INPUT_HRESET: |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 143 | /* Level sensitive - active low */ |
| 144 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 145 | LOG_IRQ("%s: reset the CPU\n", __func__); |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 146 | cpu_interrupt(cs, CPU_INTERRUPT_RESET); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 147 | } |
| 148 | break; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 149 | case PPC6xx_INPUT_SRESET: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 150 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 151 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 152 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 153 | break; |
| 154 | default: |
| 155 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 156 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 157 | return; |
| 158 | } |
| 159 | if (level) |
| 160 | env->irq_input_state |= 1 << pin; |
| 161 | else |
| 162 | env->irq_input_state &= ~(1 << pin); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 163 | } |
| 164 | } |
| 165 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 166 | void ppc6xx_irq_init(CPUPPCState *env) |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 167 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 168 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 169 | |
| 170 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 171 | PPC6xx_INPUT_NB); |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 172 | } |
| 173 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 174 | #if defined(TARGET_PPC64) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 175 | /* PowerPC 970 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 176 | static void ppc970_set_irq(void *opaque, int pin, int level) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 177 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 178 | PowerPCCPU *cpu = opaque; |
| 179 | CPUPPCState *env = &cpu->env; |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 180 | int cur_level; |
| 181 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 182 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 183 | env, pin, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 184 | cur_level = (env->irq_input_state >> pin) & 1; |
| 185 | /* Don't generate spurious events */ |
| 186 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 187 | CPUState *cs = CPU(cpu); |
| 188 | |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 189 | switch (pin) { |
| 190 | case PPC970_INPUT_INT: |
| 191 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 192 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 193 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 194 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 195 | break; |
| 196 | case PPC970_INPUT_THINT: |
| 197 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 198 | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 199 | level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 200 | ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 201 | break; |
| 202 | case PPC970_INPUT_MCP: |
| 203 | /* Negative edge sensitive */ |
| 204 | /* XXX: TODO: actual reaction may depends on HID0 status |
| 205 | * 603/604/740/750: check HID0[EMCP] |
| 206 | */ |
| 207 | if (cur_level == 1 && level == 0) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 208 | LOG_IRQ("%s: raise machine check state\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 209 | __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 210 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 211 | } |
| 212 | break; |
| 213 | case PPC970_INPUT_CKSTP: |
| 214 | /* Level sensitive - active low */ |
| 215 | /* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
| 216 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 217 | LOG_IRQ("%s: stop the CPU\n", __func__); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 218 | cs->halted = 1; |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 219 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 220 | LOG_IRQ("%s: restart the CPU\n", __func__); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 221 | cs->halted = 0; |
| 222 | qemu_cpu_kick(cs); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 223 | } |
| 224 | break; |
| 225 | case PPC970_INPUT_HRESET: |
| 226 | /* Level sensitive - active low */ |
| 227 | if (level) { |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 228 | cpu_interrupt(cs, CPU_INTERRUPT_RESET); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 229 | } |
| 230 | break; |
| 231 | case PPC970_INPUT_SRESET: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 232 | LOG_IRQ("%s: set the RESET IRQ state to %d\n", |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 233 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 234 | ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 235 | break; |
| 236 | case PPC970_INPUT_TBEN: |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 237 | LOG_IRQ("%s: set the TBEN state to %d\n", __func__, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 238 | level); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 239 | /* XXX: TODO */ |
| 240 | break; |
| 241 | default: |
| 242 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 243 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 244 | return; |
| 245 | } |
| 246 | if (level) |
| 247 | env->irq_input_state |= 1 << pin; |
| 248 | else |
| 249 | env->irq_input_state &= ~(1 << pin); |
| 250 | } |
| 251 | } |
| 252 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 253 | void ppc970_irq_init(CPUPPCState *env) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 254 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 255 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 256 | |
| 257 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 258 | PPC970_INPUT_NB); |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 259 | } |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 260 | |
| 261 | /* POWER7 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 262 | static void power7_set_irq(void *opaque, int pin, int level) |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 263 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 264 | PowerPCCPU *cpu = opaque; |
| 265 | CPUPPCState *env = &cpu->env; |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 266 | |
| 267 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
| 268 | env, pin, level); |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 269 | |
| 270 | switch (pin) { |
| 271 | case POWER7_INPUT_INT: |
| 272 | /* Level sensitive - active high */ |
| 273 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
| 274 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 275 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 276 | break; |
| 277 | default: |
| 278 | /* Unknown pin - do nothing */ |
| 279 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
| 280 | return; |
| 281 | } |
| 282 | if (level) { |
| 283 | env->irq_input_state |= 1 << pin; |
| 284 | } else { |
| 285 | env->irq_input_state &= ~(1 << pin); |
| 286 | } |
| 287 | } |
| 288 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 289 | void ppcPOWER7_irq_init(CPUPPCState *env) |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 290 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 291 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 292 | |
| 293 | env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 294 | POWER7_INPUT_NB); |
| 295 | } |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 296 | #endif /* defined(TARGET_PPC64) */ |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 297 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 298 | /* PowerPC 40x internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 299 | static void ppc40x_set_irq(void *opaque, int pin, int level) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 300 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 301 | PowerPCCPU *cpu = opaque; |
| 302 | CPUPPCState *env = &cpu->env; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 303 | int cur_level; |
| 304 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 305 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 306 | env, pin, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 307 | cur_level = (env->irq_input_state >> pin) & 1; |
| 308 | /* Don't generate spurious events */ |
| 309 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 310 | CPUState *cs = CPU(cpu); |
| 311 | |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 312 | switch (pin) { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 313 | case PPC40x_INPUT_RESET_SYS: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 314 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 315 | LOG_IRQ("%s: reset the PowerPC system\n", |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 316 | __func__); |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 317 | ppc40x_system_reset(cpu); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 318 | } |
| 319 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 320 | case PPC40x_INPUT_RESET_CHIP: |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 321 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 322 | LOG_IRQ("%s: reset the PowerPC chip\n", __func__); |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 323 | ppc40x_chip_reset(cpu); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 324 | } |
| 325 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 326 | case PPC40x_INPUT_RESET_CORE: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 327 | /* XXX: TODO: update DBSR[MRR] */ |
| 328 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 329 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 330 | ppc40x_core_reset(cpu); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 331 | } |
| 332 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 333 | case PPC40x_INPUT_CINT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 334 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 335 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 336 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 337 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 338 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 339 | case PPC40x_INPUT_INT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 340 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 341 | LOG_IRQ("%s: set the external IRQ state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 342 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 343 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 344 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 345 | case PPC40x_INPUT_HALT: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 346 | /* Level sensitive - active low */ |
| 347 | if (level) { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 348 | LOG_IRQ("%s: stop the CPU\n", __func__); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 349 | cs->halted = 1; |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 350 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 351 | LOG_IRQ("%s: restart the CPU\n", __func__); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 352 | cs->halted = 0; |
| 353 | qemu_cpu_kick(cs); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 354 | } |
| 355 | break; |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 356 | case PPC40x_INPUT_DEBUG: |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 357 | /* Level sensitive - active high */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 358 | LOG_IRQ("%s: set the debug pin state to %d\n", |
j_mayer | a496775 | 2007-04-16 07:10:48 +0000 | [diff] [blame] | 359 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 360 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 361 | break; |
| 362 | default: |
| 363 | /* Unknown pin - do nothing */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 364 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 365 | return; |
| 366 | } |
| 367 | if (level) |
| 368 | env->irq_input_state |= 1 << pin; |
| 369 | else |
| 370 | env->irq_input_state &= ~(1 << pin); |
| 371 | } |
| 372 | } |
| 373 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 374 | void ppc40x_irq_init(CPUPPCState *env) |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 375 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 376 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 377 | |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 378 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 379 | cpu, PPC40x_INPUT_NB); |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 380 | } |
| 381 | |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 382 | /* PowerPC E500 internal IRQ controller */ |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 383 | static void ppce500_set_irq(void *opaque, int pin, int level) |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 384 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 385 | PowerPCCPU *cpu = opaque; |
| 386 | CPUPPCState *env = &cpu->env; |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 387 | int cur_level; |
| 388 | |
| 389 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__, |
| 390 | env, pin, level); |
| 391 | cur_level = (env->irq_input_state >> pin) & 1; |
| 392 | /* Don't generate spurious events */ |
| 393 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
| 394 | switch (pin) { |
| 395 | case PPCE500_INPUT_MCK: |
| 396 | if (level) { |
| 397 | LOG_IRQ("%s: reset the PowerPC system\n", |
| 398 | __func__); |
| 399 | qemu_system_reset_request(); |
| 400 | } |
| 401 | break; |
| 402 | case PPCE500_INPUT_RESET_CORE: |
| 403 | if (level) { |
| 404 | LOG_IRQ("%s: reset the PowerPC core\n", __func__); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 405 | ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 406 | } |
| 407 | break; |
| 408 | case PPCE500_INPUT_CINT: |
| 409 | /* Level sensitive - active high */ |
| 410 | LOG_IRQ("%s: set the critical IRQ state to %d\n", |
| 411 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 412 | ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 413 | break; |
| 414 | case PPCE500_INPUT_INT: |
| 415 | /* Level sensitive - active high */ |
| 416 | LOG_IRQ("%s: set the core IRQ state to %d\n", |
| 417 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 418 | ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 419 | break; |
| 420 | case PPCE500_INPUT_DEBUG: |
| 421 | /* Level sensitive - active high */ |
| 422 | LOG_IRQ("%s: set the debug pin state to %d\n", |
| 423 | __func__, level); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 424 | ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 425 | break; |
| 426 | default: |
| 427 | /* Unknown pin - do nothing */ |
| 428 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); |
| 429 | return; |
| 430 | } |
| 431 | if (level) |
| 432 | env->irq_input_state |= 1 << pin; |
| 433 | else |
| 434 | env->irq_input_state &= ~(1 << pin); |
| 435 | } |
| 436 | } |
| 437 | |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 438 | void ppce500_irq_init(CPUPPCState *env) |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 439 | { |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 440 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 441 | |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 442 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, |
Andreas Färber | a096124 | 2012-05-03 02:48:44 +0200 | [diff] [blame] | 443 | cpu, PPCE500_INPUT_NB); |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 444 | } |
Alexander Graf | e49798b | 2013-01-17 11:32:21 +0100 | [diff] [blame] | 445 | |
| 446 | /* Enable or Disable the E500 EPR capability */ |
| 447 | void ppce500_set_mpic_proxy(bool enabled) |
| 448 | { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 449 | CPUState *cs; |
Alexander Graf | e49798b | 2013-01-17 11:32:21 +0100 | [diff] [blame] | 450 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 451 | CPU_FOREACH(cs) { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 452 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 453 | |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 454 | cpu->env.mpic_proxy = enabled; |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 455 | if (kvm_enabled()) { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 456 | kvmppc_set_mpic_proxy(cpu, enabled); |
Alexander Graf | 5b95b8b | 2013-01-17 11:54:38 +0100 | [diff] [blame] | 457 | } |
Alexander Graf | e49798b | 2013-01-17 11:32:21 +0100 | [diff] [blame] | 458 | } |
| 459 | } |
| 460 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 461 | /*****************************************************************************/ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 462 | /* PowerPC time base and decrementer emulation */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 463 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 464 | uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 465 | { |
| 466 | /* TB time in tb periods */ |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 467 | return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 468 | } |
| 469 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 470 | uint64_t cpu_ppc_load_tbl (CPUPPCState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 471 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 472 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 473 | uint64_t tb; |
| 474 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 475 | if (kvm_enabled()) { |
| 476 | return env->spr[SPR_TBL]; |
| 477 | } |
| 478 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 479 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 480 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 481 | |
Alexander Graf | e3ea652 | 2009-12-21 12:24:17 +0100 | [diff] [blame] | 482 | return tb; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 483 | } |
| 484 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 485 | static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 486 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 487 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 488 | uint64_t tb; |
| 489 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 490 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 491 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 492 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 493 | return tb >> 32; |
| 494 | } |
| 495 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 496 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 497 | { |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 498 | if (kvm_enabled()) { |
| 499 | return env->spr[SPR_TBU]; |
| 500 | } |
| 501 | |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 502 | return _cpu_ppc_load_tbu(env); |
| 503 | } |
| 504 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 505 | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 506 | int64_t *tb_offsetp, uint64_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 507 | { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 508 | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 509 | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 510 | __func__, value, *tb_offsetp); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 511 | } |
| 512 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 513 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 514 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 515 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 516 | uint64_t tb; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 517 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 518 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 519 | tb &= 0xFFFFFFFF00000000ULL; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 520 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 521 | &tb_env->tb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 522 | } |
| 523 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 524 | static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 525 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 526 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 527 | uint64_t tb; |
| 528 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 529 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 530 | tb &= 0x00000000FFFFFFFFULL; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 531 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 532 | &tb_env->tb_offset, ((uint64_t)value << 32) | tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 533 | } |
| 534 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 535 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 536 | { |
| 537 | _cpu_ppc_store_tbu(env, value); |
| 538 | } |
| 539 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 540 | uint64_t cpu_ppc_load_atbl (CPUPPCState *env) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 541 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 542 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 543 | uint64_t tb; |
| 544 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 545 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 546 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 547 | |
Aurelien Jarno | b711de9 | 2009-12-21 13:52:08 +0100 | [diff] [blame] | 548 | return tb; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 549 | } |
| 550 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 551 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 552 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 553 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 554 | uint64_t tb; |
| 555 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 556 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 557 | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 558 | |
| 559 | return tb >> 32; |
| 560 | } |
| 561 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 562 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 563 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 564 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 565 | uint64_t tb; |
| 566 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 567 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 568 | tb &= 0xFFFFFFFF00000000ULL; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 569 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 570 | &tb_env->atb_offset, tb | (uint64_t)value); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 571 | } |
| 572 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 573 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 574 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 575 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 576 | uint64_t tb; |
| 577 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 578 | tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 579 | tb &= 0x00000000FFFFFFFFULL; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 580 | cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 581 | &tb_env->atb_offset, ((uint64_t)value << 32) | tb); |
| 582 | } |
| 583 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 584 | static void cpu_ppc_tb_stop (CPUPPCState *env) |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 585 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 586 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 587 | uint64_t tb, atb, vmclk; |
| 588 | |
| 589 | /* If the time base is already frozen, do nothing */ |
| 590 | if (tb_env->tb_freq != 0) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 591 | vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 592 | /* Get the time base */ |
| 593 | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
| 594 | /* Get the alternate time base */ |
| 595 | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
| 596 | /* Store the time base value (ie compute the current offset) */ |
| 597 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 598 | /* Store the alternate time base value (compute the current offset) */ |
| 599 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 600 | /* Set the time base frequency to zero */ |
| 601 | tb_env->tb_freq = 0; |
| 602 | /* Now, the time bases are frozen to tb_offset / atb_offset value */ |
| 603 | } |
| 604 | } |
| 605 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 606 | static void cpu_ppc_tb_start (CPUPPCState *env) |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 607 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 608 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 609 | uint64_t tb, atb, vmclk; |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 610 | |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 611 | /* If the time base is not frozen, do nothing */ |
| 612 | if (tb_env->tb_freq == 0) { |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 613 | vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 614 | /* Get the time base from tb_offset */ |
| 615 | tb = tb_env->tb_offset; |
| 616 | /* Get the alternate time base from atb_offset */ |
| 617 | atb = tb_env->atb_offset; |
| 618 | /* Restore the tb frequency from the decrementer frequency */ |
| 619 | tb_env->tb_freq = tb_env->decr_freq; |
| 620 | /* Store the time base value */ |
| 621 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
| 622 | /* Store the alternate time base value */ |
| 623 | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
| 624 | } |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 625 | } |
| 626 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 627 | bool ppc_decr_clear_on_delivery(CPUPPCState *env) |
| 628 | { |
| 629 | ppc_tb_t *tb_env = env->tb_env; |
| 630 | int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; |
| 631 | return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); |
| 632 | } |
| 633 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 634 | static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 635 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 636 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 637 | uint32_t decr; |
bellard | 4e588a4 | 2005-07-07 21:46:29 +0000 | [diff] [blame] | 638 | int64_t diff; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 639 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 640 | diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 641 | if (diff >= 0) { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 642 | decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 643 | } else if (tb_env->flags & PPC_TIMER_BOOKE) { |
| 644 | decr = 0; |
| 645 | } else { |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 646 | decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 647 | } |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 648 | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 649 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 650 | return decr; |
| 651 | } |
| 652 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 653 | uint32_t cpu_ppc_load_decr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 654 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 655 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 656 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 657 | if (kvm_enabled()) { |
| 658 | return env->spr[SPR_DECR]; |
| 659 | } |
| 660 | |
Tristan Gingold | f55e9d9 | 2009-04-27 10:55:47 +0200 | [diff] [blame] | 661 | return _cpu_ppc_load_decr(env, tb_env->decr_next); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 662 | } |
| 663 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 664 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 665 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 666 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 667 | |
Tristan Gingold | f55e9d9 | 2009-04-27 10:55:47 +0200 | [diff] [blame] | 668 | return _cpu_ppc_load_decr(env, tb_env->hdecr_next); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 669 | } |
| 670 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 671 | uint64_t cpu_ppc_load_purr (CPUPPCState *env) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 672 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 673 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 674 | uint64_t diff; |
| 675 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 676 | diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; |
j_mayer | b33c17e | 2007-10-07 17:30:34 +0000 | [diff] [blame] | 677 | |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 678 | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec()); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 679 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 680 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 681 | /* When decrementer expires, |
| 682 | * all we need to do is generate or queue a CPU exception |
| 683 | */ |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 684 | static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 685 | { |
| 686 | /* Raise it */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 687 | LOG_TB("raise decrementer exception\n"); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 688 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 689 | } |
| 690 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 691 | static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) |
| 692 | { |
| 693 | ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); |
| 694 | } |
| 695 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 696 | static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 697 | { |
| 698 | /* Raise it */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 699 | LOG_TB("raise decrementer exception\n"); |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 700 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 701 | } |
| 702 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 703 | static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) |
| 704 | { |
| 705 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); |
| 706 | } |
| 707 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 708 | static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, |
Stefan Weil | 1246b25 | 2013-12-01 08:49:47 +0100 | [diff] [blame] | 709 | QEMUTimer *timer, |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 710 | void (*raise_excp)(void *), |
| 711 | void (*lower_excp)(PowerPCCPU *), |
| 712 | uint32_t decr, uint32_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 713 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 714 | CPUPPCState *env = &cpu->env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 715 | ppc_tb_t *tb_env = env->tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 716 | uint64_t now, next; |
| 717 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 718 | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 719 | decr, value); |
David Gibson | 55f7d4b | 2011-10-16 19:26:17 +0000 | [diff] [blame] | 720 | |
| 721 | if (kvm_enabled()) { |
| 722 | /* KVM handles decrementer exceptions, we don't need our own timer */ |
| 723 | return; |
| 724 | } |
| 725 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 726 | /* |
| 727 | * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC |
| 728 | * interrupt. |
| 729 | * |
| 730 | * If we get a really small DEC value, we can assume that by the time we |
| 731 | * handled it we should inject an interrupt already. |
| 732 | * |
| 733 | * On MSB level based DEC implementations the MSB always means the interrupt |
| 734 | * is pending, so raise it on those. |
| 735 | * |
| 736 | * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers |
| 737 | * an edge interrupt, so raise it here too. |
| 738 | */ |
| 739 | if ((value < 3) || |
| 740 | ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & 0x80000000)) || |
| 741 | ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & 0x80000000) |
| 742 | && !(decr & 0x80000000))) { |
| 743 | (*raise_excp)(cpu); |
| 744 | return; |
| 745 | } |
| 746 | |
| 747 | /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ |
| 748 | if (!(value & 0x80000000) && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { |
| 749 | (*lower_excp)(cpu); |
| 750 | } |
| 751 | |
| 752 | /* Calculate the next timer event */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 753 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 754 | next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 755 | *nextp = next; |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 756 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 757 | /* Adjust timer */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 758 | timer_mod(timer, next); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 759 | } |
| 760 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 761 | static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr, |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 762 | uint32_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 763 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 764 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 765 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 766 | __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 767 | tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, |
| 768 | value); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 769 | } |
| 770 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 771 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 772 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 773 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 774 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 775 | _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 776 | } |
| 777 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 778 | static void cpu_ppc_decr_cb(void *opaque) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 779 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 780 | PowerPCCPU *cpu = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 781 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 782 | cpu_ppc_decr_excp(cpu); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 783 | } |
| 784 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 785 | static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr, |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 786 | uint32_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 787 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 788 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 789 | |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 790 | if (tb_env->hdecr_timer != NULL) { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 791 | __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 792 | tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, |
| 793 | hdecr, value); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 794 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 795 | } |
| 796 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 797 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 798 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 799 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
| 800 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 801 | _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 802 | } |
| 803 | |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 804 | static void cpu_ppc_hdecr_cb(void *opaque) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 805 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 806 | PowerPCCPU *cpu = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 807 | |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 808 | cpu_ppc_hdecr_excp(cpu); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 809 | } |
| 810 | |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 811 | static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 812 | { |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 813 | ppc_tb_t *tb_env = cpu->env.tb_env; |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 814 | |
| 815 | tb_env->purr_load = value; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 816 | tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 817 | } |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 818 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 819 | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
| 820 | { |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 821 | CPUPPCState *env = opaque; |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 822 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 823 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 824 | |
| 825 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 826 | tb_env->decr_freq = freq; |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 827 | /* There is a bug in Linux 2.4 kernels: |
| 828 | * if a decrementer exception is pending when it enables msr_ee at startup, |
| 829 | * it's not ready to handle it... |
| 830 | */ |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 831 | _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); |
| 832 | _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF); |
Andreas Färber | 7e0a924 | 2012-12-01 04:18:02 +0100 | [diff] [blame] | 833 | cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 834 | } |
| 835 | |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 836 | static void timebase_pre_save(void *opaque) |
| 837 | { |
| 838 | PPCTimebase *tb = opaque; |
| 839 | uint64_t ticks = cpu_get_real_ticks(); |
| 840 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
| 841 | |
| 842 | if (!first_ppc_cpu->env.tb_env) { |
| 843 | error_report("No timebase object"); |
| 844 | return; |
| 845 | } |
| 846 | |
Paolo Bonzini | 77bad15 | 2014-11-26 15:01:01 +0100 | [diff] [blame] | 847 | tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 848 | /* |
| 849 | * tb_offset is only expected to be changed by migration so |
| 850 | * there is no need to update it from KVM here |
| 851 | */ |
| 852 | tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; |
| 853 | } |
| 854 | |
| 855 | static int timebase_post_load(void *opaque, int version_id) |
| 856 | { |
| 857 | PPCTimebase *tb_remote = opaque; |
| 858 | CPUState *cpu; |
| 859 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
| 860 | int64_t tb_off_adj, tb_off, ns_diff; |
| 861 | int64_t migration_duration_ns, migration_duration_tb, guest_tb, host_ns; |
| 862 | unsigned long freq; |
| 863 | |
| 864 | if (!first_ppc_cpu->env.tb_env) { |
| 865 | error_report("No timebase object"); |
| 866 | return -1; |
| 867 | } |
| 868 | |
| 869 | freq = first_ppc_cpu->env.tb_env->tb_freq; |
| 870 | /* |
| 871 | * Calculate timebase on the destination side of migration. |
| 872 | * The destination timebase must be not less than the source timebase. |
| 873 | * We try to adjust timebase by downtime if host clocks are not |
| 874 | * too much out of sync (1 second for now). |
| 875 | */ |
Paolo Bonzini | 77bad15 | 2014-11-26 15:01:01 +0100 | [diff] [blame] | 876 | host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); |
Alexey Kardashevskiy | 98a8b52 | 2014-05-01 20:37:09 +1000 | [diff] [blame] | 877 | ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns); |
| 878 | migration_duration_ns = MIN(NSEC_PER_SEC, ns_diff); |
| 879 | migration_duration_tb = muldiv64(migration_duration_ns, freq, NSEC_PER_SEC); |
| 880 | guest_tb = tb_remote->guest_timebase + MIN(0, migration_duration_tb); |
| 881 | |
| 882 | tb_off_adj = guest_tb - cpu_get_real_ticks(); |
| 883 | |
| 884 | tb_off = first_ppc_cpu->env.tb_env->tb_offset; |
| 885 | trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, |
| 886 | (tb_off_adj - tb_off) / freq); |
| 887 | |
| 888 | /* Set new offset to all CPUs */ |
| 889 | CPU_FOREACH(cpu) { |
| 890 | PowerPCCPU *pcpu = POWERPC_CPU(cpu); |
| 891 | pcpu->env.tb_env->tb_offset = tb_off_adj; |
| 892 | } |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | |
| 897 | const VMStateDescription vmstate_ppc_timebase = { |
| 898 | .name = "timebase", |
| 899 | .version_id = 1, |
| 900 | .minimum_version_id = 1, |
| 901 | .minimum_version_id_old = 1, |
| 902 | .pre_save = timebase_pre_save, |
| 903 | .post_load = timebase_post_load, |
| 904 | .fields = (VMStateField []) { |
| 905 | VMSTATE_UINT64(guest_timebase, PPCTimebase), |
| 906 | VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), |
| 907 | VMSTATE_END_OF_LIST() |
| 908 | }, |
| 909 | }; |
| 910 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 911 | /* Set up (once) timebase frequency (in Hz) */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 912 | clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 913 | { |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 914 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 915 | ppc_tb_t *tb_env; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 916 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 917 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 918 | env->tb_env = tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 919 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
Alexander Graf | e81a982 | 2014-04-06 01:32:06 +0200 | [diff] [blame] | 920 | if (env->insns_flags & PPC_SEGMENT_64B) { |
| 921 | /* All Book3S 64bit CPUs implement level based DEC logic */ |
| 922 | tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; |
| 923 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 924 | /* Create new timer */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 925 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 926 | if (0) { |
| 927 | /* XXX: find a suitable condition to enable the hypervisor decrementer |
| 928 | */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 929 | tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, |
Andreas Färber | 50c680f | 2012-12-01 04:26:55 +0100 | [diff] [blame] | 930 | cpu); |
j_mayer | b172c56 | 2007-11-17 01:37:44 +0000 | [diff] [blame] | 931 | } else { |
| 932 | tb_env->hdecr_timer = NULL; |
| 933 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 934 | cpu_ppc_set_tb_clk(env, freq); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 935 | |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 936 | return &cpu_ppc_set_tb_clk; |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 937 | } |
| 938 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 939 | /* Specific helpers for POWER & PowerPC 601 RTC */ |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 940 | #if 0 |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 941 | static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 942 | { |
| 943 | return cpu_ppc_tb_init(env, 7812500); |
| 944 | } |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 945 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 946 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 947 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 948 | { |
| 949 | _cpu_ppc_store_tbu(env, value); |
| 950 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 951 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 952 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) |
j_mayer | 8a84de2 | 2007-09-30 14:44:52 +0000 | [diff] [blame] | 953 | { |
| 954 | return _cpu_ppc_load_tbu(env); |
| 955 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 956 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 957 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 958 | { |
| 959 | cpu_ppc_store_tbl(env, value & 0x3FFFFF80); |
| 960 | } |
| 961 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 962 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 963 | { |
| 964 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
| 965 | } |
| 966 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 967 | /*****************************************************************************/ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 968 | /* PowerPC 40x timers */ |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 969 | |
| 970 | /* PIT, FIT & WDT */ |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 971 | typedef struct ppc40x_timer_t ppc40x_timer_t; |
| 972 | struct ppc40x_timer_t { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 973 | uint64_t pit_reload; /* PIT auto-reload value */ |
| 974 | uint64_t fit_next; /* Tick for next FIT interrupt */ |
Stefan Weil | 1246b25 | 2013-12-01 08:49:47 +0100 | [diff] [blame] | 975 | QEMUTimer *fit_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 976 | uint64_t wdt_next; /* Tick for next WDT interrupt */ |
Stefan Weil | 1246b25 | 2013-12-01 08:49:47 +0100 | [diff] [blame] | 977 | QEMUTimer *wdt_timer; |
Edgar E. Iglesias | d63cb48 | 2010-09-20 19:08:42 +0200 | [diff] [blame] | 978 | |
| 979 | /* 405 have the PIT, 440 have a DECR. */ |
| 980 | unsigned int decr_excp; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 981 | }; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 982 | |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 983 | /* Fixed interval timer */ |
| 984 | static void cpu_4xx_fit_cb (void *opaque) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 985 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 986 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 987 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 988 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 989 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 990 | uint64_t now, next; |
| 991 | |
| 992 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 993 | cpu = ppc_env_get_cpu(env); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 994 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 995 | ppc40x_timer = tb_env->opaque; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 996 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 997 | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
| 998 | case 0: |
| 999 | next = 1 << 9; |
| 1000 | break; |
| 1001 | case 1: |
| 1002 | next = 1 << 13; |
| 1003 | break; |
| 1004 | case 2: |
| 1005 | next = 1 << 17; |
| 1006 | break; |
| 1007 | case 3: |
| 1008 | next = 1 << 21; |
| 1009 | break; |
| 1010 | default: |
| 1011 | /* Cannot occur, but makes gcc happy */ |
| 1012 | return; |
| 1013 | } |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 1014 | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1015 | if (next == now) |
| 1016 | next++; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1017 | timer_mod(ppc40x_timer->fit_timer, next); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1018 | env->spr[SPR_40x_TSR] |= 1 << 26; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1019 | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { |
| 1020 | ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); |
| 1021 | } |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 1022 | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
| 1023 | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
| 1024 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1025 | } |
| 1026 | |
| 1027 | /* Programmable interval timer */ |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1028 | static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1029 | { |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1030 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1031 | uint64_t now, next; |
| 1032 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1033 | ppc40x_timer = tb_env->opaque; |
| 1034 | if (ppc40x_timer->pit_reload <= 1 || |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1035 | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
| 1036 | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
| 1037 | /* Stop PIT */ |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1038 | LOG_TB("%s: stop PIT\n", __func__); |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1039 | timer_del(tb_env->decr_timer); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1040 | } else { |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1041 | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1042 | __func__, ppc40x_timer->pit_reload); |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1043 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1044 | next = now + muldiv64(ppc40x_timer->pit_reload, |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 1045 | get_ticks_per_sec(), tb_env->decr_freq); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1046 | if (is_excp) |
| 1047 | next += tb_env->decr_next - now; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1048 | if (next == now) |
| 1049 | next++; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1050 | timer_mod(tb_env->decr_timer, next); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1051 | tb_env->decr_next = next; |
| 1052 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1053 | } |
| 1054 | |
| 1055 | static void cpu_4xx_pit_cb (void *opaque) |
| 1056 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1057 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1058 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1059 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1060 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1061 | |
| 1062 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1063 | cpu = ppc_env_get_cpu(env); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1064 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1065 | ppc40x_timer = tb_env->opaque; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1066 | env->spr[SPR_40x_TSR] |= 1 << 27; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1067 | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { |
| 1068 | ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); |
| 1069 | } |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1070 | start_stop_pit(env, tb_env, 1); |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 1071 | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
| 1072 | "%016" PRIx64 "\n", __func__, |
| 1073 | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
| 1074 | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
| 1075 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1076 | ppc40x_timer->pit_reload); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1077 | } |
| 1078 | |
| 1079 | /* Watchdog timer */ |
| 1080 | static void cpu_4xx_wdt_cb (void *opaque) |
| 1081 | { |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1082 | PowerPCCPU *cpu; |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1083 | CPUPPCState *env; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1084 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1085 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1086 | uint64_t now, next; |
| 1087 | |
| 1088 | env = opaque; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1089 | cpu = ppc_env_get_cpu(env); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1090 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1091 | ppc40x_timer = tb_env->opaque; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1092 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1093 | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
| 1094 | case 0: |
| 1095 | next = 1 << 17; |
| 1096 | break; |
| 1097 | case 1: |
| 1098 | next = 1 << 21; |
| 1099 | break; |
| 1100 | case 2: |
| 1101 | next = 1 << 25; |
| 1102 | break; |
| 1103 | case 3: |
| 1104 | next = 1 << 29; |
| 1105 | break; |
| 1106 | default: |
| 1107 | /* Cannot occur, but makes gcc happy */ |
| 1108 | return; |
| 1109 | } |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 1110 | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1111 | if (next == now) |
| 1112 | next++; |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 1113 | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
| 1114 | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1115 | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
| 1116 | case 0x0: |
| 1117 | case 0x1: |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1118 | timer_mod(ppc40x_timer->wdt_timer, next); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1119 | ppc40x_timer->wdt_next = next; |
Peter Maydell | a1f7f97 | 2014-03-17 16:00:37 +0000 | [diff] [blame] | 1120 | env->spr[SPR_40x_TSR] |= 1U << 31; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1121 | break; |
| 1122 | case 0x2: |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1123 | timer_mod(ppc40x_timer->wdt_timer, next); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1124 | ppc40x_timer->wdt_next = next; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1125 | env->spr[SPR_40x_TSR] |= 1 << 30; |
Andreas Färber | 7058581 | 2012-12-01 03:55:58 +0100 | [diff] [blame] | 1126 | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { |
| 1127 | ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); |
| 1128 | } |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1129 | break; |
| 1130 | case 0x3: |
| 1131 | env->spr[SPR_40x_TSR] &= ~0x30000000; |
| 1132 | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; |
| 1133 | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
| 1134 | case 0x0: |
| 1135 | /* No reset */ |
| 1136 | break; |
| 1137 | case 0x1: /* Core reset */ |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 1138 | ppc40x_core_reset(cpu); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1139 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1140 | case 0x2: /* Chip reset */ |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 1141 | ppc40x_chip_reset(cpu); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1142 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1143 | case 0x3: /* System reset */ |
Andreas Färber | f3273ba | 2013-01-18 15:57:51 +0100 | [diff] [blame] | 1144 | ppc40x_system_reset(cpu); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1145 | break; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1146 | } |
| 1147 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1148 | } |
| 1149 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1150 | void store_40x_pit (CPUPPCState *env, target_ulong val) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1151 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1152 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1153 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1154 | |
| 1155 | tb_env = env->tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1156 | ppc40x_timer = tb_env->opaque; |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 1157 | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1158 | ppc40x_timer->pit_reload = val; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1159 | start_stop_pit(env, tb_env, 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1160 | } |
| 1161 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1162 | target_ulong load_40x_pit (CPUPPCState *env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1163 | { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1164 | return cpu_ppc_load_decr(env); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1165 | } |
| 1166 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1167 | static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1168 | { |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1169 | CPUPPCState *env = opaque; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1170 | ppc_tb_t *tb_env = env->tb_env; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1171 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1172 | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 1173 | freq); |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1174 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1175 | tb_env->decr_freq = freq; |
j_mayer | 4b6d0a4 | 2007-04-24 06:32:00 +0000 | [diff] [blame] | 1176 | /* XXX: we should also update all timers */ |
| 1177 | } |
| 1178 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1179 | clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, |
Edgar E. Iglesias | d63cb48 | 2010-09-20 19:08:42 +0200 | [diff] [blame] | 1180 | unsigned int decr_excp) |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1181 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1182 | ppc_tb_t *tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1183 | ppc40x_timer_t *ppc40x_timer; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1184 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1185 | tb_env = g_malloc0(sizeof(ppc_tb_t)); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1186 | env->tb_env = tb_env; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1187 | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
| 1188 | ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1189 | tb_env->tb_freq = freq; |
j_mayer | dbdd250 | 2007-10-14 09:35:30 +0000 | [diff] [blame] | 1190 | tb_env->decr_freq = freq; |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1191 | tb_env->opaque = ppc40x_timer; |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 1192 | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1193 | if (ppc40x_timer != NULL) { |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1194 | /* We use decr timer for PIT */ |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1195 | tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1196 | ppc40x_timer->fit_timer = |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1197 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1198 | ppc40x_timer->wdt_timer = |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 1199 | timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1200 | ppc40x_timer->decr_excp = decr_excp; |
j_mayer | 636aaad | 2007-03-31 11:38:38 +0000 | [diff] [blame] | 1201 | } |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1202 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1203 | return &ppc_40x_set_tb_clk; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1204 | } |
| 1205 | |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1206 | /*****************************************************************************/ |
| 1207 | /* Embedded PowerPC Device Control Registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1208 | typedef struct ppc_dcrn_t ppc_dcrn_t; |
| 1209 | struct ppc_dcrn_t { |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1210 | dcr_read_cb dcr_read; |
| 1211 | dcr_write_cb dcr_write; |
| 1212 | void *opaque; |
| 1213 | }; |
| 1214 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1215 | /* XXX: on 460, DCR addresses are 32 bits wide, |
| 1216 | * using DCRIPR to get the 22 upper bits of the DCR address |
| 1217 | */ |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1218 | #define DCRN_NB 1024 |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1219 | struct ppc_dcr_t { |
| 1220 | ppc_dcrn_t dcrn[DCRN_NB]; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1221 | int (*read_error)(int dcrn); |
| 1222 | int (*write_error)(int dcrn); |
| 1223 | }; |
| 1224 | |
Alexander Graf | 73b0196 | 2009-12-21 14:02:39 +0100 | [diff] [blame] | 1225 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1226 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1227 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1228 | |
| 1229 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1230 | goto error; |
| 1231 | dcr = &dcr_env->dcrn[dcrn]; |
| 1232 | if (dcr->dcr_read == NULL) |
| 1233 | goto error; |
| 1234 | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
| 1235 | |
| 1236 | return 0; |
| 1237 | |
| 1238 | error: |
| 1239 | if (dcr_env->read_error != NULL) |
| 1240 | return (*dcr_env->read_error)(dcrn); |
| 1241 | |
| 1242 | return -1; |
| 1243 | } |
| 1244 | |
Alexander Graf | 73b0196 | 2009-12-21 14:02:39 +0100 | [diff] [blame] | 1245 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1246 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1247 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1248 | |
| 1249 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1250 | goto error; |
| 1251 | dcr = &dcr_env->dcrn[dcrn]; |
| 1252 | if (dcr->dcr_write == NULL) |
| 1253 | goto error; |
| 1254 | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
| 1255 | |
| 1256 | return 0; |
| 1257 | |
| 1258 | error: |
| 1259 | if (dcr_env->write_error != NULL) |
| 1260 | return (*dcr_env->write_error)(dcrn); |
| 1261 | |
| 1262 | return -1; |
| 1263 | } |
| 1264 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1265 | int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1266 | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
| 1267 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1268 | ppc_dcr_t *dcr_env; |
| 1269 | ppc_dcrn_t *dcr; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1270 | |
| 1271 | dcr_env = env->dcr_env; |
| 1272 | if (dcr_env == NULL) |
| 1273 | return -1; |
| 1274 | if (dcrn < 0 || dcrn >= DCRN_NB) |
| 1275 | return -1; |
| 1276 | dcr = &dcr_env->dcrn[dcrn]; |
| 1277 | if (dcr->opaque != NULL || |
| 1278 | dcr->dcr_read != NULL || |
| 1279 | dcr->dcr_write != NULL) |
| 1280 | return -1; |
| 1281 | dcr->opaque = opaque; |
| 1282 | dcr->dcr_read = dcr_read; |
| 1283 | dcr->dcr_write = dcr_write; |
| 1284 | |
| 1285 | return 0; |
| 1286 | } |
| 1287 | |
Andreas Färber | e2684c0 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 1288 | int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1289 | int (*write_error)(int dcrn)) |
| 1290 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1291 | ppc_dcr_t *dcr_env; |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1292 | |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 1293 | dcr_env = g_malloc0(sizeof(ppc_dcr_t)); |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1294 | dcr_env->read_error = read_error; |
| 1295 | dcr_env->write_error = write_error; |
| 1296 | env->dcr_env = dcr_env; |
| 1297 | |
| 1298 | return 0; |
| 1299 | } |
| 1300 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1301 | /*****************************************************************************/ |
| 1302 | /* Debug port */ |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1303 | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1304 | { |
| 1305 | addr &= 0xF; |
| 1306 | switch (addr) { |
| 1307 | case 0: |
| 1308 | printf("%c", val); |
| 1309 | break; |
| 1310 | case 1: |
| 1311 | printf("\n"); |
| 1312 | fflush(stdout); |
| 1313 | break; |
| 1314 | case 2: |
j_mayer | aae9366 | 2007-11-24 02:56:36 +0000 | [diff] [blame] | 1315 | printf("Set loglevel to %04" PRIx32 "\n", val); |
Peter Maydell | 24537a0 | 2013-02-11 16:41:23 +0000 | [diff] [blame] | 1316 | qemu_set_log(val | 0x100); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1317 | break; |
| 1318 | } |
| 1319 | } |
| 1320 | |
| 1321 | /*****************************************************************************/ |
| 1322 | /* NVRAM helpers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1323 | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1324 | { |
Dong Xu Wang | 3a93113 | 2011-11-29 16:52:38 +0800 | [diff] [blame] | 1325 | return (*nvram->read_fn)(nvram->opaque, addr); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1326 | } |
| 1327 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1328 | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1329 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1330 | (*nvram->write_fn)(nvram->opaque, addr, val); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1331 | } |
| 1332 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1333 | static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1334 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1335 | nvram_write(nvram, addr, value); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1336 | } |
| 1337 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1338 | static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr) |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1339 | { |
| 1340 | return nvram_read(nvram, addr); |
| 1341 | } |
| 1342 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1343 | static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value) |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1344 | { |
| 1345 | nvram_write(nvram, addr, value >> 8); |
| 1346 | nvram_write(nvram, addr + 1, value & 0xFF); |
| 1347 | } |
| 1348 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1349 | static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1350 | { |
| 1351 | uint16_t tmp; |
| 1352 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1353 | tmp = nvram_read(nvram, addr) << 8; |
| 1354 | tmp |= nvram_read(nvram, addr + 1); |
| 1355 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1356 | return tmp; |
| 1357 | } |
| 1358 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1359 | static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1360 | { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1361 | nvram_write(nvram, addr, value >> 24); |
| 1362 | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
| 1363 | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
| 1364 | nvram_write(nvram, addr + 3, value & 0xFF); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1365 | } |
| 1366 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1367 | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1368 | { |
| 1369 | uint32_t tmp; |
| 1370 | |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1371 | tmp = nvram_read(nvram, addr) << 24; |
| 1372 | tmp |= nvram_read(nvram, addr + 1) << 16; |
| 1373 | tmp |= nvram_read(nvram, addr + 2) << 8; |
| 1374 | tmp |= nvram_read(nvram, addr + 3); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1375 | |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1376 | return tmp; |
| 1377 | } |
| 1378 | |
Blue Swirl | 4344829 | 2012-10-28 11:04:49 +0000 | [diff] [blame] | 1379 | static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str, |
| 1380 | uint32_t max) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1381 | { |
| 1382 | int i; |
| 1383 | |
| 1384 | for (i = 0; i < max && str[i] != '\0'; i++) { |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1385 | nvram_write(nvram, addr + i, str[i]); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1386 | } |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1387 | nvram_write(nvram, addr + i, str[i]); |
| 1388 | nvram_write(nvram, addr + max - 1, '\0'); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1389 | } |
| 1390 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1391 | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1392 | { |
| 1393 | int i; |
| 1394 | |
| 1395 | memset(dst, 0, max); |
| 1396 | for (i = 0; i < max; i++) { |
| 1397 | dst[i] = NVRAM_get_byte(nvram, addr + i); |
| 1398 | if (dst[i] == '\0') |
| 1399 | break; |
| 1400 | } |
| 1401 | |
| 1402 | return i; |
| 1403 | } |
| 1404 | |
| 1405 | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) |
| 1406 | { |
| 1407 | uint16_t tmp; |
| 1408 | uint16_t pd, pd1, pd2; |
| 1409 | |
| 1410 | tmp = prev >> 8; |
| 1411 | pd = prev ^ value; |
| 1412 | pd1 = pd & 0x000F; |
| 1413 | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
| 1414 | tmp ^= (pd1 << 3) | (pd1 << 8); |
| 1415 | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
| 1416 | |
| 1417 | return tmp; |
| 1418 | } |
| 1419 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1420 | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1421 | { |
| 1422 | uint32_t i; |
| 1423 | uint16_t crc = 0xFFFF; |
| 1424 | int odd; |
| 1425 | |
| 1426 | odd = count & 1; |
| 1427 | count &= ~1; |
| 1428 | for (i = 0; i != count; i++) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1429 | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1430 | } |
| 1431 | if (odd) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1432 | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1433 | } |
| 1434 | |
| 1435 | return crc; |
| 1436 | } |
| 1437 | |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1438 | #define CMDLINE_ADDR 0x017ff000 |
| 1439 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1440 | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 1441 | const char *arch, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1442 | uint32_t RAM_size, int boot_device, |
| 1443 | uint32_t kernel_image, uint32_t kernel_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1444 | const char *cmdline, |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1445 | uint32_t initrd_image, uint32_t initrd_size, |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1446 | uint32_t NVRAM_image, |
| 1447 | int width, int height, int depth) |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1448 | { |
| 1449 | uint16_t crc; |
| 1450 | |
| 1451 | /* Set parameters for Open Hack'Ware BIOS */ |
| 1452 | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
| 1453 | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
| 1454 | NVRAM_set_word(nvram, 0x14, NVRAM_size); |
| 1455 | NVRAM_set_string(nvram, 0x20, arch, 16); |
| 1456 | NVRAM_set_lword(nvram, 0x30, RAM_size); |
| 1457 | NVRAM_set_byte(nvram, 0x34, boot_device); |
| 1458 | NVRAM_set_lword(nvram, 0x38, kernel_image); |
| 1459 | NVRAM_set_lword(nvram, 0x3C, kernel_size); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1460 | if (cmdline) { |
| 1461 | /* XXX: put the cmdline in NVRAM too ? */ |
Gerd Hoffmann | 3c178e7 | 2009-10-07 13:37:06 +0200 | [diff] [blame] | 1462 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1463 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
| 1464 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); |
| 1465 | } else { |
| 1466 | NVRAM_set_lword(nvram, 0x40, 0); |
| 1467 | NVRAM_set_lword(nvram, 0x44, 0); |
| 1468 | } |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1469 | NVRAM_set_lword(nvram, 0x48, initrd_image); |
| 1470 | NVRAM_set_lword(nvram, 0x4C, initrd_size); |
| 1471 | NVRAM_set_lword(nvram, 0x50, NVRAM_image); |
bellard | fd0bbb1 | 2004-06-21 16:53:42 +0000 | [diff] [blame] | 1472 | |
| 1473 | NVRAM_set_word(nvram, 0x54, width); |
| 1474 | NVRAM_set_word(nvram, 0x56, height); |
| 1475 | NVRAM_set_word(nvram, 0x58, depth); |
| 1476 | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
j_mayer | 3cbee15 | 2007-10-28 23:42:18 +0000 | [diff] [blame] | 1477 | NVRAM_set_word(nvram, 0xFC, crc); |
bellard | 6420120 | 2004-05-26 22:55:16 +0000 | [diff] [blame] | 1478 | |
| 1479 | return 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1480 | } |
Alexey Kardashevskiy | 0ce470c | 2014-02-02 01:45:51 +1100 | [diff] [blame] | 1481 | |
| 1482 | /* CPU device-tree ID helpers */ |
| 1483 | int ppc_get_vcpu_dt_id(PowerPCCPU *cpu) |
| 1484 | { |
| 1485 | return cpu->cpu_dt_id; |
| 1486 | } |
| 1487 | |
| 1488 | PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id) |
| 1489 | { |
| 1490 | CPUState *cs; |
| 1491 | |
| 1492 | CPU_FOREACH(cs) { |
| 1493 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 1494 | |
| 1495 | if (cpu->cpu_dt_id == cpu_dt_id) { |
| 1496 | return cpu; |
| 1497 | } |
| 1498 | } |
| 1499 | |
| 1500 | return NULL; |
| 1501 | } |