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j_mayer4c9649a2007-04-05 06:58:33 +00001/*
2 * Alpha emulation cpu definitions for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer4c9649a2007-04-05 06:58:33 +00004 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
j_mayer4c9649a2007-04-05 06:58:33 +000018 */
19
20#if !defined (__CPU_ALPHA_H__)
21#define __CPU_ALPHA_H__
22
23#include "config.h"
Stefan Weil2c976292012-02-01 20:51:52 +010024#include "qemu-common.h"
j_mayer4c9649a2007-04-05 06:58:33 +000025
26#define TARGET_LONG_BITS 64
Paolo Bonzinid94f0a82014-03-28 17:48:12 +010027#define ALIGNED_ONLY
j_mayer4c9649a2007-04-05 06:58:33 +000028
Andreas Färber9349b4f2012-03-14 01:38:32 +010029#define CPUArchState struct CPUAlphaState
pbrookc2764712009-03-07 15:24:59 +000030
Paolo Bonzini022c62c2012-12-17 18:19:49 +010031#include "exec/cpu-defs.h"
j_mayer4c9649a2007-04-05 06:58:33 +000032
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020033#include "fpu/softfloat.h"
j_mayer4c9649a2007-04-05 06:58:33 +000034
j_mayerf071b4d2007-10-28 00:56:24 +000035#define ELF_MACHINE EM_ALPHA
j_mayer4c9649a2007-04-05 06:58:33 +000036
37#define ICACHE_LINE_SIZE 32
38#define DCACHE_LINE_SIZE 32
39
aurel32b09d9d42009-04-07 21:47:34 +000040#define TARGET_PAGE_BITS 13
j_mayer4c9649a2007-04-05 06:58:33 +000041
Richard Henderson76393642012-05-31 16:09:39 -070042#ifdef CONFIG_USER_ONLY
43/* ??? The kernel likes to give addresses in high memory. If the host has
44 more virtual address space than the guest, this can lead to impossible
45 allocations. Honor the long-standing assumption that only kernel addrs
46 are negative, but otherwise allow allocations anywhere. This could lead
47 to tricky emulation problems for programs doing tagged addressing, but
48 that's far fewer than encounter the impossible allocation problem. */
49#define TARGET_PHYS_ADDR_SPACE_BITS 63
50#define TARGET_VIRT_ADDR_SPACE_BITS 63
51#else
Richard Henderson52705892010-03-10 14:33:23 -080052/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
Richard Henderson76393642012-05-31 16:09:39 -070053#define TARGET_PHYS_ADDR_SPACE_BITS 44
54#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
55#endif
j_mayer4c9649a2007-04-05 06:58:33 +000056
57/* Alpha major type */
58enum {
59 ALPHA_EV3 = 1,
60 ALPHA_EV4 = 2,
61 ALPHA_SIM = 3,
62 ALPHA_LCA = 4,
63 ALPHA_EV5 = 5, /* 21164 */
64 ALPHA_EV45 = 6, /* 21064A */
65 ALPHA_EV56 = 7, /* 21164A */
66};
67
68/* EV4 minor type */
69enum {
70 ALPHA_EV4_2 = 0,
71 ALPHA_EV4_3 = 1,
72};
73
74/* LCA minor type */
75enum {
76 ALPHA_LCA_1 = 1, /* 21066 */
77 ALPHA_LCA_2 = 2, /* 20166 */
78 ALPHA_LCA_3 = 3, /* 21068 */
79 ALPHA_LCA_4 = 4, /* 21068 */
80 ALPHA_LCA_5 = 5, /* 21066A */
81 ALPHA_LCA_6 = 6, /* 21068A */
82};
83
84/* EV5 minor type */
85enum {
86 ALPHA_EV5_1 = 1, /* Rev BA, CA */
87 ALPHA_EV5_2 = 2, /* Rev DA, EA */
88 ALPHA_EV5_3 = 3, /* Pass 3 */
89 ALPHA_EV5_4 = 4, /* Pass 3.2 */
90 ALPHA_EV5_5 = 5, /* Pass 4 */
91};
92
93/* EV45 minor type */
94enum {
95 ALPHA_EV45_1 = 1, /* Pass 1 */
96 ALPHA_EV45_2 = 2, /* Pass 1.1 */
97 ALPHA_EV45_3 = 3, /* Pass 2 */
98};
99
100/* EV56 minor type */
101enum {
102 ALPHA_EV56_1 = 1, /* Pass 1 */
103 ALPHA_EV56_2 = 2, /* Pass 2 */
104};
105
106enum {
107 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
108 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
109 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
110 IMPLVER_21364 = 3, /* EV7 & EV79 */
111};
112
113enum {
114 AMASK_BWX = 0x00000001,
115 AMASK_FIX = 0x00000002,
116 AMASK_CIX = 0x00000004,
117 AMASK_MVI = 0x00000100,
118 AMASK_TRAP = 0x00000200,
119 AMASK_PREFETCH = 0x00001000,
120};
121
122enum {
123 VAX_ROUND_NORMAL = 0,
124 VAX_ROUND_CHOPPED,
125};
126
127enum {
128 IEEE_ROUND_NORMAL = 0,
129 IEEE_ROUND_DYNAMIC,
130 IEEE_ROUND_PLUS,
131 IEEE_ROUND_MINUS,
132 IEEE_ROUND_CHOPPED,
133};
134
135/* IEEE floating-point operations encoding */
136/* Trap mode */
137enum {
138 FP_TRAP_I = 0x0,
139 FP_TRAP_U = 0x1,
140 FP_TRAP_S = 0x4,
141 FP_TRAP_SU = 0x5,
142 FP_TRAP_SUI = 0x7,
143};
144
145/* Rounding mode */
146enum {
147 FP_ROUND_CHOPPED = 0x0,
148 FP_ROUND_MINUS = 0x1,
149 FP_ROUND_NORMAL = 0x2,
150 FP_ROUND_DYNAMIC = 0x3,
151};
152
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000153/* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
154#define FPCR_SUM (1U << (63 - 32))
155#define FPCR_INED (1U << (62 - 32))
156#define FPCR_UNFD (1U << (61 - 32))
157#define FPCR_UNDZ (1U << (60 - 32))
158#define FPCR_DYN_SHIFT (58 - 32)
159#define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT)
160#define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
161#define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT)
162#define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT)
163#define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT)
164#define FPCR_IOV (1U << (57 - 32))
165#define FPCR_INE (1U << (56 - 32))
166#define FPCR_UNF (1U << (55 - 32))
167#define FPCR_OVF (1U << (54 - 32))
168#define FPCR_DZE (1U << (53 - 32))
169#define FPCR_INV (1U << (52 - 32))
170#define FPCR_OVFD (1U << (51 - 32))
171#define FPCR_DZED (1U << (50 - 32))
172#define FPCR_INVD (1U << (49 - 32))
173#define FPCR_DNZ (1U << (48 - 32))
174#define FPCR_DNOD (1U << (47 - 32))
175#define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
176 | FPCR_OVF | FPCR_DZE | FPCR_INV)
Richard Hendersonba0e2762009-12-09 15:56:29 -0800177
178/* The silly software trap enables implemented by the kernel emulation.
179 These are more or less architecturally required, since the real hardware
180 has read-as-zero bits in the FPCR when the features aren't implemented.
181 For the purposes of QEMU, we pretend the FPCR can hold everything. */
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000182#define SWCR_TRAP_ENABLE_INV (1U << 1)
183#define SWCR_TRAP_ENABLE_DZE (1U << 2)
184#define SWCR_TRAP_ENABLE_OVF (1U << 3)
185#define SWCR_TRAP_ENABLE_UNF (1U << 4)
186#define SWCR_TRAP_ENABLE_INE (1U << 5)
187#define SWCR_TRAP_ENABLE_DNO (1U << 6)
188#define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
Richard Hendersonba0e2762009-12-09 15:56:29 -0800189
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000190#define SWCR_MAP_DMZ (1U << 12)
191#define SWCR_MAP_UMZ (1U << 13)
192#define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
Richard Hendersonba0e2762009-12-09 15:56:29 -0800193
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000194#define SWCR_STATUS_INV (1U << 17)
195#define SWCR_STATUS_DZE (1U << 18)
196#define SWCR_STATUS_OVF (1U << 19)
197#define SWCR_STATUS_UNF (1U << 20)
198#define SWCR_STATUS_INE (1U << 21)
199#define SWCR_STATUS_DNO (1U << 22)
200#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
Richard Hendersonba0e2762009-12-09 15:56:29 -0800201
202#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
203
Richard Henderson84178452011-05-20 13:11:25 -0700204/* MMU modes definitions */
j_mayer4c9649a2007-04-05 06:58:33 +0000205
Richard Henderson84178452011-05-20 13:11:25 -0700206/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
207 The Unix PALcode only exposes the kernel and user modes; presumably
208 executive and supervisor are used by VMS.
209
210 PALcode itself uses physical mode for code and kernel mode for data;
211 there are PALmode instructions that can access data via physical mode
212 or via an os-installed "alternate mode", which is one of the 4 above.
213
214 QEMU does not currently properly distinguish between code/data when
215 looking up addresses. To avoid having to address this issue, our
216 emulated PALcode will cheat and use the KSEG mapping for its code+data
217 rather than physical addresses.
218
219 Moreover, we're only emulating Unix PALcode, and not attempting VMS.
220
221 All of which allows us to drop all but kernel and user modes.
222 Elide the unused MMU modes to save space. */
223
224#define NB_MMU_MODES 2
225
226#define MMU_MODE0_SUFFIX _kernel
227#define MMU_MODE1_SUFFIX _user
228#define MMU_KERNEL_IDX 0
229#define MMU_USER_IDX 1
230
231typedef struct CPUAlphaState CPUAlphaState;
j_mayer6ebbf392007-10-14 07:07:08 +0000232
j_mayer4c9649a2007-04-05 06:58:33 +0000233struct CPUAlphaState {
234 uint64_t ir[31];
Richard Henderson8443eff2009-12-31 12:41:07 -0800235 float64 fir[31];
j_mayer4c9649a2007-04-05 06:58:33 +0000236 uint64_t pc;
j_mayer4c9649a2007-04-05 06:58:33 +0000237 uint64_t unique;
Richard Henderson6910b8f2010-04-07 15:42:26 -0700238 uint64_t lock_addr;
239 uint64_t lock_st_addr;
240 uint64_t lock_value;
Richard Hendersonf3d3aad2014-08-08 12:17:07 -1000241
242 /* The FPCR, and disassembled portions thereof. */
243 uint32_t fpcr;
244 uint32_t fpcr_exc_enable;
Richard Henderson8443eff2009-12-31 12:41:07 -0800245 float_status fp_status;
Richard Henderson8443eff2009-12-31 12:41:07 -0800246 uint8_t fpcr_dyn_round;
247 uint8_t fpcr_flush_to_zero;
Richard Henderson8443eff2009-12-31 12:41:07 -0800248
Richard Henderson129d8aa2011-05-20 13:30:00 -0700249 /* The Internal Processor Registers. Some of these we assume always
250 exist for use in user-mode. */
251 uint8_t ps;
Richard Henderson8443eff2009-12-31 12:41:07 -0800252 uint8_t intr_flag;
Richard Henderson129d8aa2011-05-20 13:30:00 -0700253 uint8_t pal_mode;
Richard Henderson26b46092011-05-23 12:12:29 -0700254 uint8_t fen;
255
256 uint32_t pcc_ofs;
Richard Henderson129d8aa2011-05-20 13:30:00 -0700257
258 /* These pass data from the exception logic in the translator and
259 helpers to the OS entry point. This is used for both system
260 emulation and user-mode. */
261 uint64_t trap_arg0;
262 uint64_t trap_arg1;
263 uint64_t trap_arg2;
j_mayer4c9649a2007-04-05 06:58:33 +0000264
Richard Henderson26b46092011-05-23 12:12:29 -0700265#if !defined(CONFIG_USER_ONLY)
266 /* The internal data required by our emulation of the Unix PALcode. */
267 uint64_t exc_addr;
268 uint64_t palbr;
269 uint64_t ptbr;
270 uint64_t vptptr;
271 uint64_t sysval;
272 uint64_t usp;
273 uint64_t shadow[8];
274 uint64_t scratch[24];
275#endif
276
Richard Hendersonc781cf92011-04-28 10:40:08 -0700277 /* This alarm doesn't exist in real hardware; we wish it did. */
Richard Hendersonc781cf92011-04-28 10:40:08 -0700278 uint64_t alarm_expire;
279
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200280 /* Those resources are used only in QEMU core */
j_mayer4c9649a2007-04-05 06:58:33 +0000281 CPU_COMMON
282
j_mayer4c9649a2007-04-05 06:58:33 +0000283 int error_code;
j_mayer4c9649a2007-04-05 06:58:33 +0000284
285 uint32_t features;
286 uint32_t amask;
287 int implver;
j_mayer4c9649a2007-04-05 06:58:33 +0000288};
289
Andreas Färber494342b2012-10-15 17:44:21 +0200290#define cpu_list alpha_cpu_list
ths9467d442007-06-03 21:02:38 +0000291#define cpu_exec cpu_alpha_exec
292#define cpu_gen_code cpu_alpha_gen_code
293#define cpu_signal_handler cpu_alpha_signal_handler
294
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100295#include "exec/cpu-all.h"
Andreas Färber25ebd802012-04-06 19:46:48 +0200296#include "cpu-qom.h"
j_mayer4c9649a2007-04-05 06:58:33 +0000297
298enum {
299 FEATURE_ASN = 0x00000001,
300 FEATURE_SPS = 0x00000002,
301 FEATURE_VIRBND = 0x00000004,
302 FEATURE_TBCHK = 0x00000008,
303};
304
305enum {
Richard Henderson07b6c132011-05-20 14:04:57 -0700306 EXCP_RESET,
307 EXCP_MCHK,
308 EXCP_SMP_INTERRUPT,
309 EXCP_CLK_INTERRUPT,
310 EXCP_DEV_INTERRUPT,
311 EXCP_MMFAULT,
312 EXCP_UNALIGN,
313 EXCP_OPCDEC,
314 EXCP_ARITH,
315 EXCP_FEN,
316 EXCP_CALL_PAL,
317 /* For Usermode emulation. */
318 EXCP_STL_C,
319 EXCP_STQ_C,
j_mayer4c9649a2007-04-05 06:58:33 +0000320};
321
Richard Henderson6a80e082011-04-18 15:09:09 -0700322/* Alpha-specific interrupt pending bits. */
323#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
324#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
325#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
326
Richard Hendersona3b9af12011-04-18 15:59:21 -0700327/* OSF/1 Page table bits. */
328enum {
329 PTE_VALID = 0x0001,
330 PTE_FOR = 0x0002, /* used for page protection (fault on read) */
331 PTE_FOW = 0x0004, /* used for page protection (fault on write) */
332 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
333 PTE_ASM = 0x0010,
334 PTE_KRE = 0x0100,
335 PTE_URE = 0x0200,
336 PTE_KWE = 0x1000,
337 PTE_UWE = 0x2000
338};
339
Richard Hendersonea879fc2011-04-18 14:19:17 -0700340/* Hardware interrupt (entInt) constants. */
341enum {
342 INT_K_IP,
343 INT_K_CLK,
344 INT_K_MCHK,
345 INT_K_DEV,
346 INT_K_PERF,
347};
348
349/* Memory management (entMM) constants. */
350enum {
351 MM_K_TNV,
352 MM_K_ACV,
353 MM_K_FOR,
354 MM_K_FOE,
355 MM_K_FOW
356};
357
358/* Arithmetic exception (entArith) constants. */
359enum {
360 EXC_M_SWC = 1, /* Software completion */
361 EXC_M_INV = 2, /* Invalid operation */
362 EXC_M_DZE = 4, /* Division by zero */
363 EXC_M_FOV = 8, /* Overflow */
364 EXC_M_UNF = 16, /* Underflow */
365 EXC_M_INE = 32, /* Inexact result */
366 EXC_M_IOV = 64 /* Integer Overflow */
367};
368
369/* Processor status constants. */
370enum {
371 /* Low 3 bits are interrupt mask level. */
372 PS_INT_MASK = 7,
373
374 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
375 The Unix PALcode only uses bit 4. */
376 PS_USER_MODE = 8
377};
378
Andreas Färber4d5712f2012-03-14 01:38:21 +0100379static inline int cpu_mmu_index(CPUAlphaState *env)
Richard Hendersonea879fc2011-04-18 14:19:17 -0700380{
Richard Hendersonbba9bdc2011-05-20 14:14:44 -0700381 if (env->pal_mode) {
382 return MMU_KERNEL_IDX;
383 } else if (env->ps & PS_USER_MODE) {
384 return MMU_USER_IDX;
385 } else {
386 return MMU_KERNEL_IDX;
387 }
Richard Hendersonea879fc2011-04-18 14:19:17 -0700388}
j_mayer4c9649a2007-04-05 06:58:33 +0000389
390enum {
j_mayer4c9649a2007-04-05 06:58:33 +0000391 IR_V0 = 0,
392 IR_T0 = 1,
393 IR_T1 = 2,
394 IR_T2 = 3,
395 IR_T3 = 4,
396 IR_T4 = 5,
397 IR_T5 = 6,
398 IR_T6 = 7,
399 IR_T7 = 8,
400 IR_S0 = 9,
401 IR_S1 = 10,
402 IR_S2 = 11,
403 IR_S3 = 12,
404 IR_S4 = 13,
405 IR_S5 = 14,
406 IR_S6 = 15,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700407 IR_FP = IR_S6,
j_mayer4c9649a2007-04-05 06:58:33 +0000408 IR_A0 = 16,
409 IR_A1 = 17,
410 IR_A2 = 18,
411 IR_A3 = 19,
412 IR_A4 = 20,
413 IR_A5 = 21,
414 IR_T8 = 22,
415 IR_T9 = 23,
416 IR_T10 = 24,
417 IR_T11 = 25,
418 IR_RA = 26,
419 IR_T12 = 27,
Richard Hendersona4b388f2010-04-12 16:17:22 -0700420 IR_PV = IR_T12,
j_mayer4c9649a2007-04-05 06:58:33 +0000421 IR_AT = 28,
422 IR_GP = 29,
423 IR_SP = 30,
424 IR_ZERO = 31,
425};
426
Andreas Färber0c282462012-10-15 17:33:32 +0200427void alpha_translate_init(void);
428
Andreas Färber5f5e3352012-10-15 17:52:00 +0200429AlphaCPU *cpu_alpha_init(const char *cpu_model);
430
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300431#define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
Andreas Färber5f5e3352012-10-15 17:52:00 +0200432
Andreas Färber494342b2012-10-15 17:44:21 +0200433void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
j_mayere96efcf2007-04-14 12:17:09 +0000434int cpu_alpha_exec(CPUAlphaState *s);
435/* you can call this signal handler from your SIGBUS and SIGSEGV
436 signal handlers to inform the virtual CPU of exceptions. non zero
437 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000438int cpu_alpha_signal_handler(int host_signum, void *pinfo,
j_mayere96efcf2007-04-14 12:17:09 +0000439 void *puc);
Andreas Färber75104542013-08-26 03:01:33 +0200440int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
441 int mmu_idx);
Blue Swirl20503962012-04-09 14:20:20 +0000442void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
443void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
444void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
aurel3295870352008-12-11 22:42:42 +0000445
Andreas Färber4d5712f2012-03-14 01:38:21 +0100446uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
447void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
Richard Henderson5b450402011-04-18 16:13:12 -0700448#ifndef CONFIG_USER_ONLY
Andreas Färber4d5712f2012-03-14 01:38:21 +0100449void swap_shadow_regs(CPUAlphaState *env);
Andreas Färberc658b942013-05-27 06:49:53 +0200450QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
451 bool is_write, bool is_exec,
452 int unused, unsigned size);
Richard Henderson5b450402011-04-18 16:13:12 -0700453#endif
j_mayer4c9649a2007-04-05 06:58:33 +0000454
Richard Hendersona18ad892011-05-23 12:30:22 -0700455/* Bits in TB->FLAGS that control how translation is processed. */
456enum {
457 TB_FLAGS_PAL_MODE = 1,
458 TB_FLAGS_FEN = 2,
459 TB_FLAGS_USER_MODE = 8,
460
461 TB_FLAGS_AMASK_SHIFT = 4,
462 TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
463 TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
464 TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
465 TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
466 TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
467 TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
468};
469
Andreas Färber4d5712f2012-03-14 01:38:21 +0100470static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
Richard Hendersona18ad892011-05-23 12:30:22 -0700471 target_ulong *cs_base, int *pflags)
aliguori6b917542008-11-18 19:46:41 +0000472{
Richard Hendersona18ad892011-05-23 12:30:22 -0700473 int flags = 0;
474
aliguori6b917542008-11-18 19:46:41 +0000475 *pc = env->pc;
476 *cs_base = 0;
Richard Hendersona18ad892011-05-23 12:30:22 -0700477
478 if (env->pal_mode) {
479 flags = TB_FLAGS_PAL_MODE;
480 } else {
481 flags = env->ps & PS_USER_MODE;
482 }
483 if (env->fen) {
484 flags |= TB_FLAGS_FEN;
485 }
486 flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
487
488 *pflags = flags;
aliguori6b917542008-11-18 19:46:41 +0000489}
490
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100491#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +0000492
j_mayer4c9649a2007-04-05 06:58:33 +0000493#endif /* !defined (__CPU_ALPHA_H__) */