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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * ARM micro operations
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
bellardb7bcbe92005-02-22 19:27:29 +00005 * Copyright (c) 2005 CodeSourcery, LLC
bellard2c0262a2003-09-30 20:34:21 +00006 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include "exec.h"
22
23#define REGNAME r0
24#define REG (env->regs[0])
25#include "op_template.h"
26
27#define REGNAME r1
28#define REG (env->regs[1])
29#include "op_template.h"
30
31#define REGNAME r2
32#define REG (env->regs[2])
33#include "op_template.h"
34
35#define REGNAME r3
36#define REG (env->regs[3])
37#include "op_template.h"
38
39#define REGNAME r4
40#define REG (env->regs[4])
41#include "op_template.h"
42
43#define REGNAME r5
44#define REG (env->regs[5])
45#include "op_template.h"
46
47#define REGNAME r6
48#define REG (env->regs[6])
49#include "op_template.h"
50
51#define REGNAME r7
52#define REG (env->regs[7])
53#include "op_template.h"
54
55#define REGNAME r8
56#define REG (env->regs[8])
57#include "op_template.h"
58
59#define REGNAME r9
60#define REG (env->regs[9])
61#include "op_template.h"
62
63#define REGNAME r10
64#define REG (env->regs[10])
65#include "op_template.h"
66
67#define REGNAME r11
68#define REG (env->regs[11])
69#include "op_template.h"
70
71#define REGNAME r12
72#define REG (env->regs[12])
73#include "op_template.h"
74
75#define REGNAME r13
76#define REG (env->regs[13])
77#include "op_template.h"
78
79#define REGNAME r14
80#define REG (env->regs[14])
81#include "op_template.h"
82
83#define REGNAME r15
84#define REG (env->regs[15])
bellard99c475a2005-01-31 20:45:13 +000085#define SET_REG(x) REG = x & ~(uint32_t)1
bellard2c0262a2003-09-30 20:34:21 +000086#include "op_template.h"
87
bellard99c475a2005-01-31 20:45:13 +000088void OPPROTO op_bx_T0(void)
89{
90 env->regs[15] = T0 & ~(uint32_t)1;
91 env->thumb = (T0 & 1) != 0;
92}
93
bellard2c0262a2003-09-30 20:34:21 +000094void OPPROTO op_movl_T0_0(void)
95{
96 T0 = 0;
97}
98
99void OPPROTO op_movl_T0_im(void)
100{
101 T0 = PARAM1;
102}
103
bellardb5ff1b32005-11-26 10:38:39 +0000104void OPPROTO op_movl_T0_T1(void)
105{
106 T0 = T1;
107}
108
bellard2c0262a2003-09-30 20:34:21 +0000109void OPPROTO op_movl_T1_im(void)
110{
111 T1 = PARAM1;
112}
113
bellard7ff4d212005-02-07 12:42:35 +0000114void OPPROTO op_mov_CF_T1(void)
115{
116 env->CF = ((uint32_t)T1) >> 31;
117}
118
bellard2c0262a2003-09-30 20:34:21 +0000119void OPPROTO op_movl_T2_im(void)
120{
121 T2 = PARAM1;
122}
123
124void OPPROTO op_addl_T1_im(void)
125{
126 T1 += PARAM1;
127}
128
129void OPPROTO op_addl_T1_T2(void)
130{
131 T1 += T2;
132}
133
134void OPPROTO op_subl_T1_T2(void)
135{
136 T1 -= T2;
137}
138
139void OPPROTO op_addl_T0_T1(void)
140{
141 T0 += T1;
142}
143
144void OPPROTO op_addl_T0_T1_cc(void)
145{
146 unsigned int src1;
147 src1 = T0;
148 T0 += T1;
149 env->NZF = T0;
150 env->CF = T0 < src1;
151 env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
152}
153
154void OPPROTO op_adcl_T0_T1(void)
155{
156 T0 += T1 + env->CF;
157}
158
159void OPPROTO op_adcl_T0_T1_cc(void)
160{
161 unsigned int src1;
162 src1 = T0;
163 if (!env->CF) {
164 T0 += T1;
165 env->CF = T0 < src1;
166 } else {
167 T0 += T1 + 1;
168 env->CF = T0 <= src1;
169 }
170 env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
171 env->NZF = T0;
172 FORCE_RET();
173}
174
175#define OPSUB(sub, sbc, res, T0, T1) \
176 \
177void OPPROTO op_ ## sub ## l_T0_T1(void) \
178{ \
179 res = T0 - T1; \
180} \
181 \
182void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \
183{ \
184 unsigned int src1; \
185 src1 = T0; \
186 T0 -= T1; \
187 env->NZF = T0; \
188 env->CF = src1 >= T1; \
189 env->VF = (src1 ^ T1) & (src1 ^ T0); \
190 res = T0; \
191} \
192 \
193void OPPROTO op_ ## sbc ## l_T0_T1(void) \
194{ \
195 res = T0 - T1 + env->CF - 1; \
196} \
197 \
198void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \
199{ \
200 unsigned int src1; \
201 src1 = T0; \
202 if (!env->CF) { \
203 T0 = T0 - T1 - 1; \
bellard78573df2005-02-02 20:43:01 +0000204 env->CF = src1 > T1; \
bellard2c0262a2003-09-30 20:34:21 +0000205 } else { \
206 T0 = T0 - T1; \
bellard78573df2005-02-02 20:43:01 +0000207 env->CF = src1 >= T1; \
bellard2c0262a2003-09-30 20:34:21 +0000208 } \
209 env->VF = (src1 ^ T1) & (src1 ^ T0); \
210 env->NZF = T0; \
211 res = T0; \
212 FORCE_RET(); \
213}
214
215OPSUB(sub, sbc, T0, T0, T1)
216
217OPSUB(rsb, rsc, T0, T1, T0)
218
219void OPPROTO op_andl_T0_T1(void)
220{
221 T0 &= T1;
222}
223
224void OPPROTO op_xorl_T0_T1(void)
225{
226 T0 ^= T1;
227}
228
229void OPPROTO op_orl_T0_T1(void)
230{
231 T0 |= T1;
232}
233
234void OPPROTO op_bicl_T0_T1(void)
235{
236 T0 &= ~T1;
237}
238
239void OPPROTO op_notl_T1(void)
240{
241 T1 = ~T1;
242}
243
244void OPPROTO op_logic_T0_cc(void)
245{
246 env->NZF = T0;
247}
248
249void OPPROTO op_logic_T1_cc(void)
250{
251 env->NZF = T1;
252}
253
254#define EIP (env->regs[15])
255
256void OPPROTO op_test_eq(void)
257{
258 if (env->NZF == 0)
bellarde50e6a22005-04-26 20:36:11 +0000259 GOTO_LABEL_PARAM(1);;
bellard2c0262a2003-09-30 20:34:21 +0000260 FORCE_RET();
261}
262
263void OPPROTO op_test_ne(void)
264{
265 if (env->NZF != 0)
bellarde50e6a22005-04-26 20:36:11 +0000266 GOTO_LABEL_PARAM(1);;
bellard2c0262a2003-09-30 20:34:21 +0000267 FORCE_RET();
268}
269
270void OPPROTO op_test_cs(void)
271{
272 if (env->CF != 0)
bellarde50e6a22005-04-26 20:36:11 +0000273 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000274 FORCE_RET();
275}
276
277void OPPROTO op_test_cc(void)
278{
279 if (env->CF == 0)
bellarde50e6a22005-04-26 20:36:11 +0000280 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000281 FORCE_RET();
282}
283
284void OPPROTO op_test_mi(void)
285{
286 if ((env->NZF & 0x80000000) != 0)
bellarde50e6a22005-04-26 20:36:11 +0000287 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000288 FORCE_RET();
289}
290
291void OPPROTO op_test_pl(void)
292{
293 if ((env->NZF & 0x80000000) == 0)
bellarde50e6a22005-04-26 20:36:11 +0000294 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000295 FORCE_RET();
296}
297
298void OPPROTO op_test_vs(void)
299{
300 if ((env->VF & 0x80000000) != 0)
bellarde50e6a22005-04-26 20:36:11 +0000301 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000302 FORCE_RET();
303}
304
305void OPPROTO op_test_vc(void)
306{
307 if ((env->VF & 0x80000000) == 0)
bellarde50e6a22005-04-26 20:36:11 +0000308 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000309 FORCE_RET();
310}
311
312void OPPROTO op_test_hi(void)
313{
314 if (env->CF != 0 && env->NZF != 0)
bellarde50e6a22005-04-26 20:36:11 +0000315 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000316 FORCE_RET();
317}
318
319void OPPROTO op_test_ls(void)
320{
321 if (env->CF == 0 || env->NZF == 0)
bellarde50e6a22005-04-26 20:36:11 +0000322 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000323 FORCE_RET();
324}
325
326void OPPROTO op_test_ge(void)
327{
328 if (((env->VF ^ env->NZF) & 0x80000000) == 0)
bellarde50e6a22005-04-26 20:36:11 +0000329 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000330 FORCE_RET();
331}
332
333void OPPROTO op_test_lt(void)
334{
335 if (((env->VF ^ env->NZF) & 0x80000000) != 0)
bellarde50e6a22005-04-26 20:36:11 +0000336 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000337 FORCE_RET();
338}
339
340void OPPROTO op_test_gt(void)
341{
342 if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0)
bellarde50e6a22005-04-26 20:36:11 +0000343 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000344 FORCE_RET();
345}
346
347void OPPROTO op_test_le(void)
348{
349 if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0)
bellarde50e6a22005-04-26 20:36:11 +0000350 GOTO_LABEL_PARAM(1);
bellard2c0262a2003-09-30 20:34:21 +0000351 FORCE_RET();
352}
353
bellardc53be332005-10-30 21:39:19 +0000354void OPPROTO op_goto_tb0(void)
bellard2c0262a2003-09-30 20:34:21 +0000355{
bellardc53be332005-10-30 21:39:19 +0000356 GOTO_TB(op_goto_tb0, PARAM1, 0);
bellarde50e6a22005-04-26 20:36:11 +0000357}
358
bellardc53be332005-10-30 21:39:19 +0000359void OPPROTO op_goto_tb1(void)
bellarde50e6a22005-04-26 20:36:11 +0000360{
bellardc53be332005-10-30 21:39:19 +0000361 GOTO_TB(op_goto_tb1, PARAM1, 1);
bellard2c0262a2003-09-30 20:34:21 +0000362}
363
364void OPPROTO op_exit_tb(void)
365{
366 EXIT_TB();
367}
368
bellardb5ff1b32005-11-26 10:38:39 +0000369void OPPROTO op_movl_T0_cpsr(void)
bellard2c0262a2003-09-30 20:34:21 +0000370{
bellardb5ff1b32005-11-26 10:38:39 +0000371 T0 = cpsr_read(env);
372 FORCE_RET();
bellard2c0262a2003-09-30 20:34:21 +0000373}
374
bellardb5ff1b32005-11-26 10:38:39 +0000375void OPPROTO op_movl_T0_spsr(void)
bellard2c0262a2003-09-30 20:34:21 +0000376{
bellardb5ff1b32005-11-26 10:38:39 +0000377 T0 = env->spsr;
378}
379
380void OPPROTO op_movl_spsr_T0(void)
381{
382 uint32_t mask = PARAM1;
383 env->spsr = (env->spsr & ~mask) | (T0 & mask);
384}
385
386void OPPROTO op_movl_cpsr_T0(void)
387{
388 cpsr_write(env, T0, PARAM1);
389 FORCE_RET();
bellard2c0262a2003-09-30 20:34:21 +0000390}
391
392void OPPROTO op_mul_T0_T1(void)
393{
394 T0 = T0 * T1;
395}
396
397/* 64 bit unsigned mul */
398void OPPROTO op_mull_T0_T1(void)
399{
400 uint64_t res;
bellard2e134c92003-11-11 13:55:33 +0000401 res = (uint64_t)T0 * (uint64_t)T1;
bellard2c0262a2003-09-30 20:34:21 +0000402 T1 = res >> 32;
403 T0 = res;
404}
405
406/* 64 bit signed mul */
407void OPPROTO op_imull_T0_T1(void)
408{
409 uint64_t res;
bellard163a7cb2003-11-30 19:40:08 +0000410 res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
bellard2c0262a2003-09-30 20:34:21 +0000411 T1 = res >> 32;
412 T0 = res;
413}
414
bellard99c475a2005-01-31 20:45:13 +0000415/* 48 bit signed mul, top 32 bits */
416void OPPROTO op_imulw_T0_T1(void)
417{
418 uint64_t res;
419 res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
420 T0 = res >> 16;
421}
422
bellard2c0262a2003-09-30 20:34:21 +0000423void OPPROTO op_addq_T0_T1(void)
424{
425 uint64_t res;
426 res = ((uint64_t)T1 << 32) | T0;
427 res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
428 T1 = res >> 32;
429 T0 = res;
430}
431
bellard99c475a2005-01-31 20:45:13 +0000432void OPPROTO op_addq_lo_T0_T1(void)
433{
434 uint64_t res;
435 res = ((uint64_t)T1 << 32) | T0;
436 res += (uint64_t)(env->regs[PARAM1]);
437 T1 = res >> 32;
438 T0 = res;
439}
440
bellard2c0262a2003-09-30 20:34:21 +0000441void OPPROTO op_logicq_cc(void)
442{
443 env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0);
444}
445
446/* memory access */
447
bellardb5ff1b32005-11-26 10:38:39 +0000448#define MEMSUFFIX _raw
449#include "op_mem.h"
bellard2c0262a2003-09-30 20:34:21 +0000450
bellardb5ff1b32005-11-26 10:38:39 +0000451#if !defined(CONFIG_USER_ONLY)
452#define MEMSUFFIX _user
453#include "op_mem.h"
454#define MEMSUFFIX _kernel
455#include "op_mem.h"
456#endif
bellard2c0262a2003-09-30 20:34:21 +0000457
458/* shifts */
459
460/* T1 based */
bellard1e8d4ee2004-12-08 23:40:14 +0000461
bellard2c0262a2003-09-30 20:34:21 +0000462void OPPROTO op_shll_T1_im(void)
463{
464 T1 = T1 << PARAM1;
465}
466
467void OPPROTO op_shrl_T1_im(void)
468{
469 T1 = (uint32_t)T1 >> PARAM1;
470}
471
bellard1e8d4ee2004-12-08 23:40:14 +0000472void OPPROTO op_shrl_T1_0(void)
473{
474 T1 = 0;
475}
476
bellard2c0262a2003-09-30 20:34:21 +0000477void OPPROTO op_sarl_T1_im(void)
478{
479 T1 = (int32_t)T1 >> PARAM1;
480}
481
bellard1e8d4ee2004-12-08 23:40:14 +0000482void OPPROTO op_sarl_T1_0(void)
483{
484 T1 = (int32_t)T1 >> 31;
485}
486
bellard2c0262a2003-09-30 20:34:21 +0000487void OPPROTO op_rorl_T1_im(void)
488{
489 int shift;
490 shift = PARAM1;
491 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
492}
493
bellard88920f32004-12-08 22:28:39 +0000494void OPPROTO op_rrxl_T1(void)
495{
496 T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
497}
498
bellard2c0262a2003-09-30 20:34:21 +0000499/* T1 based, set C flag */
500void OPPROTO op_shll_T1_im_cc(void)
501{
502 env->CF = (T1 >> (32 - PARAM1)) & 1;
503 T1 = T1 << PARAM1;
504}
505
506void OPPROTO op_shrl_T1_im_cc(void)
507{
508 env->CF = (T1 >> (PARAM1 - 1)) & 1;
509 T1 = (uint32_t)T1 >> PARAM1;
510}
511
bellard1e8d4ee2004-12-08 23:40:14 +0000512void OPPROTO op_shrl_T1_0_cc(void)
513{
514 env->CF = (T1 >> 31) & 1;
515 T1 = 0;
516}
517
bellard2c0262a2003-09-30 20:34:21 +0000518void OPPROTO op_sarl_T1_im_cc(void)
519{
520 env->CF = (T1 >> (PARAM1 - 1)) & 1;
521 T1 = (int32_t)T1 >> PARAM1;
522}
523
bellard1e8d4ee2004-12-08 23:40:14 +0000524void OPPROTO op_sarl_T1_0_cc(void)
525{
526 env->CF = (T1 >> 31) & 1;
527 T1 = (int32_t)T1 >> 31;
528}
529
bellard2c0262a2003-09-30 20:34:21 +0000530void OPPROTO op_rorl_T1_im_cc(void)
531{
532 int shift;
533 shift = PARAM1;
534 env->CF = (T1 >> (shift - 1)) & 1;
535 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
536}
537
bellard88920f32004-12-08 22:28:39 +0000538void OPPROTO op_rrxl_T1_cc(void)
539{
540 uint32_t c;
541 c = T1 & 1;
542 T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
543 env->CF = c;
544}
545
bellard2c0262a2003-09-30 20:34:21 +0000546/* T2 based */
547void OPPROTO op_shll_T2_im(void)
548{
549 T2 = T2 << PARAM1;
550}
551
552void OPPROTO op_shrl_T2_im(void)
553{
554 T2 = (uint32_t)T2 >> PARAM1;
555}
556
bellard1e8d4ee2004-12-08 23:40:14 +0000557void OPPROTO op_shrl_T2_0(void)
558{
559 T2 = 0;
560}
561
bellard2c0262a2003-09-30 20:34:21 +0000562void OPPROTO op_sarl_T2_im(void)
563{
564 T2 = (int32_t)T2 >> PARAM1;
565}
566
bellard1e8d4ee2004-12-08 23:40:14 +0000567void OPPROTO op_sarl_T2_0(void)
568{
569 T2 = (int32_t)T2 >> 31;
570}
571
bellard2c0262a2003-09-30 20:34:21 +0000572void OPPROTO op_rorl_T2_im(void)
573{
574 int shift;
575 shift = PARAM1;
576 T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
577}
578
bellard1e8d4ee2004-12-08 23:40:14 +0000579void OPPROTO op_rrxl_T2(void)
580{
581 T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31);
582}
583
bellard2c0262a2003-09-30 20:34:21 +0000584/* T1 based, use T0 as shift count */
585
586void OPPROTO op_shll_T1_T0(void)
587{
588 int shift;
589 shift = T0 & 0xff;
590 if (shift >= 32)
591 T1 = 0;
592 else
593 T1 = T1 << shift;
594 FORCE_RET();
595}
596
597void OPPROTO op_shrl_T1_T0(void)
598{
599 int shift;
600 shift = T0 & 0xff;
601 if (shift >= 32)
602 T1 = 0;
603 else
604 T1 = (uint32_t)T1 >> shift;
605 FORCE_RET();
606}
607
608void OPPROTO op_sarl_T1_T0(void)
609{
610 int shift;
611 shift = T0 & 0xff;
612 if (shift >= 32)
613 shift = 31;
614 T1 = (int32_t)T1 >> shift;
615}
616
617void OPPROTO op_rorl_T1_T0(void)
618{
619 int shift;
620 shift = T0 & 0x1f;
621 if (shift) {
622 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
623 }
624 FORCE_RET();
625}
626
627/* T1 based, use T0 as shift count and compute CF */
628
629void OPPROTO op_shll_T1_T0_cc(void)
630{
631 int shift;
632 shift = T0 & 0xff;
633 if (shift >= 32) {
634 if (shift == 32)
635 env->CF = T1 & 1;
636 else
637 env->CF = 0;
638 T1 = 0;
639 } else if (shift != 0) {
640 env->CF = (T1 >> (32 - shift)) & 1;
641 T1 = T1 << shift;
642 }
643 FORCE_RET();
644}
645
646void OPPROTO op_shrl_T1_T0_cc(void)
647{
648 int shift;
649 shift = T0 & 0xff;
650 if (shift >= 32) {
651 if (shift == 32)
652 env->CF = (T1 >> 31) & 1;
653 else
654 env->CF = 0;
655 T1 = 0;
656 } else if (shift != 0) {
657 env->CF = (T1 >> (shift - 1)) & 1;
658 T1 = (uint32_t)T1 >> shift;
659 }
660 FORCE_RET();
661}
662
663void OPPROTO op_sarl_T1_T0_cc(void)
664{
665 int shift;
666 shift = T0 & 0xff;
667 if (shift >= 32) {
668 env->CF = (T1 >> 31) & 1;
669 T1 = (int32_t)T1 >> 31;
balrog1b1afeb2007-05-21 17:48:01 +0000670 } else if (shift != 0) {
bellard2c0262a2003-09-30 20:34:21 +0000671 env->CF = (T1 >> (shift - 1)) & 1;
672 T1 = (int32_t)T1 >> shift;
673 }
674 FORCE_RET();
675}
676
677void OPPROTO op_rorl_T1_T0_cc(void)
678{
679 int shift1, shift;
680 shift1 = T0 & 0xff;
681 shift = shift1 & 0x1f;
682 if (shift == 0) {
683 if (shift1 != 0)
684 env->CF = (T1 >> 31) & 1;
685 } else {
686 env->CF = (T1 >> (shift - 1)) & 1;
687 T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
688 }
689 FORCE_RET();
690}
691
bellard99c475a2005-01-31 20:45:13 +0000692/* misc */
693void OPPROTO op_clz_T0(void)
694{
695 int count;
696 for (count = 32; T0 > 0; count--)
697 T0 = T0 >> 1;
698 T0 = count;
699 FORCE_RET();
700}
701
702void OPPROTO op_sarl_T0_im(void)
703{
704 T0 = (int32_t)T0 >> PARAM1;
705}
706
bellardb5ff1b32005-11-26 10:38:39 +0000707/* Sign/zero extend */
708void OPPROTO op_sxth_T0(void)
bellard99c475a2005-01-31 20:45:13 +0000709{
710 T0 = (int16_t)T0;
711}
712
bellardb5ff1b32005-11-26 10:38:39 +0000713void OPPROTO op_sxth_T1(void)
bellard99c475a2005-01-31 20:45:13 +0000714{
715 T1 = (int16_t)T1;
716}
717
bellardb5ff1b32005-11-26 10:38:39 +0000718void OPPROTO op_sxtb_T1(void)
719{
720 T1 = (int8_t)T1;
721}
722
723void OPPROTO op_uxtb_T1(void)
724{
725 T1 = (uint8_t)T1;
726}
727
728void OPPROTO op_uxth_T1(void)
729{
730 T1 = (uint16_t)T1;
731}
732
733void OPPROTO op_sxtb16_T1(void)
734{
735 uint32_t res;
736 res = (uint16_t)(int8_t)T1;
737 res |= (uint32_t)(int8_t)(T1 >> 16) << 16;
738 T1 = res;
739}
740
741void OPPROTO op_uxtb16_T1(void)
742{
743 uint32_t res;
744 res = (uint16_t)(uint8_t)T1;
745 res |= (uint32_t)(uint8_t)(T1 >> 16) << 16;
746 T1 = res;
747}
748
bellard99c475a2005-01-31 20:45:13 +0000749#define SIGNBIT (uint32_t)0x80000000
750/* saturating arithmetic */
751void OPPROTO op_addl_T0_T1_setq(void)
752{
753 uint32_t res;
754
755 res = T0 + T1;
756 if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
757 env->QF = 1;
758
759 T0 = res;
760 FORCE_RET();
761}
762
763void OPPROTO op_addl_T0_T1_saturate(void)
764{
765 uint32_t res;
766
767 res = T0 + T1;
768 if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
769 env->QF = 1;
770 if (T0 & SIGNBIT)
771 T0 = 0x80000000;
772 else
773 T0 = 0x7fffffff;
774 }
775 else
776 T0 = res;
ths3b46e622007-09-17 08:09:54 +0000777
bellard99c475a2005-01-31 20:45:13 +0000778 FORCE_RET();
779}
780
781void OPPROTO op_subl_T0_T1_saturate(void)
782{
783 uint32_t res;
784
785 res = T0 - T1;
786 if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
787 env->QF = 1;
788 if (T0 & SIGNBIT)
bellard567d4102006-06-26 19:55:19 +0000789 T0 = 0x80000000;
bellard99c475a2005-01-31 20:45:13 +0000790 else
791 T0 = 0x7fffffff;
792 }
793 else
794 T0 = res;
ths3b46e622007-09-17 08:09:54 +0000795
bellard99c475a2005-01-31 20:45:13 +0000796 FORCE_RET();
797}
798
bellardff8263a2005-05-13 22:45:23 +0000799void OPPROTO op_double_T1_saturate(void)
800{
801 int32_t val;
802
803 val = T1;
804 if (val >= 0x40000000) {
805 T1 = 0x7fffffff;
806 env->QF = 1;
807 } else if (val <= (int32_t)0xc0000000) {
808 T1 = 0x80000000;
809 env->QF = 1;
810 } else {
811 T1 = val << 1;
812 }
813 FORCE_RET();
814}
815
bellard99c475a2005-01-31 20:45:13 +0000816/* thumb shift by immediate */
817void OPPROTO op_shll_T0_im_thumb(void)
818{
819 int shift;
820 shift = PARAM1;
821 if (shift != 0) {
pbrookaa268ea2007-07-22 18:16:42 +0000822 env->CF = (T0 >> (32 - shift)) & 1;
bellard99c475a2005-01-31 20:45:13 +0000823 T0 = T0 << shift;
824 }
825 env->NZF = T0;
826 FORCE_RET();
827}
828
829void OPPROTO op_shrl_T0_im_thumb(void)
830{
831 int shift;
832
833 shift = PARAM1;
834 if (shift == 0) {
pbrookaa268ea2007-07-22 18:16:42 +0000835 env->CF = ((uint32_t)T0) >> 31;
bellard99c475a2005-01-31 20:45:13 +0000836 T0 = 0;
837 } else {
838 env->CF = (T0 >> (shift - 1)) & 1;
839 T0 = T0 >> shift;
840 }
bellard5899f382005-04-27 20:25:20 +0000841 env->NZF = T0;
bellard99c475a2005-01-31 20:45:13 +0000842 FORCE_RET();
843}
844
845void OPPROTO op_sarl_T0_im_thumb(void)
846{
847 int shift;
848
849 shift = PARAM1;
850 if (shift == 0) {
851 T0 = ((int32_t)T0) >> 31;
852 env->CF = T0 & 1;
853 } else {
854 env->CF = (T0 >> (shift - 1)) & 1;
855 T0 = ((int32_t)T0) >> shift;
856 }
857 env->NZF = T0;
858 FORCE_RET();
859}
860
bellard2c0262a2003-09-30 20:34:21 +0000861/* exceptions */
862
863void OPPROTO op_swi(void)
864{
865 env->exception_index = EXCP_SWI;
866 cpu_loop_exit();
867}
868
869void OPPROTO op_undef_insn(void)
870{
871 env->exception_index = EXCP_UDEF;
872 cpu_loop_exit();
873}
874
bellard1fddef42005-04-17 19:16:13 +0000875void OPPROTO op_debug(void)
876{
877 env->exception_index = EXCP_DEBUG;
878 cpu_loop_exit();
879}
880
bellard9332f9d2005-11-26 10:46:39 +0000881void OPPROTO op_wfi(void)
882{
883 env->exception_index = EXCP_HLT;
884 env->halted = 1;
885 cpu_loop_exit();
886}
887
pbrook06c949e2006-02-04 19:35:26 +0000888void OPPROTO op_bkpt(void)
889{
890 env->exception_index = EXCP_BKPT;
891 cpu_loop_exit();
892}
893
bellardb7bcbe92005-02-22 19:27:29 +0000894/* VFP support. We follow the convention used for VFP instrunctions:
895 Single precition routines have a "s" suffix, double precision a
896 "d" suffix. */
bellard2c0262a2003-09-30 20:34:21 +0000897
bellardb7bcbe92005-02-22 19:27:29 +0000898#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
bellard2c0262a2003-09-30 20:34:21 +0000899
bellard53cd6632005-03-13 18:50:23 +0000900#define VFP_BINOP(name) \
bellardb7bcbe92005-02-22 19:27:29 +0000901VFP_OP(name, s) \
902{ \
bellard53cd6632005-03-13 18:50:23 +0000903 FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \
bellardb7bcbe92005-02-22 19:27:29 +0000904} \
905VFP_OP(name, d) \
906{ \
bellard53cd6632005-03-13 18:50:23 +0000907 FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \
bellardb7bcbe92005-02-22 19:27:29 +0000908}
bellard53cd6632005-03-13 18:50:23 +0000909VFP_BINOP(add)
910VFP_BINOP(sub)
911VFP_BINOP(mul)
912VFP_BINOP(div)
bellardb7bcbe92005-02-22 19:27:29 +0000913#undef VFP_BINOP
914
915#define VFP_HELPER(name) \
916VFP_OP(name, s) \
917{ \
918 do_vfp_##name##s(); \
919} \
920VFP_OP(name, d) \
921{ \
922 do_vfp_##name##d(); \
923}
924VFP_HELPER(abs)
925VFP_HELPER(sqrt)
926VFP_HELPER(cmp)
927VFP_HELPER(cmpe)
928#undef VFP_HELPER
929
930/* XXX: Will this do the right thing for NANs. Should invert the signbit
931 without looking at the rest of the value. */
932VFP_OP(neg, s)
bellard2c0262a2003-09-30 20:34:21 +0000933{
bellard53cd6632005-03-13 18:50:23 +0000934 FT0s = float32_chs(FT0s);
bellard2c0262a2003-09-30 20:34:21 +0000935}
936
bellardb7bcbe92005-02-22 19:27:29 +0000937VFP_OP(neg, d)
bellard2c0262a2003-09-30 20:34:21 +0000938{
bellard53cd6632005-03-13 18:50:23 +0000939 FT0d = float64_chs(FT0d);
bellard2c0262a2003-09-30 20:34:21 +0000940}
941
bellardb7bcbe92005-02-22 19:27:29 +0000942VFP_OP(F1_ld0, s)
943{
bellard53cd6632005-03-13 18:50:23 +0000944 union {
945 uint32_t i;
946 float32 s;
947 } v;
948 v.i = 0;
949 FT1s = v.s;
bellardb7bcbe92005-02-22 19:27:29 +0000950}
951
952VFP_OP(F1_ld0, d)
953{
bellard53cd6632005-03-13 18:50:23 +0000954 union {
955 uint64_t i;
956 float64 d;
957 } v;
958 v.i = 0;
959 FT1d = v.d;
bellardb7bcbe92005-02-22 19:27:29 +0000960}
961
962/* Helper routines to perform bitwise copies between float and int. */
bellard53cd6632005-03-13 18:50:23 +0000963static inline float32 vfp_itos(uint32_t i)
bellardb7bcbe92005-02-22 19:27:29 +0000964{
965 union {
966 uint32_t i;
bellard53cd6632005-03-13 18:50:23 +0000967 float32 s;
bellardb7bcbe92005-02-22 19:27:29 +0000968 } v;
969
970 v.i = i;
971 return v.s;
972}
973
bellard53cd6632005-03-13 18:50:23 +0000974static inline uint32_t vfp_stoi(float32 s)
bellardb7bcbe92005-02-22 19:27:29 +0000975{
976 union {
977 uint32_t i;
bellard53cd6632005-03-13 18:50:23 +0000978 float32 s;
bellardb7bcbe92005-02-22 19:27:29 +0000979 } v;
980
981 v.s = s;
982 return v.i;
983}
984
985/* Integer to float conversion. */
986VFP_OP(uito, s)
987{
bellard53cd6632005-03-13 18:50:23 +0000988 FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +0000989}
990
991VFP_OP(uito, d)
992{
bellard53cd6632005-03-13 18:50:23 +0000993 FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +0000994}
995
996VFP_OP(sito, s)
997{
bellard53cd6632005-03-13 18:50:23 +0000998 FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +0000999}
1000
1001VFP_OP(sito, d)
1002{
bellard53cd6632005-03-13 18:50:23 +00001003 FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +00001004}
1005
1006/* Float to integer conversion. */
1007VFP_OP(toui, s)
1008{
bellard53cd6632005-03-13 18:50:23 +00001009 FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001010}
1011
1012VFP_OP(toui, d)
1013{
bellard53cd6632005-03-13 18:50:23 +00001014 FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001015}
1016
1017VFP_OP(tosi, s)
1018{
bellard53cd6632005-03-13 18:50:23 +00001019 FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001020}
1021
1022VFP_OP(tosi, d)
1023{
bellard53cd6632005-03-13 18:50:23 +00001024 FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001025}
1026
1027/* TODO: Set rounding mode properly. */
1028VFP_OP(touiz, s)
1029{
bellard53cd6632005-03-13 18:50:23 +00001030 FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001031}
1032
1033VFP_OP(touiz, d)
1034{
bellard53cd6632005-03-13 18:50:23 +00001035 FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001036}
1037
1038VFP_OP(tosiz, s)
1039{
bellard53cd6632005-03-13 18:50:23 +00001040 FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001041}
1042
1043VFP_OP(tosiz, d)
1044{
bellard53cd6632005-03-13 18:50:23 +00001045 FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status));
bellardb7bcbe92005-02-22 19:27:29 +00001046}
1047
1048/* floating point conversion */
1049VFP_OP(fcvtd, s)
1050{
bellard53cd6632005-03-13 18:50:23 +00001051 FT0d = float32_to_float64(FT0s, &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +00001052}
1053
1054VFP_OP(fcvts, d)
1055{
bellard53cd6632005-03-13 18:50:23 +00001056 FT0s = float64_to_float32(FT0d, &env->vfp.fp_status);
bellardb7bcbe92005-02-22 19:27:29 +00001057}
1058
1059/* Get and Put values from registers. */
1060VFP_OP(getreg_F0, d)
1061{
bellard53cd6632005-03-13 18:50:23 +00001062 FT0d = *(float64 *)((char *) env + PARAM1);
bellardb7bcbe92005-02-22 19:27:29 +00001063}
1064
1065VFP_OP(getreg_F0, s)
1066{
bellard53cd6632005-03-13 18:50:23 +00001067 FT0s = *(float32 *)((char *) env + PARAM1);
bellardb7bcbe92005-02-22 19:27:29 +00001068}
1069
1070VFP_OP(getreg_F1, d)
1071{
bellard53cd6632005-03-13 18:50:23 +00001072 FT1d = *(float64 *)((char *) env + PARAM1);
bellardb7bcbe92005-02-22 19:27:29 +00001073}
1074
1075VFP_OP(getreg_F1, s)
1076{
bellard53cd6632005-03-13 18:50:23 +00001077 FT1s = *(float32 *)((char *) env + PARAM1);
bellardb7bcbe92005-02-22 19:27:29 +00001078}
1079
1080VFP_OP(setreg_F0, d)
1081{
bellard53cd6632005-03-13 18:50:23 +00001082 *(float64 *)((char *) env + PARAM1) = FT0d;
bellardb7bcbe92005-02-22 19:27:29 +00001083}
1084
1085VFP_OP(setreg_F0, s)
1086{
bellard53cd6632005-03-13 18:50:23 +00001087 *(float32 *)((char *) env + PARAM1) = FT0s;
bellardb7bcbe92005-02-22 19:27:29 +00001088}
1089
1090void OPPROTO op_vfp_movl_T0_fpscr(void)
1091{
1092 do_vfp_get_fpscr ();
1093}
1094
1095void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
1096{
pbrook40f137e2006-02-20 00:33:36 +00001097 T0 = env->vfp.xregs[ARM_VFP_FPSCR] & (0xf << 28);
bellardb7bcbe92005-02-22 19:27:29 +00001098}
1099
1100void OPPROTO op_vfp_movl_fpscr_T0(void)
1101{
1102 do_vfp_set_fpscr();
1103}
1104
pbrook40f137e2006-02-20 00:33:36 +00001105void OPPROTO op_vfp_movl_T0_xreg(void)
1106{
1107 T0 = env->vfp.xregs[PARAM1];
1108}
1109
1110void OPPROTO op_vfp_movl_xreg_T0(void)
1111{
1112 env->vfp.xregs[PARAM1] = T0;
1113}
1114
bellardb7bcbe92005-02-22 19:27:29 +00001115/* Move between FT0s to T0 */
1116void OPPROTO op_vfp_mrs(void)
1117{
1118 T0 = vfp_stoi(FT0s);
1119}
1120
1121void OPPROTO op_vfp_msr(void)
1122{
1123 FT0s = vfp_itos(T0);
1124}
1125
1126/* Move between FT0d and {T0,T1} */
1127void OPPROTO op_vfp_mrrd(void)
1128{
1129 CPU_DoubleU u;
ths3b46e622007-09-17 08:09:54 +00001130
bellardb7bcbe92005-02-22 19:27:29 +00001131 u.d = FT0d;
1132 T0 = u.l.lower;
1133 T1 = u.l.upper;
1134}
1135
1136void OPPROTO op_vfp_mdrr(void)
1137{
1138 CPU_DoubleU u;
ths3b46e622007-09-17 08:09:54 +00001139
bellardb7bcbe92005-02-22 19:27:29 +00001140 u.l.lower = T0;
1141 u.l.upper = T1;
1142 FT0d = u.d;
1143}
1144
balrogc1713132007-04-30 01:26:42 +00001145/* Copy the most significant bit of T0 to all bits of T1. */
bellardb5ff1b32005-11-26 10:38:39 +00001146void OPPROTO op_signbit_T1_T0(void)
bellardb7bcbe92005-02-22 19:27:29 +00001147{
bellardb5ff1b32005-11-26 10:38:39 +00001148 T1 = (int32_t)T0 >> 31;
bellardb7bcbe92005-02-22 19:27:29 +00001149}
1150
balrogc1713132007-04-30 01:26:42 +00001151void OPPROTO op_movl_cp_T0(void)
1152{
1153 helper_set_cp(env, PARAM1, T0);
1154 FORCE_RET();
1155}
1156
1157void OPPROTO op_movl_T0_cp(void)
1158{
1159 T0 = helper_get_cp(env, PARAM1);
1160 FORCE_RET();
1161}
1162
bellardb5ff1b32005-11-26 10:38:39 +00001163void OPPROTO op_movl_cp15_T0(void)
bellardb7bcbe92005-02-22 19:27:29 +00001164{
bellardb5ff1b32005-11-26 10:38:39 +00001165 helper_set_cp15(env, PARAM1, T0);
1166 FORCE_RET();
bellardb7bcbe92005-02-22 19:27:29 +00001167}
1168
bellardb5ff1b32005-11-26 10:38:39 +00001169void OPPROTO op_movl_T0_cp15(void)
bellardb7bcbe92005-02-22 19:27:29 +00001170{
bellardb5ff1b32005-11-26 10:38:39 +00001171 T0 = helper_get_cp15(env, PARAM1);
1172 FORCE_RET();
bellardb7bcbe92005-02-22 19:27:29 +00001173}
1174
bellardb5ff1b32005-11-26 10:38:39 +00001175/* Access to user mode registers from privileged modes. */
1176void OPPROTO op_movl_T0_user(void)
bellardb7bcbe92005-02-22 19:27:29 +00001177{
bellardb5ff1b32005-11-26 10:38:39 +00001178 int regno = PARAM1;
1179 if (regno == 13) {
1180 T0 = env->banked_r13[0];
1181 } else if (regno == 14) {
1182 T0 = env->banked_r14[0];
1183 } else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
1184 T0 = env->usr_regs[regno - 8];
1185 } else {
1186 T0 = env->regs[regno];
1187 }
1188 FORCE_RET();
1189}
1190
1191
1192void OPPROTO op_movl_user_T0(void)
1193{
1194 int regno = PARAM1;
1195 if (regno == 13) {
1196 env->banked_r13[0] = T0;
1197 } else if (regno == 14) {
1198 env->banked_r14[0] = T0;
1199 } else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
1200 env->usr_regs[regno - 8] = T0;
1201 } else {
1202 env->regs[regno] = T0;
1203 }
1204 FORCE_RET();
bellardb7bcbe92005-02-22 19:27:29 +00001205}
pbrook191abaa2006-02-04 21:50:36 +00001206
1207void OPPROTO op_movl_T2_T0(void)
1208{
1209 T2 = T0;
1210}
1211
1212void OPPROTO op_movl_T0_T2(void)
1213{
1214 T0 = T2;
1215}
balrog18c9b562007-04-30 02:02:17 +00001216
1217/* iwMMXt support */
1218#include "op_iwmmxt.c"