bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1 | /* |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 2 | * PowerPC emulation for qemu: main translation routines. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 19 | */ |
bellard | c6a1c22 | 2004-05-20 13:10:49 +0000 | [diff] [blame] | 20 | #include <stdarg.h> |
| 21 | #include <stdlib.h> |
| 22 | #include <stdio.h> |
| 23 | #include <string.h> |
| 24 | #include <inttypes.h> |
| 25 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 26 | #include "cpu.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 27 | #include "disas.h" |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 28 | #include "tcg-op.h" |
aurel32 | ca10f86 | 2008-04-11 21:35:42 +0000 | [diff] [blame] | 29 | #include "qemu-common.h" |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 30 | #include "host-utils.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 31 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 32 | #include "helper.h" |
| 33 | #define GEN_HELPER 1 |
| 34 | #include "helper.h" |
| 35 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 36 | #define CPU_SINGLE_STEP 0x1 |
| 37 | #define CPU_BRANCH_STEP 0x2 |
| 38 | #define GDBSTUB_SINGLE_STEP 0x4 |
| 39 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 40 | /* Include definitions for instructions classes and implementations flags */ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 41 | //#define PPC_DEBUG_DISAS |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 42 | //#define DO_PPC_STATISTICS |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 43 | |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 44 | #ifdef PPC_DEBUG_DISAS |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 45 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 46 | #else |
| 47 | # define LOG_DISAS(...) do { } while (0) |
| 48 | #endif |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 49 | /*****************************************************************************/ |
| 50 | /* Code translation helpers */ |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 51 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 52 | /* global register indexes */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 53 | static TCGv_ptr cpu_env; |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 54 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 55 | #if !defined(TARGET_PPC64) |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 56 | + 10*4 + 22*5 /* SPE GPRh */ |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 57 | #endif |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 58 | + 10*4 + 22*5 /* FPR */ |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 59 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
| 60 | + 8*5 /* CRF */]; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 61 | static TCGv cpu_gpr[32]; |
| 62 | #if !defined(TARGET_PPC64) |
| 63 | static TCGv cpu_gprh[32]; |
| 64 | #endif |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 65 | static TCGv_i64 cpu_fpr[32]; |
| 66 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
| 67 | static TCGv_i32 cpu_crf[8]; |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 68 | static TCGv cpu_nip; |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 69 | static TCGv cpu_msr; |
aurel32 | cfdcd37 | 2008-09-14 18:30:23 +0000 | [diff] [blame] | 70 | static TCGv cpu_ctr; |
| 71 | static TCGv cpu_lr; |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 72 | #if defined(TARGET_PPC64) |
| 73 | static TCGv cpu_cfar; |
| 74 | #endif |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 75 | static TCGv cpu_xer; |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 76 | static TCGv cpu_reserve; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 77 | static TCGv_i32 cpu_fpscr; |
aurel32 | a7859e8 | 2008-11-23 16:30:40 +0000 | [diff] [blame] | 78 | static TCGv_i32 cpu_access_type; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 79 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 80 | #include "gen-icount.h" |
| 81 | |
| 82 | void ppc_translate_init(void) |
| 83 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 84 | int i; |
| 85 | char* p; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 86 | size_t cpu_reg_names_size; |
pbrook | b2437bf | 2008-06-29 12:29:56 +0000 | [diff] [blame] | 87 | static int done_init = 0; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 88 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 89 | if (done_init) |
| 90 | return; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 91 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 92 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 93 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 94 | p = cpu_reg_names; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 95 | cpu_reg_names_size = sizeof(cpu_reg_names); |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 96 | |
| 97 | for (i = 0; i < 8; i++) { |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 98 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 99 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 100 | offsetof(CPUState, crf[i]), p); |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 101 | p += 5; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 102 | cpu_reg_names_size -= 5; |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 103 | } |
| 104 | |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 105 | for (i = 0; i < 32; i++) { |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 106 | snprintf(p, cpu_reg_names_size, "r%d", i); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 107 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 108 | offsetof(CPUState, gpr[i]), p); |
| 109 | p += (i < 10) ? 3 : 4; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 110 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 111 | #if !defined(TARGET_PPC64) |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 112 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 113 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
| 114 | offsetof(CPUState, gprh[i]), p); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 115 | p += (i < 10) ? 4 : 5; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 116 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 117 | #endif |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 118 | |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 119 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 120 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
| 121 | offsetof(CPUState, fpr[i]), p); |
aurel32 | ec1ac72 | 2008-09-04 15:49:12 +0000 | [diff] [blame] | 122 | p += (i < 10) ? 4 : 5; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 123 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
aurel32 | a5e26af | 2008-09-04 14:43:54 +0000 | [diff] [blame] | 124 | |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 125 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 126 | #ifdef HOST_WORDS_BIGENDIAN |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 127 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 128 | offsetof(CPUState, avr[i].u64[0]), p); |
| 129 | #else |
| 130 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
| 131 | offsetof(CPUState, avr[i].u64[1]), p); |
| 132 | #endif |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 133 | p += (i < 10) ? 6 : 7; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 134 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
aurel32 | ec1ac72 | 2008-09-04 15:49:12 +0000 | [diff] [blame] | 135 | |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 136 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 137 | #ifdef HOST_WORDS_BIGENDIAN |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 138 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 139 | offsetof(CPUState, avr[i].u64[1]), p); |
| 140 | #else |
| 141 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
| 142 | offsetof(CPUState, avr[i].u64[0]), p); |
| 143 | #endif |
aurel32 | 1d54269 | 2008-09-04 14:43:45 +0000 | [diff] [blame] | 144 | p += (i < 10) ? 6 : 7; |
blueswir1 | 2dc766d | 2009-04-13 16:06:19 +0000 | [diff] [blame] | 145 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 146 | } |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 147 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 148 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 149 | offsetof(CPUState, nip), "nip"); |
| 150 | |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 151 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
| 152 | offsetof(CPUState, msr), "msr"); |
| 153 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 154 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
aurel32 | cfdcd37 | 2008-09-14 18:30:23 +0000 | [diff] [blame] | 155 | offsetof(CPUState, ctr), "ctr"); |
| 156 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 157 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
aurel32 | cfdcd37 | 2008-09-14 18:30:23 +0000 | [diff] [blame] | 158 | offsetof(CPUState, lr), "lr"); |
| 159 | |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 160 | #if defined(TARGET_PPC64) |
| 161 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, |
| 162 | offsetof(CPUState, cfar), "cfar"); |
| 163 | #endif |
| 164 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 165 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 166 | offsetof(CPUState, xer), "xer"); |
| 167 | |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 168 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 169 | offsetof(CPUState, reserve_addr), |
| 170 | "reserve_addr"); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 171 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 172 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
| 173 | offsetof(CPUState, fpscr), "fpscr"); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 174 | |
aurel32 | a7859e8 | 2008-11-23 16:30:40 +0000 | [diff] [blame] | 175 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
| 176 | offsetof(CPUState, access_type), "access_type"); |
| 177 | |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 178 | /* register helpers */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 179 | #define GEN_HELPER 2 |
aurel32 | f10dc08 | 2008-08-28 21:01:45 +0000 | [diff] [blame] | 180 | #include "helper.h" |
| 181 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 182 | done_init = 1; |
| 183 | } |
| 184 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 185 | /* internal defines */ |
| 186 | typedef struct DisasContext { |
| 187 | struct TranslationBlock *tb; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 188 | target_ulong nip; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 189 | uint32_t opcode; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 190 | uint32_t exception; |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 191 | /* Routine used to access memory */ |
| 192 | int mem_idx; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 193 | int access_type; |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 194 | /* Translation flags */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 195 | int le_mode; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 196 | #if defined(TARGET_PPC64) |
| 197 | int sf_mode; |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 198 | int has_cfar; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 199 | #endif |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 200 | int fpu_enabled; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 201 | int altivec_enabled; |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 202 | int spe_enabled; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 203 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
bellard | ea4e754 | 2006-05-22 21:50:20 +0000 | [diff] [blame] | 204 | int singlestep_enabled; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 205 | } DisasContext; |
| 206 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 207 | struct opc_handler_t { |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 208 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
| 209 | uint32_t inval1; |
| 210 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ |
| 211 | uint32_t inval2; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 212 | /* instruction type */ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 213 | uint64_t type; |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 214 | /* extended instruction type */ |
| 215 | uint64_t type2; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 216 | /* handler */ |
| 217 | void (*handler)(DisasContext *ctx); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 218 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 219 | const char *oname; |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 220 | #endif |
| 221 | #if defined(DO_PPC_STATISTICS) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 222 | uint64_t count; |
| 223 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 224 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 225 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 226 | static inline void gen_reset_fpstatus(void) |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 227 | { |
aurel32 | a44d2ce | 2008-12-13 11:46:27 +0000 | [diff] [blame] | 228 | gen_helper_reset_fpstatus(); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 229 | } |
| 230 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 231 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 232 | { |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 233 | TCGv_i32 t0 = tcg_temp_new_i32(); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 234 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 235 | if (set_fprf != 0) { |
| 236 | /* This case might be optimized later */ |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 237 | tcg_gen_movi_i32(t0, 1); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 238 | gen_helper_compute_fprf(t0, arg, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 239 | if (unlikely(set_rc)) { |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 240 | tcg_gen_mov_i32(cpu_crf[1], t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 241 | } |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 242 | gen_helper_float_check_status(); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 243 | } else if (unlikely(set_rc)) { |
| 244 | /* We always need to compute fpcc */ |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 245 | tcg_gen_movi_i32(t0, 0); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 246 | gen_helper_compute_fprf(t0, arg, t0); |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 247 | tcg_gen_mov_i32(cpu_crf[1], t0); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 248 | } |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 249 | |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 250 | tcg_temp_free_i32(t0); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 251 | } |
| 252 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 253 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
aurel32 | a7859e8 | 2008-11-23 16:30:40 +0000 | [diff] [blame] | 254 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 255 | if (ctx->access_type != access_type) { |
| 256 | tcg_gen_movi_i32(cpu_access_type, access_type); |
| 257 | ctx->access_type = access_type; |
| 258 | } |
aurel32 | a7859e8 | 2008-11-23 16:30:40 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 261 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 262 | { |
| 263 | #if defined(TARGET_PPC64) |
| 264 | if (ctx->sf_mode) |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 265 | tcg_gen_movi_tl(cpu_nip, nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 266 | else |
| 267 | #endif |
aurel32 | bd568f1 | 2008-09-04 18:06:03 +0000 | [diff] [blame] | 268 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 269 | } |
| 270 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 271 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 272 | { |
| 273 | TCGv_i32 t0, t1; |
| 274 | if (ctx->exception == POWERPC_EXCP_NONE) { |
| 275 | gen_update_nip(ctx, ctx->nip); |
| 276 | } |
| 277 | t0 = tcg_const_i32(excp); |
| 278 | t1 = tcg_const_i32(error); |
| 279 | gen_helper_raise_exception_err(t0, t1); |
| 280 | tcg_temp_free_i32(t0); |
| 281 | tcg_temp_free_i32(t1); |
| 282 | ctx->exception = (excp); |
| 283 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 284 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 285 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 286 | { |
| 287 | TCGv_i32 t0; |
| 288 | if (ctx->exception == POWERPC_EXCP_NONE) { |
| 289 | gen_update_nip(ctx, ctx->nip); |
| 290 | } |
| 291 | t0 = tcg_const_i32(excp); |
| 292 | gen_helper_raise_exception(t0); |
| 293 | tcg_temp_free_i32(t0); |
| 294 | ctx->exception = (excp); |
| 295 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 296 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 297 | static inline void gen_debug_exception(DisasContext *ctx) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 298 | { |
| 299 | TCGv_i32 t0; |
blueswir1 | 5518f3a | 2009-02-19 20:17:09 +0000 | [diff] [blame] | 300 | |
Sebastian Bauer | ee2b399 | 2011-08-10 01:41:48 +0000 | [diff] [blame] | 301 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
| 302 | (ctx->exception != POWERPC_EXCP_SYNC)) { |
blueswir1 | 5518f3a | 2009-02-19 20:17:09 +0000 | [diff] [blame] | 303 | gen_update_nip(ctx, ctx->nip); |
Sebastian Bauer | ee2b399 | 2011-08-10 01:41:48 +0000 | [diff] [blame] | 304 | } |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 305 | t0 = tcg_const_i32(EXCP_DEBUG); |
| 306 | gen_helper_raise_exception(t0); |
| 307 | tcg_temp_free_i32(t0); |
| 308 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 309 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 310 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 311 | { |
| 312 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
| 313 | } |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 314 | |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 315 | /* Stop translation */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 316 | static inline void gen_stop_exception(DisasContext *ctx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 317 | { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 318 | gen_update_nip(ctx, ctx->nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 319 | ctx->exception = POWERPC_EXCP_STOP; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 320 | } |
| 321 | |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 322 | /* No need to update nip here, as execution flow will change */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 323 | static inline void gen_sync_exception(DisasContext *ctx) |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 324 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 325 | ctx->exception = POWERPC_EXCP_SYNC; |
bellard | 2be0071 | 2005-07-02 22:09:27 +0000 | [diff] [blame] | 326 | } |
| 327 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 328 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 329 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
| 330 | |
| 331 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ |
| 332 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 333 | |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 334 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 335 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
| 336 | |
| 337 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ |
| 338 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 339 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 340 | typedef struct opcode_t { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 341 | unsigned char opc1, opc2, opc3; |
ths | 1235fc0 | 2008-06-03 19:51:57 +0000 | [diff] [blame] | 342 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 343 | unsigned char pad[5]; |
| 344 | #else |
| 345 | unsigned char pad[1]; |
| 346 | #endif |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 347 | opc_handler_t handler; |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 348 | const char *oname; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 349 | } opcode_t; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 350 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 351 | /*****************************************************************************/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 352 | /*** Instruction decoding ***/ |
| 353 | #define EXTRACT_HELPER(name, shift, nb) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 354 | static inline uint32_t name(uint32_t opcode) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 355 | { \ |
| 356 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
| 357 | } |
| 358 | |
| 359 | #define EXTRACT_SHELPER(name, shift, nb) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 360 | static inline int32_t name(uint32_t opcode) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 361 | { \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 362 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | /* Opcode part 1 */ |
| 366 | EXTRACT_HELPER(opc1, 26, 6); |
| 367 | /* Opcode part 2 */ |
| 368 | EXTRACT_HELPER(opc2, 1, 5); |
| 369 | /* Opcode part 3 */ |
| 370 | EXTRACT_HELPER(opc3, 6, 5); |
| 371 | /* Update Cr0 flags */ |
| 372 | EXTRACT_HELPER(Rc, 0, 1); |
| 373 | /* Destination */ |
| 374 | EXTRACT_HELPER(rD, 21, 5); |
| 375 | /* Source */ |
| 376 | EXTRACT_HELPER(rS, 21, 5); |
| 377 | /* First operand */ |
| 378 | EXTRACT_HELPER(rA, 16, 5); |
| 379 | /* Second operand */ |
| 380 | EXTRACT_HELPER(rB, 11, 5); |
| 381 | /* Third operand */ |
| 382 | EXTRACT_HELPER(rC, 6, 5); |
| 383 | /*** Get CRn ***/ |
| 384 | EXTRACT_HELPER(crfD, 23, 3); |
| 385 | EXTRACT_HELPER(crfS, 18, 3); |
| 386 | EXTRACT_HELPER(crbD, 21, 5); |
| 387 | EXTRACT_HELPER(crbA, 16, 5); |
| 388 | EXTRACT_HELPER(crbB, 11, 5); |
| 389 | /* SPR / TBL */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 390 | EXTRACT_HELPER(_SPR, 11, 10); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 391 | static inline uint32_t SPR(uint32_t opcode) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 392 | { |
| 393 | uint32_t sprn = _SPR(opcode); |
| 394 | |
| 395 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
| 396 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 397 | /*** Get constants ***/ |
| 398 | EXTRACT_HELPER(IMM, 12, 8); |
| 399 | /* 16 bits signed immediate value */ |
| 400 | EXTRACT_SHELPER(SIMM, 0, 16); |
| 401 | /* 16 bits unsigned immediate value */ |
| 402 | EXTRACT_HELPER(UIMM, 0, 16); |
aurel32 | 21d2158 | 2009-01-04 22:10:28 +0000 | [diff] [blame] | 403 | /* 5 bits signed immediate value */ |
| 404 | EXTRACT_HELPER(SIMM5, 16, 5); |
aurel32 | 27a4edb | 2009-01-04 22:10:40 +0000 | [diff] [blame] | 405 | /* 5 bits signed immediate value */ |
| 406 | EXTRACT_HELPER(UIMM5, 16, 5); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 407 | /* Bit count */ |
| 408 | EXTRACT_HELPER(NB, 11, 5); |
| 409 | /* Shift count */ |
| 410 | EXTRACT_HELPER(SH, 11, 5); |
aurel32 | cd633b1 | 2009-01-04 22:10:09 +0000 | [diff] [blame] | 411 | /* Vector shift count */ |
| 412 | EXTRACT_HELPER(VSH, 6, 4); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 413 | /* Mask start */ |
| 414 | EXTRACT_HELPER(MB, 6, 5); |
| 415 | /* Mask end */ |
| 416 | EXTRACT_HELPER(ME, 1, 5); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 417 | /* Trap operand */ |
| 418 | EXTRACT_HELPER(TO, 21, 5); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 419 | |
| 420 | EXTRACT_HELPER(CRM, 12, 8); |
| 421 | EXTRACT_HELPER(FM, 17, 8); |
| 422 | EXTRACT_HELPER(SR, 16, 4); |
aurel32 | e4bb997 | 2008-06-18 22:10:12 +0000 | [diff] [blame] | 423 | EXTRACT_HELPER(FPIMM, 12, 4); |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 424 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 425 | /*** Jump target decoding ***/ |
| 426 | /* Displacement */ |
| 427 | EXTRACT_SHELPER(d, 0, 16); |
| 428 | /* Immediate address */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 429 | static inline target_ulong LI(uint32_t opcode) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 430 | { |
| 431 | return (opcode >> 0) & 0x03FFFFFC; |
| 432 | } |
| 433 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 434 | static inline uint32_t BD(uint32_t opcode) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 435 | { |
| 436 | return (opcode >> 0) & 0xFFFC; |
| 437 | } |
| 438 | |
| 439 | EXTRACT_HELPER(BO, 21, 5); |
| 440 | EXTRACT_HELPER(BI, 16, 5); |
| 441 | /* Absolute/relative address */ |
| 442 | EXTRACT_HELPER(AA, 1, 1); |
| 443 | /* Link */ |
| 444 | EXTRACT_HELPER(LK, 0, 1); |
| 445 | |
| 446 | /* Create a mask between <start> and <end> bits */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 447 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 448 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 449 | target_ulong ret; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 450 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 451 | #if defined(TARGET_PPC64) |
| 452 | if (likely(start == 0)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 453 | ret = UINT64_MAX << (63 - end); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 454 | } else if (likely(end == 63)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 455 | ret = UINT64_MAX >> start; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 456 | } |
| 457 | #else |
| 458 | if (likely(start == 0)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 459 | ret = UINT32_MAX << (31 - end); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 460 | } else if (likely(end == 31)) { |
j_mayer | 6f2d897 | 2007-11-12 00:04:48 +0000 | [diff] [blame] | 461 | ret = UINT32_MAX >> start; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 462 | } |
| 463 | #endif |
| 464 | else { |
| 465 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ |
| 466 | (((target_ulong)(-1ULL) >> (end)) >> 1); |
| 467 | if (unlikely(start > end)) |
| 468 | return ~ret; |
| 469 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 470 | |
| 471 | return ret; |
| 472 | } |
| 473 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 474 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 475 | /* PowerPC instructions table */ |
bellard | 933dc6e | 2004-07-10 15:33:29 +0000 | [diff] [blame] | 476 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 477 | #if defined(DO_PPC_STATISTICS) |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 478 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 479 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 480 | .opc1 = op1, \ |
| 481 | .opc2 = op2, \ |
| 482 | .opc3 = op3, \ |
| 483 | .pad = { 0, }, \ |
| 484 | .handler = { \ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 485 | .inval1 = invl, \ |
| 486 | .type = _typ, \ |
| 487 | .type2 = _typ2, \ |
| 488 | .handler = &gen_##name, \ |
| 489 | .oname = stringify(name), \ |
| 490 | }, \ |
| 491 | .oname = stringify(name), \ |
| 492 | } |
| 493 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ |
| 494 | { \ |
| 495 | .opc1 = op1, \ |
| 496 | .opc2 = op2, \ |
| 497 | .opc3 = op3, \ |
| 498 | .pad = { 0, }, \ |
| 499 | .handler = { \ |
| 500 | .inval1 = invl1, \ |
| 501 | .inval2 = invl2, \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 502 | .type = _typ, \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 503 | .type2 = _typ2, \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 504 | .handler = &gen_##name, \ |
| 505 | .oname = stringify(name), \ |
| 506 | }, \ |
| 507 | .oname = stringify(name), \ |
| 508 | } |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 509 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 510 | { \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 511 | .opc1 = op1, \ |
| 512 | .opc2 = op2, \ |
| 513 | .opc3 = op3, \ |
| 514 | .pad = { 0, }, \ |
| 515 | .handler = { \ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 516 | .inval1 = invl, \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 517 | .type = _typ, \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 518 | .type2 = _typ2, \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 519 | .handler = &gen_##name, \ |
| 520 | .oname = onam, \ |
| 521 | }, \ |
| 522 | .oname = onam, \ |
| 523 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 524 | #else |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 525 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 526 | { \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 527 | .opc1 = op1, \ |
| 528 | .opc2 = op2, \ |
| 529 | .opc3 = op3, \ |
bellard | 18fba28 | 2005-02-08 21:24:36 +0000 | [diff] [blame] | 530 | .pad = { 0, }, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 531 | .handler = { \ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 532 | .inval1 = invl, \ |
| 533 | .type = _typ, \ |
| 534 | .type2 = _typ2, \ |
| 535 | .handler = &gen_##name, \ |
| 536 | }, \ |
| 537 | .oname = stringify(name), \ |
| 538 | } |
| 539 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ |
| 540 | { \ |
| 541 | .opc1 = op1, \ |
| 542 | .opc2 = op2, \ |
| 543 | .opc3 = op3, \ |
| 544 | .pad = { 0, }, \ |
| 545 | .handler = { \ |
| 546 | .inval1 = invl1, \ |
| 547 | .inval2 = invl2, \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 548 | .type = _typ, \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 549 | .type2 = _typ2, \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 550 | .handler = &gen_##name, \ |
| 551 | }, \ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 552 | .oname = stringify(name), \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 553 | } |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 554 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 555 | { \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 556 | .opc1 = op1, \ |
| 557 | .opc2 = op2, \ |
| 558 | .opc3 = op3, \ |
| 559 | .pad = { 0, }, \ |
| 560 | .handler = { \ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 561 | .inval1 = invl, \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 562 | .type = _typ, \ |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 563 | .type2 = _typ2, \ |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 564 | .handler = &gen_##name, \ |
| 565 | }, \ |
| 566 | .oname = onam, \ |
| 567 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 568 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 569 | |
aurel32 | 54cdcae | 2008-12-05 07:21:31 +0000 | [diff] [blame] | 570 | /* SPR load/store helpers */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 571 | static inline void gen_load_spr(TCGv t, int reg) |
aurel32 | 54cdcae | 2008-12-05 07:21:31 +0000 | [diff] [blame] | 572 | { |
| 573 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
| 574 | } |
| 575 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 576 | static inline void gen_store_spr(int reg, TCGv t) |
aurel32 | 54cdcae | 2008-12-05 07:21:31 +0000 | [diff] [blame] | 577 | { |
| 578 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); |
| 579 | } |
| 580 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 581 | /* Invalid instruction */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 582 | static void gen_invalid(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 583 | { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 584 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 585 | } |
| 586 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 587 | static opc_handler_t invalid_handler = { |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 588 | .inval1 = 0xFFFFFFFF, |
| 589 | .inval2 = 0xFFFFFFFF, |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 590 | .type = PPC_NONE, |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 591 | .type2 = PPC_NONE, |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 592 | .handler = gen_invalid, |
| 593 | }; |
| 594 | |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 595 | /*** Integer comparison ***/ |
| 596 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 597 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 598 | { |
| 599 | int l1, l2, l3; |
| 600 | |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 601 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
| 602 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 603 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); |
| 604 | |
| 605 | l1 = gen_new_label(); |
| 606 | l2 = gen_new_label(); |
| 607 | l3 = gen_new_label(); |
| 608 | if (s) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 609 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
| 610 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 611 | } else { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 612 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
| 613 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 614 | } |
| 615 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); |
| 616 | tcg_gen_br(l3); |
| 617 | gen_set_label(l1); |
| 618 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); |
| 619 | tcg_gen_br(l3); |
| 620 | gen_set_label(l2); |
| 621 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); |
| 622 | gen_set_label(l3); |
| 623 | } |
| 624 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 625 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 626 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 627 | TCGv t0 = tcg_const_local_tl(arg1); |
| 628 | gen_op_cmp(arg0, t0, s, crf); |
| 629 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | #if defined(TARGET_PPC64) |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 633 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 634 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 635 | TCGv t0, t1; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 636 | t0 = tcg_temp_local_new(); |
| 637 | t1 = tcg_temp_local_new(); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 638 | if (s) { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 639 | tcg_gen_ext32s_tl(t0, arg0); |
| 640 | tcg_gen_ext32s_tl(t1, arg1); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 641 | } else { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 642 | tcg_gen_ext32u_tl(t0, arg0); |
| 643 | tcg_gen_ext32u_tl(t1, arg1); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 644 | } |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 645 | gen_op_cmp(t0, t1, s, crf); |
| 646 | tcg_temp_free(t1); |
| 647 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 648 | } |
| 649 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 650 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 651 | { |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 652 | TCGv t0 = tcg_const_local_tl(arg1); |
| 653 | gen_op_cmp32(arg0, t0, s, crf); |
| 654 | tcg_temp_free(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 655 | } |
| 656 | #endif |
| 657 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 658 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 659 | { |
| 660 | #if defined(TARGET_PPC64) |
| 661 | if (!(ctx->sf_mode)) |
| 662 | gen_op_cmpi32(reg, 0, 1, 0); |
| 663 | else |
| 664 | #endif |
| 665 | gen_op_cmpi(reg, 0, 1, 0); |
| 666 | } |
| 667 | |
| 668 | /* cmp */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 669 | static void gen_cmp(DisasContext *ctx) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 670 | { |
| 671 | #if defined(TARGET_PPC64) |
| 672 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 673 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 674 | 1, crfD(ctx->opcode)); |
| 675 | else |
| 676 | #endif |
| 677 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 678 | 1, crfD(ctx->opcode)); |
| 679 | } |
| 680 | |
| 681 | /* cmpi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 682 | static void gen_cmpi(DisasContext *ctx) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 683 | { |
| 684 | #if defined(TARGET_PPC64) |
| 685 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 686 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 687 | 1, crfD(ctx->opcode)); |
| 688 | else |
| 689 | #endif |
| 690 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
| 691 | 1, crfD(ctx->opcode)); |
| 692 | } |
| 693 | |
| 694 | /* cmpl */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 695 | static void gen_cmpl(DisasContext *ctx) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 696 | { |
| 697 | #if defined(TARGET_PPC64) |
| 698 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 699 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 700 | 0, crfD(ctx->opcode)); |
| 701 | else |
| 702 | #endif |
| 703 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
| 704 | 0, crfD(ctx->opcode)); |
| 705 | } |
| 706 | |
| 707 | /* cmpli */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 708 | static void gen_cmpli(DisasContext *ctx) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 709 | { |
| 710 | #if defined(TARGET_PPC64) |
| 711 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) |
| 712 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 713 | 0, crfD(ctx->opcode)); |
| 714 | else |
| 715 | #endif |
| 716 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
| 717 | 0, crfD(ctx->opcode)); |
| 718 | } |
| 719 | |
| 720 | /* isel (PowerPC 2.03 specification) */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 721 | static void gen_isel(DisasContext *ctx) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 722 | { |
| 723 | int l1, l2; |
| 724 | uint32_t bi = rC(ctx->opcode); |
| 725 | uint32_t mask; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 726 | TCGv_i32 t0; |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 727 | |
| 728 | l1 = gen_new_label(); |
| 729 | l2 = gen_new_label(); |
| 730 | |
| 731 | mask = 1 << (3 - (bi & 0x03)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 732 | t0 = tcg_temp_new_i32(); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 733 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
| 734 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 735 | if (rA(ctx->opcode) == 0) |
| 736 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
| 737 | else |
| 738 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 739 | tcg_gen_br(l2); |
| 740 | gen_set_label(l1); |
| 741 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 742 | gen_set_label(l2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 743 | tcg_temp_free_i32(t0); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 744 | } |
| 745 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 746 | /*** Integer arithmetic ***/ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 747 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 748 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
| 749 | TCGv arg1, TCGv arg2, int sub) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 750 | { |
| 751 | int l1; |
| 752 | TCGv t0; |
| 753 | |
| 754 | l1 = gen_new_label(); |
| 755 | /* Start with XER OV disabled, the most likely case */ |
| 756 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 757 | t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 758 | tcg_gen_xor_tl(t0, arg0, arg1); |
| 759 | #if defined(TARGET_PPC64) |
| 760 | if (!ctx->sf_mode) |
| 761 | tcg_gen_ext32s_tl(t0, t0); |
| 762 | #endif |
| 763 | if (sub) |
| 764 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); |
| 765 | else |
| 766 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); |
| 767 | tcg_gen_xor_tl(t0, arg1, arg2); |
| 768 | #if defined(TARGET_PPC64) |
| 769 | if (!ctx->sf_mode) |
| 770 | tcg_gen_ext32s_tl(t0, t0); |
| 771 | #endif |
| 772 | if (sub) |
| 773 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); |
| 774 | else |
| 775 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); |
| 776 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 777 | gen_set_label(l1); |
| 778 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 779 | } |
| 780 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 781 | static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, |
| 782 | TCGv arg2, int sub) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 783 | { |
| 784 | int l1 = gen_new_label(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 785 | |
| 786 | #if defined(TARGET_PPC64) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 787 | if (!(ctx->sf_mode)) { |
| 788 | TCGv t0, t1; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 789 | t0 = tcg_temp_new(); |
| 790 | t1 = tcg_temp_new(); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 791 | |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 792 | tcg_gen_ext32u_tl(t0, arg1); |
| 793 | tcg_gen_ext32u_tl(t1, arg2); |
| 794 | if (sub) { |
| 795 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); |
aurel32 | bdc4e05 | 2008-11-09 17:27:03 +0000 | [diff] [blame] | 796 | } else { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 797 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
| 798 | } |
aurel32 | a973001 | 2008-11-09 17:27:36 +0000 | [diff] [blame] | 799 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
| 800 | gen_set_label(l1); |
| 801 | tcg_temp_free(t0); |
| 802 | tcg_temp_free(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 803 | } else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 804 | #endif |
aurel32 | a973001 | 2008-11-09 17:27:36 +0000 | [diff] [blame] | 805 | { |
| 806 | if (sub) { |
| 807 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); |
| 808 | } else { |
| 809 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); |
| 810 | } |
| 811 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
| 812 | gen_set_label(l1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 813 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 814 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 815 | |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 816 | /* Common add function */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 817 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 818 | TCGv arg2, int add_ca, int compute_ca, |
| 819 | int compute_ov) |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 820 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 821 | TCGv t0, t1; |
| 822 | |
| 823 | if ((!compute_ca && !compute_ov) || |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 824 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 825 | t0 = ret; |
| 826 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 827 | t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 828 | } |
| 829 | |
| 830 | if (add_ca) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 831 | t1 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 832 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
| 833 | tcg_gen_shri_tl(t1, t1, XER_CA); |
malc | d2e9fd8 | 2009-06-20 05:51:47 +0400 | [diff] [blame] | 834 | } else { |
| 835 | TCGV_UNUSED(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 836 | } |
| 837 | |
| 838 | if (compute_ca && compute_ov) { |
| 839 | /* Start with XER CA and OV disabled, the most likely case */ |
| 840 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
| 841 | } else if (compute_ca) { |
| 842 | /* Start with XER CA disabled, the most likely case */ |
| 843 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
| 844 | } else if (compute_ov) { |
| 845 | /* Start with XER OV disabled, the most likely case */ |
| 846 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 847 | } |
| 848 | |
| 849 | tcg_gen_add_tl(t0, arg1, arg2); |
| 850 | |
| 851 | if (compute_ca) { |
| 852 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); |
| 853 | } |
| 854 | if (add_ca) { |
| 855 | tcg_gen_add_tl(t0, t0, t1); |
| 856 | gen_op_arith_compute_ca(ctx, t0, t1, 0); |
| 857 | tcg_temp_free(t1); |
| 858 | } |
| 859 | if (compute_ov) { |
| 860 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); |
| 861 | } |
| 862 | |
| 863 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 864 | gen_set_Rc0(ctx, t0); |
| 865 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 866 | if (!TCGV_EQUAL(t0, ret)) { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 867 | tcg_gen_mov_tl(ret, t0); |
| 868 | tcg_temp_free(t0); |
| 869 | } |
aurel32 | 39dd32e | 2008-09-05 14:19:43 +0000 | [diff] [blame] | 870 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 871 | /* Add functions with two operands */ |
| 872 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 873 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 874 | { \ |
| 875 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 876 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
| 877 | add_ca, compute_ca, compute_ov); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 878 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 879 | /* Add functions with one operand and one immediate */ |
| 880 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ |
| 881 | add_ca, compute_ca, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 882 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 883 | { \ |
| 884 | TCGv t0 = tcg_const_local_tl(const_val); \ |
| 885 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 886 | cpu_gpr[rA(ctx->opcode)], t0, \ |
| 887 | add_ca, compute_ca, compute_ov); \ |
| 888 | tcg_temp_free(t0); \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 889 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 890 | |
| 891 | /* add add. addo addo. */ |
| 892 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
| 893 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
| 894 | /* addc addc. addco addco. */ |
| 895 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
| 896 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
| 897 | /* adde adde. addeo addeo. */ |
| 898 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
| 899 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 900 | /* addme addme. addmeo addmeo. */ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 901 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
| 902 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
| 903 | /* addze addze. addzeo addzeo.*/ |
| 904 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
| 905 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 906 | /* addi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 907 | static void gen_addi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 908 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 909 | target_long simm = SIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 910 | |
| 911 | if (rA(ctx->opcode) == 0) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 912 | /* li case */ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 913 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 914 | } else { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 915 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 916 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 917 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 918 | /* addic addic.*/ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 919 | static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 920 | int compute_Rc0) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 921 | { |
| 922 | target_long simm = SIMM(ctx->opcode); |
| 923 | |
| 924 | /* Start with XER CA and OV disabled, the most likely case */ |
| 925 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
| 926 | |
| 927 | if (likely(simm != 0)) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 928 | TCGv t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 929 | tcg_gen_addi_tl(t0, arg1, simm); |
| 930 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); |
| 931 | tcg_gen_mov_tl(ret, t0); |
| 932 | tcg_temp_free(t0); |
| 933 | } else { |
| 934 | tcg_gen_mov_tl(ret, arg1); |
| 935 | } |
| 936 | if (compute_Rc0) { |
| 937 | gen_set_Rc0(ctx, ret); |
| 938 | } |
| 939 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 940 | |
| 941 | static void gen_addic(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 942 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 943 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 944 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 945 | |
| 946 | static void gen_addic_(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 947 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 948 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 949 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 950 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 951 | /* addis */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 952 | static void gen_addis(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 953 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 954 | target_long simm = SIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 955 | |
| 956 | if (rA(ctx->opcode) == 0) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 957 | /* lis case */ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 958 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 959 | } else { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 960 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 961 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 962 | } |
| 963 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 964 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 965 | TCGv arg2, int sign, int compute_ov) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 966 | { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 967 | int l1 = gen_new_label(); |
| 968 | int l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 969 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
| 970 | TCGv_i32 t1 = tcg_temp_local_new_i32(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 971 | |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 972 | tcg_gen_trunc_tl_i32(t0, arg1); |
| 973 | tcg_gen_trunc_tl_i32(t1, arg2); |
| 974 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 975 | if (sign) { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 976 | int l3 = gen_new_label(); |
| 977 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); |
| 978 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 979 | gen_set_label(l3); |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 980 | tcg_gen_div_i32(t0, t0, t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 981 | } else { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 982 | tcg_gen_divu_i32(t0, t0, t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 983 | } |
| 984 | if (compute_ov) { |
| 985 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 986 | } |
| 987 | tcg_gen_br(l2); |
| 988 | gen_set_label(l1); |
| 989 | if (sign) { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 990 | tcg_gen_sari_i32(t0, t0, 31); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 991 | } else { |
| 992 | tcg_gen_movi_i32(t0, 0); |
| 993 | } |
| 994 | if (compute_ov) { |
| 995 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 996 | } |
| 997 | gen_set_label(l2); |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 998 | tcg_gen_extu_i32_tl(ret, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 999 | tcg_temp_free_i32(t0); |
| 1000 | tcg_temp_free_i32(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1001 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1002 | gen_set_Rc0(ctx, ret); |
| 1003 | } |
| 1004 | /* Div functions */ |
| 1005 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1006 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1007 | { \ |
| 1008 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 1009 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
| 1010 | sign, compute_ov); \ |
| 1011 | } |
| 1012 | /* divwu divwu. divwuo divwuo. */ |
| 1013 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
| 1014 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
| 1015 | /* divw divw. divwo divwo. */ |
| 1016 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
| 1017 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
| 1018 | #if defined(TARGET_PPC64) |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1019 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 1020 | TCGv arg2, int sign, int compute_ov) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1021 | { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 1022 | int l1 = gen_new_label(); |
| 1023 | int l2 = gen_new_label(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1024 | |
| 1025 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); |
| 1026 | if (sign) { |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 1027 | int l3 = gen_new_label(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1028 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
| 1029 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); |
| 1030 | gen_set_label(l3); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1031 | tcg_gen_div_i64(ret, arg1, arg2); |
| 1032 | } else { |
| 1033 | tcg_gen_divu_i64(ret, arg1, arg2); |
| 1034 | } |
| 1035 | if (compute_ov) { |
| 1036 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 1037 | } |
| 1038 | tcg_gen_br(l2); |
| 1039 | gen_set_label(l1); |
| 1040 | if (sign) { |
| 1041 | tcg_gen_sari_i64(ret, arg1, 63); |
| 1042 | } else { |
| 1043 | tcg_gen_movi_i64(ret, 0); |
| 1044 | } |
| 1045 | if (compute_ov) { |
| 1046 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 1047 | } |
| 1048 | gen_set_label(l2); |
| 1049 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1050 | gen_set_Rc0(ctx, ret); |
| 1051 | } |
| 1052 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1053 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1054 | { \ |
aurel32 | 2ef1b12 | 2008-11-09 17:27:19 +0000 | [diff] [blame] | 1055 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 1056 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
| 1057 | sign, compute_ov); \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1058 | } |
| 1059 | /* divwu divwu. divwuo divwuo. */ |
| 1060 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
| 1061 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
| 1062 | /* divw divw. divwo divwo. */ |
| 1063 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
| 1064 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
| 1065 | #endif |
| 1066 | |
| 1067 | /* mulhw mulhw. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1068 | static void gen_mulhw(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1069 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1070 | TCGv_i64 t0, t1; |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1071 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1072 | t0 = tcg_temp_new_i64(); |
| 1073 | t1 = tcg_temp_new_i64(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1074 | #if defined(TARGET_PPC64) |
| 1075 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1076 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1077 | tcg_gen_mul_i64(t0, t0, t1); |
| 1078 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); |
| 1079 | #else |
| 1080 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1081 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1082 | tcg_gen_mul_i64(t0, t0, t1); |
| 1083 | tcg_gen_shri_i64(t0, t0, 32); |
| 1084 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 1085 | #endif |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1086 | tcg_temp_free_i64(t0); |
| 1087 | tcg_temp_free_i64(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1088 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1089 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
| 1090 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1091 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1092 | /* mulhwu mulhwu. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1093 | static void gen_mulhwu(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1094 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1095 | TCGv_i64 t0, t1; |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1096 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1097 | t0 = tcg_temp_new_i64(); |
| 1098 | t1 = tcg_temp_new_i64(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1099 | #if defined(TARGET_PPC64) |
| 1100 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1101 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1102 | tcg_gen_mul_i64(t0, t0, t1); |
| 1103 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); |
| 1104 | #else |
| 1105 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1106 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1107 | tcg_gen_mul_i64(t0, t0, t1); |
| 1108 | tcg_gen_shri_i64(t0, t0, 32); |
| 1109 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 1110 | #endif |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1111 | tcg_temp_free_i64(t0); |
| 1112 | tcg_temp_free_i64(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1113 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1114 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
| 1115 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1116 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1117 | /* mullw mullw. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1118 | static void gen_mullw(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1119 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1120 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
| 1121 | cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 1e4c090 | 2008-11-09 17:27:11 +0000 | [diff] [blame] | 1122 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1123 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1124 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
| 1125 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1126 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1127 | /* mullwo mullwo. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1128 | static void gen_mullwo(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1129 | { |
| 1130 | int l1; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1131 | TCGv_i64 t0, t1; |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1132 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1133 | t0 = tcg_temp_new_i64(); |
| 1134 | t1 = tcg_temp_new_i64(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1135 | l1 = gen_new_label(); |
| 1136 | /* Start with XER OV disabled, the most likely case */ |
| 1137 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 1138 | #if defined(TARGET_PPC64) |
| 1139 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1140 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1141 | #else |
| 1142 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 1143 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 1144 | #endif |
| 1145 | tcg_gen_mul_i64(t0, t0, t1); |
| 1146 | #if defined(TARGET_PPC64) |
| 1147 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); |
| 1148 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); |
| 1149 | #else |
| 1150 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 1151 | tcg_gen_ext32s_i64(t1, t0); |
| 1152 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
| 1153 | #endif |
| 1154 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 1155 | gen_set_label(l1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1156 | tcg_temp_free_i64(t0); |
| 1157 | tcg_temp_free_i64(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1158 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1159 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1160 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1161 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1162 | /* mulli */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1163 | static void gen_mulli(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1164 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1165 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
| 1166 | SIMM(ctx->opcode)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1167 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1168 | #if defined(TARGET_PPC64) |
| 1169 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1170 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1171 | { \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1172 | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1173 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
| 1174 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
| 1175 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
| 1176 | } |
| 1177 | /* mulhd mulhd. */ |
| 1178 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00); |
| 1179 | /* mulhdu mulhdu. */ |
| 1180 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1181 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1182 | /* mulld mulld. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1183 | static void gen_mulld(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1184 | { |
| 1185 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
| 1186 | cpu_gpr[rB(ctx->opcode)]); |
| 1187 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1188 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
| 1189 | } |
| 1190 | /* mulldo mulldo. */ |
| 1191 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17); |
| 1192 | #endif |
| 1193 | |
| 1194 | /* neg neg. nego nego. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1195 | static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 1196 | int ov_check) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1197 | { |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1198 | int l1 = gen_new_label(); |
| 1199 | int l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1200 | TCGv t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1201 | #if defined(TARGET_PPC64) |
| 1202 | if (ctx->sf_mode) { |
aurel32 | 741a744 | 2008-11-09 18:27:28 +0000 | [diff] [blame] | 1203 | tcg_gen_mov_tl(t0, arg1); |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1204 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
| 1205 | } else |
| 1206 | #endif |
| 1207 | { |
| 1208 | tcg_gen_ext32s_tl(t0, arg1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1209 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
| 1210 | } |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1211 | tcg_gen_neg_tl(ret, arg1); |
| 1212 | if (ov_check) { |
| 1213 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 1214 | } |
| 1215 | tcg_gen_br(l2); |
| 1216 | gen_set_label(l1); |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1217 | tcg_gen_mov_tl(ret, t0); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1218 | if (ov_check) { |
| 1219 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 1220 | } |
| 1221 | gen_set_label(l2); |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1222 | tcg_temp_free(t0); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1223 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1224 | gen_set_Rc0(ctx, ret); |
| 1225 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1226 | |
| 1227 | static void gen_neg(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1228 | { |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1229 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1230 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1231 | |
| 1232 | static void gen_nego(DisasContext *ctx) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1233 | { |
aurel32 | ec6469a | 2008-11-09 17:27:27 +0000 | [diff] [blame] | 1234 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1235 | } |
| 1236 | |
| 1237 | /* Common subf function */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1238 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 1239 | TCGv arg2, int add_ca, int compute_ca, |
| 1240 | int compute_ov) |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1241 | { |
| 1242 | TCGv t0, t1; |
| 1243 | |
| 1244 | if ((!compute_ca && !compute_ov) || |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1245 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1246 | t0 = ret; |
| 1247 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1248 | t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1249 | } |
| 1250 | |
| 1251 | if (add_ca) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1252 | t1 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1253 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
| 1254 | tcg_gen_shri_tl(t1, t1, XER_CA); |
malc | d2e9fd8 | 2009-06-20 05:51:47 +0400 | [diff] [blame] | 1255 | } else { |
| 1256 | TCGV_UNUSED(t1); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1257 | } |
| 1258 | |
| 1259 | if (compute_ca && compute_ov) { |
| 1260 | /* Start with XER CA and OV disabled, the most likely case */ |
| 1261 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); |
| 1262 | } else if (compute_ca) { |
| 1263 | /* Start with XER CA disabled, the most likely case */ |
| 1264 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
| 1265 | } else if (compute_ov) { |
| 1266 | /* Start with XER OV disabled, the most likely case */ |
| 1267 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 1268 | } |
| 1269 | |
| 1270 | if (add_ca) { |
| 1271 | tcg_gen_not_tl(t0, arg1); |
| 1272 | tcg_gen_add_tl(t0, t0, arg2); |
| 1273 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); |
| 1274 | tcg_gen_add_tl(t0, t0, t1); |
| 1275 | gen_op_arith_compute_ca(ctx, t0, t1, 0); |
| 1276 | tcg_temp_free(t1); |
| 1277 | } else { |
| 1278 | tcg_gen_sub_tl(t0, arg2, arg1); |
| 1279 | if (compute_ca) { |
| 1280 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); |
| 1281 | } |
| 1282 | } |
| 1283 | if (compute_ov) { |
| 1284 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); |
| 1285 | } |
| 1286 | |
| 1287 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1288 | gen_set_Rc0(ctx, t0); |
| 1289 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1290 | if (!TCGV_EQUAL(t0, ret)) { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1291 | tcg_gen_mov_tl(ret, t0); |
| 1292 | tcg_temp_free(t0); |
| 1293 | } |
| 1294 | } |
| 1295 | /* Sub functions with Two operands functions */ |
| 1296 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1297 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1298 | { \ |
| 1299 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 1300 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
| 1301 | add_ca, compute_ca, compute_ov); \ |
| 1302 | } |
| 1303 | /* Sub functions with one operand and one immediate */ |
| 1304 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ |
| 1305 | add_ca, compute_ca, compute_ov) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1306 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1307 | { \ |
| 1308 | TCGv t0 = tcg_const_local_tl(const_val); \ |
| 1309 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
| 1310 | cpu_gpr[rA(ctx->opcode)], t0, \ |
| 1311 | add_ca, compute_ca, compute_ov); \ |
| 1312 | tcg_temp_free(t0); \ |
| 1313 | } |
| 1314 | /* subf subf. subfo subfo. */ |
| 1315 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
| 1316 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
| 1317 | /* subfc subfc. subfco subfco. */ |
| 1318 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
| 1319 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
| 1320 | /* subfe subfe. subfeo subfo. */ |
| 1321 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
| 1322 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
| 1323 | /* subfme subfme. subfmeo subfmeo. */ |
| 1324 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
| 1325 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
| 1326 | /* subfze subfze. subfzeo subfzeo.*/ |
| 1327 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
| 1328 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1329 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1330 | /* subfic */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1331 | static void gen_subfic(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1332 | { |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1333 | /* Start with XER CA and OV disabled, the most likely case */ |
| 1334 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1335 | TCGv t0 = tcg_temp_local_new(); |
aurel32 | 7463740 | 2008-11-01 00:54:12 +0000 | [diff] [blame] | 1336 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
| 1337 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); |
| 1338 | gen_op_arith_compute_ca(ctx, t0, t1, 1); |
| 1339 | tcg_temp_free(t1); |
| 1340 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 1341 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1342 | } |
| 1343 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1344 | /*** Integer logical ***/ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1345 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1346 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1347 | { \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1348 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
| 1349 | cpu_gpr[rB(ctx->opcode)]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1350 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1351 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1352 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1353 | |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1354 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1355 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1356 | { \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1357 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1358 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1359 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1360 | } |
| 1361 | |
| 1362 | /* and & and. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1363 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1364 | /* andc & andc. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1365 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1366 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1367 | /* andi. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1368 | static void gen_andi_(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1369 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1370 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
| 1371 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1372 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1373 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1374 | /* andis. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1375 | static void gen_andis_(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1376 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1377 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
| 1378 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1379 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1380 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1381 | /* cntlzw */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1382 | static void gen_cntlzw(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1383 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1384 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1385 | if (unlikely(Rc(ctx->opcode) != 0)) |
pbrook | 2e31f5d | 2008-10-24 12:03:16 +0000 | [diff] [blame] | 1386 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1387 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1388 | /* eqv & eqv. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1389 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1390 | /* extsb & extsb. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1391 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1392 | /* extsh & extsh. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1393 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1394 | /* nand & nand. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1395 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1396 | /* nor & nor. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1397 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1398 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1399 | /* or & or. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1400 | static void gen_or(DisasContext *ctx) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1401 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1402 | int rs, ra, rb; |
| 1403 | |
| 1404 | rs = rS(ctx->opcode); |
| 1405 | ra = rA(ctx->opcode); |
| 1406 | rb = rB(ctx->opcode); |
| 1407 | /* Optimisation for mr. ri case */ |
| 1408 | if (rs != ra || rs != rb) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1409 | if (rs != rb) |
| 1410 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
| 1411 | else |
| 1412 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1413 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1414 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1415 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1416 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1417 | #if defined(TARGET_PPC64) |
| 1418 | } else { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1419 | int prio = 0; |
| 1420 | |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1421 | switch (rs) { |
| 1422 | case 1: |
| 1423 | /* Set process priority to low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1424 | prio = 2; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1425 | break; |
| 1426 | case 6: |
| 1427 | /* Set process priority to medium-low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1428 | prio = 3; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1429 | break; |
| 1430 | case 2: |
| 1431 | /* Set process priority to normal */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1432 | prio = 4; |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1433 | break; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1434 | #if !defined(CONFIG_USER_ONLY) |
| 1435 | case 31: |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 1436 | if (ctx->mem_idx > 0) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1437 | /* Set process priority to very low */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1438 | prio = 1; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1439 | } |
| 1440 | break; |
| 1441 | case 5: |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 1442 | if (ctx->mem_idx > 0) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1443 | /* Set process priority to medium-hight */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1444 | prio = 5; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1445 | } |
| 1446 | break; |
| 1447 | case 3: |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 1448 | if (ctx->mem_idx > 0) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1449 | /* Set process priority to high */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1450 | prio = 6; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1451 | } |
| 1452 | break; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1453 | case 7: |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 1454 | if (ctx->mem_idx > 1) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1455 | /* Set process priority to very high */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1456 | prio = 7; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 1457 | } |
| 1458 | break; |
| 1459 | #endif |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1460 | default: |
| 1461 | /* nop */ |
| 1462 | break; |
| 1463 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1464 | if (prio) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1465 | TCGv t0 = tcg_temp_new(); |
aurel32 | 54cdcae | 2008-12-05 07:21:31 +0000 | [diff] [blame] | 1466 | gen_load_spr(t0, SPR_PPR); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 1467 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
| 1468 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); |
aurel32 | 54cdcae | 2008-12-05 07:21:31 +0000 | [diff] [blame] | 1469 | gen_store_spr(SPR_PPR, t0); |
aurel32 | ea36369 | 2008-10-27 22:50:39 +0000 | [diff] [blame] | 1470 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1471 | } |
j_mayer | c80f84e | 2007-09-30 01:18:26 +0000 | [diff] [blame] | 1472 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1473 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1474 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1475 | /* orc & orc. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1476 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1477 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1478 | /* xor & xor. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1479 | static void gen_xor(DisasContext *ctx) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1480 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1481 | /* Optimisation for "set to zero" case */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1482 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
aurel32 | 312179c | 2008-10-27 22:50:31 +0000 | [diff] [blame] | 1483 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1484 | else |
| 1485 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1486 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1487 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1488 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1489 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1490 | /* ori */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1491 | static void gen_ori(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1492 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1493 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1494 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1495 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1496 | /* NOP */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1497 | /* XXX: should handle special NOPs for POWER series */ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1498 | return; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1499 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1500 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1501 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1502 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1503 | /* oris */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1504 | static void gen_oris(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1505 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1506 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1507 | |
| 1508 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1509 | /* NOP */ |
| 1510 | return; |
| 1511 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1512 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1513 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1514 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1515 | /* xori */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1516 | static void gen_xori(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1517 | { |
| 1518 | target_ulong uimm = UIMM(ctx->opcode); |
| 1519 | |
| 1520 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1521 | /* NOP */ |
| 1522 | return; |
| 1523 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1524 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1525 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1526 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1527 | /* xoris */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1528 | static void gen_xoris(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1529 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1530 | target_ulong uimm = UIMM(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1531 | |
| 1532 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
| 1533 | /* NOP */ |
| 1534 | return; |
| 1535 | } |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1536 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1537 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1538 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1539 | /* popcntb : PowerPC 2.03 specification */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1540 | static void gen_popcntb(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1541 | { |
David Gibson | eaabeef | 2011-04-01 15:15:13 +1100 | [diff] [blame] | 1542 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1543 | } |
| 1544 | |
David Gibson | eaabeef | 2011-04-01 15:15:13 +1100 | [diff] [blame] | 1545 | static void gen_popcntw(DisasContext *ctx) |
| 1546 | { |
| 1547 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1548 | } |
| 1549 | |
| 1550 | #if defined(TARGET_PPC64) |
| 1551 | /* popcntd: PowerPC 2.06 specification */ |
| 1552 | static void gen_popcntd(DisasContext *ctx) |
| 1553 | { |
| 1554 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1555 | } |
| 1556 | #endif |
| 1557 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1558 | #if defined(TARGET_PPC64) |
| 1559 | /* extsw & extsw. */ |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1560 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1561 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1562 | /* cntlzd */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1563 | static void gen_cntlzd(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1564 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1565 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1566 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1567 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1568 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1569 | #endif |
| 1570 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1571 | /*** Integer rotate ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1572 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1573 | /* rlwimi & rlwimi. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1574 | static void gen_rlwimi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1575 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1576 | uint32_t mb, me, sh; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1577 | |
| 1578 | mb = MB(ctx->opcode); |
| 1579 | me = ME(ctx->opcode); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1580 | sh = SH(ctx->opcode); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1581 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
| 1582 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1583 | } else { |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1584 | target_ulong mask; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1585 | TCGv t1; |
| 1586 | TCGv t0 = tcg_temp_new(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1587 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1588 | TCGv_i32 t2 = tcg_temp_new_i32(); |
| 1589 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); |
| 1590 | tcg_gen_rotli_i32(t2, t2, sh); |
| 1591 | tcg_gen_extu_i32_i64(t0, t2); |
| 1592 | tcg_temp_free_i32(t2); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1593 | #else |
| 1594 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 1595 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1596 | #if defined(TARGET_PPC64) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1597 | mb += 32; |
| 1598 | me += 32; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1599 | #endif |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1600 | mask = MASK(mb, me); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1601 | t1 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1602 | tcg_gen_andi_tl(t0, t0, mask); |
| 1603 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
| 1604 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1605 | tcg_temp_free(t0); |
| 1606 | tcg_temp_free(t1); |
| 1607 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1608 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1609 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1610 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1611 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1612 | /* rlwinm & rlwinm. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1613 | static void gen_rlwinm(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1614 | { |
| 1615 | uint32_t mb, me, sh; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 1616 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1617 | sh = SH(ctx->opcode); |
| 1618 | mb = MB(ctx->opcode); |
| 1619 | me = ME(ctx->opcode); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1620 | |
| 1621 | if (likely(mb == 0 && me == (31 - sh))) { |
| 1622 | if (likely(sh == 0)) { |
| 1623 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1624 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1625 | TCGv t0 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1626 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1627 | tcg_gen_shli_tl(t0, t0, sh); |
| 1628 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1629 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1630 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1631 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1632 | TCGv t0 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1633 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1634 | tcg_gen_shri_tl(t0, t0, mb); |
| 1635 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1636 | tcg_temp_free(t0); |
| 1637 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1638 | TCGv t0 = tcg_temp_new(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1639 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1640 | TCGv_i32 t1 = tcg_temp_new_i32(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1641 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
| 1642 | tcg_gen_rotli_i32(t1, t1, sh); |
| 1643 | tcg_gen_extu_i32_i64(t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1644 | tcg_temp_free_i32(t1); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1645 | #else |
| 1646 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 1647 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1648 | #if defined(TARGET_PPC64) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1649 | mb += 32; |
| 1650 | me += 32; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1651 | #endif |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1652 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
| 1653 | tcg_temp_free(t0); |
| 1654 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1655 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1656 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1657 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1658 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1659 | /* rlwnm & rlwnm. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1660 | static void gen_rlwnm(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1661 | { |
| 1662 | uint32_t mb, me; |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1663 | TCGv t0; |
| 1664 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1665 | TCGv_i32 t1, t2; |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1666 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1667 | |
| 1668 | mb = MB(ctx->opcode); |
| 1669 | me = ME(ctx->opcode); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1670 | t0 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1671 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1672 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1673 | t1 = tcg_temp_new_i32(); |
| 1674 | t2 = tcg_temp_new_i32(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1675 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
| 1676 | tcg_gen_trunc_i64_i32(t2, t0); |
| 1677 | tcg_gen_rotl_i32(t1, t1, t2); |
| 1678 | tcg_gen_extu_i32_i64(t0, t1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1679 | tcg_temp_free_i32(t1); |
| 1680 | tcg_temp_free_i32(t2); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1681 | #else |
| 1682 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 1683 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1684 | if (unlikely(mb != 0 || me != 31)) { |
| 1685 | #if defined(TARGET_PPC64) |
| 1686 | mb += 32; |
| 1687 | me += 32; |
| 1688 | #endif |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1689 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1690 | } else { |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1691 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1692 | } |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1693 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1694 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1695 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1696 | } |
| 1697 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1698 | #if defined(TARGET_PPC64) |
| 1699 | #define GEN_PPC64_R2(name, opc1, opc2) \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1700 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1701 | { \ |
| 1702 | gen_##name(ctx, 0); \ |
| 1703 | } \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1704 | \ |
| 1705 | static void glue(gen_, name##1)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1706 | { \ |
| 1707 | gen_##name(ctx, 1); \ |
| 1708 | } |
| 1709 | #define GEN_PPC64_R4(name, opc1, opc2) \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1710 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1711 | { \ |
| 1712 | gen_##name(ctx, 0, 0); \ |
| 1713 | } \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1714 | \ |
| 1715 | static void glue(gen_, name##1)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1716 | { \ |
| 1717 | gen_##name(ctx, 0, 1); \ |
| 1718 | } \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1719 | \ |
| 1720 | static void glue(gen_, name##2)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1721 | { \ |
| 1722 | gen_##name(ctx, 1, 0); \ |
| 1723 | } \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1724 | \ |
| 1725 | static void glue(gen_, name##3)(DisasContext *ctx) \ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1726 | { \ |
| 1727 | gen_##name(ctx, 1, 1); \ |
| 1728 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1729 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1730 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
| 1731 | uint32_t sh) |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1732 | { |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1733 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
| 1734 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
| 1735 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
| 1736 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
| 1737 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1738 | TCGv t0 = tcg_temp_new(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1739 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1740 | if (likely(mb == 0 && me == 63)) { |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1741 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1742 | } else { |
| 1743 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1744 | } |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1745 | tcg_temp_free(t0); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1746 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1747 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1748 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1749 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1750 | /* rldicl - rldicl. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1751 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1752 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1753 | uint32_t sh, mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1754 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1755 | sh = SH(ctx->opcode) | (shn << 5); |
| 1756 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1757 | gen_rldinm(ctx, mb, 63, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1758 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1759 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1760 | /* rldicr - rldicr. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1761 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1762 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1763 | uint32_t sh, me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1764 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1765 | sh = SH(ctx->opcode) | (shn << 5); |
| 1766 | me = MB(ctx->opcode) | (men << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1767 | gen_rldinm(ctx, 0, me, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1768 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1769 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1770 | /* rldic - rldic. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1771 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1772 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1773 | uint32_t sh, mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1774 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1775 | sh = SH(ctx->opcode) | (shn << 5); |
| 1776 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1777 | gen_rldinm(ctx, mb, 63 - sh, sh); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1778 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1779 | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
| 1780 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1781 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1782 | { |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1783 | TCGv t0; |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1784 | |
| 1785 | mb = MB(ctx->opcode); |
| 1786 | me = ME(ctx->opcode); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1787 | t0 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1788 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1789 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1790 | if (unlikely(mb != 0 || me != 63)) { |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1791 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
| 1792 | } else { |
| 1793 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 1794 | } |
| 1795 | tcg_temp_free(t0); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1796 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1797 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1798 | } |
| 1799 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1800 | /* rldcl - rldcl. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1801 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1802 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1803 | uint32_t mb; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1804 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1805 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1806 | gen_rldnm(ctx, mb, 63); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1807 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1808 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1809 | /* rldcr - rldcr. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1810 | static inline void gen_rldcr(DisasContext *ctx, int men) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1811 | { |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1812 | uint32_t me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1813 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1814 | me = MB(ctx->opcode) | (men << 5); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1815 | gen_rldnm(ctx, 0, me); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1816 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1817 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1818 | /* rldimi - rldimi. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1819 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1820 | { |
j_mayer | 271a916 | 2007-11-14 05:26:46 +0000 | [diff] [blame] | 1821 | uint32_t sh, mb, me; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1822 | |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 1823 | sh = SH(ctx->opcode) | (shn << 5); |
| 1824 | mb = MB(ctx->opcode) | (mbn << 5); |
j_mayer | 271a916 | 2007-11-14 05:26:46 +0000 | [diff] [blame] | 1825 | me = 63 - sh; |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1826 | if (unlikely(sh == 0 && mb == 0)) { |
| 1827 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 1828 | } else { |
| 1829 | TCGv t0, t1; |
| 1830 | target_ulong mask; |
| 1831 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1832 | t0 = tcg_temp_new(); |
aurel32 | 54843a5 | 2008-11-03 07:08:44 +0000 | [diff] [blame] | 1833 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1834 | t1 = tcg_temp_new(); |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1835 | mask = MASK(mb, me); |
| 1836 | tcg_gen_andi_tl(t0, t0, mask); |
| 1837 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
| 1838 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1839 | tcg_temp_free(t0); |
| 1840 | tcg_temp_free(t1); |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1841 | } |
j_mayer | 51789c4 | 2007-03-22 22:41:50 +0000 | [diff] [blame] | 1842 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | d03ef51 | 2008-10-27 22:50:22 +0000 | [diff] [blame] | 1843 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1844 | } |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1845 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1846 | #endif |
| 1847 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1848 | /*** Integer shift ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1849 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1850 | /* slw & slw. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1851 | static void gen_slw(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1852 | { |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1853 | TCGv t0, t1; |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1854 | |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1855 | t0 = tcg_temp_new(); |
| 1856 | /* AND rS with a mask that is 0 when rB >= 0x20 */ |
| 1857 | #if defined(TARGET_PPC64) |
| 1858 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); |
| 1859 | tcg_gen_sari_tl(t0, t0, 0x3f); |
| 1860 | #else |
| 1861 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); |
| 1862 | tcg_gen_sari_tl(t0, t0, 0x1f); |
| 1863 | #endif |
| 1864 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 1865 | t1 = tcg_temp_new(); |
| 1866 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
| 1867 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1868 | tcg_temp_free(t1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1869 | tcg_temp_free(t0); |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1870 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1871 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1872 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1873 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1874 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1875 | /* sraw & sraw. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1876 | static void gen_sraw(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1877 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1878 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
| 1879 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1880 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1881 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1882 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1883 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1884 | /* srawi & srawi. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1885 | static void gen_srawi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1886 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1887 | int sh = SH(ctx->opcode); |
| 1888 | if (sh != 0) { |
| 1889 | int l1, l2; |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1890 | TCGv t0; |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1891 | l1 = gen_new_label(); |
| 1892 | l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1893 | t0 = tcg_temp_local_new(); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1894 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1895 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); |
| 1896 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
| 1897 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1898 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1899 | tcg_gen_br(l2); |
| 1900 | gen_set_label(l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1901 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1902 | gen_set_label(l2); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1903 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
| 1904 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); |
| 1905 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1906 | } else { |
| 1907 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1908 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1909 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1910 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1911 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1912 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1913 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1914 | /* srw & srw. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1915 | static void gen_srw(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1916 | { |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1917 | TCGv t0, t1; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1918 | |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1919 | t0 = tcg_temp_new(); |
| 1920 | /* AND rS with a mask that is 0 when rB >= 0x20 */ |
| 1921 | #if defined(TARGET_PPC64) |
| 1922 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); |
| 1923 | tcg_gen_sari_tl(t0, t0, 0x3f); |
| 1924 | #else |
| 1925 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); |
| 1926 | tcg_gen_sari_tl(t0, t0, 0x1f); |
| 1927 | #endif |
| 1928 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 1929 | tcg_gen_ext32u_tl(t0, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1930 | t1 = tcg_temp_new(); |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1931 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
| 1932 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1933 | tcg_temp_free(t1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1934 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1935 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1936 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1937 | } |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1938 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1939 | #if defined(TARGET_PPC64) |
| 1940 | /* sld & sld. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1941 | static void gen_sld(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1942 | { |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1943 | TCGv t0, t1; |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1944 | |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 1945 | t0 = tcg_temp_new(); |
| 1946 | /* AND rS with a mask that is 0 when rB >= 0x40 */ |
| 1947 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); |
| 1948 | tcg_gen_sari_tl(t0, t0, 0x3f); |
| 1949 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 1950 | t1 = tcg_temp_new(); |
| 1951 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); |
| 1952 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 1953 | tcg_temp_free(t1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1954 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1955 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1956 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1957 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1958 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 1959 | /* srad & srad. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 1960 | static void gen_srad(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1961 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1962 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
| 1963 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1964 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 1965 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 1966 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1967 | /* sradi & sradi. */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1968 | static inline void gen_sradi(DisasContext *ctx, int n) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1969 | { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1970 | int sh = SH(ctx->opcode) + (n << 5); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1971 | if (sh != 0) { |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1972 | int l1, l2; |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1973 | TCGv t0; |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1974 | l1 = gen_new_label(); |
| 1975 | l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1976 | t0 = tcg_temp_local_new(); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1977 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 1978 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
| 1979 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1980 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1981 | tcg_gen_br(l2); |
| 1982 | gen_set_label(l1); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1983 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1984 | gen_set_label(l2); |
aurel32 | a973001 | 2008-11-09 17:27:36 +0000 | [diff] [blame] | 1985 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1986 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
| 1987 | } else { |
| 1988 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 1989 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1990 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1991 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 1992 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1993 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1994 | |
| 1995 | static void gen_sradi0(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1996 | { |
| 1997 | gen_sradi(ctx, 0); |
| 1998 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 1999 | |
| 2000 | static void gen_sradi1(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2001 | { |
| 2002 | gen_sradi(ctx, 1); |
| 2003 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2004 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2005 | /* srd & srd. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2006 | static void gen_srd(DisasContext *ctx) |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 2007 | { |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 2008 | TCGv t0, t1; |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 2009 | |
Aurelien Jarno | 7fd6bf7 | 2009-09-18 16:56:30 +0200 | [diff] [blame] | 2010 | t0 = tcg_temp_new(); |
| 2011 | /* AND rS with a mask that is 0 when rB >= 0x40 */ |
| 2012 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); |
| 2013 | tcg_gen_sari_tl(t0, t0, 0x3f); |
| 2014 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 2015 | t1 = tcg_temp_new(); |
| 2016 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); |
| 2017 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 2018 | tcg_temp_free(t1); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 2019 | tcg_temp_free(t0); |
aurel32 | 26d6736 | 2008-10-21 11:31:27 +0000 | [diff] [blame] | 2020 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 2021 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
| 2022 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2023 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2024 | |
| 2025 | /*** Floating-Point arithmetic ***/ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2026 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2027 | static void gen_f##name(DisasContext *ctx) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2028 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2029 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2030 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2031 | return; \ |
| 2032 | } \ |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2033 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
| 2034 | gen_update_nip(ctx, ctx->nip - 4); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2035 | gen_reset_fpstatus(); \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2036 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
| 2037 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2038 | if (isfloat) { \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2039 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2040 | } \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2041 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
| 2042 | Rc(ctx->opcode) != 0); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2043 | } |
| 2044 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2045 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
| 2046 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
| 2047 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2048 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2049 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2050 | static void gen_f##name(DisasContext *ctx) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2051 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2052 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2053 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2054 | return; \ |
| 2055 | } \ |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2056 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
| 2057 | gen_update_nip(ctx, ctx->nip - 4); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2058 | gen_reset_fpstatus(); \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2059 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
| 2060 | cpu_fpr[rB(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2061 | if (isfloat) { \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2062 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2063 | } \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2064 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
| 2065 | set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2066 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2067 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
| 2068 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
| 2069 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2070 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2071 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2072 | static void gen_f##name(DisasContext *ctx) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2073 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2074 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2075 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2076 | return; \ |
| 2077 | } \ |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2078 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
| 2079 | gen_update_nip(ctx, ctx->nip - 4); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2080 | gen_reset_fpstatus(); \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2081 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
| 2082 | cpu_fpr[rC(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2083 | if (isfloat) { \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2084 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2085 | } \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2086 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
| 2087 | set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2088 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2089 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
| 2090 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
| 2091 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2092 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2093 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2094 | static void gen_f##name(DisasContext *ctx) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2095 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2096 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2097 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2098 | return; \ |
| 2099 | } \ |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2100 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
| 2101 | gen_update_nip(ctx, ctx->nip - 4); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2102 | gen_reset_fpstatus(); \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2103 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
| 2104 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
| 2105 | set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2106 | } |
| 2107 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2108 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2109 | static void gen_f##name(DisasContext *ctx) \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2110 | { \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2111 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2112 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2113 | return; \ |
| 2114 | } \ |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2115 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
| 2116 | gen_update_nip(ctx, ctx->nip - 4); \ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2117 | gen_reset_fpstatus(); \ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2118 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
| 2119 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
| 2120 | set_fprf, Rc(ctx->opcode) != 0); \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2121 | } |
| 2122 | |
| 2123 | /* fadd - fadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2124 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2125 | /* fdiv - fdivs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2126 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2127 | /* fmul - fmuls */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2128 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2129 | |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2130 | /* fre */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2131 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2132 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2133 | /* fres */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2134 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2135 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2136 | /* frsqrte */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2137 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
| 2138 | |
| 2139 | /* frsqrtes */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2140 | static void gen_frsqrtes(DisasContext *ctx) |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2141 | { |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2142 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2143 | gen_exception(ctx, POWERPC_EXCP_FPU); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2144 | return; |
| 2145 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2146 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2147 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2148 | gen_reset_fpstatus(); |
| 2149 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
| 2150 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
| 2151 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2152 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2153 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 2154 | /* fsel */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2155 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2156 | /* fsub - fsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2157 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2158 | /* Optional: */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2159 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2160 | /* fsqrt */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2161 | static void gen_fsqrt(DisasContext *ctx) |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2162 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2163 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2164 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2165 | return; |
| 2166 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2167 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2168 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2169 | gen_reset_fpstatus(); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2170 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
| 2171 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
bellard | c7d344a | 2005-04-23 18:05:46 +0000 | [diff] [blame] | 2172 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2173 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2174 | static void gen_fsqrts(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2175 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2176 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2177 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2178 | return; |
| 2179 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2180 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2181 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2182 | gen_reset_fpstatus(); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2183 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
| 2184 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); |
| 2185 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2186 | } |
| 2187 | |
| 2188 | /*** Floating-Point multiply-and-add ***/ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2189 | /* fmadd - fmadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2190 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2191 | /* fmsub - fmsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2192 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2193 | /* fnmadd - fnmadds */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2194 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 2195 | /* fnmsub - fnmsubs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2196 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2197 | |
| 2198 | /*** Floating-Point round & convert ***/ |
| 2199 | /* fctiw */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2200 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2201 | /* fctiwz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2202 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2203 | /* frsp */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2204 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2205 | #if defined(TARGET_PPC64) |
| 2206 | /* fcfid */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2207 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2208 | /* fctid */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2209 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2210 | /* fctidz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2211 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 2212 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2213 | |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2214 | /* frin */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2215 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2216 | /* friz */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2217 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2218 | /* frip */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2219 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2220 | /* frim */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2221 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
j_mayer | d7e4b87 | 2007-09-30 01:11:48 +0000 | [diff] [blame] | 2222 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2223 | /*** Floating-Point compare ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2224 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2225 | /* fcmpo */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2226 | static void gen_fcmpo(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2227 | { |
aurel32 | 330c483 | 2008-12-15 17:13:31 +0000 | [diff] [blame] | 2228 | TCGv_i32 crf; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2229 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2230 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2231 | return; |
| 2232 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2233 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2234 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2235 | gen_reset_fpstatus(); |
aurel32 | 9a81937 | 2008-12-14 19:34:09 +0000 | [diff] [blame] | 2236 | crf = tcg_const_i32(crfD(ctx->opcode)); |
| 2237 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
aurel32 | 330c483 | 2008-12-15 17:13:31 +0000 | [diff] [blame] | 2238 | tcg_temp_free_i32(crf); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2239 | gen_helper_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2240 | } |
| 2241 | |
| 2242 | /* fcmpu */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2243 | static void gen_fcmpu(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2244 | { |
aurel32 | 330c483 | 2008-12-15 17:13:31 +0000 | [diff] [blame] | 2245 | TCGv_i32 crf; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2246 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2247 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2248 | return; |
| 2249 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2250 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2251 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2252 | gen_reset_fpstatus(); |
aurel32 | 9a81937 | 2008-12-14 19:34:09 +0000 | [diff] [blame] | 2253 | crf = tcg_const_i32(crfD(ctx->opcode)); |
| 2254 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); |
aurel32 | 330c483 | 2008-12-15 17:13:31 +0000 | [diff] [blame] | 2255 | tcg_temp_free_i32(crf); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2256 | gen_helper_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2257 | } |
| 2258 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2259 | /*** Floating-point move ***/ |
| 2260 | /* fabs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2261 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
| 2262 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2263 | |
| 2264 | /* fmr - fmr. */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2265 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2266 | static void gen_fmr(DisasContext *ctx) |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2267 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2268 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2269 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2270 | return; |
| 2271 | } |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2272 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
| 2273 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2274 | } |
| 2275 | |
| 2276 | /* fnabs */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2277 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
| 2278 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2279 | /* fneg */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2280 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
| 2281 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2282 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2283 | /*** Floating-Point status & ctrl register ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2284 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2285 | /* mcrfs */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2286 | static void gen_mcrfs(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2287 | { |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2288 | int bfa; |
| 2289 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2290 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2291 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2292 | return; |
| 2293 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2294 | bfa = 4 * (7 - crfS(ctx->opcode)); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2295 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
| 2296 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2297 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2298 | } |
| 2299 | |
| 2300 | /* mffs */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2301 | static void gen_mffs(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2302 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2303 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2304 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2305 | return; |
| 2306 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2307 | gen_reset_fpstatus(); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2308 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
| 2309 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2310 | } |
| 2311 | |
| 2312 | /* mtfsb0 */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2313 | static void gen_mtfsb0(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2314 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2315 | uint8_t crb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2316 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2317 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2318 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2319 | return; |
| 2320 | } |
aurel32 | 6e35d52 | 2008-12-14 18:40:58 +0000 | [diff] [blame] | 2321 | crb = 31 - crbD(ctx->opcode); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2322 | gen_reset_fpstatus(); |
aurel32 | 6e35d52 | 2008-12-14 18:40:58 +0000 | [diff] [blame] | 2323 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2324 | TCGv_i32 t0; |
| 2325 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2326 | gen_update_nip(ctx, ctx->nip - 4); |
| 2327 | t0 = tcg_const_i32(crb); |
aurel32 | 6e35d52 | 2008-12-14 18:40:58 +0000 | [diff] [blame] | 2328 | gen_helper_fpscr_clrbit(t0); |
| 2329 | tcg_temp_free_i32(t0); |
| 2330 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2331 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2332 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2333 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2334 | } |
| 2335 | |
| 2336 | /* mtfsb1 */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2337 | static void gen_mtfsb1(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2338 | { |
bellard | fb0eaff | 2004-01-04 14:57:11 +0000 | [diff] [blame] | 2339 | uint8_t crb; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2340 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2341 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2342 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2343 | return; |
| 2344 | } |
aurel32 | 6e35d52 | 2008-12-14 18:40:58 +0000 | [diff] [blame] | 2345 | crb = 31 - crbD(ctx->opcode); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2346 | gen_reset_fpstatus(); |
| 2347 | /* XXX: we pretend we can only do IEEE floating-point computations */ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2348 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2349 | TCGv_i32 t0; |
| 2350 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2351 | gen_update_nip(ctx, ctx->nip - 4); |
| 2352 | t0 = tcg_const_i32(crb); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2353 | gen_helper_fpscr_setbit(t0); |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2354 | tcg_temp_free_i32(t0); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2355 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2356 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2357 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2358 | } |
| 2359 | /* We can raise a differed exception */ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2360 | gen_helper_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2361 | } |
| 2362 | |
| 2363 | /* mtfsf */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2364 | static void gen_mtfsf(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2365 | { |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2366 | TCGv_i32 t0; |
blueswir1 | 4911012 | 2009-03-07 20:55:31 +0000 | [diff] [blame] | 2367 | int L = ctx->opcode & 0x02000000; |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2368 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2369 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2370 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2371 | return; |
| 2372 | } |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2373 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2374 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2375 | gen_reset_fpstatus(); |
blueswir1 | 4911012 | 2009-03-07 20:55:31 +0000 | [diff] [blame] | 2376 | if (L) |
| 2377 | t0 = tcg_const_i32(0xff); |
| 2378 | else |
| 2379 | t0 = tcg_const_i32(FM(ctx->opcode)); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2380 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2381 | tcg_temp_free_i32(t0); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2382 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2383 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2384 | } |
| 2385 | /* We can raise a differed exception */ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2386 | gen_helper_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2387 | } |
| 2388 | |
| 2389 | /* mtfsfi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2390 | static void gen_mtfsfi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2391 | { |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2392 | int bf, sh; |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2393 | TCGv_i64 t0; |
| 2394 | TCGv_i32 t1; |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2395 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2396 | if (unlikely(!ctx->fpu_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2397 | gen_exception(ctx, POWERPC_EXCP_FPU); |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 2398 | return; |
| 2399 | } |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2400 | bf = crbD(ctx->opcode) >> 2; |
| 2401 | sh = 7 - bf; |
aurel32 | eb44b95 | 2008-12-15 17:13:39 +0000 | [diff] [blame] | 2402 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2403 | gen_update_nip(ctx, ctx->nip - 4); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2404 | gen_reset_fpstatus(); |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2405 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2406 | t1 = tcg_const_i32(1 << sh); |
| 2407 | gen_helper_store_fpscr(t0, t1); |
aurel32 | 0f2f39c | 2008-11-19 17:54:49 +0000 | [diff] [blame] | 2408 | tcg_temp_free_i64(t0); |
| 2409 | tcg_temp_free_i32(t1); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2410 | if (unlikely(Rc(ctx->opcode) != 0)) { |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 2411 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 2412 | } |
| 2413 | /* We can raise a differed exception */ |
aurel32 | af12906 | 2008-11-19 16:10:23 +0000 | [diff] [blame] | 2414 | gen_helper_float_check_status(); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2415 | } |
| 2416 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2417 | /*** Addressing modes ***/ |
| 2418 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2419 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
| 2420 | target_long maskl) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2421 | { |
| 2422 | target_long simm = SIMM(ctx->opcode); |
| 2423 | |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2424 | simm &= ~maskl; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2425 | if (rA(ctx->opcode) == 0) { |
| 2426 | #if defined(TARGET_PPC64) |
| 2427 | if (!ctx->sf_mode) { |
| 2428 | tcg_gen_movi_tl(EA, (uint32_t)simm); |
| 2429 | } else |
| 2430 | #endif |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2431 | tcg_gen_movi_tl(EA, simm); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2432 | } else if (likely(simm != 0)) { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2433 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2434 | #if defined(TARGET_PPC64) |
| 2435 | if (!ctx->sf_mode) { |
| 2436 | tcg_gen_ext32u_tl(EA, EA); |
| 2437 | } |
| 2438 | #endif |
| 2439 | } else { |
| 2440 | #if defined(TARGET_PPC64) |
| 2441 | if (!ctx->sf_mode) { |
| 2442 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
| 2443 | } else |
| 2444 | #endif |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2445 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2446 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2447 | } |
| 2448 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2449 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2450 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2451 | if (rA(ctx->opcode) == 0) { |
| 2452 | #if defined(TARGET_PPC64) |
| 2453 | if (!ctx->sf_mode) { |
| 2454 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
| 2455 | } else |
| 2456 | #endif |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2457 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2458 | } else { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2459 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2460 | #if defined(TARGET_PPC64) |
| 2461 | if (!ctx->sf_mode) { |
| 2462 | tcg_gen_ext32u_tl(EA, EA); |
| 2463 | } |
| 2464 | #endif |
| 2465 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2466 | } |
| 2467 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2468 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2469 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2470 | if (rA(ctx->opcode) == 0) { |
aurel32 | e2be8d8 | 2008-10-14 19:55:54 +0000 | [diff] [blame] | 2471 | tcg_gen_movi_tl(EA, 0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2472 | } else { |
| 2473 | #if defined(TARGET_PPC64) |
| 2474 | if (!ctx->sf_mode) { |
| 2475 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
| 2476 | } else |
| 2477 | #endif |
| 2478 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
| 2479 | } |
| 2480 | } |
| 2481 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2482 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
| 2483 | target_long val) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2484 | { |
| 2485 | tcg_gen_addi_tl(ret, arg1, val); |
| 2486 | #if defined(TARGET_PPC64) |
| 2487 | if (!ctx->sf_mode) { |
| 2488 | tcg_gen_ext32u_tl(ret, ret); |
| 2489 | } |
| 2490 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2491 | } |
| 2492 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2493 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 2494 | { |
| 2495 | int l1 = gen_new_label(); |
| 2496 | TCGv t0 = tcg_temp_new(); |
| 2497 | TCGv_i32 t1, t2; |
| 2498 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 2499 | gen_update_nip(ctx, ctx->nip - 4); |
| 2500 | tcg_gen_andi_tl(t0, EA, mask); |
| 2501 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 2502 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); |
| 2503 | t2 = tcg_const_i32(0); |
| 2504 | gen_helper_raise_exception_err(t1, t2); |
| 2505 | tcg_temp_free_i32(t1); |
| 2506 | tcg_temp_free_i32(t2); |
| 2507 | gen_set_label(l1); |
| 2508 | tcg_temp_free(t0); |
| 2509 | } |
| 2510 | |
j_mayer | 7863667 | 2007-11-16 14:11:28 +0000 | [diff] [blame] | 2511 | /*** Integer load ***/ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2512 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2513 | { |
| 2514 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
| 2515 | } |
| 2516 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2517 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2518 | { |
| 2519 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
| 2520 | } |
| 2521 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2522 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2523 | { |
| 2524 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
| 2525 | if (unlikely(ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2526 | tcg_gen_bswap16_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2527 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2528 | } |
| 2529 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2530 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2531 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2532 | if (unlikely(ctx->le_mode)) { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2533 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2534 | tcg_gen_bswap16_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2535 | tcg_gen_ext16s_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2536 | } else { |
| 2537 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); |
| 2538 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2539 | } |
| 2540 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2541 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2542 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2543 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
| 2544 | if (unlikely(ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2545 | tcg_gen_bswap32_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2546 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2547 | } |
| 2548 | |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2549 | #if defined(TARGET_PPC64) |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2550 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2551 | { |
blueswir1 | a457e7e | 2009-02-28 08:25:29 +0000 | [diff] [blame] | 2552 | if (unlikely(ctx->le_mode)) { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2553 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2554 | tcg_gen_bswap32_tl(arg1, arg1); |
| 2555 | tcg_gen_ext32s_tl(arg1, arg1); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2556 | } else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2557 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 2558 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2559 | #endif |
| 2560 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2561 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2562 | { |
| 2563 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
| 2564 | if (unlikely(ctx->le_mode)) { |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 2565 | tcg_gen_bswap64_i64(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2566 | } |
| 2567 | } |
| 2568 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2569 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2570 | { |
| 2571 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
| 2572 | } |
| 2573 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2574 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2575 | { |
| 2576 | if (unlikely(ctx->le_mode)) { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2577 | TCGv t0 = tcg_temp_new(); |
| 2578 | tcg_gen_ext16u_tl(t0, arg1); |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2579 | tcg_gen_bswap16_tl(t0, t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2580 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
| 2581 | tcg_temp_free(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2582 | } else { |
| 2583 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
| 2584 | } |
| 2585 | } |
| 2586 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2587 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2588 | { |
| 2589 | if (unlikely(ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2590 | TCGv t0 = tcg_temp_new(); |
| 2591 | tcg_gen_ext32u_tl(t0, arg1); |
| 2592 | tcg_gen_bswap32_tl(t0, t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2593 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
| 2594 | tcg_temp_free(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2595 | } else { |
| 2596 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
| 2597 | } |
| 2598 | } |
| 2599 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 2600 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2601 | { |
| 2602 | if (unlikely(ctx->le_mode)) { |
| 2603 | TCGv_i64 t0 = tcg_temp_new_i64(); |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 2604 | tcg_gen_bswap64_i64(t0, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2605 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
| 2606 | tcg_temp_free_i64(t0); |
| 2607 | } else |
| 2608 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
| 2609 | } |
| 2610 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2611 | #define GEN_LD(name, ldop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2612 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2613 | { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2614 | TCGv EA; \ |
| 2615 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 2616 | EA = tcg_temp_new(); \ |
| 2617 | gen_addr_imm_index(ctx, EA, 0); \ |
| 2618 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2619 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2620 | } |
| 2621 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2622 | #define GEN_LDU(name, ldop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2623 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2624 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2625 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2626 | if (unlikely(rA(ctx->opcode) == 0 || \ |
| 2627 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2628 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2629 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2630 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2631 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2632 | EA = tcg_temp_new(); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2633 | if (type == PPC_64B) \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2634 | gen_addr_imm_index(ctx, EA, 0x03); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2635 | else \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2636 | gen_addr_imm_index(ctx, EA, 0); \ |
| 2637 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2638 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2639 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2640 | } |
| 2641 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2642 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2643 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2644 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2645 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2646 | if (unlikely(rA(ctx->opcode) == 0 || \ |
| 2647 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2648 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2649 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2650 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2651 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2652 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2653 | gen_addr_reg_index(ctx, EA); \ |
| 2654 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2655 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2656 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2657 | } |
| 2658 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2659 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2660 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2661 | { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2662 | TCGv EA; \ |
| 2663 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 2664 | EA = tcg_temp_new(); \ |
| 2665 | gen_addr_reg_index(ctx, EA); \ |
| 2666 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2667 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2668 | } |
| 2669 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2670 | #define GEN_LDS(name, ldop, op, type) \ |
| 2671 | GEN_LD(name, ldop, op | 0x20, type); \ |
| 2672 | GEN_LDU(name, ldop, op | 0x21, type); \ |
| 2673 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
| 2674 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2675 | |
| 2676 | /* lbz lbzu lbzux lbzx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2677 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2678 | /* lha lhau lhaux lhax */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2679 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2680 | /* lhz lhzu lhzux lhzx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2681 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2682 | /* lwz lwzu lwzux lwzx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2683 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2684 | #if defined(TARGET_PPC64) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2685 | /* lwaux */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2686 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2687 | /* lwax */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2688 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2689 | /* ldux */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2690 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2691 | /* ldx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2692 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2693 | |
| 2694 | static void gen_ld(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2695 | { |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2696 | TCGv EA; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2697 | if (Rc(ctx->opcode)) { |
| 2698 | if (unlikely(rA(ctx->opcode) == 0 || |
| 2699 | rA(ctx->opcode) == rD(ctx->opcode))) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2700 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2701 | return; |
| 2702 | } |
| 2703 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2704 | gen_set_access_type(ctx, ACCESS_INT); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2705 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2706 | gen_addr_imm_index(ctx, EA, 0x03); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2707 | if (ctx->opcode & 0x02) { |
| 2708 | /* lwa (lwau is undefined) */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2709 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2710 | } else { |
| 2711 | /* ld - ldu */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2712 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2713 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2714 | if (Rc(ctx->opcode)) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2715 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
| 2716 | tcg_temp_free(EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2717 | } |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2718 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2719 | /* lq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2720 | static void gen_lq(DisasContext *ctx) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2721 | { |
| 2722 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2723 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2724 | #else |
| 2725 | int ra, rd; |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2726 | TCGv EA; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2727 | |
| 2728 | /* Restore CPU state */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2729 | if (unlikely(ctx->mem_idx == 0)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2730 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2731 | return; |
| 2732 | } |
| 2733 | ra = rA(ctx->opcode); |
| 2734 | rd = rD(ctx->opcode); |
| 2735 | if (unlikely((rd & 1) || rd == ra)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2736 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2737 | return; |
| 2738 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2739 | if (unlikely(ctx->le_mode)) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2740 | /* Little-endian mode is not handled */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2741 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2742 | return; |
| 2743 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2744 | gen_set_access_type(ctx, ACCESS_INT); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2745 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2746 | gen_addr_imm_index(ctx, EA, 0x0F); |
| 2747 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); |
| 2748 | gen_addr_add(ctx, EA, EA, 8); |
| 2749 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2750 | tcg_temp_free(EA); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2751 | #endif |
| 2752 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2753 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2754 | |
| 2755 | /*** Integer store ***/ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2756 | #define GEN_ST(name, stop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2757 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2758 | { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2759 | TCGv EA; \ |
| 2760 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 2761 | EA = tcg_temp_new(); \ |
| 2762 | gen_addr_imm_index(ctx, EA, 0); \ |
| 2763 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2764 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2765 | } |
| 2766 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2767 | #define GEN_STU(name, stop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2768 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2769 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2770 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2771 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2772 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2773 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2774 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2775 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2776 | EA = tcg_temp_new(); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2777 | if (type == PPC_64B) \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2778 | gen_addr_imm_index(ctx, EA, 0x03); \ |
j_mayer | 9d53c75 | 2007-04-06 07:59:47 +0000 | [diff] [blame] | 2779 | else \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2780 | gen_addr_imm_index(ctx, EA, 0); \ |
| 2781 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2782 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2783 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2784 | } |
| 2785 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2786 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2787 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2788 | { \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2789 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2790 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2791 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2792 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2793 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2794 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2795 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2796 | gen_addr_reg_index(ctx, EA); \ |
| 2797 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2798 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 2799 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2800 | } |
| 2801 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2802 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2803 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2804 | { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2805 | TCGv EA; \ |
| 2806 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 2807 | EA = tcg_temp_new(); \ |
| 2808 | gen_addr_reg_index(ctx, EA); \ |
| 2809 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2810 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2811 | } |
| 2812 | |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2813 | #define GEN_STS(name, stop, op, type) \ |
| 2814 | GEN_ST(name, stop, op | 0x20, type); \ |
| 2815 | GEN_STU(name, stop, op | 0x21, type); \ |
| 2816 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
| 2817 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2818 | |
| 2819 | /* stb stbu stbux stbx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2820 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2821 | /* sth sthu sthux sthx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2822 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2823 | /* stw stwu stwux stwx */ |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2824 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2825 | #if defined(TARGET_PPC64) |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2826 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
| 2827 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2828 | |
| 2829 | static void gen_std(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2830 | { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2831 | int rs; |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2832 | TCGv EA; |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2833 | |
| 2834 | rs = rS(ctx->opcode); |
| 2835 | if ((ctx->opcode & 0x3) == 0x2) { |
| 2836 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2837 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2838 | #else |
| 2839 | /* stq */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2840 | if (unlikely(ctx->mem_idx == 0)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2841 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2842 | return; |
| 2843 | } |
| 2844 | if (unlikely(rs & 1)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2845 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2846 | return; |
| 2847 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2848 | if (unlikely(ctx->le_mode)) { |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2849 | /* Little-endian mode is not handled */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2850 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2851 | return; |
| 2852 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2853 | gen_set_access_type(ctx, ACCESS_INT); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2854 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2855 | gen_addr_imm_index(ctx, EA, 0x03); |
| 2856 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
| 2857 | gen_addr_add(ctx, EA, EA, 8); |
| 2858 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2859 | tcg_temp_free(EA); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2860 | #endif |
| 2861 | } else { |
| 2862 | /* std / stdu */ |
| 2863 | if (Rc(ctx->opcode)) { |
| 2864 | if (unlikely(rA(ctx->opcode) == 0)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2865 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2866 | return; |
| 2867 | } |
| 2868 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2869 | gen_set_access_type(ctx, ACCESS_INT); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2870 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2871 | gen_addr_imm_index(ctx, EA, 0x03); |
| 2872 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 2873 | if (Rc(ctx->opcode)) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2874 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
| 2875 | tcg_temp_free(EA); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2876 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2877 | } |
| 2878 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2879 | /*** Integer load and store with byte reverse ***/ |
| 2880 | /* lhbrx */ |
Juan Quintela | 86178a5 | 2009-09-23 01:19:00 +0200 | [diff] [blame] | 2881 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2882 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2883 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
| 2884 | if (likely(!ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2885 | tcg_gen_bswap16_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2886 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2887 | } |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2888 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2889 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2890 | /* lwbrx */ |
Juan Quintela | 86178a5 | 2009-09-23 01:19:00 +0200 | [diff] [blame] | 2891 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2892 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2893 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
| 2894 | if (likely(!ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2895 | tcg_gen_bswap32_tl(arg1, arg1); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2896 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2897 | } |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2898 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2899 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2900 | /* sthbrx */ |
Juan Quintela | 86178a5 | 2009-09-23 01:19:00 +0200 | [diff] [blame] | 2901 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2902 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2903 | if (likely(!ctx->le_mode)) { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2904 | TCGv t0 = tcg_temp_new(); |
| 2905 | tcg_gen_ext16u_tl(t0, arg1); |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2906 | tcg_gen_bswap16_tl(t0, t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2907 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
| 2908 | tcg_temp_free(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2909 | } else { |
| 2910 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
| 2911 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2912 | } |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2913 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2914 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2915 | /* stwbrx */ |
Juan Quintela | 86178a5 | 2009-09-23 01:19:00 +0200 | [diff] [blame] | 2916 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2917 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2918 | if (likely(!ctx->le_mode)) { |
aurel32 | fa3966a | 2009-03-13 09:35:34 +0000 | [diff] [blame] | 2919 | TCGv t0 = tcg_temp_new(); |
| 2920 | tcg_gen_ext32u_tl(t0, arg1); |
| 2921 | tcg_gen_bswap32_tl(t0, t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2922 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
| 2923 | tcg_temp_free(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2924 | } else { |
| 2925 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
| 2926 | } |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 2927 | } |
aurel32 | 0c8aacd | 2008-11-23 16:30:28 +0000 | [diff] [blame] | 2928 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2929 | |
| 2930 | /*** Integer load and store multiple ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2931 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2932 | /* lmw */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2933 | static void gen_lmw(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2934 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2935 | TCGv t0; |
| 2936 | TCGv_i32 t1; |
| 2937 | gen_set_access_type(ctx, ACCESS_INT); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2938 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2939 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2940 | t0 = tcg_temp_new(); |
| 2941 | t1 = tcg_const_i32(rD(ctx->opcode)); |
| 2942 | gen_addr_imm_index(ctx, t0, 0); |
aurel32 | ff4a62c | 2008-11-30 16:23:56 +0000 | [diff] [blame] | 2943 | gen_helper_lmw(t0, t1); |
| 2944 | tcg_temp_free(t0); |
| 2945 | tcg_temp_free_i32(t1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2946 | } |
| 2947 | |
| 2948 | /* stmw */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2949 | static void gen_stmw(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2950 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2951 | TCGv t0; |
| 2952 | TCGv_i32 t1; |
| 2953 | gen_set_access_type(ctx, ACCESS_INT); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2954 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2955 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2956 | t0 = tcg_temp_new(); |
| 2957 | t1 = tcg_const_i32(rS(ctx->opcode)); |
| 2958 | gen_addr_imm_index(ctx, t0, 0); |
aurel32 | ff4a62c | 2008-11-30 16:23:56 +0000 | [diff] [blame] | 2959 | gen_helper_stmw(t0, t1); |
| 2960 | tcg_temp_free(t0); |
| 2961 | tcg_temp_free_i32(t1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2962 | } |
| 2963 | |
| 2964 | /*** Integer load and store strings ***/ |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 2965 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2966 | /* lswi */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 2967 | /* PowerPC32 specification says we must generate an exception if |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2968 | * rA is in the range of registers to be loaded. |
| 2969 | * In an other hand, IBM says this is valid, but rA won't be loaded. |
| 2970 | * For now, I'll follow the spec... |
| 2971 | */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 2972 | static void gen_lswi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2973 | { |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 2974 | TCGv t0; |
| 2975 | TCGv_i32 t1, t2; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2976 | int nb = NB(ctx->opcode); |
| 2977 | int start = rD(ctx->opcode); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2978 | int ra = rA(ctx->opcode); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2979 | int nr; |
| 2980 | |
| 2981 | if (nb == 0) |
| 2982 | nb = 32; |
| 2983 | nr = nb / 4; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 2984 | if (unlikely(((start + nr) > 32 && |
| 2985 | start <= ra && (start + nr - 32) > ra) || |
| 2986 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 2987 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 2988 | return; |
bellard | 297d8e6 | 2004-02-21 14:11:27 +0000 | [diff] [blame] | 2989 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2990 | gen_set_access_type(ctx, ACCESS_INT); |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 2991 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 2992 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 2993 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 2994 | gen_addr_register(ctx, t0); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 2995 | t1 = tcg_const_i32(nb); |
| 2996 | t2 = tcg_const_i32(start); |
| 2997 | gen_helper_lsw(t0, t1, t2); |
| 2998 | tcg_temp_free(t0); |
| 2999 | tcg_temp_free_i32(t1); |
| 3000 | tcg_temp_free_i32(t2); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3001 | } |
| 3002 | |
| 3003 | /* lswx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3004 | static void gen_lswx(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3005 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3006 | TCGv t0; |
| 3007 | TCGv_i32 t1, t2, t3; |
| 3008 | gen_set_access_type(ctx, ACCESS_INT); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3009 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3010 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3011 | t0 = tcg_temp_new(); |
| 3012 | gen_addr_reg_index(ctx, t0); |
| 3013 | t1 = tcg_const_i32(rD(ctx->opcode)); |
| 3014 | t2 = tcg_const_i32(rA(ctx->opcode)); |
| 3015 | t3 = tcg_const_i32(rB(ctx->opcode)); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 3016 | gen_helper_lswx(t0, t1, t2, t3); |
| 3017 | tcg_temp_free(t0); |
| 3018 | tcg_temp_free_i32(t1); |
| 3019 | tcg_temp_free_i32(t2); |
| 3020 | tcg_temp_free_i32(t3); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3021 | } |
| 3022 | |
| 3023 | /* stswi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3024 | static void gen_stswi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3025 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3026 | TCGv t0; |
| 3027 | TCGv_i32 t1, t2; |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3028 | int nb = NB(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3029 | gen_set_access_type(ctx, ACCESS_INT); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3030 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3031 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3032 | t0 = tcg_temp_new(); |
| 3033 | gen_addr_register(ctx, t0); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 3034 | if (nb == 0) |
| 3035 | nb = 32; |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 3036 | t1 = tcg_const_i32(nb); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3037 | t2 = tcg_const_i32(rS(ctx->opcode)); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 3038 | gen_helper_stsw(t0, t1, t2); |
| 3039 | tcg_temp_free(t0); |
| 3040 | tcg_temp_free_i32(t1); |
| 3041 | tcg_temp_free_i32(t2); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3042 | } |
| 3043 | |
| 3044 | /* stswx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3045 | static void gen_stswx(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3046 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3047 | TCGv t0; |
| 3048 | TCGv_i32 t1, t2; |
| 3049 | gen_set_access_type(ctx, ACCESS_INT); |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 3050 | /* NIP cannot be restored if the memory exception comes from an helper */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3051 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3052 | t0 = tcg_temp_new(); |
| 3053 | gen_addr_reg_index(ctx, t0); |
| 3054 | t1 = tcg_temp_new_i32(); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 3055 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
| 3056 | tcg_gen_andi_i32(t1, t1, 0x7F); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3057 | t2 = tcg_const_i32(rS(ctx->opcode)); |
aurel32 | dfbc799 | 2008-11-30 16:24:21 +0000 | [diff] [blame] | 3058 | gen_helper_stsw(t0, t1, t2); |
| 3059 | tcg_temp_free(t0); |
| 3060 | tcg_temp_free_i32(t1); |
| 3061 | tcg_temp_free_i32(t2); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3062 | } |
| 3063 | |
| 3064 | /*** Memory synchronisation ***/ |
| 3065 | /* eieio */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3066 | static void gen_eieio(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3067 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3068 | } |
| 3069 | |
| 3070 | /* isync */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3071 | static void gen_isync(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3072 | { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3073 | gen_stop_exception(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3074 | } |
| 3075 | |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 3076 | /* lwarx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3077 | static void gen_lwarx(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3078 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3079 | TCGv t0; |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3080 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3081 | gen_set_access_type(ctx, ACCESS_RES); |
| 3082 | t0 = tcg_temp_local_new(); |
| 3083 | gen_addr_reg_index(ctx, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3084 | gen_check_align(ctx, t0, 0x03); |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3085 | gen_qemu_ld32u(ctx, gpr, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3086 | tcg_gen_mov_tl(cpu_reserve, t0); |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3087 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3088 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3089 | } |
| 3090 | |
Nathan Froyd | 4425265 | 2009-08-03 08:43:26 -0700 | [diff] [blame] | 3091 | #if defined(CONFIG_USER_ONLY) |
| 3092 | static void gen_conditional_store (DisasContext *ctx, TCGv EA, |
| 3093 | int reg, int size) |
| 3094 | { |
| 3095 | TCGv t0 = tcg_temp_new(); |
| 3096 | uint32_t save_exception = ctx->exception; |
| 3097 | |
| 3098 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea)); |
| 3099 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
| 3100 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info)); |
| 3101 | tcg_temp_free(t0); |
| 3102 | gen_update_nip(ctx, ctx->nip-4); |
| 3103 | ctx->exception = POWERPC_EXCP_BRANCH; |
| 3104 | gen_exception(ctx, POWERPC_EXCP_STCX); |
| 3105 | ctx->exception = save_exception; |
| 3106 | } |
| 3107 | #endif |
| 3108 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3109 | /* stwcx. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 3110 | static void gen_stwcx_(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3111 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3112 | TCGv t0; |
| 3113 | gen_set_access_type(ctx, ACCESS_RES); |
| 3114 | t0 = tcg_temp_local_new(); |
| 3115 | gen_addr_reg_index(ctx, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3116 | gen_check_align(ctx, t0, 0x03); |
Nathan Froyd | 4425265 | 2009-08-03 08:43:26 -0700 | [diff] [blame] | 3117 | #if defined(CONFIG_USER_ONLY) |
| 3118 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); |
| 3119 | #else |
| 3120 | { |
| 3121 | int l1; |
| 3122 | |
| 3123 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
| 3124 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
| 3125 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
| 3126 | l1 = gen_new_label(); |
| 3127 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
| 3128 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
| 3129 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
| 3130 | gen_set_label(l1); |
| 3131 | tcg_gen_movi_tl(cpu_reserve, -1); |
| 3132 | } |
| 3133 | #endif |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3134 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3135 | } |
| 3136 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3137 | #if defined(TARGET_PPC64) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3138 | /* ldarx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3139 | static void gen_ldarx(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3140 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3141 | TCGv t0; |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3142 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3143 | gen_set_access_type(ctx, ACCESS_RES); |
| 3144 | t0 = tcg_temp_local_new(); |
| 3145 | gen_addr_reg_index(ctx, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3146 | gen_check_align(ctx, t0, 0x07); |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3147 | gen_qemu_ld64(ctx, gpr, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3148 | tcg_gen_mov_tl(cpu_reserve, t0); |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 3149 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val)); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3150 | tcg_temp_free(t0); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3151 | } |
| 3152 | |
| 3153 | /* stdcx. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 3154 | static void gen_stdcx_(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3155 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3156 | TCGv t0; |
| 3157 | gen_set_access_type(ctx, ACCESS_RES); |
| 3158 | t0 = tcg_temp_local_new(); |
| 3159 | gen_addr_reg_index(ctx, t0); |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3160 | gen_check_align(ctx, t0, 0x07); |
Nathan Froyd | 4425265 | 2009-08-03 08:43:26 -0700 | [diff] [blame] | 3161 | #if defined(CONFIG_USER_ONLY) |
| 3162 | gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); |
| 3163 | #else |
| 3164 | { |
| 3165 | int l1; |
| 3166 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
| 3167 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
| 3168 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
| 3169 | l1 = gen_new_label(); |
| 3170 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
| 3171 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
| 3172 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
| 3173 | gen_set_label(l1); |
| 3174 | tcg_gen_movi_tl(cpu_reserve, -1); |
| 3175 | } |
| 3176 | #endif |
aurel32 | cf360a3 | 2008-11-30 16:24:39 +0000 | [diff] [blame] | 3177 | tcg_temp_free(t0); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3178 | } |
| 3179 | #endif /* defined(TARGET_PPC64) */ |
| 3180 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3181 | /* sync */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3182 | static void gen_sync(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3183 | { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3184 | } |
| 3185 | |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3186 | /* wait */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3187 | static void gen_wait(DisasContext *ctx) |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3188 | { |
aurel32 | 931ff27 | 2008-11-30 16:23:46 +0000 | [diff] [blame] | 3189 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 3190 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); |
| 3191 | tcg_temp_free_i32(t0); |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3192 | /* Stop translation, as the CPU is supposed to sleep from now */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3193 | gen_exception_err(ctx, EXCP_HLT, 1); |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 3194 | } |
| 3195 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3196 | /*** Floating-point load ***/ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3197 | #define GEN_LDF(name, ldop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3198 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3199 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3200 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3201 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3202 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3203 | return; \ |
| 3204 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3205 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3206 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3207 | gen_addr_imm_index(ctx, EA, 0); \ |
| 3208 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3209 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3210 | } |
| 3211 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3212 | #define GEN_LDUF(name, ldop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3213 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3214 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3215 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3216 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3217 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3218 | return; \ |
| 3219 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3220 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3221 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3222 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3223 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3224 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3225 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3226 | gen_addr_imm_index(ctx, EA, 0); \ |
| 3227 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3228 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 3229 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3230 | } |
| 3231 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3232 | #define GEN_LDUXF(name, ldop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3233 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3234 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3235 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3236 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3237 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3238 | return; \ |
| 3239 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3240 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3241 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3242 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3243 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3244 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3245 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3246 | gen_addr_reg_index(ctx, EA); \ |
| 3247 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3248 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 3249 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3250 | } |
| 3251 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3252 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3253 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3254 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3255 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3256 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3257 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3258 | return; \ |
| 3259 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3260 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3261 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3262 | gen_addr_reg_index(ctx, EA); \ |
| 3263 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3264 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3265 | } |
| 3266 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3267 | #define GEN_LDFS(name, ldop, op, type) \ |
| 3268 | GEN_LDF(name, ldop, op | 0x20, type); \ |
| 3269 | GEN_LDUF(name, ldop, op | 0x21, type); \ |
| 3270 | GEN_LDUXF(name, ldop, op | 0x01, type); \ |
| 3271 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3272 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3273 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3274 | { |
| 3275 | TCGv t0 = tcg_temp_new(); |
| 3276 | TCGv_i32 t1 = tcg_temp_new_i32(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3277 | gen_qemu_ld32u(ctx, t0, arg2); |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3278 | tcg_gen_trunc_tl_i32(t1, t0); |
| 3279 | tcg_temp_free(t0); |
| 3280 | gen_helper_float32_to_float64(arg1, t1); |
| 3281 | tcg_temp_free_i32(t1); |
| 3282 | } |
| 3283 | |
| 3284 | /* lfd lfdu lfdux lfdx */ |
| 3285 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); |
| 3286 | /* lfs lfsu lfsux lfsx */ |
| 3287 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3288 | |
| 3289 | /*** Floating-point store ***/ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3290 | #define GEN_STF(name, stop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3291 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3292 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3293 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3294 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3295 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3296 | return; \ |
| 3297 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3298 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3299 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3300 | gen_addr_imm_index(ctx, EA, 0); \ |
| 3301 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3302 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3303 | } |
| 3304 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3305 | #define GEN_STUF(name, stop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3306 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3307 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3308 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3309 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3310 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3311 | return; \ |
| 3312 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3313 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3314 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3315 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3316 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3317 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3318 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3319 | gen_addr_imm_index(ctx, EA, 0); \ |
| 3320 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3321 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 3322 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3323 | } |
| 3324 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3325 | #define GEN_STUXF(name, stop, opc, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3326 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3327 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3328 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3329 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3330 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3331 | return; \ |
| 3332 | } \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3333 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3334 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3335 | return; \ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3336 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3337 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3338 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3339 | gen_addr_reg_index(ctx, EA); \ |
| 3340 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3341 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
| 3342 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3343 | } |
| 3344 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3345 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3346 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3347 | { \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3348 | TCGv EA; \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3349 | if (unlikely(!ctx->fpu_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3350 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 3351 | return; \ |
| 3352 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3353 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3354 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3355 | gen_addr_reg_index(ctx, EA); \ |
| 3356 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3357 | tcg_temp_free(EA); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3358 | } |
| 3359 | |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3360 | #define GEN_STFS(name, stop, op, type) \ |
| 3361 | GEN_STF(name, stop, op | 0x20, type); \ |
| 3362 | GEN_STUF(name, stop, op | 0x21, type); \ |
| 3363 | GEN_STUXF(name, stop, op | 0x01, type); \ |
| 3364 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
| 3365 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3366 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3367 | { |
| 3368 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 3369 | TCGv t1 = tcg_temp_new(); |
| 3370 | gen_helper_float64_to_float32(t0, arg1); |
| 3371 | tcg_gen_extu_i32_tl(t1, t0); |
| 3372 | tcg_temp_free_i32(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3373 | gen_qemu_st32(ctx, t1, arg2); |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3374 | tcg_temp_free(t1); |
| 3375 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3376 | |
| 3377 | /* stfd stfdu stfdux stfdx */ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3378 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3379 | /* stfs stfsu stfsux stfsx */ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3380 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3381 | |
| 3382 | /* Optional: */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3383 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3384 | { |
| 3385 | TCGv t0 = tcg_temp_new(); |
| 3386 | tcg_gen_trunc_i64_tl(t0, arg1), |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3387 | gen_qemu_st32(ctx, t0, arg2); |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3388 | tcg_temp_free(t0); |
| 3389 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3390 | /* stfiwx */ |
aurel32 | a0d7d5a | 2008-11-23 16:30:50 +0000 | [diff] [blame] | 3391 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3392 | |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 3393 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
| 3394 | { |
| 3395 | #if defined(TARGET_PPC64) |
| 3396 | if (ctx->has_cfar) |
| 3397 | tcg_gen_movi_tl(cpu_cfar, nip); |
| 3398 | #endif |
| 3399 | } |
| 3400 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3401 | /*** Branch ***/ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3402 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3403 | { |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3404 | TranslationBlock *tb; |
| 3405 | tb = ctx->tb; |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3406 | #if defined(TARGET_PPC64) |
| 3407 | if (!ctx->sf_mode) |
| 3408 | dest = (uint32_t) dest; |
| 3409 | #endif |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3410 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3411 | likely(!ctx->singlestep_enabled)) { |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3412 | tcg_gen_goto_tb(n); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3413 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
Stefan Weil | 4b4a72e | 2011-04-02 13:36:31 +0200 | [diff] [blame] | 3414 | tcg_gen_exit_tb((tcg_target_long)tb + n); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3415 | } else { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3416 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3417 | if (unlikely(ctx->singlestep_enabled)) { |
| 3418 | if ((ctx->singlestep_enabled & |
aurel32 | bdc4e05 | 2008-11-09 17:27:03 +0000 | [diff] [blame] | 3419 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3420 | ctx->exception == POWERPC_EXCP_BRANCH) { |
| 3421 | target_ulong tmp = ctx->nip; |
| 3422 | ctx->nip = dest; |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3423 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3424 | ctx->nip = tmp; |
| 3425 | } |
| 3426 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3427 | gen_debug_exception(ctx); |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3428 | } |
| 3429 | } |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3430 | tcg_gen_exit_tb(0); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3431 | } |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3432 | } |
| 3433 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3434 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3435 | { |
| 3436 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3437 | if (ctx->sf_mode == 0) |
| 3438 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3439 | else |
| 3440 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3441 | tcg_gen_movi_tl(cpu_lr, nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3442 | } |
| 3443 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3444 | /* b ba bl bla */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3445 | static void gen_b(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3446 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3447 | target_ulong li, target; |
bellard | 38a64f9 | 2004-07-07 22:06:01 +0000 | [diff] [blame] | 3448 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3449 | ctx->exception = POWERPC_EXCP_BRANCH; |
bellard | 38a64f9 | 2004-07-07 22:06:01 +0000 | [diff] [blame] | 3450 | /* sign extend LI */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3451 | #if defined(TARGET_PPC64) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3452 | if (ctx->sf_mode) |
| 3453 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; |
| 3454 | else |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3455 | #endif |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3456 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3457 | if (likely(AA(ctx->opcode) == 0)) |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 3458 | target = ctx->nip + li - 4; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3459 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3460 | target = li; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3461 | if (LK(ctx->opcode)) |
| 3462 | gen_setlr(ctx, ctx->nip); |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 3463 | gen_update_cfar(ctx, ctx->nip); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3464 | gen_goto_tb(ctx, 0, target); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3465 | } |
| 3466 | |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3467 | #define BCOND_IM 0 |
| 3468 | #define BCOND_LR 1 |
| 3469 | #define BCOND_CTR 2 |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3470 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3471 | static inline void gen_bcond(DisasContext *ctx, int type) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3472 | { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3473 | uint32_t bo = BO(ctx->opcode); |
Blue Swirl | 05f9240 | 2010-04-25 20:32:49 +0000 | [diff] [blame] | 3474 | int l1; |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3475 | TCGv target; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3476 | |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 3477 | ctx->exception = POWERPC_EXCP_BRANCH; |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3478 | if (type == BCOND_LR || type == BCOND_CTR) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3479 | target = tcg_temp_local_new(); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3480 | if (type == BCOND_CTR) |
| 3481 | tcg_gen_mov_tl(target, cpu_ctr); |
| 3482 | else |
| 3483 | tcg_gen_mov_tl(target, cpu_lr); |
malc | d2e9fd8 | 2009-06-20 05:51:47 +0400 | [diff] [blame] | 3484 | } else { |
| 3485 | TCGV_UNUSED(target); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3486 | } |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3487 | if (LK(ctx->opcode)) |
| 3488 | gen_setlr(ctx, ctx->nip); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3489 | l1 = gen_new_label(); |
| 3490 | if ((bo & 0x4) == 0) { |
| 3491 | /* Decrement and test CTR */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3492 | TCGv temp = tcg_temp_new(); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3493 | if (unlikely(type == BCOND_CTR)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3494 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3495 | return; |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3496 | } |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3497 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3498 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3499 | if (!ctx->sf_mode) |
| 3500 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
| 3501 | else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3502 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3503 | tcg_gen_mov_tl(temp, cpu_ctr); |
| 3504 | if (bo & 0x2) { |
| 3505 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3506 | } else { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3507 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
| 3508 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3509 | tcg_temp_free(temp); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3510 | } |
| 3511 | if ((bo & 0x10) == 0) { |
| 3512 | /* Test CR */ |
| 3513 | uint32_t bi = BI(ctx->opcode); |
| 3514 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3515 | TCGv_i32 temp = tcg_temp_new_i32(); |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3516 | |
| 3517 | if (bo & 0x8) { |
| 3518 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
| 3519 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); |
| 3520 | } else { |
| 3521 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
| 3522 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3523 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3524 | tcg_temp_free_i32(temp); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3525 | } |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 3526 | gen_update_cfar(ctx, ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3527 | if (type == BCOND_IM) { |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3528 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
| 3529 | if (likely(AA(ctx->opcode) == 0)) { |
| 3530 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
| 3531 | } else { |
| 3532 | gen_goto_tb(ctx, 0, li); |
| 3533 | } |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3534 | gen_set_label(l1); |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 3535 | gen_goto_tb(ctx, 1, ctx->nip); |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3536 | } else { |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3537 | #if defined(TARGET_PPC64) |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3538 | if (!(ctx->sf_mode)) |
| 3539 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3540 | else |
| 3541 | #endif |
aurel32 | a2ffb81 | 2008-10-21 16:31:31 +0000 | [diff] [blame] | 3542 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
| 3543 | tcg_gen_exit_tb(0); |
| 3544 | gen_set_label(l1); |
| 3545 | #if defined(TARGET_PPC64) |
| 3546 | if (!(ctx->sf_mode)) |
| 3547 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); |
| 3548 | else |
| 3549 | #endif |
| 3550 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3551 | tcg_gen_exit_tb(0); |
j_mayer | 08e46e5 | 2007-04-16 07:18:42 +0000 | [diff] [blame] | 3552 | } |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3553 | } |
| 3554 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3555 | static void gen_bc(DisasContext *ctx) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3556 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3557 | gen_bcond(ctx, BCOND_IM); |
| 3558 | } |
| 3559 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3560 | static void gen_bcctr(DisasContext *ctx) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3561 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3562 | gen_bcond(ctx, BCOND_CTR); |
| 3563 | } |
| 3564 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3565 | static void gen_bclr(DisasContext *ctx) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3566 | { |
bellard | e98a6e4 | 2004-02-21 15:35:00 +0000 | [diff] [blame] | 3567 | gen_bcond(ctx, BCOND_LR); |
| 3568 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3569 | |
| 3570 | /*** Condition register logical ***/ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3571 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3572 | static void glue(gen_, name)(DisasContext *ctx) \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3573 | { \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3574 | uint8_t bitmask; \ |
| 3575 | int sh; \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3576 | TCGv_i32 t0, t1; \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3577 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3578 | t0 = tcg_temp_new_i32(); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3579 | if (sh > 0) \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3580 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3581 | else if (sh < 0) \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3582 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3583 | else \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3584 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3585 | t1 = tcg_temp_new_i32(); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3586 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
| 3587 | if (sh > 0) \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3588 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3589 | else if (sh < 0) \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3590 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3591 | else \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3592 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
| 3593 | tcg_op(t0, t0, t1); \ |
j_mayer | fc0d441 | 2007-10-31 22:02:17 +0000 | [diff] [blame] | 3594 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 3595 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
| 3596 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ |
| 3597 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3598 | tcg_temp_free_i32(t0); \ |
| 3599 | tcg_temp_free_i32(t1); \ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3600 | } |
| 3601 | |
| 3602 | /* crand */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3603 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3604 | /* crandc */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3605 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3606 | /* creqv */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3607 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3608 | /* crnand */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3609 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3610 | /* crnor */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3611 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3612 | /* cror */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3613 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3614 | /* crorc */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3615 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3616 | /* crxor */ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3617 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3618 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 3619 | /* mcrf */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3620 | static void gen_mcrf(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3621 | { |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 3622 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3623 | } |
| 3624 | |
| 3625 | /*** System linkage ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3626 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 3627 | /* rfi (mem_idx only) */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3628 | static void gen_rfi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3629 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3630 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3631 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3632 | #else |
| 3633 | /* Restore CPU state */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3634 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3635 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3636 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3637 | } |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 3638 | gen_update_cfar(ctx, ctx->nip); |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 3639 | gen_helper_rfi(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3640 | gen_sync_exception(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3641 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3642 | } |
| 3643 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3644 | #if defined(TARGET_PPC64) |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3645 | static void gen_rfid(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3646 | { |
| 3647 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3648 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3649 | #else |
| 3650 | /* Restore CPU state */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3651 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3652 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3653 | return; |
| 3654 | } |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 3655 | gen_update_cfar(ctx, ctx->nip); |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 3656 | gen_helper_rfid(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3657 | gen_sync_exception(ctx); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3658 | #endif |
| 3659 | } |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3660 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3661 | static void gen_hrfid(DisasContext *ctx) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3662 | { |
| 3663 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3665 | #else |
| 3666 | /* Restore CPU state */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3667 | if (unlikely(ctx->mem_idx <= 1)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3668 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3669 | return; |
| 3670 | } |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 3671 | gen_helper_hrfid(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3672 | gen_sync_exception(ctx); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3673 | #endif |
| 3674 | } |
| 3675 | #endif |
| 3676 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3677 | /* sc */ |
j_mayer | 417bf01 | 2007-10-07 23:10:08 +0000 | [diff] [blame] | 3678 | #if defined(CONFIG_USER_ONLY) |
| 3679 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER |
| 3680 | #else |
| 3681 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL |
| 3682 | #endif |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3683 | static void gen_sc(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3684 | { |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 3685 | uint32_t lev; |
| 3686 | |
| 3687 | lev = (ctx->opcode >> 5) & 0x7F; |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3688 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3689 | } |
| 3690 | |
| 3691 | /*** Trap ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3692 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 3693 | /* tw */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3694 | static void gen_tw(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3695 | { |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3696 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
Aurelien Jarno | db9a231 | 2010-02-28 16:02:28 +0100 | [diff] [blame] | 3697 | /* Update the nip since this might generate a trap exception */ |
| 3698 | gen_update_nip(ctx, ctx->nip); |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3699 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
| 3700 | tcg_temp_free_i32(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3701 | } |
| 3702 | |
| 3703 | /* twi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3704 | static void gen_twi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3705 | { |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3706 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
| 3707 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
Aurelien Jarno | db9a231 | 2010-02-28 16:02:28 +0100 | [diff] [blame] | 3708 | /* Update the nip since this might generate a trap exception */ |
| 3709 | gen_update_nip(ctx, ctx->nip); |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3710 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 3711 | tcg_temp_free(t0); |
| 3712 | tcg_temp_free_i32(t1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3713 | } |
| 3714 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3715 | #if defined(TARGET_PPC64) |
| 3716 | /* td */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3717 | static void gen_td(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3718 | { |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3719 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
Aurelien Jarno | db9a231 | 2010-02-28 16:02:28 +0100 | [diff] [blame] | 3720 | /* Update the nip since this might generate a trap exception */ |
| 3721 | gen_update_nip(ctx, ctx->nip); |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3722 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
| 3723 | tcg_temp_free_i32(t0); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3724 | } |
| 3725 | |
| 3726 | /* tdi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3727 | static void gen_tdi(DisasContext *ctx) |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3728 | { |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3729 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
| 3730 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
Aurelien Jarno | db9a231 | 2010-02-28 16:02:28 +0100 | [diff] [blame] | 3731 | /* Update the nip since this might generate a trap exception */ |
| 3732 | gen_update_nip(ctx, ctx->nip); |
aurel32 | cab3bee | 2008-11-24 11:28:19 +0000 | [diff] [blame] | 3733 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 3734 | tcg_temp_free(t0); |
| 3735 | tcg_temp_free_i32(t1); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3736 | } |
| 3737 | #endif |
| 3738 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3739 | /*** Processor control ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3740 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 3741 | /* mcrxr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3742 | static void gen_mcrxr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3743 | { |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 3744 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
| 3745 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); |
aurel32 | 269f3e9 | 2008-11-01 00:53:48 +0000 | [diff] [blame] | 3746 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3747 | } |
| 3748 | |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 3749 | /* mfcr mfocrf */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3750 | static void gen_mfcr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3751 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3752 | uint32_t crm, crn; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3753 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3754 | if (likely(ctx->opcode & 0x00100000)) { |
| 3755 | crm = CRM(ctx->opcode); |
malc | 8dd640e | 2009-03-02 22:39:39 +0000 | [diff] [blame] | 3756 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 3757 | crn = ctz32 (crm); |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 3758 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
aurel32 | 0497d2f | 2009-03-07 20:57:47 +0000 | [diff] [blame] | 3759 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
| 3760 | cpu_gpr[rD(ctx->opcode)], crn * 4); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3761 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3762 | } else { |
aurel32 | 651721b | 2009-03-09 18:50:24 +0000 | [diff] [blame] | 3763 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 3764 | tcg_gen_mov_i32(t0, cpu_crf[0]); |
| 3765 | tcg_gen_shli_i32(t0, t0, 4); |
| 3766 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); |
| 3767 | tcg_gen_shli_i32(t0, t0, 4); |
| 3768 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); |
| 3769 | tcg_gen_shli_i32(t0, t0, 4); |
| 3770 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); |
| 3771 | tcg_gen_shli_i32(t0, t0, 4); |
| 3772 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); |
| 3773 | tcg_gen_shli_i32(t0, t0, 4); |
| 3774 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); |
| 3775 | tcg_gen_shli_i32(t0, t0, 4); |
| 3776 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); |
| 3777 | tcg_gen_shli_i32(t0, t0, 4); |
| 3778 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); |
| 3779 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 3780 | tcg_temp_free_i32(t0); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3781 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3782 | } |
| 3783 | |
| 3784 | /* mfmsr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3785 | static void gen_mfmsr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3786 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3787 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3788 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3789 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3790 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3791 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3792 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3793 | } |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 3794 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3795 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3796 | } |
| 3797 | |
Blue Swirl | 7b13448 | 2010-04-18 14:26:51 +0000 | [diff] [blame] | 3798 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3799 | { |
Blue Swirl | 7b13448 | 2010-04-18 14:26:51 +0000 | [diff] [blame] | 3800 | #if 0 |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3801 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
| 3802 | printf("ERROR: try to access SPR %d !\n", sprn); |
Blue Swirl | 7b13448 | 2010-04-18 14:26:51 +0000 | [diff] [blame] | 3803 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3804 | } |
| 3805 | #define SPR_NOACCESS (&spr_noaccess) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3806 | |
| 3807 | /* mfspr */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 3808 | static inline void gen_op_mfspr(DisasContext *ctx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3809 | { |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 3810 | void (*read_cb)(void *opaque, int gprn, int sprn); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3811 | uint32_t sprn = SPR(ctx->opcode); |
| 3812 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3813 | #if !defined(CONFIG_USER_ONLY) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3814 | if (ctx->mem_idx == 2) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3815 | read_cb = ctx->spr_cb[sprn].hea_read; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3816 | else if (ctx->mem_idx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3817 | read_cb = ctx->spr_cb[sprn].oea_read; |
| 3818 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3819 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3820 | read_cb = ctx->spr_cb[sprn].uea_read; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3821 | if (likely(read_cb != NULL)) { |
| 3822 | if (likely(read_cb != SPR_NOACCESS)) { |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 3823 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3824 | } else { |
| 3825 | /* Privilege exception */ |
j_mayer | 9fceefa | 2007-11-02 22:47:50 +0000 | [diff] [blame] | 3826 | /* This is a hack to avoid warnings when running Linux: |
| 3827 | * this OS breaks the PowerPC virtualisation model, |
| 3828 | * allowing userland application to read the PVR |
| 3829 | */ |
| 3830 | if (sprn != SPR_PVR) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 3831 | qemu_log("Trying to read privileged spr %d %03x at " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 3832 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
| 3833 | printf("Trying to read privileged spr %d %03x at " |
| 3834 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
bellard | f24e569 | 2005-11-23 21:36:30 +0000 | [diff] [blame] | 3835 | } |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3836 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3837 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3838 | } else { |
| 3839 | /* Not defined */ |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 3840 | qemu_log("Trying to read invalid spr %d %03x at " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 3841 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
| 3842 | printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n", |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3843 | sprn, sprn, ctx->nip); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3844 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3845 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3846 | } |
| 3847 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3848 | static void gen_mfspr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3849 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3850 | gen_op_mfspr(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3851 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3852 | |
| 3853 | /* mftb */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3854 | static void gen_mftb(DisasContext *ctx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3855 | { |
| 3856 | gen_op_mfspr(ctx); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3857 | } |
| 3858 | |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 3859 | /* mtcrf mtocrf*/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3860 | static void gen_mtcrf(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3861 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3862 | uint32_t crm, crn; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3863 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3864 | crm = CRM(ctx->opcode); |
malc | 8dd640e | 2009-03-02 22:39:39 +0000 | [diff] [blame] | 3865 | if (likely((ctx->opcode & 0x00100000))) { |
| 3866 | if (crm && ((crm & (crm - 1)) == 0)) { |
| 3867 | TCGv_i32 temp = tcg_temp_new_i32(); |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 3868 | crn = ctz32 (crm); |
malc | 8dd640e | 2009-03-02 22:39:39 +0000 | [diff] [blame] | 3869 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 0cfe11e | 2009-03-03 06:12:14 +0000 | [diff] [blame] | 3870 | tcg_gen_shri_i32(temp, temp, crn * 4); |
| 3871 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
malc | 8dd640e | 2009-03-02 22:39:39 +0000 | [diff] [blame] | 3872 | tcg_temp_free_i32(temp); |
| 3873 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3874 | } else { |
aurel32 | 651721b | 2009-03-09 18:50:24 +0000 | [diff] [blame] | 3875 | TCGv_i32 temp = tcg_temp_new_i32(); |
| 3876 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
| 3877 | for (crn = 0 ; crn < 8 ; crn++) { |
| 3878 | if (crm & (1 << crn)) { |
| 3879 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
| 3880 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
| 3881 | } |
| 3882 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3883 | tcg_temp_free_i32(temp); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3884 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3885 | } |
| 3886 | |
| 3887 | /* mtmsr */ |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3888 | #if defined(TARGET_PPC64) |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3889 | static void gen_mtmsrd(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3890 | { |
| 3891 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3892 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3893 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3894 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3895 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3896 | return; |
| 3897 | } |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3898 | if (ctx->opcode & 0x00010000) { |
| 3899 | /* Special form that does not need any synchronisation */ |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 3900 | TCGv t0 = tcg_temp_new(); |
| 3901 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
| 3902 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
| 3903 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
| 3904 | tcg_temp_free(t0); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3905 | } else { |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3906 | /* XXX: we need to update nip before the store |
| 3907 | * if we enter power saving mode, we will exit the loop |
| 3908 | * directly from ppc_store_msr |
| 3909 | */ |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3910 | gen_update_nip(ctx, ctx->nip); |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 3911 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3912 | /* Must stop the translation as machine state (may have) changed */ |
| 3913 | /* Note that mtmsr is not always defined as context-synchronizing */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3914 | gen_stop_exception(ctx); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3915 | } |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 3916 | #endif |
| 3917 | } |
| 3918 | #endif |
| 3919 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3920 | static void gen_mtmsr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3921 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3922 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3923 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3924 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3925 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3926 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 3927 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3928 | } |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3929 | if (ctx->opcode & 0x00010000) { |
| 3930 | /* Special form that does not need any synchronisation */ |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 3931 | TCGv t0 = tcg_temp_new(); |
| 3932 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
| 3933 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
| 3934 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
| 3935 | tcg_temp_free(t0); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3936 | } else { |
Alexander Graf | 8018dc6 | 2011-06-16 10:44:23 +0200 | [diff] [blame] | 3937 | TCGv msr = tcg_temp_new(); |
| 3938 | |
j_mayer | 056b05f | 2007-10-01 03:03:51 +0000 | [diff] [blame] | 3939 | /* XXX: we need to update nip before the store |
| 3940 | * if we enter power saving mode, we will exit the loop |
| 3941 | * directly from ppc_store_msr |
| 3942 | */ |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3943 | gen_update_nip(ctx, ctx->nip); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3944 | #if defined(TARGET_PPC64) |
Alexander Graf | 8018dc6 | 2011-06-16 10:44:23 +0200 | [diff] [blame] | 3945 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
| 3946 | #else |
| 3947 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 3948 | #endif |
Alexander Graf | 8018dc6 | 2011-06-16 10:44:23 +0200 | [diff] [blame] | 3949 | gen_helper_store_msr(msr); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3950 | /* Must stop the translation as machine state (may have) changed */ |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 3951 | /* Note that mtmsr is not always defined as context-synchronizing */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3952 | gen_stop_exception(ctx); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3953 | } |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3954 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3955 | } |
| 3956 | |
| 3957 | /* mtspr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3958 | static void gen_mtspr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3959 | { |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 3960 | void (*write_cb)(void *opaque, int sprn, int gprn); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3961 | uint32_t sprn = SPR(ctx->opcode); |
| 3962 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3963 | #if !defined(CONFIG_USER_ONLY) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3964 | if (ctx->mem_idx == 2) |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 3965 | write_cb = ctx->spr_cb[sprn].hea_write; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3966 | else if (ctx->mem_idx) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3967 | write_cb = ctx->spr_cb[sprn].oea_write; |
| 3968 | else |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3969 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3970 | write_cb = ctx->spr_cb[sprn].uea_write; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3971 | if (likely(write_cb != NULL)) { |
| 3972 | if (likely(write_cb != SPR_NOACCESS)) { |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 3973 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3974 | } else { |
| 3975 | /* Privilege exception */ |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 3976 | qemu_log("Trying to write privileged spr %d %03x at " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 3977 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
| 3978 | printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx |
| 3979 | "\n", sprn, sprn, ctx->nip); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3980 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 3981 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 3982 | } else { |
| 3983 | /* Not defined */ |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 3984 | qemu_log("Trying to write invalid spr %d %03x at " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 3985 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip); |
| 3986 | printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n", |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 3987 | sprn, sprn, ctx->nip); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 3988 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 3989 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3990 | } |
| 3991 | |
| 3992 | /*** Cache management ***/ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3993 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 3994 | /* dcbf */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 3995 | static void gen_dcbf(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 3996 | { |
j_mayer | dac454a | 2007-10-26 00:48:00 +0000 | [diff] [blame] | 3997 | /* XXX: specification says this is treated as a load by the MMU */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 3998 | TCGv t0; |
| 3999 | gen_set_access_type(ctx, ACCESS_CACHE); |
| 4000 | t0 = tcg_temp_new(); |
| 4001 | gen_addr_reg_index(ctx, t0); |
| 4002 | gen_qemu_ld8u(ctx, t0, t0); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 4003 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4004 | } |
| 4005 | |
| 4006 | /* dcbi (Supervisor only) */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4007 | static void gen_dcbi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4008 | { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 4009 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4010 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 4011 | #else |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 4012 | TCGv EA, val; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4013 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4014 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4015 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4016 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4017 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4018 | gen_set_access_type(ctx, ACCESS_CACHE); |
| 4019 | gen_addr_reg_index(ctx, EA); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4020 | val = tcg_temp_new(); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4021 | /* XXX: specification says this should be treated as a store by the MMU */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4022 | gen_qemu_ld8u(ctx, val, EA); |
| 4023 | gen_qemu_st8(ctx, val, EA); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 4024 | tcg_temp_free(val); |
| 4025 | tcg_temp_free(EA); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 4026 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4027 | } |
| 4028 | |
| 4029 | /* dcdst */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4030 | static void gen_dcbst(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4031 | { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4032 | /* XXX: specification say this is treated as a load by the MMU */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4033 | TCGv t0; |
| 4034 | gen_set_access_type(ctx, ACCESS_CACHE); |
| 4035 | t0 = tcg_temp_new(); |
| 4036 | gen_addr_reg_index(ctx, t0); |
| 4037 | gen_qemu_ld8u(ctx, t0, t0); |
aurel32 | fea0c50 | 2008-11-02 08:22:34 +0000 | [diff] [blame] | 4038 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4039 | } |
| 4040 | |
| 4041 | /* dcbt */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4042 | static void gen_dcbt(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4043 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 4044 | /* interpreted as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4045 | /* XXX: specification say this is treated as a load by the MMU |
| 4046 | * but does not generate any exception |
| 4047 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4048 | } |
| 4049 | |
| 4050 | /* dcbtst */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4051 | static void gen_dcbtst(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4052 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 4053 | /* interpreted as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4054 | /* XXX: specification say this is treated as a load by the MMU |
| 4055 | * but does not generate any exception |
| 4056 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4057 | } |
| 4058 | |
| 4059 | /* dcbz */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4060 | static void gen_dcbz(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4061 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4062 | TCGv t0; |
| 4063 | gen_set_access_type(ctx, ACCESS_CACHE); |
aurel32 | 799a8c8 | 2008-11-30 16:24:05 +0000 | [diff] [blame] | 4064 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 4065 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4066 | t0 = tcg_temp_new(); |
| 4067 | gen_addr_reg_index(ctx, t0); |
aurel32 | 799a8c8 | 2008-11-30 16:24:05 +0000 | [diff] [blame] | 4068 | gen_helper_dcbz(t0); |
| 4069 | tcg_temp_free(t0); |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4070 | } |
| 4071 | |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4072 | static void gen_dcbz_970(DisasContext *ctx) |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4073 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4074 | TCGv t0; |
| 4075 | gen_set_access_type(ctx, ACCESS_CACHE); |
aurel32 | 799a8c8 | 2008-11-30 16:24:05 +0000 | [diff] [blame] | 4076 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 4077 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4078 | t0 = tcg_temp_new(); |
| 4079 | gen_addr_reg_index(ctx, t0); |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4080 | if (ctx->opcode & 0x00200000) |
aurel32 | 799a8c8 | 2008-11-30 16:24:05 +0000 | [diff] [blame] | 4081 | gen_helper_dcbz(t0); |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 4082 | else |
aurel32 | 799a8c8 | 2008-11-30 16:24:05 +0000 | [diff] [blame] | 4083 | gen_helper_dcbz_970(t0); |
| 4084 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4085 | } |
| 4086 | |
aurel32 | ae1c1a3 | 2009-01-12 21:33:02 +0000 | [diff] [blame] | 4087 | /* dst / dstt */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4088 | static void gen_dst(DisasContext *ctx) |
aurel32 | ae1c1a3 | 2009-01-12 21:33:02 +0000 | [diff] [blame] | 4089 | { |
| 4090 | if (rA(ctx->opcode) == 0) { |
| 4091 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
| 4092 | } else { |
| 4093 | /* interpreted as no-op */ |
| 4094 | } |
| 4095 | } |
| 4096 | |
| 4097 | /* dstst /dststt */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4098 | static void gen_dstst(DisasContext *ctx) |
aurel32 | ae1c1a3 | 2009-01-12 21:33:02 +0000 | [diff] [blame] | 4099 | { |
| 4100 | if (rA(ctx->opcode) == 0) { |
| 4101 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
| 4102 | } else { |
| 4103 | /* interpreted as no-op */ |
| 4104 | } |
| 4105 | |
| 4106 | } |
| 4107 | |
| 4108 | /* dss / dssall */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4109 | static void gen_dss(DisasContext *ctx) |
aurel32 | ae1c1a3 | 2009-01-12 21:33:02 +0000 | [diff] [blame] | 4110 | { |
| 4111 | /* interpreted as no-op */ |
| 4112 | } |
| 4113 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4114 | /* icbi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4115 | static void gen_icbi(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4116 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4117 | TCGv t0; |
| 4118 | gen_set_access_type(ctx, ACCESS_CACHE); |
j_mayer | 30032c9 | 2007-10-01 05:22:17 +0000 | [diff] [blame] | 4119 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 4120 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4121 | t0 = tcg_temp_new(); |
| 4122 | gen_addr_reg_index(ctx, t0); |
aurel32 | 37d269d | 2008-11-30 16:24:13 +0000 | [diff] [blame] | 4123 | gen_helper_icbi(t0); |
| 4124 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4125 | } |
| 4126 | |
| 4127 | /* Optional: */ |
| 4128 | /* dcba */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4129 | static void gen_dcba(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4130 | { |
j_mayer | 0db1b20 | 2007-09-30 03:46:38 +0000 | [diff] [blame] | 4131 | /* interpreted as no-op */ |
| 4132 | /* XXX: specification say this is treated as a store by the MMU |
| 4133 | * but does not generate any exception |
| 4134 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4135 | } |
| 4136 | |
| 4137 | /*** Segment register manipulation ***/ |
| 4138 | /* Supervisor only: */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4139 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 4140 | /* mfsr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4141 | static void gen_mfsr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4142 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4143 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4144 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4145 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4146 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4147 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4148 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4149 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4150 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4151 | t0 = tcg_const_tl(SR(ctx->opcode)); |
| 4152 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
| 4153 | tcg_temp_free(t0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4154 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4155 | } |
| 4156 | |
| 4157 | /* mfsrin */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4158 | static void gen_mfsrin(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4159 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4160 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4161 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4162 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4163 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4164 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4165 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4166 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4167 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4168 | t0 = tcg_temp_new(); |
| 4169 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); |
| 4170 | tcg_gen_andi_tl(t0, t0, 0xF); |
| 4171 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
| 4172 | tcg_temp_free(t0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4173 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4174 | } |
| 4175 | |
| 4176 | /* mtsr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4177 | static void gen_mtsr(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4178 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4179 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4180 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4181 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4182 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4183 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4184 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4185 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4186 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4187 | t0 = tcg_const_tl(SR(ctx->opcode)); |
| 4188 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
| 4189 | tcg_temp_free(t0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4190 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4191 | } |
| 4192 | |
| 4193 | /* mtsrin */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4194 | static void gen_mtsrin(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4195 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4196 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4197 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4198 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4199 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4200 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4201 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4202 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4203 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4204 | t0 = tcg_temp_new(); |
| 4205 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); |
| 4206 | tcg_gen_andi_tl(t0, t0, 0xF); |
| 4207 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); |
| 4208 | tcg_temp_free(t0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4209 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4210 | } |
| 4211 | |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4212 | #if defined(TARGET_PPC64) |
| 4213 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4214 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 4215 | /* mfsr */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4216 | static void gen_mfsr_64b(DisasContext *ctx) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4217 | { |
| 4218 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4219 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4220 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4221 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4222 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4223 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4224 | return; |
| 4225 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4226 | t0 = tcg_const_tl(SR(ctx->opcode)); |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4227 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4228 | tcg_temp_free(t0); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4229 | #endif |
| 4230 | } |
| 4231 | |
| 4232 | /* mfsrin */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4233 | static void gen_mfsrin_64b(DisasContext *ctx) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4234 | { |
| 4235 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4236 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4237 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4238 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4239 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4240 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4241 | return; |
| 4242 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4243 | t0 = tcg_temp_new(); |
| 4244 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); |
| 4245 | tcg_gen_andi_tl(t0, t0, 0xF); |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4246 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4247 | tcg_temp_free(t0); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4248 | #endif |
| 4249 | } |
| 4250 | |
| 4251 | /* mtsr */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4252 | static void gen_mtsr_64b(DisasContext *ctx) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4253 | { |
| 4254 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4255 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4256 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4257 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4258 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4259 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4260 | return; |
| 4261 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4262 | t0 = tcg_const_tl(SR(ctx->opcode)); |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4263 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4264 | tcg_temp_free(t0); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4265 | #endif |
| 4266 | } |
| 4267 | |
| 4268 | /* mtsrin */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4269 | static void gen_mtsrin_64b(DisasContext *ctx) |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4270 | { |
| 4271 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4272 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4273 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4274 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4275 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4276 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4277 | return; |
| 4278 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4279 | t0 = tcg_temp_new(); |
| 4280 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); |
| 4281 | tcg_gen_andi_tl(t0, t0, 0xF); |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4282 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4283 | tcg_temp_free(t0); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4284 | #endif |
| 4285 | } |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4286 | |
| 4287 | /* slbmte */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 4288 | static void gen_slbmte(DisasContext *ctx) |
blueswir1 | f6b868fc | 2009-03-07 20:50:01 +0000 | [diff] [blame] | 4289 | { |
| 4290 | #if defined(CONFIG_USER_ONLY) |
| 4291 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4292 | #else |
| 4293 | if (unlikely(!ctx->mem_idx)) { |
| 4294 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4295 | return; |
| 4296 | } |
| 4297 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 4298 | #endif |
| 4299 | } |
| 4300 | |
David Gibson | efdef95 | 2011-04-01 15:15:11 +1100 | [diff] [blame] | 4301 | static void gen_slbmfee(DisasContext *ctx) |
| 4302 | { |
| 4303 | #if defined(CONFIG_USER_ONLY) |
| 4304 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4305 | #else |
| 4306 | if (unlikely(!ctx->mem_idx)) { |
| 4307 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4308 | return; |
| 4309 | } |
| 4310 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], |
| 4311 | cpu_gpr[rB(ctx->opcode)]); |
| 4312 | #endif |
| 4313 | } |
| 4314 | |
| 4315 | static void gen_slbmfev(DisasContext *ctx) |
| 4316 | { |
| 4317 | #if defined(CONFIG_USER_ONLY) |
| 4318 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4319 | #else |
| 4320 | if (unlikely(!ctx->mem_idx)) { |
| 4321 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| 4322 | return; |
| 4323 | } |
| 4324 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], |
| 4325 | cpu_gpr[rB(ctx->opcode)]); |
| 4326 | #endif |
| 4327 | } |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 4328 | #endif /* defined(TARGET_PPC64) */ |
| 4329 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4330 | /*** Lookaside buffer management ***/ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4331 | /* Optional & mem_idx only: */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4332 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 4333 | /* tlbia */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4334 | static void gen_tlbia(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4335 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4336 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4337 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4338 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4339 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4340 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4341 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4342 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4343 | gen_helper_tlbia(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4344 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4345 | } |
| 4346 | |
blueswir1 | bf14b1c | 2009-03-07 20:52:22 +0000 | [diff] [blame] | 4347 | /* tlbiel */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4348 | static void gen_tlbiel(DisasContext *ctx) |
blueswir1 | bf14b1c | 2009-03-07 20:52:22 +0000 | [diff] [blame] | 4349 | { |
| 4350 | #if defined(CONFIG_USER_ONLY) |
| 4351 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 4352 | #else |
| 4353 | if (unlikely(!ctx->mem_idx)) { |
| 4354 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 4355 | return; |
| 4356 | } |
| 4357 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
| 4358 | #endif |
| 4359 | } |
| 4360 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4361 | /* tlbie */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4362 | static void gen_tlbie(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4363 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4364 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4365 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4366 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4367 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4368 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4369 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4370 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4371 | #if defined(TARGET_PPC64) |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4372 | if (!ctx->sf_mode) { |
| 4373 | TCGv t0 = tcg_temp_new(); |
| 4374 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
| 4375 | gen_helper_tlbie(t0); |
| 4376 | tcg_temp_free(t0); |
| 4377 | } else |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4378 | #endif |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4379 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4380 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4381 | } |
| 4382 | |
| 4383 | /* tlbsync */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4384 | static void gen_tlbsync(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4385 | { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4386 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4387 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4388 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4389 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4390 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 4391 | return; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4392 | } |
| 4393 | /* This has no effect: it should ensure that all previous |
| 4394 | * tlbie have completed |
| 4395 | */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4396 | gen_stop_exception(ctx); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 4397 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4398 | } |
| 4399 | |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4400 | #if defined(TARGET_PPC64) |
| 4401 | /* slbia */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4402 | static void gen_slbia(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4403 | { |
| 4404 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4405 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4406 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4407 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4408 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4409 | return; |
| 4410 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4411 | gen_helper_slbia(); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4412 | #endif |
| 4413 | } |
| 4414 | |
| 4415 | /* slbie */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4416 | static void gen_slbie(DisasContext *ctx) |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4417 | { |
| 4418 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4419 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4420 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4421 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 4422 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4423 | return; |
| 4424 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 4425 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 426613d | 2007-03-23 09:45:27 +0000 | [diff] [blame] | 4426 | #endif |
| 4427 | } |
| 4428 | #endif |
| 4429 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4430 | /*** External control ***/ |
| 4431 | /* Optional: */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4432 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 4433 | /* eciwx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4434 | static void gen_eciwx(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4435 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4436 | TCGv t0; |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4437 | /* Should check EAR[E] ! */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4438 | gen_set_access_type(ctx, ACCESS_EXT); |
| 4439 | t0 = tcg_temp_new(); |
| 4440 | gen_addr_reg_index(ctx, t0); |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4441 | gen_check_align(ctx, t0, 0x03); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4442 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4443 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4444 | } |
| 4445 | |
| 4446 | /* ecowx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4447 | static void gen_ecowx(DisasContext *ctx) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4448 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4449 | TCGv t0; |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4450 | /* Should check EAR[E] ! */ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4451 | gen_set_access_type(ctx, ACCESS_EXT); |
| 4452 | t0 = tcg_temp_new(); |
| 4453 | gen_addr_reg_index(ctx, t0); |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4454 | gen_check_align(ctx, t0, 0x03); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4455 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | fa407c0 | 2008-11-30 16:24:47 +0000 | [diff] [blame] | 4456 | tcg_temp_free(t0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 4457 | } |
| 4458 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4459 | /* PowerPC 601 specific instructions */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4460 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 4461 | /* abs - abs. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4462 | static void gen_abs(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4463 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4464 | int l1 = gen_new_label(); |
| 4465 | int l2 = gen_new_label(); |
| 4466 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
| 4467 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4468 | tcg_gen_br(l2); |
| 4469 | gen_set_label(l1); |
| 4470 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4471 | gen_set_label(l2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4472 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4473 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4474 | } |
| 4475 | |
| 4476 | /* abso - abso. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4477 | static void gen_abso(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4478 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4479 | int l1 = gen_new_label(); |
| 4480 | int l2 = gen_new_label(); |
| 4481 | int l3 = gen_new_label(); |
| 4482 | /* Start with XER OV disabled, the most likely case */ |
| 4483 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 4484 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
| 4485 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); |
| 4486 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 4487 | tcg_gen_br(l2); |
| 4488 | gen_set_label(l1); |
| 4489 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4490 | tcg_gen_br(l3); |
| 4491 | gen_set_label(l2); |
| 4492 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4493 | gen_set_label(l3); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4494 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4495 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4496 | } |
| 4497 | |
| 4498 | /* clcs */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4499 | static void gen_clcs(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4500 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4501 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
| 4502 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); |
| 4503 | tcg_temp_free_i32(t0); |
j_mayer | c7697e1 | 2007-10-26 00:46:07 +0000 | [diff] [blame] | 4504 | /* Rc=1 sets CR0 to an undefined state */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4505 | } |
| 4506 | |
| 4507 | /* div - div. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4508 | static void gen_div(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4509 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4510 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4511 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4512 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4513 | } |
| 4514 | |
| 4515 | /* divo - divo. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4516 | static void gen_divo(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4517 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4518 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4519 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4520 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4521 | } |
| 4522 | |
| 4523 | /* divs - divs. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4524 | static void gen_divs(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4525 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4526 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4527 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4528 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4529 | } |
| 4530 | |
| 4531 | /* divso - divso. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4532 | static void gen_divso(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4533 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4534 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4535 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4536 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4537 | } |
| 4538 | |
| 4539 | /* doz - doz. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4540 | static void gen_doz(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4541 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4542 | int l1 = gen_new_label(); |
| 4543 | int l2 = gen_new_label(); |
| 4544 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
| 4545 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4546 | tcg_gen_br(l2); |
| 4547 | gen_set_label(l1); |
| 4548 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
| 4549 | gen_set_label(l2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4550 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4551 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4552 | } |
| 4553 | |
| 4554 | /* dozo - dozo. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4555 | static void gen_dozo(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4556 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4557 | int l1 = gen_new_label(); |
| 4558 | int l2 = gen_new_label(); |
| 4559 | TCGv t0 = tcg_temp_new(); |
| 4560 | TCGv t1 = tcg_temp_new(); |
| 4561 | TCGv t2 = tcg_temp_new(); |
| 4562 | /* Start with XER OV disabled, the most likely case */ |
| 4563 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 4564 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
| 4565 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4566 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4567 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
| 4568 | tcg_gen_andc_tl(t1, t1, t2); |
| 4569 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 4570 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
| 4571 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 4572 | tcg_gen_br(l2); |
| 4573 | gen_set_label(l1); |
| 4574 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
| 4575 | gen_set_label(l2); |
| 4576 | tcg_temp_free(t0); |
| 4577 | tcg_temp_free(t1); |
| 4578 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4579 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4580 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4581 | } |
| 4582 | |
| 4583 | /* dozi */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4584 | static void gen_dozi(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4585 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4586 | target_long simm = SIMM(ctx->opcode); |
| 4587 | int l1 = gen_new_label(); |
| 4588 | int l2 = gen_new_label(); |
| 4589 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
| 4590 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
| 4591 | tcg_gen_br(l2); |
| 4592 | gen_set_label(l1); |
| 4593 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
| 4594 | gen_set_label(l2); |
| 4595 | if (unlikely(Rc(ctx->opcode) != 0)) |
| 4596 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4597 | } |
| 4598 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4599 | /* lscbx - lscbx. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4600 | static void gen_lscbx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4601 | { |
aurel32 | bdb4b68 | 2008-11-30 16:24:30 +0000 | [diff] [blame] | 4602 | TCGv t0 = tcg_temp_new(); |
| 4603 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
| 4604 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
| 4605 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4606 | |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 4607 | gen_addr_reg_index(ctx, t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4608 | /* NIP cannot be restored if the memory exception comes from an helper */ |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4609 | gen_update_nip(ctx, ctx->nip - 4); |
aurel32 | bdb4b68 | 2008-11-30 16:24:30 +0000 | [diff] [blame] | 4610 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
| 4611 | tcg_temp_free_i32(t1); |
| 4612 | tcg_temp_free_i32(t2); |
| 4613 | tcg_temp_free_i32(t3); |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 4614 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
aurel32 | bdb4b68 | 2008-11-30 16:24:30 +0000 | [diff] [blame] | 4615 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4616 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | bdb4b68 | 2008-11-30 16:24:30 +0000 | [diff] [blame] | 4617 | gen_set_Rc0(ctx, t0); |
| 4618 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4619 | } |
| 4620 | |
| 4621 | /* maskg - maskg. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4622 | static void gen_maskg(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4623 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4624 | int l1 = gen_new_label(); |
| 4625 | TCGv t0 = tcg_temp_new(); |
| 4626 | TCGv t1 = tcg_temp_new(); |
| 4627 | TCGv t2 = tcg_temp_new(); |
| 4628 | TCGv t3 = tcg_temp_new(); |
| 4629 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); |
| 4630 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4631 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); |
| 4632 | tcg_gen_addi_tl(t2, t0, 1); |
| 4633 | tcg_gen_shr_tl(t2, t3, t2); |
| 4634 | tcg_gen_shr_tl(t3, t3, t1); |
| 4635 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
| 4636 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
| 4637 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4638 | gen_set_label(l1); |
| 4639 | tcg_temp_free(t0); |
| 4640 | tcg_temp_free(t1); |
| 4641 | tcg_temp_free(t2); |
| 4642 | tcg_temp_free(t3); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4643 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4644 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4645 | } |
| 4646 | |
| 4647 | /* maskir - maskir. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4648 | static void gen_maskir(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4649 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4650 | TCGv t0 = tcg_temp_new(); |
| 4651 | TCGv t1 = tcg_temp_new(); |
| 4652 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 4653 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 4654 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4655 | tcg_temp_free(t0); |
| 4656 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4657 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4658 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4659 | } |
| 4660 | |
| 4661 | /* mul - mul. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4662 | static void gen_mul(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4663 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4664 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 4665 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 4666 | TCGv t2 = tcg_temp_new(); |
| 4667 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 4668 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 4669 | tcg_gen_mul_i64(t0, t0, t1); |
| 4670 | tcg_gen_trunc_i64_tl(t2, t0); |
| 4671 | gen_store_spr(SPR_MQ, t2); |
| 4672 | tcg_gen_shri_i64(t1, t0, 32); |
| 4673 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
| 4674 | tcg_temp_free_i64(t0); |
| 4675 | tcg_temp_free_i64(t1); |
| 4676 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4677 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4678 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4679 | } |
| 4680 | |
| 4681 | /* mulo - mulo. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4682 | static void gen_mulo(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4683 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4684 | int l1 = gen_new_label(); |
| 4685 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 4686 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 4687 | TCGv t2 = tcg_temp_new(); |
| 4688 | /* Start with XER OV disabled, the most likely case */ |
| 4689 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 4690 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 4691 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 4692 | tcg_gen_mul_i64(t0, t0, t1); |
| 4693 | tcg_gen_trunc_i64_tl(t2, t0); |
| 4694 | gen_store_spr(SPR_MQ, t2); |
| 4695 | tcg_gen_shri_i64(t1, t0, 32); |
| 4696 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
| 4697 | tcg_gen_ext32s_i64(t1, t0); |
| 4698 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
| 4699 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 4700 | gen_set_label(l1); |
| 4701 | tcg_temp_free_i64(t0); |
| 4702 | tcg_temp_free_i64(t1); |
| 4703 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4704 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4705 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4706 | } |
| 4707 | |
| 4708 | /* nabs - nabs. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4709 | static void gen_nabs(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4710 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4711 | int l1 = gen_new_label(); |
| 4712 | int l2 = gen_new_label(); |
| 4713 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
| 4714 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4715 | tcg_gen_br(l2); |
| 4716 | gen_set_label(l1); |
| 4717 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4718 | gen_set_label(l2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4719 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4720 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4721 | } |
| 4722 | |
| 4723 | /* nabso - nabso. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4724 | static void gen_nabso(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4725 | { |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4726 | int l1 = gen_new_label(); |
| 4727 | int l2 = gen_new_label(); |
| 4728 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
| 4729 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4730 | tcg_gen_br(l2); |
| 4731 | gen_set_label(l1); |
| 4732 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 4733 | gen_set_label(l2); |
| 4734 | /* nabs never overflows */ |
| 4735 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4736 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 4737 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4738 | } |
| 4739 | |
| 4740 | /* rlmi - rlmi. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4741 | static void gen_rlmi(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4742 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4743 | uint32_t mb = MB(ctx->opcode); |
| 4744 | uint32_t me = ME(ctx->opcode); |
| 4745 | TCGv t0 = tcg_temp_new(); |
| 4746 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4747 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 4748 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
| 4749 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); |
| 4750 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
| 4751 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4752 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4753 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4754 | } |
| 4755 | |
| 4756 | /* rrib - rrib. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4757 | static void gen_rrib(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4758 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4759 | TCGv t0 = tcg_temp_new(); |
| 4760 | TCGv t1 = tcg_temp_new(); |
| 4761 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4762 | tcg_gen_movi_tl(t1, 0x80000000); |
| 4763 | tcg_gen_shr_tl(t1, t1, t0); |
| 4764 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 4765 | tcg_gen_and_tl(t0, t0, t1); |
| 4766 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
| 4767 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4768 | tcg_temp_free(t0); |
| 4769 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4770 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4771 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4772 | } |
| 4773 | |
| 4774 | /* sle - sle. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4775 | static void gen_sle(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4776 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4777 | TCGv t0 = tcg_temp_new(); |
| 4778 | TCGv t1 = tcg_temp_new(); |
| 4779 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4780 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
| 4781 | tcg_gen_subfi_tl(t1, 32, t1); |
| 4782 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
| 4783 | tcg_gen_or_tl(t1, t0, t1); |
| 4784 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 4785 | gen_store_spr(SPR_MQ, t1); |
| 4786 | tcg_temp_free(t0); |
| 4787 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4788 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4789 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4790 | } |
| 4791 | |
| 4792 | /* sleq - sleq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4793 | static void gen_sleq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4794 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4795 | TCGv t0 = tcg_temp_new(); |
| 4796 | TCGv t1 = tcg_temp_new(); |
| 4797 | TCGv t2 = tcg_temp_new(); |
| 4798 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4799 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); |
| 4800 | tcg_gen_shl_tl(t2, t2, t0); |
| 4801 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 4802 | gen_load_spr(t1, SPR_MQ); |
| 4803 | gen_store_spr(SPR_MQ, t0); |
| 4804 | tcg_gen_and_tl(t0, t0, t2); |
| 4805 | tcg_gen_andc_tl(t1, t1, t2); |
| 4806 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4807 | tcg_temp_free(t0); |
| 4808 | tcg_temp_free(t1); |
| 4809 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4810 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4811 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4812 | } |
| 4813 | |
| 4814 | /* sliq - sliq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4815 | static void gen_sliq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4816 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4817 | int sh = SH(ctx->opcode); |
| 4818 | TCGv t0 = tcg_temp_new(); |
| 4819 | TCGv t1 = tcg_temp_new(); |
| 4820 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 4821 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
| 4822 | tcg_gen_or_tl(t1, t0, t1); |
| 4823 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 4824 | gen_store_spr(SPR_MQ, t1); |
| 4825 | tcg_temp_free(t0); |
| 4826 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4827 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4828 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4829 | } |
| 4830 | |
| 4831 | /* slliq - slliq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4832 | static void gen_slliq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4833 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4834 | int sh = SH(ctx->opcode); |
| 4835 | TCGv t0 = tcg_temp_new(); |
| 4836 | TCGv t1 = tcg_temp_new(); |
| 4837 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 4838 | gen_load_spr(t1, SPR_MQ); |
| 4839 | gen_store_spr(SPR_MQ, t0); |
| 4840 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); |
| 4841 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); |
| 4842 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4843 | tcg_temp_free(t0); |
| 4844 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4845 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4846 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4847 | } |
| 4848 | |
| 4849 | /* sllq - sllq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4850 | static void gen_sllq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4851 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4852 | int l1 = gen_new_label(); |
| 4853 | int l2 = gen_new_label(); |
| 4854 | TCGv t0 = tcg_temp_local_new(); |
| 4855 | TCGv t1 = tcg_temp_local_new(); |
| 4856 | TCGv t2 = tcg_temp_local_new(); |
| 4857 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4858 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
| 4859 | tcg_gen_shl_tl(t1, t1, t2); |
| 4860 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 4861 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 4862 | gen_load_spr(t0, SPR_MQ); |
| 4863 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4864 | tcg_gen_br(l2); |
| 4865 | gen_set_label(l1); |
| 4866 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
| 4867 | gen_load_spr(t2, SPR_MQ); |
| 4868 | tcg_gen_andc_tl(t1, t2, t1); |
| 4869 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 4870 | gen_set_label(l2); |
| 4871 | tcg_temp_free(t0); |
| 4872 | tcg_temp_free(t1); |
| 4873 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4874 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4875 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4876 | } |
| 4877 | |
| 4878 | /* slq - slq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4879 | static void gen_slq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4880 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4881 | int l1 = gen_new_label(); |
| 4882 | TCGv t0 = tcg_temp_new(); |
| 4883 | TCGv t1 = tcg_temp_new(); |
| 4884 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4885 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
| 4886 | tcg_gen_subfi_tl(t1, 32, t1); |
| 4887 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
| 4888 | tcg_gen_or_tl(t1, t0, t1); |
| 4889 | gen_store_spr(SPR_MQ, t1); |
| 4890 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 4891 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 4892 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
| 4893 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 4894 | gen_set_label(l1); |
| 4895 | tcg_temp_free(t0); |
| 4896 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4897 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4898 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4899 | } |
| 4900 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 4901 | /* sraiq - sraiq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4902 | static void gen_sraiq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4903 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4904 | int sh = SH(ctx->opcode); |
| 4905 | int l1 = gen_new_label(); |
| 4906 | TCGv t0 = tcg_temp_new(); |
| 4907 | TCGv t1 = tcg_temp_new(); |
| 4908 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 4909 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
| 4910 | tcg_gen_or_tl(t0, t0, t1); |
| 4911 | gen_store_spr(SPR_MQ, t0); |
| 4912 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
| 4913 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
| 4914 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
| 4915 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); |
| 4916 | gen_set_label(l1); |
| 4917 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
| 4918 | tcg_temp_free(t0); |
| 4919 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4920 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4921 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4922 | } |
| 4923 | |
| 4924 | /* sraq - sraq. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4925 | static void gen_sraq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4926 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4927 | int l1 = gen_new_label(); |
| 4928 | int l2 = gen_new_label(); |
| 4929 | TCGv t0 = tcg_temp_new(); |
| 4930 | TCGv t1 = tcg_temp_local_new(); |
| 4931 | TCGv t2 = tcg_temp_local_new(); |
| 4932 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4933 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
| 4934 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
| 4935 | tcg_gen_subfi_tl(t2, 32, t2); |
| 4936 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
| 4937 | tcg_gen_or_tl(t0, t0, t2); |
| 4938 | gen_store_spr(SPR_MQ, t0); |
| 4939 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 4940 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); |
| 4941 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
| 4942 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); |
| 4943 | gen_set_label(l1); |
| 4944 | tcg_temp_free(t0); |
| 4945 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
| 4946 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
| 4947 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
| 4948 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); |
| 4949 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); |
| 4950 | gen_set_label(l2); |
| 4951 | tcg_temp_free(t1); |
| 4952 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4953 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4954 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4955 | } |
| 4956 | |
| 4957 | /* sre - sre. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4958 | static void gen_sre(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4959 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4960 | TCGv t0 = tcg_temp_new(); |
| 4961 | TCGv t1 = tcg_temp_new(); |
| 4962 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4963 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
| 4964 | tcg_gen_subfi_tl(t1, 32, t1); |
| 4965 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
| 4966 | tcg_gen_or_tl(t1, t0, t1); |
| 4967 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 4968 | gen_store_spr(SPR_MQ, t1); |
| 4969 | tcg_temp_free(t0); |
| 4970 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4971 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4972 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4973 | } |
| 4974 | |
| 4975 | /* srea - srea. */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4976 | static void gen_srea(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4977 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4978 | TCGv t0 = tcg_temp_new(); |
| 4979 | TCGv t1 = tcg_temp_new(); |
| 4980 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4981 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
| 4982 | gen_store_spr(SPR_MQ, t0); |
| 4983 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
| 4984 | tcg_temp_free(t0); |
| 4985 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4986 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4987 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4988 | } |
| 4989 | |
| 4990 | /* sreq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 4991 | static void gen_sreq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4992 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 4993 | TCGv t0 = tcg_temp_new(); |
| 4994 | TCGv t1 = tcg_temp_new(); |
| 4995 | TCGv t2 = tcg_temp_new(); |
| 4996 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 4997 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
| 4998 | tcg_gen_shr_tl(t1, t1, t0); |
| 4999 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
| 5000 | gen_load_spr(t2, SPR_MQ); |
| 5001 | gen_store_spr(SPR_MQ, t0); |
| 5002 | tcg_gen_and_tl(t0, t0, t1); |
| 5003 | tcg_gen_andc_tl(t2, t2, t1); |
| 5004 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
| 5005 | tcg_temp_free(t0); |
| 5006 | tcg_temp_free(t1); |
| 5007 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5008 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5009 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5010 | } |
| 5011 | |
| 5012 | /* sriq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5013 | static void gen_sriq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5014 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5015 | int sh = SH(ctx->opcode); |
| 5016 | TCGv t0 = tcg_temp_new(); |
| 5017 | TCGv t1 = tcg_temp_new(); |
| 5018 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 5019 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
| 5020 | tcg_gen_or_tl(t1, t0, t1); |
| 5021 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 5022 | gen_store_spr(SPR_MQ, t1); |
| 5023 | tcg_temp_free(t0); |
| 5024 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5025 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5026 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5027 | } |
| 5028 | |
| 5029 | /* srliq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5030 | static void gen_srliq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5031 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5032 | int sh = SH(ctx->opcode); |
| 5033 | TCGv t0 = tcg_temp_new(); |
| 5034 | TCGv t1 = tcg_temp_new(); |
| 5035 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
| 5036 | gen_load_spr(t1, SPR_MQ); |
| 5037 | gen_store_spr(SPR_MQ, t0); |
| 5038 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); |
| 5039 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); |
| 5040 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 5041 | tcg_temp_free(t0); |
| 5042 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5043 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5044 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5045 | } |
| 5046 | |
| 5047 | /* srlq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5048 | static void gen_srlq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5049 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5050 | int l1 = gen_new_label(); |
| 5051 | int l2 = gen_new_label(); |
| 5052 | TCGv t0 = tcg_temp_local_new(); |
| 5053 | TCGv t1 = tcg_temp_local_new(); |
| 5054 | TCGv t2 = tcg_temp_local_new(); |
| 5055 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 5056 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
| 5057 | tcg_gen_shr_tl(t2, t1, t2); |
| 5058 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 5059 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 5060 | gen_load_spr(t0, SPR_MQ); |
| 5061 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
| 5062 | tcg_gen_br(l2); |
| 5063 | gen_set_label(l1); |
| 5064 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
| 5065 | tcg_gen_and_tl(t0, t0, t2); |
| 5066 | gen_load_spr(t1, SPR_MQ); |
| 5067 | tcg_gen_andc_tl(t1, t1, t2); |
| 5068 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
| 5069 | gen_set_label(l2); |
| 5070 | tcg_temp_free(t0); |
| 5071 | tcg_temp_free(t1); |
| 5072 | tcg_temp_free(t2); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5073 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5074 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5075 | } |
| 5076 | |
| 5077 | /* srq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5078 | static void gen_srq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5079 | { |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5080 | int l1 = gen_new_label(); |
| 5081 | TCGv t0 = tcg_temp_new(); |
| 5082 | TCGv t1 = tcg_temp_new(); |
| 5083 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
| 5084 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
| 5085 | tcg_gen_subfi_tl(t1, 32, t1); |
| 5086 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
| 5087 | tcg_gen_or_tl(t1, t0, t1); |
| 5088 | gen_store_spr(SPR_MQ, t1); |
| 5089 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); |
| 5090 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
| 5091 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
| 5092 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
| 5093 | gen_set_label(l1); |
| 5094 | tcg_temp_free(t0); |
| 5095 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5096 | if (unlikely(Rc(ctx->opcode) != 0)) |
aurel32 | 7487953 | 2008-12-05 07:21:44 +0000 | [diff] [blame] | 5097 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5098 | } |
| 5099 | |
| 5100 | /* PowerPC 602 specific instructions */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5101 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5102 | /* dsa */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5103 | static void gen_dsa(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5104 | { |
| 5105 | /* XXX: TODO */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5106 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5107 | } |
| 5108 | |
| 5109 | /* esa */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5110 | static void gen_esa(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5111 | { |
| 5112 | /* XXX: TODO */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5113 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5114 | } |
| 5115 | |
| 5116 | /* mfrom */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5117 | static void gen_mfrom(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5118 | { |
| 5119 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5120 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5121 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5122 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5123 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5124 | return; |
| 5125 | } |
aurel32 | cf02a65 | 2008-11-30 16:23:35 +0000 | [diff] [blame] | 5126 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5127 | #endif |
| 5128 | } |
| 5129 | |
| 5130 | /* 602 - 603 - G2 TLB management */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5131 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5132 | /* tlbld */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5133 | static void gen_tlbld_6xx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5134 | { |
| 5135 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5136 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5137 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5138 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5139 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5140 | return; |
| 5141 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5142 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5143 | #endif |
| 5144 | } |
| 5145 | |
| 5146 | /* tlbli */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5147 | static void gen_tlbli_6xx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5148 | { |
| 5149 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5150 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5151 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5152 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5153 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5154 | return; |
| 5155 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5156 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5157 | #endif |
| 5158 | } |
| 5159 | |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5160 | /* 74xx TLB management */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5161 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5162 | /* tlbld */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5163 | static void gen_tlbld_74xx(DisasContext *ctx) |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5164 | { |
| 5165 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5166 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5167 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5168 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5169 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5170 | return; |
| 5171 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5172 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5173 | #endif |
| 5174 | } |
| 5175 | |
| 5176 | /* tlbli */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5177 | static void gen_tlbli_74xx(DisasContext *ctx) |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5178 | { |
| 5179 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5180 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5181 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5182 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5183 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5184 | return; |
| 5185 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5186 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 7dbe11a | 2007-10-01 05:16:57 +0000 | [diff] [blame] | 5187 | #endif |
| 5188 | } |
| 5189 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5190 | /* POWER instructions not in PowerPC 601 */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5191 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5192 | /* clf */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5193 | static void gen_clf(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5194 | { |
| 5195 | /* Cache line flush: implemented as no-op */ |
| 5196 | } |
| 5197 | |
| 5198 | /* cli */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5199 | static void gen_cli(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5200 | { |
blueswir1 | 7f75ffd | 2007-05-27 19:39:27 +0000 | [diff] [blame] | 5201 | /* Cache line invalidate: privileged and treated as no-op */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5202 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5203 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5204 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5205 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5206 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5207 | return; |
| 5208 | } |
| 5209 | #endif |
| 5210 | } |
| 5211 | |
| 5212 | /* dclst */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5213 | static void gen_dclst(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5214 | { |
| 5215 | /* Data cache line store: treated as no-op */ |
| 5216 | } |
| 5217 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5218 | static void gen_mfsri(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5219 | { |
| 5220 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5221 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5222 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5223 | int ra = rA(ctx->opcode); |
| 5224 | int rd = rD(ctx->opcode); |
| 5225 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5226 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5227 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5228 | return; |
| 5229 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5230 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5231 | gen_addr_reg_index(ctx, t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5232 | tcg_gen_shri_tl(t0, t0, 28); |
| 5233 | tcg_gen_andi_tl(t0, t0, 0xF); |
| 5234 | gen_helper_load_sr(cpu_gpr[rd], t0); |
| 5235 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5236 | if (ra != 0 && ra != rd) |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5237 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5238 | #endif |
| 5239 | } |
| 5240 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5241 | static void gen_rac(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5242 | { |
| 5243 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5244 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5245 | #else |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 5246 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5247 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5248 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5249 | return; |
| 5250 | } |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 5251 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5252 | gen_addr_reg_index(ctx, t0); |
aurel32 | 22e0e17 | 2008-12-06 12:19:14 +0000 | [diff] [blame] | 5253 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
| 5254 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5255 | #endif |
| 5256 | } |
| 5257 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5258 | static void gen_rfsvc(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5259 | { |
| 5260 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5261 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5262 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5263 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5264 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5265 | return; |
| 5266 | } |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 5267 | gen_helper_rfsvc(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5268 | gen_sync_exception(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5269 | #endif |
| 5270 | } |
| 5271 | |
| 5272 | /* svc is not implemented for now */ |
| 5273 | |
| 5274 | /* POWER2 specific instructions */ |
| 5275 | /* Quad manipulation (load/store two floats at a time) */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5276 | |
| 5277 | /* lfq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5278 | static void gen_lfq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5279 | { |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5280 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5281 | TCGv t0; |
| 5282 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5283 | t0 = tcg_temp_new(); |
| 5284 | gen_addr_imm_index(ctx, t0, 0); |
| 5285 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
| 5286 | gen_addr_add(ctx, t0, t0, 8); |
| 5287 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5288 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5289 | } |
| 5290 | |
| 5291 | /* lfqu */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5292 | static void gen_lfqu(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5293 | { |
| 5294 | int ra = rA(ctx->opcode); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5295 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5296 | TCGv t0, t1; |
| 5297 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5298 | t0 = tcg_temp_new(); |
| 5299 | t1 = tcg_temp_new(); |
| 5300 | gen_addr_imm_index(ctx, t0, 0); |
| 5301 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
| 5302 | gen_addr_add(ctx, t1, t0, 8); |
| 5303 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5304 | if (ra != 0) |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5305 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
| 5306 | tcg_temp_free(t0); |
| 5307 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5308 | } |
| 5309 | |
| 5310 | /* lfqux */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5311 | static void gen_lfqux(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5312 | { |
| 5313 | int ra = rA(ctx->opcode); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5314 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5315 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5316 | TCGv t0, t1; |
| 5317 | t0 = tcg_temp_new(); |
| 5318 | gen_addr_reg_index(ctx, t0); |
| 5319 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
| 5320 | t1 = tcg_temp_new(); |
| 5321 | gen_addr_add(ctx, t1, t0, 8); |
| 5322 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
| 5323 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5324 | if (ra != 0) |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5325 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
| 5326 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5327 | } |
| 5328 | |
| 5329 | /* lfqx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5330 | static void gen_lfqx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5331 | { |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5332 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5333 | TCGv t0; |
| 5334 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5335 | t0 = tcg_temp_new(); |
| 5336 | gen_addr_reg_index(ctx, t0); |
| 5337 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
| 5338 | gen_addr_add(ctx, t0, t0, 8); |
| 5339 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5340 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5341 | } |
| 5342 | |
| 5343 | /* stfq */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5344 | static void gen_stfq(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5345 | { |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5346 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5347 | TCGv t0; |
| 5348 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5349 | t0 = tcg_temp_new(); |
| 5350 | gen_addr_imm_index(ctx, t0, 0); |
| 5351 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
| 5352 | gen_addr_add(ctx, t0, t0, 8); |
| 5353 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5354 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5355 | } |
| 5356 | |
| 5357 | /* stfqu */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5358 | static void gen_stfqu(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5359 | { |
| 5360 | int ra = rA(ctx->opcode); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5361 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5362 | TCGv t0, t1; |
| 5363 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5364 | t0 = tcg_temp_new(); |
| 5365 | gen_addr_imm_index(ctx, t0, 0); |
| 5366 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
| 5367 | t1 = tcg_temp_new(); |
| 5368 | gen_addr_add(ctx, t1, t0, 8); |
| 5369 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
| 5370 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5371 | if (ra != 0) |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5372 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
| 5373 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5374 | } |
| 5375 | |
| 5376 | /* stfqux */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5377 | static void gen_stfqux(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5378 | { |
| 5379 | int ra = rA(ctx->opcode); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5380 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5381 | TCGv t0, t1; |
| 5382 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5383 | t0 = tcg_temp_new(); |
| 5384 | gen_addr_reg_index(ctx, t0); |
| 5385 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
| 5386 | t1 = tcg_temp_new(); |
| 5387 | gen_addr_add(ctx, t1, t0, 8); |
| 5388 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
| 5389 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5390 | if (ra != 0) |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5391 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
| 5392 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5393 | } |
| 5394 | |
| 5395 | /* stfqx */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5396 | static void gen_stfqx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5397 | { |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5398 | int rd = rD(ctx->opcode); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5399 | TCGv t0; |
| 5400 | gen_set_access_type(ctx, ACCESS_FLOAT); |
| 5401 | t0 = tcg_temp_new(); |
| 5402 | gen_addr_reg_index(ctx, t0); |
| 5403 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
| 5404 | gen_addr_add(ctx, t0, t0, 8); |
| 5405 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
aurel32 | 01a4afe | 2008-11-27 19:30:56 +0000 | [diff] [blame] | 5406 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5407 | } |
| 5408 | |
| 5409 | /* BookE specific instructions */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5410 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5411 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5412 | static void gen_mfapidi(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5413 | { |
| 5414 | /* XXX: TODO */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5415 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5416 | } |
| 5417 | |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5418 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5419 | static void gen_tlbiva(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5420 | { |
| 5421 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5422 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5423 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5424 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5425 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5426 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5427 | return; |
| 5428 | } |
aurel32 | ec72e27 | 2008-12-07 15:45:15 +0000 | [diff] [blame] | 5429 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5430 | gen_addr_reg_index(ctx, t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5431 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
| 5432 | tcg_temp_free(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5433 | #endif |
| 5434 | } |
| 5435 | |
| 5436 | /* All 405 MAC instructions are translated here */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 5437 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
| 5438 | int ra, int rb, int rt, int Rc) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5439 | { |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5440 | TCGv t0, t1; |
| 5441 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5442 | t0 = tcg_temp_local_new(); |
| 5443 | t1 = tcg_temp_local_new(); |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5444 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5445 | switch (opc3 & 0x0D) { |
| 5446 | case 0x05: |
| 5447 | /* macchw - macchw. - macchwo - macchwo. */ |
| 5448 | /* macchws - macchws. - macchwso - macchwso. */ |
| 5449 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ |
| 5450 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ |
| 5451 | /* mulchw - mulchw. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5452 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
| 5453 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); |
| 5454 | tcg_gen_ext16s_tl(t1, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5455 | break; |
| 5456 | case 0x04: |
| 5457 | /* macchwu - macchwu. - macchwuo - macchwuo. */ |
| 5458 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ |
| 5459 | /* mulchwu - mulchwu. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5460 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
| 5461 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); |
| 5462 | tcg_gen_ext16u_tl(t1, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5463 | break; |
| 5464 | case 0x01: |
| 5465 | /* machhw - machhw. - machhwo - machhwo. */ |
| 5466 | /* machhws - machhws. - machhwso - machhwso. */ |
| 5467 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ |
| 5468 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ |
| 5469 | /* mulhhw - mulhhw. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5470 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
| 5471 | tcg_gen_ext16s_tl(t0, t0); |
| 5472 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); |
| 5473 | tcg_gen_ext16s_tl(t1, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5474 | break; |
| 5475 | case 0x00: |
| 5476 | /* machhwu - machhwu. - machhwuo - machhwuo. */ |
| 5477 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ |
| 5478 | /* mulhhwu - mulhhwu. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5479 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
| 5480 | tcg_gen_ext16u_tl(t0, t0); |
| 5481 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); |
| 5482 | tcg_gen_ext16u_tl(t1, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5483 | break; |
| 5484 | case 0x0D: |
| 5485 | /* maclhw - maclhw. - maclhwo - maclhwo. */ |
| 5486 | /* maclhws - maclhws. - maclhwso - maclhwso. */ |
| 5487 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ |
| 5488 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ |
| 5489 | /* mullhw - mullhw. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5490 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
| 5491 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5492 | break; |
| 5493 | case 0x0C: |
| 5494 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ |
| 5495 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ |
| 5496 | /* mullhwu - mullhwu. */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5497 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
| 5498 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5499 | break; |
| 5500 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5501 | if (opc2 & 0x04) { |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5502 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
| 5503 | tcg_gen_mul_tl(t1, t0, t1); |
| 5504 | if (opc2 & 0x02) { |
| 5505 | /* nmultiply-and-accumulate (0x0E) */ |
| 5506 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
| 5507 | } else { |
| 5508 | /* multiply-and-accumulate (0x0C) */ |
| 5509 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
| 5510 | } |
| 5511 | |
| 5512 | if (opc3 & 0x12) { |
| 5513 | /* Check overflow and/or saturate */ |
| 5514 | int l1 = gen_new_label(); |
| 5515 | |
| 5516 | if (opc3 & 0x10) { |
| 5517 | /* Start with XER OV disabled, the most likely case */ |
| 5518 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); |
| 5519 | } |
| 5520 | if (opc3 & 0x01) { |
| 5521 | /* Signed */ |
| 5522 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
| 5523 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); |
| 5524 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
| 5525 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); |
aurel32 | bdc4e05 | 2008-11-09 17:27:03 +0000 | [diff] [blame] | 5526 | if (opc3 & 0x02) { |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5527 | /* Saturate */ |
| 5528 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); |
| 5529 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); |
| 5530 | } |
| 5531 | } else { |
| 5532 | /* Unsigned */ |
| 5533 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
aurel32 | bdc4e05 | 2008-11-09 17:27:03 +0000 | [diff] [blame] | 5534 | if (opc3 & 0x02) { |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5535 | /* Saturate */ |
| 5536 | tcg_gen_movi_tl(t0, UINT32_MAX); |
| 5537 | } |
| 5538 | } |
| 5539 | if (opc3 & 0x10) { |
| 5540 | /* Check overflow */ |
| 5541 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); |
| 5542 | } |
| 5543 | gen_set_label(l1); |
| 5544 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
| 5545 | } |
| 5546 | } else { |
| 5547 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5548 | } |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5549 | tcg_temp_free(t0); |
| 5550 | tcg_temp_free(t1); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5551 | if (unlikely(Rc) != 0) { |
| 5552 | /* Update Rc0 */ |
aurel32 | 182608d | 2008-11-01 00:54:23 +0000 | [diff] [blame] | 5553 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5554 | } |
| 5555 | } |
| 5556 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5557 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5558 | static void glue(gen_, name)(DisasContext *ctx) \ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5559 | { \ |
| 5560 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
| 5561 | rD(ctx->opcode), Rc(ctx->opcode)); \ |
| 5562 | } |
| 5563 | |
| 5564 | /* macchw - macchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5565 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5566 | /* macchwo - macchwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5567 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5568 | /* macchws - macchws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5569 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5570 | /* macchwso - macchwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5571 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5572 | /* macchwsu - macchwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5573 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5574 | /* macchwsuo - macchwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5575 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5576 | /* macchwu - macchwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5577 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5578 | /* macchwuo - macchwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5579 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5580 | /* machhw - machhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5581 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5582 | /* machhwo - machhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5583 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5584 | /* machhws - machhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5585 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5586 | /* machhwso - machhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5587 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5588 | /* machhwsu - machhwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5589 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5590 | /* machhwsuo - machhwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5591 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5592 | /* machhwu - machhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5593 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5594 | /* machhwuo - machhwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5595 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5596 | /* maclhw - maclhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5597 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5598 | /* maclhwo - maclhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5599 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5600 | /* maclhws - maclhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5601 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5602 | /* maclhwso - maclhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5603 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5604 | /* maclhwu - maclhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5605 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5606 | /* maclhwuo - maclhwuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5607 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5608 | /* maclhwsu - maclhwsu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5609 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5610 | /* maclhwsuo - maclhwsuo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5611 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5612 | /* nmacchw - nmacchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5613 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5614 | /* nmacchwo - nmacchwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5615 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5616 | /* nmacchws - nmacchws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5617 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5618 | /* nmacchwso - nmacchwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5619 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5620 | /* nmachhw - nmachhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5621 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5622 | /* nmachhwo - nmachhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5623 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5624 | /* nmachhws - nmachhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5625 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5626 | /* nmachhwso - nmachhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5627 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5628 | /* nmaclhw - nmaclhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5629 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5630 | /* nmaclhwo - nmaclhwo. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5631 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5632 | /* nmaclhws - nmaclhws. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5633 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5634 | /* nmaclhwso - nmaclhwso. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5635 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5636 | |
| 5637 | /* mulchw - mulchw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5638 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5639 | /* mulchwu - mulchwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5640 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5641 | /* mulhhw - mulhhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5642 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5643 | /* mulhhwu - mulhhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5644 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5645 | /* mullhw - mullhw. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5646 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5647 | /* mullhwu - mullhwu. */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5648 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5649 | |
| 5650 | /* mfdcr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5651 | static void gen_mfdcr(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5652 | { |
| 5653 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5654 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5655 | #else |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5656 | TCGv dcrn; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5657 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5658 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5659 | return; |
| 5660 | } |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5661 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5662 | gen_update_nip(ctx, ctx->nip - 4); |
| 5663 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
| 5664 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); |
| 5665 | tcg_temp_free(dcrn); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5666 | #endif |
| 5667 | } |
| 5668 | |
| 5669 | /* mtdcr */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5670 | static void gen_mtdcr(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5671 | { |
| 5672 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5673 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5674 | #else |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5675 | TCGv dcrn; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5676 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5677 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5678 | return; |
| 5679 | } |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5680 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5681 | gen_update_nip(ctx, ctx->nip - 4); |
| 5682 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
| 5683 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); |
| 5684 | tcg_temp_free(dcrn); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5685 | #endif |
| 5686 | } |
| 5687 | |
| 5688 | /* mfdcrx */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5689 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5690 | static void gen_mfdcrx(DisasContext *ctx) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5691 | { |
| 5692 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5693 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5694 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5695 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5696 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5697 | return; |
| 5698 | } |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5699 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5700 | gen_update_nip(ctx, ctx->nip - 4); |
| 5701 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5702 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5703 | #endif |
| 5704 | } |
| 5705 | |
| 5706 | /* mtdcrx */ |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5707 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5708 | static void gen_mtdcrx(DisasContext *ctx) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5709 | { |
| 5710 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5711 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5712 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5713 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5714 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5715 | return; |
| 5716 | } |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5717 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5718 | gen_update_nip(ctx, ctx->nip - 4); |
| 5719 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5720 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5721 | #endif |
| 5722 | } |
| 5723 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5724 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5725 | static void gen_mfdcrux(DisasContext *ctx) |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5726 | { |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5727 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5728 | gen_update_nip(ctx, ctx->nip - 4); |
| 5729 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5730 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
| 5731 | } |
| 5732 | |
| 5733 | /* mtdcrux (PPC 460) : user-mode access to DCR */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5734 | static void gen_mtdcrux(DisasContext *ctx) |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5735 | { |
aurel32 | 06dca6a | 2008-12-06 16:37:18 +0000 | [diff] [blame] | 5736 | /* NIP cannot be restored if the memory exception comes from an helper */ |
| 5737 | gen_update_nip(ctx, ctx->nip - 4); |
| 5738 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 5739 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
| 5740 | } |
| 5741 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5742 | /* dccci */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5743 | static void gen_dccci(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5744 | { |
| 5745 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5746 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5747 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5748 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5749 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5750 | return; |
| 5751 | } |
| 5752 | /* interpreted as no-op */ |
| 5753 | #endif |
| 5754 | } |
| 5755 | |
| 5756 | /* dcread */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5757 | static void gen_dcread(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5758 | { |
| 5759 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5760 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5761 | #else |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 5762 | TCGv EA, val; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5763 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5764 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5765 | return; |
| 5766 | } |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5767 | gen_set_access_type(ctx, ACCESS_CACHE); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5768 | EA = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5769 | gen_addr_reg_index(ctx, EA); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5770 | val = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5771 | gen_qemu_ld32u(ctx, val, EA); |
aurel32 | b61f275 | 2008-10-15 17:00:37 +0000 | [diff] [blame] | 5772 | tcg_temp_free(val); |
| 5773 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
| 5774 | tcg_temp_free(EA); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5775 | #endif |
| 5776 | } |
| 5777 | |
| 5778 | /* icbt */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5779 | static void gen_icbt_40x(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5780 | { |
| 5781 | /* interpreted as no-op */ |
| 5782 | /* XXX: specification say this is treated as a load by the MMU |
| 5783 | * but does not generate any exception |
| 5784 | */ |
| 5785 | } |
| 5786 | |
| 5787 | /* iccci */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5788 | static void gen_iccci(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5789 | { |
| 5790 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5791 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5792 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5793 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5794 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5795 | return; |
| 5796 | } |
| 5797 | /* interpreted as no-op */ |
| 5798 | #endif |
| 5799 | } |
| 5800 | |
| 5801 | /* icread */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5802 | static void gen_icread(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5803 | { |
| 5804 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5805 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5806 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5807 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5808 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5809 | return; |
| 5810 | } |
| 5811 | /* interpreted as no-op */ |
| 5812 | #endif |
| 5813 | } |
| 5814 | |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5815 | /* rfci (mem_idx only) */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5816 | static void gen_rfci_40x(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5817 | { |
| 5818 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5819 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5820 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5821 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5822 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5823 | return; |
| 5824 | } |
| 5825 | /* Restore CPU state */ |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 5826 | gen_helper_40x_rfci(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5827 | gen_sync_exception(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5828 | #endif |
| 5829 | } |
| 5830 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5831 | static void gen_rfci(DisasContext *ctx) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5832 | { |
| 5833 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5834 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5835 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5836 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5837 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5838 | return; |
| 5839 | } |
| 5840 | /* Restore CPU state */ |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 5841 | gen_helper_rfci(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5842 | gen_sync_exception(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5843 | #endif |
| 5844 | } |
| 5845 | |
| 5846 | /* BookE specific */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5847 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5848 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5849 | static void gen_rfdi(DisasContext *ctx) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5850 | { |
| 5851 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5852 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5853 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5854 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5855 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5856 | return; |
| 5857 | } |
| 5858 | /* Restore CPU state */ |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 5859 | gen_helper_rfdi(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5860 | gen_sync_exception(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5861 | #endif |
| 5862 | } |
| 5863 | |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 5864 | /* XXX: not implemented on 440 ? */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 5865 | static void gen_rfmci(DisasContext *ctx) |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5866 | { |
| 5867 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5868 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5869 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5870 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5871 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5872 | return; |
| 5873 | } |
| 5874 | /* Restore CPU state */ |
aurel32 | d72a19f | 2008-11-30 16:24:55 +0000 | [diff] [blame] | 5875 | gen_helper_rfmci(); |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5876 | gen_sync_exception(ctx); |
j_mayer | a42bd6c | 2007-03-30 10:22:46 +0000 | [diff] [blame] | 5877 | #endif |
| 5878 | } |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5879 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5880 | /* TLB management - PowerPC 405 implementation */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5881 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5882 | /* tlbre */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5883 | static void gen_tlbre_40x(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5884 | { |
| 5885 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5886 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5887 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5888 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5890 | return; |
| 5891 | } |
| 5892 | switch (rB(ctx->opcode)) { |
| 5893 | case 0: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5894 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5895 | break; |
| 5896 | case 1: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5897 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5898 | break; |
| 5899 | default: |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5900 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5901 | break; |
| 5902 | } |
| 5903 | #endif |
| 5904 | } |
| 5905 | |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 5906 | /* tlbsx - tlbsx. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5907 | static void gen_tlbsx_40x(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5908 | { |
| 5909 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5910 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5911 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5912 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5913 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5914 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5915 | return; |
| 5916 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5917 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5918 | gen_addr_reg_index(ctx, t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5919 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
| 5920 | tcg_temp_free(t0); |
| 5921 | if (Rc(ctx->opcode)) { |
| 5922 | int l1 = gen_new_label(); |
| 5923 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
| 5924 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
| 5925 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
| 5926 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
| 5927 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
| 5928 | gen_set_label(l1); |
| 5929 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5930 | #endif |
| 5931 | } |
| 5932 | |
| 5933 | /* tlbwe */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5934 | static void gen_tlbwe_40x(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5935 | { |
| 5936 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5937 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5938 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5939 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5940 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5941 | return; |
| 5942 | } |
| 5943 | switch (rB(ctx->opcode)) { |
| 5944 | case 0: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5945 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5946 | break; |
| 5947 | case 1: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5948 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5949 | break; |
| 5950 | default: |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5951 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 5952 | break; |
| 5953 | } |
| 5954 | #endif |
| 5955 | } |
| 5956 | |
j_mayer | a4bb6c3 | 2007-09-21 05:28:33 +0000 | [diff] [blame] | 5957 | /* TLB management - PowerPC 440 implementation */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5958 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 5959 | /* tlbre */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5960 | static void gen_tlbre_440(DisasContext *ctx) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5961 | { |
| 5962 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5963 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5964 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5965 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5966 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5967 | return; |
| 5968 | } |
| 5969 | switch (rB(ctx->opcode)) { |
| 5970 | case 0: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5971 | case 1: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5972 | case 2: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5973 | { |
| 5974 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
Edgar E. Iglesias | 5823947 | 2011-01-21 23:12:42 +0100 | [diff] [blame] | 5975 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5976 | tcg_temp_free_i32(t0); |
| 5977 | } |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5978 | break; |
| 5979 | default: |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5980 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5981 | break; |
| 5982 | } |
| 5983 | #endif |
| 5984 | } |
| 5985 | |
| 5986 | /* tlbsx - tlbsx. */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 5987 | static void gen_tlbsx_440(DisasContext *ctx) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5988 | { |
| 5989 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5990 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5991 | #else |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5992 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5993 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 5994 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 5995 | return; |
| 5996 | } |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5997 | t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 5998 | gen_addr_reg_index(ctx, t0); |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 5999 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
| 6000 | tcg_temp_free(t0); |
| 6001 | if (Rc(ctx->opcode)) { |
| 6002 | int l1 = gen_new_label(); |
| 6003 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
| 6004 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); |
| 6005 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); |
| 6006 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
| 6007 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
| 6008 | gen_set_label(l1); |
| 6009 | } |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6010 | #endif |
| 6011 | } |
| 6012 | |
| 6013 | /* tlbwe */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 6014 | static void gen_tlbwe_440(DisasContext *ctx) |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6015 | { |
| 6016 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6017 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6018 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6019 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6020 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6021 | return; |
| 6022 | } |
| 6023 | switch (rB(ctx->opcode)) { |
| 6024 | case 0: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6025 | case 1: |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6026 | case 2: |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 6027 | { |
| 6028 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
| 6029 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
| 6030 | tcg_temp_free_i32(t0); |
| 6031 | } |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6032 | break; |
| 6033 | default: |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6034 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 5eb7995 | 2007-09-19 05:44:04 +0000 | [diff] [blame] | 6035 | break; |
| 6036 | } |
| 6037 | #endif |
| 6038 | } |
| 6039 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 6040 | /* TLB management - PowerPC BookE 2.06 implementation */ |
| 6041 | |
| 6042 | /* tlbre */ |
| 6043 | static void gen_tlbre_booke206(DisasContext *ctx) |
| 6044 | { |
| 6045 | #if defined(CONFIG_USER_ONLY) |
| 6046 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6047 | #else |
| 6048 | if (unlikely(!ctx->mem_idx)) { |
| 6049 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6050 | return; |
| 6051 | } |
| 6052 | |
| 6053 | gen_helper_booke206_tlbre(); |
| 6054 | #endif |
| 6055 | } |
| 6056 | |
| 6057 | /* tlbsx - tlbsx. */ |
| 6058 | static void gen_tlbsx_booke206(DisasContext *ctx) |
| 6059 | { |
| 6060 | #if defined(CONFIG_USER_ONLY) |
| 6061 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6062 | #else |
| 6063 | TCGv t0; |
| 6064 | if (unlikely(!ctx->mem_idx)) { |
| 6065 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6066 | return; |
| 6067 | } |
| 6068 | |
| 6069 | if (rA(ctx->opcode)) { |
| 6070 | t0 = tcg_temp_new(); |
| 6071 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); |
| 6072 | } else { |
| 6073 | t0 = tcg_const_tl(0); |
| 6074 | } |
| 6075 | |
| 6076 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); |
| 6077 | gen_helper_booke206_tlbsx(t0); |
| 6078 | #endif |
| 6079 | } |
| 6080 | |
| 6081 | /* tlbwe */ |
| 6082 | static void gen_tlbwe_booke206(DisasContext *ctx) |
| 6083 | { |
| 6084 | #if defined(CONFIG_USER_ONLY) |
| 6085 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6086 | #else |
| 6087 | if (unlikely(!ctx->mem_idx)) { |
| 6088 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6089 | return; |
| 6090 | } |
Alexander Graf | 3f162d1 | 2012-01-25 16:27:26 +0100 | [diff] [blame] | 6091 | gen_update_nip(ctx, ctx->nip - 4); |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 6092 | gen_helper_booke206_tlbwe(); |
| 6093 | #endif |
| 6094 | } |
| 6095 | |
| 6096 | static void gen_tlbivax_booke206(DisasContext *ctx) |
| 6097 | { |
| 6098 | #if defined(CONFIG_USER_ONLY) |
| 6099 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6100 | #else |
| 6101 | TCGv t0; |
| 6102 | if (unlikely(!ctx->mem_idx)) { |
| 6103 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6104 | return; |
| 6105 | } |
| 6106 | |
| 6107 | t0 = tcg_temp_new(); |
| 6108 | gen_addr_reg_index(ctx, t0); |
| 6109 | |
| 6110 | gen_helper_booke206_tlbivax(t0); |
| 6111 | #endif |
| 6112 | } |
| 6113 | |
Alexander Graf | 6d3db82 | 2012-01-20 04:09:15 +0100 | [diff] [blame] | 6114 | static void gen_tlbilx_booke206(DisasContext *ctx) |
| 6115 | { |
| 6116 | #if defined(CONFIG_USER_ONLY) |
| 6117 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6118 | #else |
| 6119 | TCGv t0; |
| 6120 | if (unlikely(!ctx->mem_idx)) { |
| 6121 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6122 | return; |
| 6123 | } |
| 6124 | |
| 6125 | t0 = tcg_temp_new(); |
| 6126 | gen_addr_reg_index(ctx, t0); |
| 6127 | |
| 6128 | switch((ctx->opcode >> 21) & 0x3) { |
| 6129 | case 0: |
| 6130 | gen_helper_booke206_tlbilx0(t0); |
| 6131 | break; |
| 6132 | case 1: |
| 6133 | gen_helper_booke206_tlbilx1(t0); |
| 6134 | break; |
| 6135 | case 3: |
| 6136 | gen_helper_booke206_tlbilx3(t0); |
| 6137 | break; |
| 6138 | default: |
| 6139 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
| 6140 | break; |
| 6141 | } |
| 6142 | |
| 6143 | tcg_temp_free(t0); |
| 6144 | #endif |
| 6145 | } |
| 6146 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 6147 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6148 | /* wrtee */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6149 | static void gen_wrtee(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6150 | { |
| 6151 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6152 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6153 | #else |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 6154 | TCGv t0; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6155 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6156 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6157 | return; |
| 6158 | } |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 6159 | t0 = tcg_temp_new(); |
| 6160 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); |
| 6161 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
| 6162 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
| 6163 | tcg_temp_free(t0); |
j_mayer | dee96f6 | 2007-09-29 15:02:38 +0000 | [diff] [blame] | 6164 | /* Stop translation to have a chance to raise an exception |
| 6165 | * if we just set msr_ee to 1 |
| 6166 | */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6167 | gen_stop_exception(ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6168 | #endif |
| 6169 | } |
| 6170 | |
| 6171 | /* wrteei */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6172 | static void gen_wrteei(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6173 | { |
| 6174 | #if defined(CONFIG_USER_ONLY) |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6175 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6176 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6177 | if (unlikely(!ctx->mem_idx)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6178 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6179 | return; |
| 6180 | } |
Baojun Wang | fbe7300 | 2009-07-03 18:56:57 +0800 | [diff] [blame] | 6181 | if (ctx->opcode & 0x00008000) { |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 6182 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
| 6183 | /* Stop translation to have a chance to raise an exception */ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6184 | gen_stop_exception(ctx); |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 6185 | } else { |
aurel32 | 1b6e5f9 | 2009-01-14 19:40:54 +0000 | [diff] [blame] | 6186 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
aurel32 | 6527f6e | 2008-12-06 13:03:35 +0000 | [diff] [blame] | 6187 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6188 | #endif |
| 6189 | } |
| 6190 | |
j_mayer | 08e46e5 | 2007-04-16 07:18:42 +0000 | [diff] [blame] | 6191 | /* PowerPC 440 specific instructions */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6192 | |
Blue Swirl | 5462327 | 2009-06-17 15:22:19 +0000 | [diff] [blame] | 6193 | /* dlmzb */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6194 | static void gen_dlmzb(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6195 | { |
aurel32 | ef0d51a | 2008-11-30 17:26:29 +0000 | [diff] [blame] | 6196 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
| 6197 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
| 6198 | cpu_gpr[rB(ctx->opcode)], t0); |
| 6199 | tcg_temp_free_i32(t0); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6200 | } |
| 6201 | |
| 6202 | /* mbar replaces eieio on 440 */ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6203 | static void gen_mbar(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6204 | { |
| 6205 | /* interpreted as no-op */ |
| 6206 | } |
| 6207 | |
| 6208 | /* msync replaces sync on 440 */ |
Alexander Graf | dcb2b9e1 | 2012-01-21 03:48:58 +0100 | [diff] [blame] | 6209 | static void gen_msync_4xx(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6210 | { |
| 6211 | /* interpreted as no-op */ |
| 6212 | } |
| 6213 | |
| 6214 | /* icbt */ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 6215 | static void gen_icbt_440(DisasContext *ctx) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 6216 | { |
| 6217 | /* interpreted as no-op */ |
| 6218 | /* XXX: specification say this is treated as a load by the MMU |
| 6219 | * but does not generate any exception |
| 6220 | */ |
| 6221 | } |
| 6222 | |
Alexander Graf | 9e0b5cb | 2012-01-31 03:18:35 +0100 | [diff] [blame] | 6223 | /* Embedded.Processor Control */ |
| 6224 | |
| 6225 | static void gen_msgclr(DisasContext *ctx) |
| 6226 | { |
| 6227 | #if defined(CONFIG_USER_ONLY) |
| 6228 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6229 | #else |
| 6230 | if (unlikely(ctx->mem_idx == 0)) { |
| 6231 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6232 | return; |
| 6233 | } |
| 6234 | |
| 6235 | gen_helper_msgclr(cpu_gpr[rB(ctx->opcode)]); |
| 6236 | #endif |
| 6237 | } |
| 6238 | |
Alexander Graf | d5d11a3 | 2012-01-31 03:19:23 +0100 | [diff] [blame] | 6239 | static void gen_msgsnd(DisasContext *ctx) |
| 6240 | { |
| 6241 | #if defined(CONFIG_USER_ONLY) |
| 6242 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6243 | #else |
| 6244 | if (unlikely(ctx->mem_idx == 0)) { |
| 6245 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
| 6246 | return; |
| 6247 | } |
| 6248 | |
| 6249 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
| 6250 | #endif |
| 6251 | } |
| 6252 | |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6253 | /*** Altivec vector extension ***/ |
| 6254 | /* Altivec registers moves */ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6255 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6256 | static inline TCGv_ptr gen_avr_ptr(int reg) |
aurel32 | 564e571 | 2008-12-18 22:51:31 +0000 | [diff] [blame] | 6257 | { |
aurel32 | e4704b3 | 2009-01-03 13:31:10 +0000 | [diff] [blame] | 6258 | TCGv_ptr r = tcg_temp_new_ptr(); |
aurel32 | 564e571 | 2008-12-18 22:51:31 +0000 | [diff] [blame] | 6259 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
| 6260 | return r; |
| 6261 | } |
| 6262 | |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6263 | #define GEN_VR_LDX(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6264 | static void glue(gen_, name)(DisasContext *ctx) \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6265 | { \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6266 | TCGv EA; \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6267 | if (unlikely(!ctx->altivec_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6268 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6269 | return; \ |
| 6270 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6271 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6272 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6273 | gen_addr_reg_index(ctx, EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6274 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6275 | if (ctx->le_mode) { \ |
| 6276 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6277 | tcg_gen_addi_tl(EA, EA, 8); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6278 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6279 | } else { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6280 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6281 | tcg_gen_addi_tl(EA, EA, 8); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6282 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6283 | } \ |
| 6284 | tcg_temp_free(EA); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6285 | } |
| 6286 | |
| 6287 | #define GEN_VR_STX(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6288 | static void gen_st##name(DisasContext *ctx) \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6289 | { \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6290 | TCGv EA; \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6291 | if (unlikely(!ctx->altivec_enabled)) { \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6292 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6293 | return; \ |
| 6294 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6295 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6296 | EA = tcg_temp_new(); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6297 | gen_addr_reg_index(ctx, EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6298 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6299 | if (ctx->le_mode) { \ |
| 6300 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6301 | tcg_gen_addi_tl(EA, EA, 8); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6302 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6303 | } else { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6304 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6305 | tcg_gen_addi_tl(EA, EA, 8); \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 6306 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6307 | } \ |
| 6308 | tcg_temp_free(EA); \ |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6309 | } |
| 6310 | |
aurel32 | cbfb6ae | 2009-01-04 22:13:10 +0000 | [diff] [blame] | 6311 | #define GEN_VR_LVE(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6312 | static void gen_lve##name(DisasContext *ctx) \ |
aurel32 | cbfb6ae | 2009-01-04 22:13:10 +0000 | [diff] [blame] | 6313 | { \ |
| 6314 | TCGv EA; \ |
| 6315 | TCGv_ptr rs; \ |
| 6316 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6317 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6318 | return; \ |
| 6319 | } \ |
| 6320 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 6321 | EA = tcg_temp_new(); \ |
| 6322 | gen_addr_reg_index(ctx, EA); \ |
| 6323 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
| 6324 | gen_helper_lve##name (rs, EA); \ |
| 6325 | tcg_temp_free(EA); \ |
| 6326 | tcg_temp_free_ptr(rs); \ |
| 6327 | } |
| 6328 | |
| 6329 | #define GEN_VR_STVE(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6330 | static void gen_stve##name(DisasContext *ctx) \ |
aurel32 | cbfb6ae | 2009-01-04 22:13:10 +0000 | [diff] [blame] | 6331 | { \ |
| 6332 | TCGv EA; \ |
| 6333 | TCGv_ptr rs; \ |
| 6334 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6335 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6336 | return; \ |
| 6337 | } \ |
| 6338 | gen_set_access_type(ctx, ACCESS_INT); \ |
| 6339 | EA = tcg_temp_new(); \ |
| 6340 | gen_addr_reg_index(ctx, EA); \ |
| 6341 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
| 6342 | gen_helper_stve##name (rs, EA); \ |
| 6343 | tcg_temp_free(EA); \ |
| 6344 | tcg_temp_free_ptr(rs); \ |
| 6345 | } |
| 6346 | |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6347 | GEN_VR_LDX(lvx, 0x07, 0x03); |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6348 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6349 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6350 | |
aurel32 | cbfb6ae | 2009-01-04 22:13:10 +0000 | [diff] [blame] | 6351 | GEN_VR_LVE(bx, 0x07, 0x00); |
| 6352 | GEN_VR_LVE(hx, 0x07, 0x01); |
| 6353 | GEN_VR_LVE(wx, 0x07, 0x02); |
| 6354 | |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6355 | GEN_VR_STX(svx, 0x07, 0x07); |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6356 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
aurel32 | fe1e5c5 | 2008-11-24 08:47:21 +0000 | [diff] [blame] | 6357 | GEN_VR_STX(svxl, 0x07, 0x0F); |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 6358 | |
aurel32 | cbfb6ae | 2009-01-04 22:13:10 +0000 | [diff] [blame] | 6359 | GEN_VR_STVE(bx, 0x07, 0x04); |
| 6360 | GEN_VR_STVE(hx, 0x07, 0x05); |
| 6361 | GEN_VR_STVE(wx, 0x07, 0x06); |
| 6362 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6363 | static void gen_lvsl(DisasContext *ctx) |
aurel32 | bf8d8de | 2009-01-04 22:09:42 +0000 | [diff] [blame] | 6364 | { |
| 6365 | TCGv_ptr rd; |
| 6366 | TCGv EA; |
| 6367 | if (unlikely(!ctx->altivec_enabled)) { |
| 6368 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6369 | return; |
| 6370 | } |
| 6371 | EA = tcg_temp_new(); |
| 6372 | gen_addr_reg_index(ctx, EA); |
| 6373 | rd = gen_avr_ptr(rD(ctx->opcode)); |
| 6374 | gen_helper_lvsl(rd, EA); |
| 6375 | tcg_temp_free(EA); |
| 6376 | tcg_temp_free_ptr(rd); |
| 6377 | } |
| 6378 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6379 | static void gen_lvsr(DisasContext *ctx) |
aurel32 | bf8d8de | 2009-01-04 22:09:42 +0000 | [diff] [blame] | 6380 | { |
| 6381 | TCGv_ptr rd; |
| 6382 | TCGv EA; |
| 6383 | if (unlikely(!ctx->altivec_enabled)) { |
| 6384 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6385 | return; |
| 6386 | } |
| 6387 | EA = tcg_temp_new(); |
| 6388 | gen_addr_reg_index(ctx, EA); |
| 6389 | rd = gen_avr_ptr(rD(ctx->opcode)); |
| 6390 | gen_helper_lvsr(rd, EA); |
| 6391 | tcg_temp_free(EA); |
| 6392 | tcg_temp_free_ptr(rd); |
| 6393 | } |
| 6394 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6395 | static void gen_mfvscr(DisasContext *ctx) |
aurel32 | 785f451 | 2009-01-04 22:51:59 +0000 | [diff] [blame] | 6396 | { |
| 6397 | TCGv_i32 t; |
| 6398 | if (unlikely(!ctx->altivec_enabled)) { |
| 6399 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6400 | return; |
| 6401 | } |
| 6402 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); |
| 6403 | t = tcg_temp_new_i32(); |
| 6404 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); |
| 6405 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
aurel32 | fce5ecb | 2009-02-03 19:55:13 +0000 | [diff] [blame] | 6406 | tcg_temp_free_i32(t); |
aurel32 | 785f451 | 2009-01-04 22:51:59 +0000 | [diff] [blame] | 6407 | } |
| 6408 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6409 | static void gen_mtvscr(DisasContext *ctx) |
aurel32 | 785f451 | 2009-01-04 22:51:59 +0000 | [diff] [blame] | 6410 | { |
aurel32 | 6e87b7c | 2009-02-03 19:56:09 +0000 | [diff] [blame] | 6411 | TCGv_ptr p; |
aurel32 | 785f451 | 2009-01-04 22:51:59 +0000 | [diff] [blame] | 6412 | if (unlikely(!ctx->altivec_enabled)) { |
| 6413 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6414 | return; |
| 6415 | } |
aurel32 | 6e87b7c | 2009-02-03 19:56:09 +0000 | [diff] [blame] | 6416 | p = gen_avr_ptr(rD(ctx->opcode)); |
| 6417 | gen_helper_mtvscr(p); |
| 6418 | tcg_temp_free_ptr(p); |
aurel32 | 785f451 | 2009-01-04 22:51:59 +0000 | [diff] [blame] | 6419 | } |
| 6420 | |
aurel32 | 7a9b96c | 2008-12-18 22:42:58 +0000 | [diff] [blame] | 6421 | /* Logical operations */ |
| 6422 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6423 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 7a9b96c | 2008-12-18 22:42:58 +0000 | [diff] [blame] | 6424 | { \ |
| 6425 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6426 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6427 | return; \ |
| 6428 | } \ |
| 6429 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ |
| 6430 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ |
| 6431 | } |
| 6432 | |
| 6433 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); |
| 6434 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); |
| 6435 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); |
| 6436 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); |
| 6437 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); |
| 6438 | |
aurel32 | 8e27dd6 | 2009-01-03 13:31:30 +0000 | [diff] [blame] | 6439 | #define GEN_VXFORM(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6440 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 8e27dd6 | 2009-01-03 13:31:30 +0000 | [diff] [blame] | 6441 | { \ |
| 6442 | TCGv_ptr ra, rb, rd; \ |
| 6443 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6444 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6445 | return; \ |
| 6446 | } \ |
| 6447 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
| 6448 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
| 6449 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6450 | gen_helper_##name (rd, ra, rb); \ |
| 6451 | tcg_temp_free_ptr(ra); \ |
| 6452 | tcg_temp_free_ptr(rb); \ |
| 6453 | tcg_temp_free_ptr(rd); \ |
| 6454 | } |
| 6455 | |
aurel32 | 7872c51 | 2009-01-03 13:31:40 +0000 | [diff] [blame] | 6456 | GEN_VXFORM(vaddubm, 0, 0); |
| 6457 | GEN_VXFORM(vadduhm, 0, 1); |
| 6458 | GEN_VXFORM(vadduwm, 0, 2); |
| 6459 | GEN_VXFORM(vsububm, 0, 16); |
| 6460 | GEN_VXFORM(vsubuhm, 0, 17); |
| 6461 | GEN_VXFORM(vsubuwm, 0, 18); |
aurel32 | e403933 | 2009-01-03 13:31:58 +0000 | [diff] [blame] | 6462 | GEN_VXFORM(vmaxub, 1, 0); |
| 6463 | GEN_VXFORM(vmaxuh, 1, 1); |
| 6464 | GEN_VXFORM(vmaxuw, 1, 2); |
| 6465 | GEN_VXFORM(vmaxsb, 1, 4); |
| 6466 | GEN_VXFORM(vmaxsh, 1, 5); |
| 6467 | GEN_VXFORM(vmaxsw, 1, 6); |
| 6468 | GEN_VXFORM(vminub, 1, 8); |
| 6469 | GEN_VXFORM(vminuh, 1, 9); |
| 6470 | GEN_VXFORM(vminuw, 1, 10); |
| 6471 | GEN_VXFORM(vminsb, 1, 12); |
| 6472 | GEN_VXFORM(vminsh, 1, 13); |
| 6473 | GEN_VXFORM(vminsw, 1, 14); |
aurel32 | fab3cbe | 2009-01-03 13:31:49 +0000 | [diff] [blame] | 6474 | GEN_VXFORM(vavgub, 1, 16); |
| 6475 | GEN_VXFORM(vavguh, 1, 17); |
| 6476 | GEN_VXFORM(vavguw, 1, 18); |
| 6477 | GEN_VXFORM(vavgsb, 1, 20); |
| 6478 | GEN_VXFORM(vavgsh, 1, 21); |
| 6479 | GEN_VXFORM(vavgsw, 1, 22); |
aurel32 | 3b43004 | 2009-01-04 22:08:38 +0000 | [diff] [blame] | 6480 | GEN_VXFORM(vmrghb, 6, 0); |
| 6481 | GEN_VXFORM(vmrghh, 6, 1); |
| 6482 | GEN_VXFORM(vmrghw, 6, 2); |
| 6483 | GEN_VXFORM(vmrglb, 6, 4); |
| 6484 | GEN_VXFORM(vmrglh, 6, 5); |
| 6485 | GEN_VXFORM(vmrglw, 6, 6); |
aurel32 | 2c27790 | 2009-01-04 22:08:48 +0000 | [diff] [blame] | 6486 | GEN_VXFORM(vmuloub, 4, 0); |
| 6487 | GEN_VXFORM(vmulouh, 4, 1); |
| 6488 | GEN_VXFORM(vmulosb, 4, 4); |
| 6489 | GEN_VXFORM(vmulosh, 4, 5); |
| 6490 | GEN_VXFORM(vmuleub, 4, 8); |
| 6491 | GEN_VXFORM(vmuleuh, 4, 9); |
| 6492 | GEN_VXFORM(vmulesb, 4, 12); |
| 6493 | GEN_VXFORM(vmulesh, 4, 13); |
aurel32 | d79f080 | 2009-01-04 22:09:08 +0000 | [diff] [blame] | 6494 | GEN_VXFORM(vslb, 2, 4); |
| 6495 | GEN_VXFORM(vslh, 2, 5); |
| 6496 | GEN_VXFORM(vslw, 2, 6); |
aurel32 | 07ef34c | 2009-01-04 22:08:58 +0000 | [diff] [blame] | 6497 | GEN_VXFORM(vsrb, 2, 8); |
| 6498 | GEN_VXFORM(vsrh, 2, 9); |
| 6499 | GEN_VXFORM(vsrw, 2, 10); |
| 6500 | GEN_VXFORM(vsrab, 2, 12); |
| 6501 | GEN_VXFORM(vsrah, 2, 13); |
| 6502 | GEN_VXFORM(vsraw, 2, 14); |
aurel32 | 7b239be | 2009-01-04 22:09:19 +0000 | [diff] [blame] | 6503 | GEN_VXFORM(vslo, 6, 16); |
| 6504 | GEN_VXFORM(vsro, 6, 17); |
aurel32 | e343da7 | 2009-01-04 22:09:31 +0000 | [diff] [blame] | 6505 | GEN_VXFORM(vaddcuw, 0, 6); |
| 6506 | GEN_VXFORM(vsubcuw, 0, 22); |
aurel32 | 5ab09f3 | 2009-01-08 23:19:50 +0000 | [diff] [blame] | 6507 | GEN_VXFORM(vaddubs, 0, 8); |
| 6508 | GEN_VXFORM(vadduhs, 0, 9); |
| 6509 | GEN_VXFORM(vadduws, 0, 10); |
| 6510 | GEN_VXFORM(vaddsbs, 0, 12); |
| 6511 | GEN_VXFORM(vaddshs, 0, 13); |
| 6512 | GEN_VXFORM(vaddsws, 0, 14); |
| 6513 | GEN_VXFORM(vsububs, 0, 24); |
| 6514 | GEN_VXFORM(vsubuhs, 0, 25); |
| 6515 | GEN_VXFORM(vsubuws, 0, 26); |
| 6516 | GEN_VXFORM(vsubsbs, 0, 28); |
| 6517 | GEN_VXFORM(vsubshs, 0, 29); |
| 6518 | GEN_VXFORM(vsubsws, 0, 30); |
aurel32 | 5e1d098 | 2009-01-04 22:09:52 +0000 | [diff] [blame] | 6519 | GEN_VXFORM(vrlb, 2, 0); |
| 6520 | GEN_VXFORM(vrlh, 2, 1); |
| 6521 | GEN_VXFORM(vrlw, 2, 2); |
aurel32 | d9430ad | 2009-01-08 18:54:48 +0000 | [diff] [blame] | 6522 | GEN_VXFORM(vsl, 2, 7); |
| 6523 | GEN_VXFORM(vsr, 2, 11); |
aurel32 | 5335a14 | 2009-01-04 22:12:09 +0000 | [diff] [blame] | 6524 | GEN_VXFORM(vpkuhum, 7, 0); |
| 6525 | GEN_VXFORM(vpkuwum, 7, 1); |
| 6526 | GEN_VXFORM(vpkuhus, 7, 2); |
| 6527 | GEN_VXFORM(vpkuwus, 7, 3); |
| 6528 | GEN_VXFORM(vpkshus, 7, 4); |
| 6529 | GEN_VXFORM(vpkswus, 7, 5); |
| 6530 | GEN_VXFORM(vpkshss, 7, 6); |
| 6531 | GEN_VXFORM(vpkswss, 7, 7); |
aurel32 | 1dd9ffb | 2009-01-04 22:12:19 +0000 | [diff] [blame] | 6532 | GEN_VXFORM(vpkpx, 7, 12); |
aurel32 | 8142cdd | 2009-01-04 22:13:21 +0000 | [diff] [blame] | 6533 | GEN_VXFORM(vsum4ubs, 4, 24); |
| 6534 | GEN_VXFORM(vsum4sbs, 4, 28); |
| 6535 | GEN_VXFORM(vsum4shs, 4, 25); |
| 6536 | GEN_VXFORM(vsum2sws, 4, 26); |
| 6537 | GEN_VXFORM(vsumsws, 4, 30); |
aurel32 | 56fdd21 | 2009-02-09 16:48:51 +0000 | [diff] [blame] | 6538 | GEN_VXFORM(vaddfp, 5, 0); |
| 6539 | GEN_VXFORM(vsubfp, 5, 1); |
aurel32 | 1536ff6 | 2009-02-09 16:48:39 +0000 | [diff] [blame] | 6540 | GEN_VXFORM(vmaxfp, 5, 16); |
| 6541 | GEN_VXFORM(vminfp, 5, 17); |
aurel32 | fab3cbe | 2009-01-03 13:31:49 +0000 | [diff] [blame] | 6542 | |
aurel32 | 0cbcd90 | 2009-01-08 18:54:26 +0000 | [diff] [blame] | 6543 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 6544 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 0cbcd90 | 2009-01-08 18:54:26 +0000 | [diff] [blame] | 6545 | { \ |
| 6546 | TCGv_ptr ra, rb, rd; \ |
| 6547 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6548 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6549 | return; \ |
| 6550 | } \ |
| 6551 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
| 6552 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
| 6553 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6554 | gen_helper_##opname (rd, ra, rb); \ |
| 6555 | tcg_temp_free_ptr(ra); \ |
| 6556 | tcg_temp_free_ptr(rb); \ |
| 6557 | tcg_temp_free_ptr(rd); \ |
| 6558 | } |
| 6559 | |
| 6560 | #define GEN_VXRFORM(name, opc2, opc3) \ |
| 6561 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ |
| 6562 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
| 6563 | |
aurel32 | 1add6e2 | 2009-01-08 18:54:38 +0000 | [diff] [blame] | 6564 | GEN_VXRFORM(vcmpequb, 3, 0) |
| 6565 | GEN_VXRFORM(vcmpequh, 3, 1) |
| 6566 | GEN_VXRFORM(vcmpequw, 3, 2) |
| 6567 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
| 6568 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
| 6569 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
| 6570 | GEN_VXRFORM(vcmpgtub, 3, 8) |
| 6571 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
| 6572 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
aurel32 | 819ca12 | 2009-02-09 16:49:10 +0000 | [diff] [blame] | 6573 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
| 6574 | GEN_VXRFORM(vcmpgefp, 3, 7) |
| 6575 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
| 6576 | GEN_VXRFORM(vcmpbfp, 3, 15) |
aurel32 | 1add6e2 | 2009-01-08 18:54:38 +0000 | [diff] [blame] | 6577 | |
aurel32 | c026766 | 2009-01-08 18:54:57 +0000 | [diff] [blame] | 6578 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6579 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | c026766 | 2009-01-08 18:54:57 +0000 | [diff] [blame] | 6580 | { \ |
| 6581 | TCGv_ptr rd; \ |
| 6582 | TCGv_i32 simm; \ |
| 6583 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6584 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6585 | return; \ |
| 6586 | } \ |
| 6587 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
| 6588 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6589 | gen_helper_##name (rd, simm); \ |
| 6590 | tcg_temp_free_i32(simm); \ |
| 6591 | tcg_temp_free_ptr(rd); \ |
| 6592 | } |
| 6593 | |
| 6594 | GEN_VXFORM_SIMM(vspltisb, 6, 12); |
| 6595 | GEN_VXFORM_SIMM(vspltish, 6, 13); |
| 6596 | GEN_VXFORM_SIMM(vspltisw, 6, 14); |
| 6597 | |
aurel32 | de5f248 | 2009-01-04 22:10:59 +0000 | [diff] [blame] | 6598 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6599 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | de5f248 | 2009-01-04 22:10:59 +0000 | [diff] [blame] | 6600 | { \ |
| 6601 | TCGv_ptr rb, rd; \ |
| 6602 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6603 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6604 | return; \ |
| 6605 | } \ |
| 6606 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
| 6607 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6608 | gen_helper_##name (rd, rb); \ |
| 6609 | tcg_temp_free_ptr(rb); \ |
| 6610 | tcg_temp_free_ptr(rd); \ |
| 6611 | } |
| 6612 | |
aurel32 | 6cf1c6e | 2009-01-04 22:11:20 +0000 | [diff] [blame] | 6613 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
| 6614 | GEN_VXFORM_NOA(vupkhsh, 7, 9); |
| 6615 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
| 6616 | GEN_VXFORM_NOA(vupklsh, 7, 11); |
aurel32 | 79f85c3 | 2009-01-04 22:11:10 +0000 | [diff] [blame] | 6617 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
| 6618 | GEN_VXFORM_NOA(vupklpx, 7, 15); |
aurel32 | bdfbac3 | 2009-02-09 16:49:29 +0000 | [diff] [blame] | 6619 | GEN_VXFORM_NOA(vrefp, 5, 4); |
aurel32 | 071fc3b | 2009-02-09 16:49:40 +0000 | [diff] [blame] | 6620 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
Aurelien Jarno | 0bffbc6 | 2009-02-09 12:20:50 +0100 | [diff] [blame] | 6621 | GEN_VXFORM_NOA(vexptefp, 5, 6); |
aurel32 | b580763 | 2009-02-05 22:33:36 +0000 | [diff] [blame] | 6622 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
aurel32 | f6b1964 | 2009-02-04 13:52:03 +0000 | [diff] [blame] | 6623 | GEN_VXFORM_NOA(vrfim, 5, 8); |
| 6624 | GEN_VXFORM_NOA(vrfin, 5, 9); |
| 6625 | GEN_VXFORM_NOA(vrfip, 5, 10); |
| 6626 | GEN_VXFORM_NOA(vrfiz, 5, 11); |
aurel32 | 79f85c3 | 2009-01-04 22:11:10 +0000 | [diff] [blame] | 6627 | |
aurel32 | 21d2158 | 2009-01-04 22:10:28 +0000 | [diff] [blame] | 6628 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6629 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 21d2158 | 2009-01-04 22:10:28 +0000 | [diff] [blame] | 6630 | { \ |
| 6631 | TCGv_ptr rd; \ |
| 6632 | TCGv_i32 simm; \ |
| 6633 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6634 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6635 | return; \ |
| 6636 | } \ |
| 6637 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
| 6638 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6639 | gen_helper_##name (rd, simm); \ |
| 6640 | tcg_temp_free_i32(simm); \ |
| 6641 | tcg_temp_free_ptr(rd); \ |
| 6642 | } |
| 6643 | |
aurel32 | 27a4edb | 2009-01-04 22:10:40 +0000 | [diff] [blame] | 6644 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6645 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 27a4edb | 2009-01-04 22:10:40 +0000 | [diff] [blame] | 6646 | { \ |
| 6647 | TCGv_ptr rb, rd; \ |
| 6648 | TCGv_i32 uimm; \ |
| 6649 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6650 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6651 | return; \ |
| 6652 | } \ |
| 6653 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
| 6654 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
| 6655 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6656 | gen_helper_##name (rd, rb, uimm); \ |
| 6657 | tcg_temp_free_i32(uimm); \ |
| 6658 | tcg_temp_free_ptr(rb); \ |
| 6659 | tcg_temp_free_ptr(rd); \ |
| 6660 | } |
| 6661 | |
aurel32 | e4e6bee | 2009-01-04 22:10:49 +0000 | [diff] [blame] | 6662 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
| 6663 | GEN_VXFORM_UIMM(vsplth, 6, 9); |
| 6664 | GEN_VXFORM_UIMM(vspltw, 6, 10); |
aurel32 | e140632 | 2009-02-04 13:52:17 +0000 | [diff] [blame] | 6665 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
| 6666 | GEN_VXFORM_UIMM(vcfsx, 5, 13); |
aurel32 | 875b31d | 2009-02-09 16:49:20 +0000 | [diff] [blame] | 6667 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
| 6668 | GEN_VXFORM_UIMM(vctsxs, 5, 15); |
aurel32 | e4e6bee | 2009-01-04 22:10:49 +0000 | [diff] [blame] | 6669 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6670 | static void gen_vsldoi(DisasContext *ctx) |
aurel32 | cd633b1 | 2009-01-04 22:10:09 +0000 | [diff] [blame] | 6671 | { |
| 6672 | TCGv_ptr ra, rb, rd; |
aurel32 | fce5ecb | 2009-02-03 19:55:13 +0000 | [diff] [blame] | 6673 | TCGv_i32 sh; |
aurel32 | cd633b1 | 2009-01-04 22:10:09 +0000 | [diff] [blame] | 6674 | if (unlikely(!ctx->altivec_enabled)) { |
| 6675 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6676 | return; |
| 6677 | } |
| 6678 | ra = gen_avr_ptr(rA(ctx->opcode)); |
| 6679 | rb = gen_avr_ptr(rB(ctx->opcode)); |
| 6680 | rd = gen_avr_ptr(rD(ctx->opcode)); |
| 6681 | sh = tcg_const_i32(VSH(ctx->opcode)); |
| 6682 | gen_helper_vsldoi (rd, ra, rb, sh); |
| 6683 | tcg_temp_free_ptr(ra); |
| 6684 | tcg_temp_free_ptr(rb); |
| 6685 | tcg_temp_free_ptr(rd); |
aurel32 | fce5ecb | 2009-02-03 19:55:13 +0000 | [diff] [blame] | 6686 | tcg_temp_free_i32(sh); |
aurel32 | cd633b1 | 2009-01-04 22:10:09 +0000 | [diff] [blame] | 6687 | } |
| 6688 | |
aurel32 | 707cec3 | 2009-01-04 22:11:29 +0000 | [diff] [blame] | 6689 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6690 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
aurel32 | 707cec3 | 2009-01-04 22:11:29 +0000 | [diff] [blame] | 6691 | { \ |
| 6692 | TCGv_ptr ra, rb, rc, rd; \ |
| 6693 | if (unlikely(!ctx->altivec_enabled)) { \ |
| 6694 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
| 6695 | return; \ |
| 6696 | } \ |
| 6697 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
| 6698 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
| 6699 | rc = gen_avr_ptr(rC(ctx->opcode)); \ |
| 6700 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
| 6701 | if (Rc(ctx->opcode)) { \ |
| 6702 | gen_helper_##name1 (rd, ra, rb, rc); \ |
| 6703 | } else { \ |
| 6704 | gen_helper_##name0 (rd, ra, rb, rc); \ |
| 6705 | } \ |
| 6706 | tcg_temp_free_ptr(ra); \ |
| 6707 | tcg_temp_free_ptr(rb); \ |
| 6708 | tcg_temp_free_ptr(rc); \ |
| 6709 | tcg_temp_free_ptr(rd); \ |
| 6710 | } |
| 6711 | |
aurel32 | b161ae2 | 2009-01-04 22:12:29 +0000 | [diff] [blame] | 6712 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
| 6713 | |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6714 | static void gen_vmladduhm(DisasContext *ctx) |
aurel32 | bcd2ee2 | 2009-01-04 22:13:00 +0000 | [diff] [blame] | 6715 | { |
| 6716 | TCGv_ptr ra, rb, rc, rd; |
| 6717 | if (unlikely(!ctx->altivec_enabled)) { |
| 6718 | gen_exception(ctx, POWERPC_EXCP_VPU); |
| 6719 | return; |
| 6720 | } |
| 6721 | ra = gen_avr_ptr(rA(ctx->opcode)); |
| 6722 | rb = gen_avr_ptr(rB(ctx->opcode)); |
| 6723 | rc = gen_avr_ptr(rC(ctx->opcode)); |
| 6724 | rd = gen_avr_ptr(rD(ctx->opcode)); |
| 6725 | gen_helper_vmladduhm(rd, ra, rb, rc); |
| 6726 | tcg_temp_free_ptr(ra); |
| 6727 | tcg_temp_free_ptr(rb); |
| 6728 | tcg_temp_free_ptr(rc); |
| 6729 | tcg_temp_free_ptr(rd); |
| 6730 | } |
| 6731 | |
aurel32 | b04ae98 | 2009-01-04 22:11:39 +0000 | [diff] [blame] | 6732 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
aurel32 | 4d9903b | 2009-01-04 22:12:39 +0000 | [diff] [blame] | 6733 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
aurel32 | eae0726 | 2009-01-04 22:12:49 +0000 | [diff] [blame] | 6734 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
aurel32 | d125869 | 2009-01-04 22:11:49 +0000 | [diff] [blame] | 6735 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
aurel32 | 35cf7c7 | 2009-02-09 16:48:59 +0000 | [diff] [blame] | 6736 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
aurel32 | b04ae98 | 2009-01-04 22:11:39 +0000 | [diff] [blame] | 6737 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6738 | /*** SPE extension ***/ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6739 | /* Register moves */ |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 6740 | |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 6741 | |
| 6742 | static inline void gen_evmra(DisasContext *ctx) |
| 6743 | { |
| 6744 | |
| 6745 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6746 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 6747 | return; |
| 6748 | } |
| 6749 | |
| 6750 | #if defined(TARGET_PPC64) |
| 6751 | /* rD := rA */ |
| 6752 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 6753 | |
| 6754 | /* spe_acc := rA */ |
| 6755 | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], |
| 6756 | cpu_env, |
| 6757 | offsetof(CPUState, spe_acc)); |
| 6758 | #else |
| 6759 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 6760 | |
| 6761 | /* tmp := rA_lo + rA_hi << 32 */ |
| 6762 | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
| 6763 | |
| 6764 | /* spe_acc := tmp */ |
| 6765 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
| 6766 | tcg_temp_free_i64(tmp); |
| 6767 | |
| 6768 | /* rD := rA */ |
| 6769 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 6770 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
| 6771 | #endif |
| 6772 | } |
| 6773 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6774 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
| 6775 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6776 | #if defined(TARGET_PPC64) |
| 6777 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
| 6778 | #else |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 6779 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6780 | #endif |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6781 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6782 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6783 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
| 6784 | { |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6785 | #if defined(TARGET_PPC64) |
| 6786 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
| 6787 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6788 | TCGv_i64 tmp = tcg_temp_new_i64(); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6789 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6790 | tcg_gen_shri_i64(tmp, t, 32); |
| 6791 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6792 | tcg_temp_free_i64(tmp); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6793 | #endif |
aurel32 | f78fb44 | 2008-09-04 05:25:47 +0000 | [diff] [blame] | 6794 | } |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 6795 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 6796 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 6797 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6798 | { \ |
| 6799 | if (Rc(ctx->opcode)) \ |
| 6800 | gen_##name1(ctx); \ |
| 6801 | else \ |
| 6802 | gen_##name0(ctx); \ |
| 6803 | } |
| 6804 | |
| 6805 | /* Handler for undefined SPE opcodes */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6806 | static inline void gen_speundef(DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6807 | { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 6808 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6809 | } |
| 6810 | |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6811 | /* SPE logic */ |
| 6812 | #if defined(TARGET_PPC64) |
| 6813 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6814 | static inline void gen_##name(DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6815 | { \ |
| 6816 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6817 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6818 | return; \ |
| 6819 | } \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6820 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
| 6821 | cpu_gpr[rB(ctx->opcode)]); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6822 | } |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6823 | #else |
| 6824 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6825 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 3d3a6a0 | 2008-10-15 17:00:45 +0000 | [diff] [blame] | 6826 | { \ |
| 6827 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6828 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 3d3a6a0 | 2008-10-15 17:00:45 +0000 | [diff] [blame] | 6829 | return; \ |
| 6830 | } \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6831 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
| 6832 | cpu_gpr[rB(ctx->opcode)]); \ |
| 6833 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
| 6834 | cpu_gprh[rB(ctx->opcode)]); \ |
| 6835 | } |
| 6836 | #endif |
| 6837 | |
| 6838 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); |
| 6839 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); |
| 6840 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); |
| 6841 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); |
| 6842 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); |
| 6843 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); |
| 6844 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); |
| 6845 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); |
| 6846 | |
| 6847 | /* SPE logic immediate */ |
| 6848 | #if defined(TARGET_PPC64) |
| 6849 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6850 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6851 | { \ |
| 6852 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6853 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6854 | return; \ |
| 6855 | } \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6856 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
| 6857 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
| 6858 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6859 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 6860 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
| 6861 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ |
| 6862 | tcg_gen_trunc_i64_i32(t1, t2); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6863 | tcg_temp_free_i64(t2); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6864 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
| 6865 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6866 | tcg_temp_free_i32(t0); \ |
| 6867 | tcg_temp_free_i32(t1); \ |
aurel32 | 3d3a6a0 | 2008-10-15 17:00:45 +0000 | [diff] [blame] | 6868 | } |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6869 | #else |
| 6870 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6871 | static inline void gen_##name(DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6872 | { \ |
| 6873 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6874 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6875 | return; \ |
| 6876 | } \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6877 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
| 6878 | rB(ctx->opcode)); \ |
| 6879 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
| 6880 | rB(ctx->opcode)); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6881 | } |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6882 | #endif |
| 6883 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
| 6884 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); |
| 6885 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); |
| 6886 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6887 | |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6888 | /* SPE arithmetic */ |
| 6889 | #if defined(TARGET_PPC64) |
| 6890 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6891 | static inline void gen_##name(DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6892 | { \ |
| 6893 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6894 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6895 | return; \ |
| 6896 | } \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6897 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
| 6898 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
| 6899 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6900 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 6901 | tcg_op(t0, t0); \ |
| 6902 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ |
| 6903 | tcg_gen_trunc_i64_i32(t1, t2); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6904 | tcg_temp_free_i64(t2); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6905 | tcg_op(t1, t1); \ |
| 6906 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6907 | tcg_temp_free_i32(t0); \ |
| 6908 | tcg_temp_free_i32(t1); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6909 | } |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6910 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6911 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6912 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6913 | { \ |
| 6914 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6915 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6916 | return; \ |
| 6917 | } \ |
| 6918 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
| 6919 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ |
| 6920 | } |
| 6921 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6922 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6923 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6924 | { |
| 6925 | int l1 = gen_new_label(); |
| 6926 | int l2 = gen_new_label(); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 6927 | |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6928 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
| 6929 | tcg_gen_neg_i32(ret, arg1); |
| 6930 | tcg_gen_br(l2); |
| 6931 | gen_set_label(l1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6932 | tcg_gen_mov_i32(ret, arg1); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6933 | gen_set_label(l2); |
| 6934 | } |
| 6935 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); |
| 6936 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
| 6937 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
| 6938 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6939 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6940 | { |
| 6941 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
| 6942 | tcg_gen_ext16u_i32(ret, ret); |
| 6943 | } |
| 6944 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6945 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
| 6946 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6947 | |
| 6948 | #if defined(TARGET_PPC64) |
| 6949 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6950 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6951 | { \ |
| 6952 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6953 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6954 | return; \ |
| 6955 | } \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6956 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
| 6957 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
| 6958 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ |
aurel32 | 501e23c | 2009-01-03 12:35:38 +0000 | [diff] [blame] | 6959 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6960 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 6961 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ |
| 6962 | tcg_op(t0, t0, t2); \ |
| 6963 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ |
| 6964 | tcg_gen_trunc_i64_i32(t1, t3); \ |
| 6965 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ |
| 6966 | tcg_gen_trunc_i64_i32(t2, t3); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6967 | tcg_temp_free_i64(t3); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6968 | tcg_op(t1, t1, t2); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6969 | tcg_temp_free_i32(t2); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6970 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6971 | tcg_temp_free_i32(t0); \ |
| 6972 | tcg_temp_free_i32(t1); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6973 | } |
| 6974 | #else |
| 6975 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6976 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6977 | { \ |
| 6978 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 6979 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6980 | return; \ |
| 6981 | } \ |
| 6982 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
| 6983 | cpu_gpr[rB(ctx->opcode)]); \ |
| 6984 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
| 6985 | cpu_gprh[rB(ctx->opcode)]); \ |
| 6986 | } |
| 6987 | #endif |
| 6988 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 6989 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6990 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6991 | TCGv_i32 t0; |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6992 | int l1, l2; |
| 6993 | |
| 6994 | l1 = gen_new_label(); |
| 6995 | l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6996 | t0 = tcg_temp_local_new_i32(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 6997 | /* No error here: 6 bits are used */ |
| 6998 | tcg_gen_andi_i32(t0, arg2, 0x3F); |
| 6999 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); |
| 7000 | tcg_gen_shr_i32(ret, arg1, t0); |
| 7001 | tcg_gen_br(l2); |
| 7002 | gen_set_label(l1); |
| 7003 | tcg_gen_movi_i32(ret, 0); |
Aurelien Jarno | 0aef426 | 2010-03-11 21:29:42 +0100 | [diff] [blame] | 7004 | gen_set_label(l2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7005 | tcg_temp_free_i32(t0); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7006 | } |
| 7007 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7008 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7009 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7010 | TCGv_i32 t0; |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7011 | int l1, l2; |
| 7012 | |
| 7013 | l1 = gen_new_label(); |
| 7014 | l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7015 | t0 = tcg_temp_local_new_i32(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7016 | /* No error here: 6 bits are used */ |
| 7017 | tcg_gen_andi_i32(t0, arg2, 0x3F); |
| 7018 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); |
| 7019 | tcg_gen_sar_i32(ret, arg1, t0); |
| 7020 | tcg_gen_br(l2); |
| 7021 | gen_set_label(l1); |
| 7022 | tcg_gen_movi_i32(ret, 0); |
Aurelien Jarno | 0aef426 | 2010-03-11 21:29:42 +0100 | [diff] [blame] | 7023 | gen_set_label(l2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7024 | tcg_temp_free_i32(t0); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7025 | } |
| 7026 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7027 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7028 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7029 | TCGv_i32 t0; |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7030 | int l1, l2; |
| 7031 | |
| 7032 | l1 = gen_new_label(); |
| 7033 | l2 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7034 | t0 = tcg_temp_local_new_i32(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7035 | /* No error here: 6 bits are used */ |
| 7036 | tcg_gen_andi_i32(t0, arg2, 0x3F); |
| 7037 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); |
| 7038 | tcg_gen_shl_i32(ret, arg1, t0); |
| 7039 | tcg_gen_br(l2); |
| 7040 | gen_set_label(l1); |
| 7041 | tcg_gen_movi_i32(ret, 0); |
Aurelien Jarno | e29ef9f | 2010-03-11 21:14:47 +0100 | [diff] [blame] | 7042 | gen_set_label(l2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7043 | tcg_temp_free_i32(t0); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7044 | } |
| 7045 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7046 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7047 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7048 | TCGv_i32 t0 = tcg_temp_new_i32(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7049 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
| 7050 | tcg_gen_rotl_i32(ret, arg1, t0); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7051 | tcg_temp_free_i32(t0); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7052 | } |
| 7053 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7054 | static inline void gen_evmergehi(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7055 | { |
| 7056 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7057 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7058 | return; |
| 7059 | } |
| 7060 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7061 | TCGv t0 = tcg_temp_new(); |
| 7062 | TCGv t1 = tcg_temp_new(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7063 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
| 7064 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
| 7065 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
| 7066 | tcg_temp_free(t0); |
| 7067 | tcg_temp_free(t1); |
| 7068 | #else |
| 7069 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
| 7070 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
| 7071 | #endif |
| 7072 | } |
| 7073 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7074 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7075 | { |
| 7076 | tcg_gen_sub_i32(ret, arg2, arg1); |
| 7077 | } |
| 7078 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); |
| 7079 | |
| 7080 | /* SPE arithmetic immediate */ |
| 7081 | #if defined(TARGET_PPC64) |
| 7082 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7083 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7084 | { \ |
| 7085 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7086 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7087 | return; \ |
| 7088 | } \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7089 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
| 7090 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
| 7091 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7092 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
| 7093 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
| 7094 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ |
| 7095 | tcg_gen_trunc_i64_i32(t1, t2); \ |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 7096 | tcg_temp_free_i64(t2); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7097 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
| 7098 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7099 | tcg_temp_free_i32(t0); \ |
| 7100 | tcg_temp_free_i32(t1); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7101 | } |
| 7102 | #else |
| 7103 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7104 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7105 | { \ |
| 7106 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7107 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7108 | return; \ |
| 7109 | } \ |
| 7110 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
| 7111 | rA(ctx->opcode)); \ |
| 7112 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ |
| 7113 | rA(ctx->opcode)); \ |
| 7114 | } |
| 7115 | #endif |
| 7116 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
| 7117 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); |
| 7118 | |
| 7119 | /* SPE comparison */ |
| 7120 | #if defined(TARGET_PPC64) |
| 7121 | #define GEN_SPEOP_COMP(name, tcg_cond) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7122 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7123 | { \ |
| 7124 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7125 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7126 | return; \ |
| 7127 | } \ |
| 7128 | int l1 = gen_new_label(); \ |
| 7129 | int l2 = gen_new_label(); \ |
| 7130 | int l3 = gen_new_label(); \ |
| 7131 | int l4 = gen_new_label(); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7132 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
| 7133 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
| 7134 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7135 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 7136 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
| 7137 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7138 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7139 | tcg_gen_br(l2); \ |
| 7140 | gen_set_label(l1); \ |
| 7141 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
| 7142 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
| 7143 | gen_set_label(l2); \ |
| 7144 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ |
| 7145 | tcg_gen_trunc_i64_i32(t0, t2); \ |
| 7146 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ |
| 7147 | tcg_gen_trunc_i64_i32(t1, t2); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7148 | tcg_temp_free_i64(t2); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7149 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
| 7150 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
| 7151 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
| 7152 | tcg_gen_br(l4); \ |
| 7153 | gen_set_label(l3); \ |
| 7154 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
| 7155 | CRF_CH | CRF_CH_OR_CL); \ |
| 7156 | gen_set_label(l4); \ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7157 | tcg_temp_free_i32(t0); \ |
| 7158 | tcg_temp_free_i32(t1); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7159 | } |
| 7160 | #else |
| 7161 | #define GEN_SPEOP_COMP(name, tcg_cond) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7162 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7163 | { \ |
| 7164 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7165 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7166 | return; \ |
| 7167 | } \ |
| 7168 | int l1 = gen_new_label(); \ |
| 7169 | int l2 = gen_new_label(); \ |
| 7170 | int l3 = gen_new_label(); \ |
| 7171 | int l4 = gen_new_label(); \ |
| 7172 | \ |
| 7173 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ |
| 7174 | cpu_gpr[rB(ctx->opcode)], l1); \ |
| 7175 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ |
| 7176 | tcg_gen_br(l2); \ |
| 7177 | gen_set_label(l1); \ |
| 7178 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
| 7179 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
| 7180 | gen_set_label(l2); \ |
| 7181 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
| 7182 | cpu_gprh[rB(ctx->opcode)], l3); \ |
| 7183 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
| 7184 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
| 7185 | tcg_gen_br(l4); \ |
| 7186 | gen_set_label(l3); \ |
| 7187 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
| 7188 | CRF_CH | CRF_CH_OR_CL); \ |
| 7189 | gen_set_label(l4); \ |
| 7190 | } |
| 7191 | #endif |
| 7192 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
| 7193 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); |
| 7194 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); |
| 7195 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); |
| 7196 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
| 7197 | |
| 7198 | /* SPE misc */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7199 | static inline void gen_brinc(DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7200 | { |
| 7201 | /* Note: brinc is usable even if SPE is disabled */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7202 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
| 7203 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7204 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7205 | static inline void gen_evmergelo(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7206 | { |
| 7207 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7208 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7209 | return; |
| 7210 | } |
| 7211 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7212 | TCGv t0 = tcg_temp_new(); |
| 7213 | TCGv t1 = tcg_temp_new(); |
Aurelien Jarno | 17d9b3a | 2011-03-22 07:41:29 +0100 | [diff] [blame] | 7214 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7215 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
| 7216 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
| 7217 | tcg_temp_free(t0); |
| 7218 | tcg_temp_free(t1); |
| 7219 | #else |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7220 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
Nathan Froyd | 33890b3 | 2009-06-04 13:46:41 -0700 | [diff] [blame] | 7221 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7222 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7223 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7224 | static inline void gen_evmergehilo(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7225 | { |
| 7226 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7227 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7228 | return; |
| 7229 | } |
| 7230 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7231 | TCGv t0 = tcg_temp_new(); |
| 7232 | TCGv t1 = tcg_temp_new(); |
Aurelien Jarno | 17d9b3a | 2011-03-22 07:41:29 +0100 | [diff] [blame] | 7233 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7234 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); |
| 7235 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
| 7236 | tcg_temp_free(t0); |
| 7237 | tcg_temp_free(t1); |
| 7238 | #else |
| 7239 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 7240 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
| 7241 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7242 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7243 | static inline void gen_evmergelohi(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7244 | { |
| 7245 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7246 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7247 | return; |
| 7248 | } |
| 7249 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7250 | TCGv t0 = tcg_temp_new(); |
| 7251 | TCGv t1 = tcg_temp_new(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7252 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
| 7253 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); |
| 7254 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
| 7255 | tcg_temp_free(t0); |
| 7256 | tcg_temp_free(t1); |
| 7257 | #else |
Nathan Froyd | 33890b3 | 2009-06-04 13:46:41 -0700 | [diff] [blame] | 7258 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
| 7259 | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 7260 | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); |
| 7261 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
| 7262 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); |
| 7263 | tcg_temp_free_i32(tmp); |
| 7264 | } else { |
| 7265 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
| 7266 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 7267 | } |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7268 | #endif |
| 7269 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7270 | static inline void gen_evsplati(DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7271 | { |
Nathan Froyd | ae01847 | 2010-02-23 12:21:31 -0800 | [diff] [blame] | 7272 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7273 | |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7274 | #if defined(TARGET_PPC64) |
aurel32 | 38d1495 | 2008-11-27 19:30:38 +0000 | [diff] [blame] | 7275 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7276 | #else |
| 7277 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
| 7278 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
| 7279 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7280 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7281 | static inline void gen_evsplatfi(DisasContext *ctx) |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7282 | { |
Nathan Froyd | ae01847 | 2010-02-23 12:21:31 -0800 | [diff] [blame] | 7283 | uint64_t imm = rA(ctx->opcode) << 27; |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7284 | |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7285 | #if defined(TARGET_PPC64) |
aurel32 | 38d1495 | 2008-11-27 19:30:38 +0000 | [diff] [blame] | 7286 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7287 | #else |
| 7288 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
| 7289 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
| 7290 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7291 | } |
| 7292 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7293 | static inline void gen_evsel(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7294 | { |
| 7295 | int l1 = gen_new_label(); |
| 7296 | int l2 = gen_new_label(); |
| 7297 | int l3 = gen_new_label(); |
| 7298 | int l4 = gen_new_label(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7299 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7300 | #if defined(TARGET_PPC64) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7301 | TCGv t1 = tcg_temp_local_new(); |
| 7302 | TCGv t2 = tcg_temp_local_new(); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7303 | #endif |
| 7304 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
| 7305 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
| 7306 | #if defined(TARGET_PPC64) |
| 7307 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); |
| 7308 | #else |
| 7309 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
| 7310 | #endif |
| 7311 | tcg_gen_br(l2); |
| 7312 | gen_set_label(l1); |
| 7313 | #if defined(TARGET_PPC64) |
| 7314 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); |
| 7315 | #else |
| 7316 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
| 7317 | #endif |
| 7318 | gen_set_label(l2); |
| 7319 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); |
| 7320 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); |
| 7321 | #if defined(TARGET_PPC64) |
Aurelien Jarno | 17d9b3a | 2011-03-22 07:41:29 +0100 | [diff] [blame] | 7322 | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7323 | #else |
| 7324 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 7325 | #endif |
| 7326 | tcg_gen_br(l4); |
| 7327 | gen_set_label(l3); |
| 7328 | #if defined(TARGET_PPC64) |
Aurelien Jarno | 17d9b3a | 2011-03-22 07:41:29 +0100 | [diff] [blame] | 7329 | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7330 | #else |
| 7331 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
| 7332 | #endif |
| 7333 | gen_set_label(l4); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7334 | tcg_temp_free_i32(t0); |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7335 | #if defined(TARGET_PPC64) |
| 7336 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); |
| 7337 | tcg_temp_free(t1); |
| 7338 | tcg_temp_free(t2); |
| 7339 | #endif |
| 7340 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 7341 | |
| 7342 | static void gen_evsel0(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7343 | { |
| 7344 | gen_evsel(ctx); |
| 7345 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 7346 | |
| 7347 | static void gen_evsel1(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7348 | { |
| 7349 | gen_evsel(ctx); |
| 7350 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 7351 | |
| 7352 | static void gen_evsel2(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7353 | { |
| 7354 | gen_evsel(ctx); |
| 7355 | } |
Blue Swirl | e8eaa2c | 2009-06-17 15:22:14 +0000 | [diff] [blame] | 7356 | |
| 7357 | static void gen_evsel3(DisasContext *ctx) |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 7358 | { |
| 7359 | gen_evsel(ctx); |
| 7360 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7361 | |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 7362 | /* Multiply */ |
| 7363 | |
| 7364 | static inline void gen_evmwumi(DisasContext *ctx) |
| 7365 | { |
| 7366 | TCGv_i64 t0, t1; |
| 7367 | |
| 7368 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7369 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 7370 | return; |
| 7371 | } |
| 7372 | |
| 7373 | t0 = tcg_temp_new_i64(); |
| 7374 | t1 = tcg_temp_new_i64(); |
| 7375 | |
| 7376 | /* t0 := rA; t1 := rB */ |
| 7377 | #if defined(TARGET_PPC64) |
| 7378 | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
| 7379 | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
| 7380 | #else |
| 7381 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 7382 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 7383 | #endif |
| 7384 | |
| 7385 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ |
| 7386 | |
| 7387 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ |
| 7388 | |
| 7389 | tcg_temp_free_i64(t0); |
| 7390 | tcg_temp_free_i64(t1); |
| 7391 | } |
| 7392 | |
| 7393 | static inline void gen_evmwumia(DisasContext *ctx) |
| 7394 | { |
| 7395 | TCGv_i64 tmp; |
| 7396 | |
| 7397 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7398 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 7399 | return; |
| 7400 | } |
| 7401 | |
| 7402 | gen_evmwumi(ctx); /* rD := rA * rB */ |
| 7403 | |
| 7404 | tmp = tcg_temp_new_i64(); |
| 7405 | |
| 7406 | /* acc := rD */ |
| 7407 | gen_load_gpr64(tmp, rD(ctx->opcode)); |
| 7408 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
| 7409 | tcg_temp_free_i64(tmp); |
| 7410 | } |
| 7411 | |
| 7412 | static inline void gen_evmwumiaa(DisasContext *ctx) |
| 7413 | { |
| 7414 | TCGv_i64 acc; |
| 7415 | TCGv_i64 tmp; |
| 7416 | |
| 7417 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7418 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 7419 | return; |
| 7420 | } |
| 7421 | |
| 7422 | gen_evmwumi(ctx); /* rD := rA * rB */ |
| 7423 | |
| 7424 | acc = tcg_temp_new_i64(); |
| 7425 | tmp = tcg_temp_new_i64(); |
| 7426 | |
| 7427 | /* tmp := rD */ |
| 7428 | gen_load_gpr64(tmp, rD(ctx->opcode)); |
| 7429 | |
| 7430 | /* Load acc */ |
| 7431 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
| 7432 | |
| 7433 | /* acc := tmp + acc */ |
| 7434 | tcg_gen_add_i64(acc, acc, tmp); |
| 7435 | |
| 7436 | /* Store acc */ |
| 7437 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
| 7438 | |
| 7439 | /* rD := acc */ |
| 7440 | gen_store_gpr64(rD(ctx->opcode), acc); |
| 7441 | |
| 7442 | tcg_temp_free_i64(acc); |
| 7443 | tcg_temp_free_i64(tmp); |
| 7444 | } |
| 7445 | |
| 7446 | static inline void gen_evmwsmi(DisasContext *ctx) |
| 7447 | { |
| 7448 | TCGv_i64 t0, t1; |
| 7449 | |
| 7450 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7451 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
Fabien Chouteau | a0e1390 | 2011-03-16 11:21:22 +0100 | [diff] [blame] | 7452 | return; |
| 7453 | } |
| 7454 | |
| 7455 | t0 = tcg_temp_new_i64(); |
| 7456 | t1 = tcg_temp_new_i64(); |
| 7457 | |
| 7458 | /* t0 := rA; t1 := rB */ |
| 7459 | #if defined(TARGET_PPC64) |
| 7460 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
| 7461 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
| 7462 | #else |
| 7463 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
| 7464 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
| 7465 | #endif |
| 7466 | |
| 7467 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ |
| 7468 | |
| 7469 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ |
| 7470 | |
| 7471 | tcg_temp_free_i64(t0); |
| 7472 | tcg_temp_free_i64(t1); |
| 7473 | } |
| 7474 | |
| 7475 | static inline void gen_evmwsmia(DisasContext *ctx) |
| 7476 | { |
| 7477 | TCGv_i64 tmp; |
| 7478 | |
| 7479 | gen_evmwsmi(ctx); /* rD := rA * rB */ |
| 7480 | |
| 7481 | tmp = tcg_temp_new_i64(); |
| 7482 | |
| 7483 | /* acc := rD */ |
| 7484 | gen_load_gpr64(tmp, rD(ctx->opcode)); |
| 7485 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc)); |
| 7486 | |
| 7487 | tcg_temp_free_i64(tmp); |
| 7488 | } |
| 7489 | |
| 7490 | static inline void gen_evmwsmiaa(DisasContext *ctx) |
| 7491 | { |
| 7492 | TCGv_i64 acc = tcg_temp_new_i64(); |
| 7493 | TCGv_i64 tmp = tcg_temp_new_i64(); |
| 7494 | |
| 7495 | gen_evmwsmi(ctx); /* rD := rA * rB */ |
| 7496 | |
| 7497 | acc = tcg_temp_new_i64(); |
| 7498 | tmp = tcg_temp_new_i64(); |
| 7499 | |
| 7500 | /* tmp := rD */ |
| 7501 | gen_load_gpr64(tmp, rD(ctx->opcode)); |
| 7502 | |
| 7503 | /* Load acc */ |
| 7504 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
| 7505 | |
| 7506 | /* acc := tmp + acc */ |
| 7507 | tcg_gen_add_i64(acc, acc, tmp); |
| 7508 | |
| 7509 | /* Store acc */ |
| 7510 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc)); |
| 7511 | |
| 7512 | /* rD := acc */ |
| 7513 | gen_store_gpr64(rD(ctx->opcode), acc); |
| 7514 | |
| 7515 | tcg_temp_free_i64(acc); |
| 7516 | tcg_temp_free_i64(tmp); |
| 7517 | } |
| 7518 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7519 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
| 7520 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
| 7521 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
| 7522 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
| 7523 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
| 7524 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
| 7525 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
| 7526 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // |
| 7527 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); |
| 7528 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// |
| 7529 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
| 7530 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
| 7531 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
| 7532 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
| 7533 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
| 7534 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); |
| 7535 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// |
| 7536 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
| 7537 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
| 7538 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); |
| 7539 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
| 7540 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
| 7541 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // |
| 7542 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); |
| 7543 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
| 7544 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
| 7545 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// |
| 7546 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// |
| 7547 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7548 | |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7549 | /* SPE load and stores */ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7550 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7551 | { |
| 7552 | target_ulong uimm = rB(ctx->opcode); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7553 | |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7554 | if (rA(ctx->opcode) == 0) { |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7555 | tcg_gen_movi_tl(EA, uimm << sh); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7556 | } else { |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7557 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7558 | #if defined(TARGET_PPC64) |
| 7559 | if (!ctx->sf_mode) { |
| 7560 | tcg_gen_ext32u_tl(EA, EA); |
| 7561 | } |
| 7562 | #endif |
| 7563 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7564 | } |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7565 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7566 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7567 | { |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7568 | #if defined(TARGET_PPC64) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7569 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7570 | #else |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7571 | TCGv_i64 t0 = tcg_temp_new_i64(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7572 | gen_qemu_ld64(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7573 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
| 7574 | tcg_gen_shri_i64(t0, t0, 32); |
| 7575 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); |
| 7576 | tcg_temp_free_i64(t0); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7577 | #endif |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7578 | } |
| 7579 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7580 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7581 | { |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7582 | #if defined(TARGET_PPC64) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7583 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7584 | gen_qemu_ld32u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7585 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7586 | gen_addr_add(ctx, addr, addr, 4); |
| 7587 | gen_qemu_ld32u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7588 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7589 | tcg_temp_free(t0); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7590 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7591 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
| 7592 | gen_addr_add(ctx, addr, addr, 4); |
| 7593 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7594 | #endif |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7595 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7596 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7597 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7598 | { |
| 7599 | TCGv t0 = tcg_temp_new(); |
| 7600 | #if defined(TARGET_PPC64) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7601 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7602 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7603 | gen_addr_add(ctx, addr, addr, 2); |
| 7604 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7605 | tcg_gen_shli_tl(t0, t0, 32); |
| 7606 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7607 | gen_addr_add(ctx, addr, addr, 2); |
| 7608 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7609 | tcg_gen_shli_tl(t0, t0, 16); |
| 7610 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7611 | gen_addr_add(ctx, addr, addr, 2); |
| 7612 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7613 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7614 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7615 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7616 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7617 | gen_addr_add(ctx, addr, addr, 2); |
| 7618 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7619 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7620 | gen_addr_add(ctx, addr, addr, 2); |
| 7621 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7622 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7623 | gen_addr_add(ctx, addr, addr, 2); |
| 7624 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7625 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7626 | #endif |
| 7627 | tcg_temp_free(t0); |
| 7628 | } |
| 7629 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7630 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7631 | { |
| 7632 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7633 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7634 | #if defined(TARGET_PPC64) |
| 7635 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
| 7636 | tcg_gen_shli_tl(t0, t0, 16); |
| 7637 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7638 | #else |
| 7639 | tcg_gen_shli_tl(t0, t0, 16); |
| 7640 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
| 7641 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 7642 | #endif |
| 7643 | tcg_temp_free(t0); |
| 7644 | } |
| 7645 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7646 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7647 | { |
| 7648 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7649 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7650 | #if defined(TARGET_PPC64) |
| 7651 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
| 7652 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7653 | #else |
| 7654 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
| 7655 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 7656 | #endif |
| 7657 | tcg_temp_free(t0); |
| 7658 | } |
| 7659 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7660 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7661 | { |
| 7662 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7663 | gen_qemu_ld16s(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7664 | #if defined(TARGET_PPC64) |
| 7665 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
| 7666 | tcg_gen_ext32u_tl(t0, t0); |
| 7667 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7668 | #else |
| 7669 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
| 7670 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 7671 | #endif |
| 7672 | tcg_temp_free(t0); |
| 7673 | } |
| 7674 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7675 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7676 | { |
| 7677 | TCGv t0 = tcg_temp_new(); |
| 7678 | #if defined(TARGET_PPC64) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7679 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7680 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7681 | gen_addr_add(ctx, addr, addr, 2); |
| 7682 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7683 | tcg_gen_shli_tl(t0, t0, 16); |
| 7684 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7685 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7686 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7687 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7688 | gen_addr_add(ctx, addr, addr, 2); |
| 7689 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7690 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
| 7691 | #endif |
| 7692 | tcg_temp_free(t0); |
| 7693 | } |
| 7694 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7695 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7696 | { |
| 7697 | #if defined(TARGET_PPC64) |
| 7698 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7699 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
| 7700 | gen_addr_add(ctx, addr, addr, 2); |
| 7701 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7702 | tcg_gen_shli_tl(t0, t0, 32); |
| 7703 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7704 | tcg_temp_free(t0); |
| 7705 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7706 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
| 7707 | gen_addr_add(ctx, addr, addr, 2); |
| 7708 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7709 | #endif |
| 7710 | } |
| 7711 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7712 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7713 | { |
| 7714 | #if defined(TARGET_PPC64) |
| 7715 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7716 | gen_qemu_ld16s(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7717 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7718 | gen_addr_add(ctx, addr, addr, 2); |
| 7719 | gen_qemu_ld16s(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7720 | tcg_gen_shli_tl(t0, t0, 32); |
| 7721 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7722 | tcg_temp_free(t0); |
| 7723 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7724 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
| 7725 | gen_addr_add(ctx, addr, addr, 2); |
| 7726 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7727 | #endif |
| 7728 | } |
| 7729 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7730 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7731 | { |
| 7732 | TCGv t0 = tcg_temp_new(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7733 | gen_qemu_ld32u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7734 | #if defined(TARGET_PPC64) |
| 7735 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
| 7736 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7737 | #else |
| 7738 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
| 7739 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
| 7740 | #endif |
| 7741 | tcg_temp_free(t0); |
| 7742 | } |
| 7743 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7744 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7745 | { |
| 7746 | TCGv t0 = tcg_temp_new(); |
| 7747 | #if defined(TARGET_PPC64) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7748 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7749 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
| 7750 | tcg_gen_shli_tl(t0, t0, 32); |
| 7751 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7752 | gen_addr_add(ctx, addr, addr, 2); |
| 7753 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7754 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7755 | tcg_gen_shli_tl(t0, t0, 16); |
| 7756 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
| 7757 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7758 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7759 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
| 7760 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7761 | gen_addr_add(ctx, addr, addr, 2); |
| 7762 | gen_qemu_ld16u(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7763 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
| 7764 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
| 7765 | #endif |
| 7766 | tcg_temp_free(t0); |
| 7767 | } |
| 7768 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7769 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7770 | { |
| 7771 | #if defined(TARGET_PPC64) |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7772 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7773 | #else |
| 7774 | TCGv_i64 t0 = tcg_temp_new_i64(); |
| 7775 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7776 | gen_qemu_st64(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7777 | tcg_temp_free_i64(t0); |
| 7778 | #endif |
| 7779 | } |
| 7780 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7781 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7782 | { |
| 7783 | #if defined(TARGET_PPC64) |
| 7784 | TCGv t0 = tcg_temp_new(); |
| 7785 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7786 | gen_qemu_st32(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7787 | tcg_temp_free(t0); |
| 7788 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7789 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7790 | #endif |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7791 | gen_addr_add(ctx, addr, addr, 4); |
| 7792 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7793 | } |
| 7794 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7795 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7796 | { |
| 7797 | TCGv t0 = tcg_temp_new(); |
| 7798 | #if defined(TARGET_PPC64) |
| 7799 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); |
| 7800 | #else |
| 7801 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
| 7802 | #endif |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7803 | gen_qemu_st16(ctx, t0, addr); |
| 7804 | gen_addr_add(ctx, addr, addr, 2); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7805 | #if defined(TARGET_PPC64) |
| 7806 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7807 | gen_qemu_st16(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7808 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7809 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7810 | #endif |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7811 | gen_addr_add(ctx, addr, addr, 2); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7812 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7813 | gen_qemu_st16(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7814 | tcg_temp_free(t0); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7815 | gen_addr_add(ctx, addr, addr, 2); |
| 7816 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7817 | } |
| 7818 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7819 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7820 | { |
| 7821 | TCGv t0 = tcg_temp_new(); |
| 7822 | #if defined(TARGET_PPC64) |
| 7823 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); |
| 7824 | #else |
| 7825 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
| 7826 | #endif |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7827 | gen_qemu_st16(ctx, t0, addr); |
| 7828 | gen_addr_add(ctx, addr, addr, 2); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7829 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7830 | gen_qemu_st16(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7831 | tcg_temp_free(t0); |
| 7832 | } |
| 7833 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7834 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7835 | { |
| 7836 | #if defined(TARGET_PPC64) |
| 7837 | TCGv t0 = tcg_temp_new(); |
| 7838 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7839 | gen_qemu_st16(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7840 | tcg_temp_free(t0); |
| 7841 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7842 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7843 | #endif |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7844 | gen_addr_add(ctx, addr, addr, 2); |
| 7845 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7846 | } |
| 7847 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7848 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7849 | { |
| 7850 | #if defined(TARGET_PPC64) |
| 7851 | TCGv t0 = tcg_temp_new(); |
| 7852 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7853 | gen_qemu_st32(ctx, t0, addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7854 | tcg_temp_free(t0); |
| 7855 | #else |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7856 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7857 | #endif |
| 7858 | } |
| 7859 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7860 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7861 | { |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7862 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7863 | } |
| 7864 | |
| 7865 | #define GEN_SPEOP_LDST(name, opc2, sh) \ |
Blue Swirl | 99e300e | 2009-06-17 15:22:09 +0000 | [diff] [blame] | 7866 | static void glue(gen_, name)(DisasContext *ctx) \ |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7867 | { \ |
| 7868 | TCGv t0; \ |
| 7869 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 7870 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7871 | return; \ |
| 7872 | } \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7873 | gen_set_access_type(ctx, ACCESS_INT); \ |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7874 | t0 = tcg_temp_new(); \ |
| 7875 | if (Rc(ctx->opcode)) { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7876 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7877 | } else { \ |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 7878 | gen_addr_reg_index(ctx, t0); \ |
aurel32 | 6a6ae23 | 2008-11-27 19:30:47 +0000 | [diff] [blame] | 7879 | } \ |
| 7880 | gen_op_##name(ctx, t0); \ |
| 7881 | tcg_temp_free(t0); \ |
| 7882 | } |
| 7883 | |
| 7884 | GEN_SPEOP_LDST(evldd, 0x00, 3); |
| 7885 | GEN_SPEOP_LDST(evldw, 0x01, 3); |
| 7886 | GEN_SPEOP_LDST(evldh, 0x02, 3); |
| 7887 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); |
| 7888 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); |
| 7889 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); |
| 7890 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); |
| 7891 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); |
| 7892 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); |
| 7893 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); |
| 7894 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); |
| 7895 | |
| 7896 | GEN_SPEOP_LDST(evstdd, 0x10, 3); |
| 7897 | GEN_SPEOP_LDST(evstdw, 0x11, 3); |
| 7898 | GEN_SPEOP_LDST(evstdh, 0x12, 3); |
| 7899 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); |
| 7900 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); |
| 7901 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); |
| 7902 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7903 | |
| 7904 | /* Multiply and add - TODO */ |
| 7905 | #if 0 |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7906 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
| 7907 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7908 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); |
| 7909 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7910 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); |
| 7911 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7912 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7913 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7914 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); |
| 7915 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7916 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); |
| 7917 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7918 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7919 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7920 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
| 7921 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
| 7922 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7923 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7924 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7925 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7926 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
| 7927 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
| 7928 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7929 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7930 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7931 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7932 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); |
| 7933 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); |
| 7934 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); |
| 7935 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); |
| 7936 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7937 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7938 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7939 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7940 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7941 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7942 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7943 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7944 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7945 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7946 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7947 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7948 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); |
| 7949 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7950 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7951 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); |
| 7952 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); |
| 7953 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7954 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7955 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7956 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7957 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7958 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7959 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7960 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7961 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7962 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7963 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7964 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7965 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7966 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); |
| 7967 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7968 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 7969 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); |
| 7970 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); |
| 7971 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
| 7972 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); |
| 7973 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7974 | #endif |
| 7975 | |
| 7976 | /*** SPE floating-point extension ***/ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 7977 | #if defined(TARGET_PPC64) |
| 7978 | #define GEN_SPEFPUOP_CONV_32_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7979 | static inline void gen_##name(DisasContext *ctx) \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7980 | { \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 7981 | TCGv_i32 t0; \ |
| 7982 | TCGv t1; \ |
| 7983 | t0 = tcg_temp_new_i32(); \ |
| 7984 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
| 7985 | gen_helper_##name(t0, t0); \ |
| 7986 | t1 = tcg_temp_new(); \ |
| 7987 | tcg_gen_extu_i32_tl(t1, t0); \ |
| 7988 | tcg_temp_free_i32(t0); \ |
| 7989 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
| 7990 | 0xFFFFFFFF00000000ULL); \ |
| 7991 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
| 7992 | tcg_temp_free(t1); \ |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 7993 | } |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 7994 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 7995 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 7996 | { \ |
| 7997 | TCGv_i32 t0; \ |
| 7998 | TCGv t1; \ |
| 7999 | t0 = tcg_temp_new_i32(); \ |
| 8000 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
| 8001 | t1 = tcg_temp_new(); \ |
| 8002 | tcg_gen_extu_i32_tl(t1, t0); \ |
| 8003 | tcg_temp_free_i32(t0); \ |
| 8004 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
| 8005 | 0xFFFFFFFF00000000ULL); \ |
| 8006 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
| 8007 | tcg_temp_free(t1); \ |
| 8008 | } |
| 8009 | #define GEN_SPEFPUOP_CONV_64_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8010 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8011 | { \ |
| 8012 | TCGv_i32 t0 = tcg_temp_new_i32(); \ |
| 8013 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
| 8014 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
| 8015 | tcg_temp_free_i32(t0); \ |
| 8016 | } |
| 8017 | #define GEN_SPEFPUOP_CONV_64_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8018 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8019 | { \ |
| 8020 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
| 8021 | } |
| 8022 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8023 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8024 | { \ |
| 8025 | TCGv_i32 t0, t1; \ |
| 8026 | TCGv_i64 t2; \ |
| 8027 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8028 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8029 | return; \ |
| 8030 | } \ |
| 8031 | t0 = tcg_temp_new_i32(); \ |
| 8032 | t1 = tcg_temp_new_i32(); \ |
| 8033 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 8034 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
| 8035 | gen_helper_##name(t0, t0, t1); \ |
| 8036 | tcg_temp_free_i32(t1); \ |
| 8037 | t2 = tcg_temp_new(); \ |
| 8038 | tcg_gen_extu_i32_tl(t2, t0); \ |
| 8039 | tcg_temp_free_i32(t0); \ |
| 8040 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
| 8041 | 0xFFFFFFFF00000000ULL); \ |
| 8042 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ |
| 8043 | tcg_temp_free(t2); \ |
| 8044 | } |
| 8045 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8046 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8047 | { \ |
| 8048 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8049 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8050 | return; \ |
| 8051 | } \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8052 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
| 8053 | cpu_gpr[rB(ctx->opcode)]); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8054 | } |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8055 | #define GEN_SPEFPUOP_COMP_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8056 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8057 | { \ |
| 8058 | TCGv_i32 t0, t1; \ |
| 8059 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8060 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8061 | return; \ |
| 8062 | } \ |
| 8063 | t0 = tcg_temp_new_i32(); \ |
| 8064 | t1 = tcg_temp_new_i32(); \ |
| 8065 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
| 8066 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
| 8067 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
| 8068 | tcg_temp_free_i32(t0); \ |
| 8069 | tcg_temp_free_i32(t1); \ |
| 8070 | } |
| 8071 | #define GEN_SPEFPUOP_COMP_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8072 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8073 | { \ |
| 8074 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8075 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8076 | return; \ |
| 8077 | } \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8078 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
| 8079 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8080 | } |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8081 | #else |
| 8082 | #define GEN_SPEFPUOP_CONV_32_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8083 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8084 | { \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8085 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
| 8086 | } |
| 8087 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8088 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8089 | { \ |
| 8090 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
| 8091 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
| 8092 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ |
| 8093 | tcg_temp_free_i64(t0); \ |
| 8094 | } |
| 8095 | #define GEN_SPEFPUOP_CONV_64_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8096 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8097 | { \ |
| 8098 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
| 8099 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ |
| 8100 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
| 8101 | tcg_temp_free_i64(t0); \ |
| 8102 | } |
| 8103 | #define GEN_SPEFPUOP_CONV_64_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8104 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8105 | { \ |
| 8106 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
| 8107 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
| 8108 | gen_helper_##name(t0, t0); \ |
| 8109 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
| 8110 | tcg_temp_free_i64(t0); \ |
| 8111 | } |
| 8112 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8113 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8114 | { \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8115 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8116 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8117 | return; \ |
| 8118 | } \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8119 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ |
| 8120 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8121 | } |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8122 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8123 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8124 | { \ |
| 8125 | TCGv_i64 t0, t1; \ |
| 8126 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8127 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8128 | return; \ |
| 8129 | } \ |
| 8130 | t0 = tcg_temp_new_i64(); \ |
| 8131 | t1 = tcg_temp_new_i64(); \ |
| 8132 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
| 8133 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
| 8134 | gen_helper_##name(t0, t0, t1); \ |
| 8135 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
| 8136 | tcg_temp_free_i64(t0); \ |
| 8137 | tcg_temp_free_i64(t1); \ |
| 8138 | } |
| 8139 | #define GEN_SPEFPUOP_COMP_32(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8140 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8141 | { \ |
| 8142 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8143 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8144 | return; \ |
| 8145 | } \ |
| 8146 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ |
| 8147 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
| 8148 | } |
| 8149 | #define GEN_SPEFPUOP_COMP_64(name) \ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8150 | static inline void gen_##name(DisasContext *ctx) \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8151 | { \ |
| 8152 | TCGv_i64 t0, t1; \ |
| 8153 | if (unlikely(!ctx->spe_enabled)) { \ |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8154 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8155 | return; \ |
| 8156 | } \ |
| 8157 | t0 = tcg_temp_new_i64(); \ |
| 8158 | t1 = tcg_temp_new_i64(); \ |
| 8159 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
| 8160 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
| 8161 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ |
| 8162 | tcg_temp_free_i64(t0); \ |
| 8163 | tcg_temp_free_i64(t1); \ |
| 8164 | } |
| 8165 | #endif |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 8166 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8167 | /* Single precision floating-point vectors operations */ |
| 8168 | /* Arithmetic */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8169 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
| 8170 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
| 8171 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
| 8172 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8173 | static inline void gen_evfsabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8174 | { |
| 8175 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8176 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8177 | return; |
| 8178 | } |
| 8179 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8180 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8181 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8182 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); |
| 8183 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8184 | #endif |
| 8185 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8186 | static inline void gen_evfsnabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8187 | { |
| 8188 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8189 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8190 | return; |
| 8191 | } |
| 8192 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8193 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8194 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8195 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
| 8196 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8197 | #endif |
| 8198 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8199 | static inline void gen_evfsneg(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8200 | { |
| 8201 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8202 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8203 | return; |
| 8204 | } |
| 8205 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8206 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8207 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8208 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
| 8209 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8210 | #endif |
| 8211 | } |
| 8212 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8213 | /* Conversion */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8214 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
| 8215 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); |
| 8216 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); |
| 8217 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); |
| 8218 | GEN_SPEFPUOP_CONV_64_64(evfsctui); |
| 8219 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); |
| 8220 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); |
| 8221 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); |
| 8222 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); |
| 8223 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); |
| 8224 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8225 | /* Comparison */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8226 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
| 8227 | GEN_SPEFPUOP_COMP_64(evfscmplt); |
| 8228 | GEN_SPEFPUOP_COMP_64(evfscmpeq); |
| 8229 | GEN_SPEFPUOP_COMP_64(evfststgt); |
| 8230 | GEN_SPEFPUOP_COMP_64(evfststlt); |
| 8231 | GEN_SPEFPUOP_COMP_64(evfststeq); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8232 | |
| 8233 | /* Opcodes definitions */ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 8234 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
| 8235 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // |
| 8236 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8237 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
| 8238 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
| 8239 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8240 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8241 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8242 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8243 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8244 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8245 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8246 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
| 8247 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8248 | |
| 8249 | /* Single precision floating-point operations */ |
| 8250 | /* Arithmetic */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8251 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
| 8252 | GEN_SPEFPUOP_ARITH2_32_32(efssub); |
| 8253 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
| 8254 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8255 | static inline void gen_efsabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8256 | { |
| 8257 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8258 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8259 | return; |
| 8260 | } |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8261 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8262 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8263 | static inline void gen_efsnabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8264 | { |
| 8265 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8266 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8267 | return; |
| 8268 | } |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8269 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8270 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8271 | static inline void gen_efsneg(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8272 | { |
| 8273 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8274 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8275 | return; |
| 8276 | } |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8277 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8278 | } |
| 8279 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8280 | /* Conversion */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8281 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
| 8282 | GEN_SPEFPUOP_CONV_32_32(efscfsi); |
| 8283 | GEN_SPEFPUOP_CONV_32_32(efscfuf); |
| 8284 | GEN_SPEFPUOP_CONV_32_32(efscfsf); |
| 8285 | GEN_SPEFPUOP_CONV_32_32(efsctui); |
| 8286 | GEN_SPEFPUOP_CONV_32_32(efsctsi); |
| 8287 | GEN_SPEFPUOP_CONV_32_32(efsctuf); |
| 8288 | GEN_SPEFPUOP_CONV_32_32(efsctsf); |
| 8289 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); |
| 8290 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); |
| 8291 | GEN_SPEFPUOP_CONV_32_64(efscfd); |
| 8292 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8293 | /* Comparison */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8294 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
| 8295 | GEN_SPEFPUOP_COMP_32(efscmplt); |
| 8296 | GEN_SPEFPUOP_COMP_32(efscmpeq); |
| 8297 | GEN_SPEFPUOP_COMP_32(efststgt); |
| 8298 | GEN_SPEFPUOP_COMP_32(efststlt); |
| 8299 | GEN_SPEFPUOP_COMP_32(efststeq); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8300 | |
| 8301 | /* Opcodes definitions */ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 8302 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
| 8303 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // |
| 8304 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8305 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
| 8306 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
| 8307 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // |
| 8308 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8309 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8310 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8311 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
| 8312 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8313 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
| 8314 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
| 8315 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8316 | |
| 8317 | /* Double precision floating-point operations */ |
| 8318 | /* Arithmetic */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8319 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
| 8320 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
| 8321 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
| 8322 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8323 | static inline void gen_efdabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8324 | { |
| 8325 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8326 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8327 | return; |
| 8328 | } |
| 8329 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8330 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8331 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8332 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 8333 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8334 | #endif |
| 8335 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8336 | static inline void gen_efdnabs(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8337 | { |
| 8338 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8339 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8340 | return; |
| 8341 | } |
| 8342 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8343 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8344 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8345 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 8346 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8347 | #endif |
| 8348 | } |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 8349 | static inline void gen_efdneg(DisasContext *ctx) |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8350 | { |
| 8351 | if (unlikely(!ctx->spe_enabled)) { |
Alexander Graf | 27a69bb | 2011-08-23 06:55:43 +0200 | [diff] [blame] | 8352 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8353 | return; |
| 8354 | } |
| 8355 | #if defined(TARGET_PPC64) |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8356 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8357 | #else |
Mike Pall | 6d5c34f | 2010-12-31 21:17:53 +0100 | [diff] [blame] | 8358 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
| 8359 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8360 | #endif |
| 8361 | } |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8362 | |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8363 | /* Conversion */ |
| 8364 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
| 8365 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); |
| 8366 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); |
| 8367 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); |
| 8368 | GEN_SPEFPUOP_CONV_32_64(efdctui); |
| 8369 | GEN_SPEFPUOP_CONV_32_64(efdctsi); |
| 8370 | GEN_SPEFPUOP_CONV_32_64(efdctuf); |
| 8371 | GEN_SPEFPUOP_CONV_32_64(efdctsf); |
| 8372 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); |
| 8373 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); |
| 8374 | GEN_SPEFPUOP_CONV_64_32(efdcfs); |
| 8375 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); |
| 8376 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); |
| 8377 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); |
| 8378 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); |
| 8379 | |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8380 | /* Comparison */ |
aurel32 | 1c97856 | 2008-11-23 10:54:04 +0000 | [diff] [blame] | 8381 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
| 8382 | GEN_SPEFPUOP_COMP_64(efdcmplt); |
| 8383 | GEN_SPEFPUOP_COMP_64(efdcmpeq); |
| 8384 | GEN_SPEFPUOP_COMP_64(efdtstgt); |
| 8385 | GEN_SPEFPUOP_COMP_64(efdtstlt); |
| 8386 | GEN_SPEFPUOP_COMP_64(efdtsteq); |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8387 | |
| 8388 | /* Opcodes definitions */ |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 8389 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
| 8390 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8391 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // |
| 8392 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
| 8393 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
| 8394 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8395 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // |
| 8396 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8397 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8398 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8399 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8400 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
| 8401 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
| 8402 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
| 8403 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // |
| 8404 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
j_mayer | 0487d6a | 2007-03-20 22:11:31 +0000 | [diff] [blame] | 8405 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 8406 | static opcode_t opcodes[] = { |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8407 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
| 8408 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
| 8409 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
| 8410 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), |
| 8411 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
| 8412 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
| 8413 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8414 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8415 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8416 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8417 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
| 8418 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
| 8419 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
| 8420 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
| 8421 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8422 | #if defined(TARGET_PPC64) |
| 8423 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
| 8424 | #endif |
| 8425 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
| 8426 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
| 8427 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8428 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8429 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8430 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
| 8431 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
| 8432 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
| 8433 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8434 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8435 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8436 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8437 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), |
David Gibson | eaabeef | 2011-04-01 15:15:13 +1100 | [diff] [blame] | 8438 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8439 | #if defined(TARGET_PPC64) |
David Gibson | eaabeef | 2011-04-01 15:15:13 +1100 | [diff] [blame] | 8440 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8441 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
| 8442 | #endif |
| 8443 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8444 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8445 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8446 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
| 8447 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
| 8448 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
| 8449 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
| 8450 | #if defined(TARGET_PPC64) |
| 8451 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
| 8452 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
| 8453 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
| 8454 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
| 8455 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
| 8456 | #endif |
| 8457 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), |
| 8458 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
| 8459 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
| 8460 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), |
| 8461 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), |
| 8462 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
| 8463 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
| 8464 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), |
| 8465 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), |
| 8466 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), |
| 8467 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT), |
| 8468 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT), |
| 8469 | #if defined(TARGET_PPC64) |
| 8470 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
| 8471 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
| 8472 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
| 8473 | #endif |
| 8474 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8475 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
| 8476 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
| 8477 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
| 8478 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
| 8479 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
| 8480 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), |
| 8481 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
Alexander Graf | f844c81 | 2010-09-10 15:08:33 +0000 | [diff] [blame] | 8482 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8483 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
| 8484 | #if defined(TARGET_PPC64) |
Alexander Graf | f844c81 | 2010-09-10 15:08:33 +0000 | [diff] [blame] | 8485 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8486 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
| 8487 | #endif |
| 8488 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
| 8489 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
| 8490 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
| 8491 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
| 8492 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
| 8493 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
| 8494 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
| 8495 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
| 8496 | #if defined(TARGET_PPC64) |
| 8497 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
| 8498 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
| 8499 | #endif |
| 8500 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
| 8501 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
| 8502 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
| 8503 | #if defined(TARGET_PPC64) |
| 8504 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
| 8505 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
| 8506 | #endif |
| 8507 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
| 8508 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
| 8509 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
| 8510 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
| 8511 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
| 8512 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
| 8513 | #if defined(TARGET_PPC64) |
| 8514 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
| 8515 | #endif |
| 8516 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), |
| 8517 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), |
| 8518 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
| 8519 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
| 8520 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
| 8521 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), |
| 8522 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), |
| 8523 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), |
| 8524 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), |
| 8525 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
| 8526 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |
| 8527 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
| 8528 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
| 8529 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
| 8530 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
| 8531 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
| 8532 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
| 8533 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
| 8534 | #if defined(TARGET_PPC64) |
| 8535 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
| 8536 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
| 8537 | PPC_SEGMENT_64B), |
| 8538 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
| 8539 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
| 8540 | PPC_SEGMENT_64B), |
David Gibson | efdef95 | 2011-04-01 15:15:11 +1100 | [diff] [blame] | 8541 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
| 8542 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), |
| 8543 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8544 | #endif |
| 8545 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
| 8546 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), |
| 8547 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), |
| 8548 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
| 8549 | #if defined(TARGET_PPC64) |
| 8550 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |
| 8551 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
| 8552 | #endif |
| 8553 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
| 8554 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
| 8555 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
| 8556 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
| 8557 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
| 8558 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
| 8559 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
| 8560 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
| 8561 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
| 8562 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
| 8563 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
| 8564 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
| 8565 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
| 8566 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
| 8567 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
| 8568 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
| 8569 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
| 8570 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
| 8571 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
| 8572 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
| 8573 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
| 8574 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
| 8575 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
| 8576 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
| 8577 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
| 8578 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
| 8579 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
| 8580 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
| 8581 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
| 8582 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
| 8583 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
| 8584 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
| 8585 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
| 8586 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
| 8587 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
| 8588 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
| 8589 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
| 8590 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
| 8591 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
| 8592 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
| 8593 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
| 8594 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
| 8595 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
| 8596 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
| 8597 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
| 8598 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
| 8599 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
| 8600 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
| 8601 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
| 8602 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
| 8603 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
| 8604 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
| 8605 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
| 8606 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
| 8607 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
| 8608 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
| 8609 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
| 8610 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
| 8611 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
| 8612 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
| 8613 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
| 8614 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
| 8615 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
| 8616 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
| 8617 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
| 8618 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
| 8619 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
| 8620 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
| 8621 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
| 8622 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
| 8623 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 8624 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8625 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
| 8626 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
| 8627 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
| 8628 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
| 8629 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
| 8630 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
| 8631 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
| 8632 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 8633 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
| 8634 | PPC_NONE, PPC2_BOOKE206), |
| 8635 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, |
| 8636 | PPC_NONE, PPC2_BOOKE206), |
| 8637 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, |
| 8638 | PPC_NONE, PPC2_BOOKE206), |
| 8639 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, |
| 8640 | PPC_NONE, PPC2_BOOKE206), |
Alexander Graf | 6d3db82 | 2012-01-20 04:09:15 +0100 | [diff] [blame] | 8641 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
| 8642 | PPC_NONE, PPC2_BOOKE206), |
Alexander Graf | d5d11a3 | 2012-01-31 03:19:23 +0100 | [diff] [blame] | 8643 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
| 8644 | PPC_NONE, PPC2_PRCNTL), |
Alexander Graf | 9e0b5cb | 2012-01-31 03:18:35 +0100 | [diff] [blame] | 8645 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
| 8646 | PPC_NONE, PPC2_PRCNTL), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8647 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
Baojun Wang | fbe7300 | 2009-07-03 18:56:57 +0800 | [diff] [blame] | 8648 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8649 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 8650 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
| 8651 | PPC_BOOKE, PPC2_BOOKE206), |
Alexander Graf | dcb2b9e1 | 2012-01-21 03:48:58 +0100 | [diff] [blame] | 8652 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 8653 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
| 8654 | PPC_BOOKE, PPC2_BOOKE206), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 8655 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
| 8656 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
| 8657 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
| 8658 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
| 8659 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), |
| 8660 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
| 8661 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), |
| 8662 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), |
| 8663 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), |
| 8664 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), |
| 8665 | |
| 8666 | #undef GEN_INT_ARITH_ADD |
| 8667 | #undef GEN_INT_ARITH_ADD_CONST |
| 8668 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ |
| 8669 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
| 8670 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ |
| 8671 | add_ca, compute_ca, compute_ov) \ |
| 8672 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
| 8673 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
| 8674 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
| 8675 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
| 8676 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
| 8677 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
| 8678 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
| 8679 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
| 8680 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
| 8681 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
| 8682 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
| 8683 | |
| 8684 | #undef GEN_INT_ARITH_DIVW |
| 8685 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ |
| 8686 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
| 8687 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
| 8688 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
| 8689 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
| 8690 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
| 8691 | |
| 8692 | #if defined(TARGET_PPC64) |
| 8693 | #undef GEN_INT_ARITH_DIVD |
| 8694 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
| 8695 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
| 8696 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
| 8697 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
| 8698 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
| 8699 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
| 8700 | |
| 8701 | #undef GEN_INT_ARITH_MUL_HELPER |
| 8702 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
| 8703 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
| 8704 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), |
| 8705 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), |
| 8706 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), |
| 8707 | #endif |
| 8708 | |
| 8709 | #undef GEN_INT_ARITH_SUBF |
| 8710 | #undef GEN_INT_ARITH_SUBF_CONST |
| 8711 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ |
| 8712 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
| 8713 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ |
| 8714 | add_ca, compute_ca, compute_ov) \ |
| 8715 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
| 8716 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
| 8717 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
| 8718 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
| 8719 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
| 8720 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
| 8721 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
| 8722 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
| 8723 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
| 8724 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
| 8725 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
| 8726 | |
| 8727 | #undef GEN_LOGICAL1 |
| 8728 | #undef GEN_LOGICAL2 |
| 8729 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
| 8730 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
| 8731 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
| 8732 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
| 8733 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), |
| 8734 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), |
| 8735 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), |
| 8736 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), |
| 8737 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), |
| 8738 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), |
| 8739 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), |
| 8740 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), |
| 8741 | #if defined(TARGET_PPC64) |
| 8742 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), |
| 8743 | #endif |
| 8744 | |
| 8745 | #if defined(TARGET_PPC64) |
| 8746 | #undef GEN_PPC64_R2 |
| 8747 | #undef GEN_PPC64_R4 |
| 8748 | #define GEN_PPC64_R2(name, opc1, opc2) \ |
| 8749 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
| 8750 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
| 8751 | PPC_64B) |
| 8752 | #define GEN_PPC64_R4(name, opc1, opc2) \ |
| 8753 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
| 8754 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
| 8755 | PPC_64B), \ |
| 8756 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
| 8757 | PPC_64B), \ |
| 8758 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
| 8759 | PPC_64B) |
| 8760 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
| 8761 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
| 8762 | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
| 8763 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
| 8764 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
| 8765 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
| 8766 | #endif |
| 8767 | |
| 8768 | #undef _GEN_FLOAT_ACB |
| 8769 | #undef GEN_FLOAT_ACB |
| 8770 | #undef _GEN_FLOAT_AB |
| 8771 | #undef GEN_FLOAT_AB |
| 8772 | #undef _GEN_FLOAT_AC |
| 8773 | #undef GEN_FLOAT_AC |
| 8774 | #undef GEN_FLOAT_B |
| 8775 | #undef GEN_FLOAT_BS |
| 8776 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
| 8777 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) |
| 8778 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
| 8779 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ |
| 8780 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) |
| 8781 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
| 8782 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
| 8783 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
| 8784 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
| 8785 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
| 8786 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
| 8787 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
| 8788 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
| 8789 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
| 8790 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
| 8791 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
| 8792 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) |
| 8793 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
| 8794 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) |
| 8795 | |
| 8796 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), |
| 8797 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), |
| 8798 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), |
| 8799 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), |
| 8800 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), |
| 8801 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), |
| 8802 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), |
| 8803 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), |
| 8804 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), |
| 8805 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), |
| 8806 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), |
| 8807 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), |
| 8808 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
| 8809 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
| 8810 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
| 8811 | #if defined(TARGET_PPC64) |
| 8812 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), |
| 8813 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
| 8814 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
| 8815 | #endif |
| 8816 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
| 8817 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), |
| 8818 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), |
| 8819 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), |
| 8820 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT), |
| 8821 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT), |
| 8822 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT), |
| 8823 | |
| 8824 | #undef GEN_LD |
| 8825 | #undef GEN_LDU |
| 8826 | #undef GEN_LDUX |
| 8827 | #undef GEN_LDX |
| 8828 | #undef GEN_LDS |
| 8829 | #define GEN_LD(name, ldop, opc, type) \ |
| 8830 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8831 | #define GEN_LDU(name, ldop, opc, type) \ |
| 8832 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8833 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
| 8834 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
| 8835 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
| 8836 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
| 8837 | #define GEN_LDS(name, ldop, op, type) \ |
| 8838 | GEN_LD(name, ldop, op | 0x20, type) \ |
| 8839 | GEN_LDU(name, ldop, op | 0x21, type) \ |
| 8840 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
| 8841 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
| 8842 | |
| 8843 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) |
| 8844 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) |
| 8845 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) |
| 8846 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) |
| 8847 | #if defined(TARGET_PPC64) |
| 8848 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
| 8849 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
| 8850 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) |
| 8851 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) |
| 8852 | #endif |
| 8853 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
| 8854 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
| 8855 | |
| 8856 | #undef GEN_ST |
| 8857 | #undef GEN_STU |
| 8858 | #undef GEN_STUX |
| 8859 | #undef GEN_STX |
| 8860 | #undef GEN_STS |
| 8861 | #define GEN_ST(name, stop, opc, type) \ |
| 8862 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8863 | #define GEN_STU(name, stop, opc, type) \ |
| 8864 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8865 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
| 8866 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
| 8867 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
| 8868 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
| 8869 | #define GEN_STS(name, stop, op, type) \ |
| 8870 | GEN_ST(name, stop, op | 0x20, type) \ |
| 8871 | GEN_STU(name, stop, op | 0x21, type) \ |
| 8872 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
| 8873 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
| 8874 | |
| 8875 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) |
| 8876 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) |
| 8877 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) |
| 8878 | #if defined(TARGET_PPC64) |
| 8879 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) |
| 8880 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) |
| 8881 | #endif |
| 8882 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
| 8883 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
| 8884 | |
| 8885 | #undef GEN_LDF |
| 8886 | #undef GEN_LDUF |
| 8887 | #undef GEN_LDUXF |
| 8888 | #undef GEN_LDXF |
| 8889 | #undef GEN_LDFS |
| 8890 | #define GEN_LDF(name, ldop, opc, type) \ |
| 8891 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8892 | #define GEN_LDUF(name, ldop, opc, type) \ |
| 8893 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8894 | #define GEN_LDUXF(name, ldop, opc, type) \ |
| 8895 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
| 8896 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
| 8897 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
| 8898 | #define GEN_LDFS(name, ldop, op, type) \ |
| 8899 | GEN_LDF(name, ldop, op | 0x20, type) \ |
| 8900 | GEN_LDUF(name, ldop, op | 0x21, type) \ |
| 8901 | GEN_LDUXF(name, ldop, op | 0x01, type) \ |
| 8902 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
| 8903 | |
| 8904 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) |
| 8905 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) |
| 8906 | |
| 8907 | #undef GEN_STF |
| 8908 | #undef GEN_STUF |
| 8909 | #undef GEN_STUXF |
| 8910 | #undef GEN_STXF |
| 8911 | #undef GEN_STFS |
| 8912 | #define GEN_STF(name, stop, opc, type) \ |
| 8913 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8914 | #define GEN_STUF(name, stop, opc, type) \ |
| 8915 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
| 8916 | #define GEN_STUXF(name, stop, opc, type) \ |
| 8917 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
| 8918 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
| 8919 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
| 8920 | #define GEN_STFS(name, stop, op, type) \ |
| 8921 | GEN_STF(name, stop, op | 0x20, type) \ |
| 8922 | GEN_STUF(name, stop, op | 0x21, type) \ |
| 8923 | GEN_STUXF(name, stop, op | 0x01, type) \ |
| 8924 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
| 8925 | |
| 8926 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) |
| 8927 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) |
| 8928 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) |
| 8929 | |
| 8930 | #undef GEN_CRLOGIC |
| 8931 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
| 8932 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
| 8933 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), |
| 8934 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), |
| 8935 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), |
| 8936 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), |
| 8937 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), |
| 8938 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), |
| 8939 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), |
| 8940 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), |
| 8941 | |
| 8942 | #undef GEN_MAC_HANDLER |
| 8943 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
| 8944 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
| 8945 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
| 8946 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
| 8947 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
| 8948 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
| 8949 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
| 8950 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
| 8951 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
| 8952 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
| 8953 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
| 8954 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
| 8955 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
| 8956 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
| 8957 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
| 8958 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
| 8959 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
| 8960 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
| 8961 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
| 8962 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
| 8963 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
| 8964 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
| 8965 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
| 8966 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
| 8967 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
| 8968 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
| 8969 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
| 8970 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
| 8971 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
| 8972 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
| 8973 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
| 8974 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
| 8975 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
| 8976 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
| 8977 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
| 8978 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
| 8979 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
| 8980 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
| 8981 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
| 8982 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
| 8983 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
| 8984 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
| 8985 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
| 8986 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
| 8987 | |
| 8988 | #undef GEN_VR_LDX |
| 8989 | #undef GEN_VR_STX |
| 8990 | #undef GEN_VR_LVE |
| 8991 | #undef GEN_VR_STVE |
| 8992 | #define GEN_VR_LDX(name, opc2, opc3) \ |
| 8993 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
| 8994 | #define GEN_VR_STX(name, opc2, opc3) \ |
| 8995 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
| 8996 | #define GEN_VR_LVE(name, opc2, opc3) \ |
| 8997 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
| 8998 | #define GEN_VR_STVE(name, opc2, opc3) \ |
| 8999 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
| 9000 | GEN_VR_LDX(lvx, 0x07, 0x03), |
| 9001 | GEN_VR_LDX(lvxl, 0x07, 0x0B), |
| 9002 | GEN_VR_LVE(bx, 0x07, 0x00), |
| 9003 | GEN_VR_LVE(hx, 0x07, 0x01), |
| 9004 | GEN_VR_LVE(wx, 0x07, 0x02), |
| 9005 | GEN_VR_STX(svx, 0x07, 0x07), |
| 9006 | GEN_VR_STX(svxl, 0x07, 0x0F), |
| 9007 | GEN_VR_STVE(bx, 0x07, 0x04), |
| 9008 | GEN_VR_STVE(hx, 0x07, 0x05), |
| 9009 | GEN_VR_STVE(wx, 0x07, 0x06), |
| 9010 | |
| 9011 | #undef GEN_VX_LOGICAL |
| 9012 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ |
| 9013 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
| 9014 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
| 9015 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), |
| 9016 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), |
| 9017 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), |
| 9018 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), |
| 9019 | |
| 9020 | #undef GEN_VXFORM |
| 9021 | #define GEN_VXFORM(name, opc2, opc3) \ |
| 9022 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
| 9023 | GEN_VXFORM(vaddubm, 0, 0), |
| 9024 | GEN_VXFORM(vadduhm, 0, 1), |
| 9025 | GEN_VXFORM(vadduwm, 0, 2), |
| 9026 | GEN_VXFORM(vsububm, 0, 16), |
| 9027 | GEN_VXFORM(vsubuhm, 0, 17), |
| 9028 | GEN_VXFORM(vsubuwm, 0, 18), |
| 9029 | GEN_VXFORM(vmaxub, 1, 0), |
| 9030 | GEN_VXFORM(vmaxuh, 1, 1), |
| 9031 | GEN_VXFORM(vmaxuw, 1, 2), |
| 9032 | GEN_VXFORM(vmaxsb, 1, 4), |
| 9033 | GEN_VXFORM(vmaxsh, 1, 5), |
| 9034 | GEN_VXFORM(vmaxsw, 1, 6), |
| 9035 | GEN_VXFORM(vminub, 1, 8), |
| 9036 | GEN_VXFORM(vminuh, 1, 9), |
| 9037 | GEN_VXFORM(vminuw, 1, 10), |
| 9038 | GEN_VXFORM(vminsb, 1, 12), |
| 9039 | GEN_VXFORM(vminsh, 1, 13), |
| 9040 | GEN_VXFORM(vminsw, 1, 14), |
| 9041 | GEN_VXFORM(vavgub, 1, 16), |
| 9042 | GEN_VXFORM(vavguh, 1, 17), |
| 9043 | GEN_VXFORM(vavguw, 1, 18), |
| 9044 | GEN_VXFORM(vavgsb, 1, 20), |
| 9045 | GEN_VXFORM(vavgsh, 1, 21), |
| 9046 | GEN_VXFORM(vavgsw, 1, 22), |
| 9047 | GEN_VXFORM(vmrghb, 6, 0), |
| 9048 | GEN_VXFORM(vmrghh, 6, 1), |
| 9049 | GEN_VXFORM(vmrghw, 6, 2), |
| 9050 | GEN_VXFORM(vmrglb, 6, 4), |
| 9051 | GEN_VXFORM(vmrglh, 6, 5), |
| 9052 | GEN_VXFORM(vmrglw, 6, 6), |
| 9053 | GEN_VXFORM(vmuloub, 4, 0), |
| 9054 | GEN_VXFORM(vmulouh, 4, 1), |
| 9055 | GEN_VXFORM(vmulosb, 4, 4), |
| 9056 | GEN_VXFORM(vmulosh, 4, 5), |
| 9057 | GEN_VXFORM(vmuleub, 4, 8), |
| 9058 | GEN_VXFORM(vmuleuh, 4, 9), |
| 9059 | GEN_VXFORM(vmulesb, 4, 12), |
| 9060 | GEN_VXFORM(vmulesh, 4, 13), |
| 9061 | GEN_VXFORM(vslb, 2, 4), |
| 9062 | GEN_VXFORM(vslh, 2, 5), |
| 9063 | GEN_VXFORM(vslw, 2, 6), |
| 9064 | GEN_VXFORM(vsrb, 2, 8), |
| 9065 | GEN_VXFORM(vsrh, 2, 9), |
| 9066 | GEN_VXFORM(vsrw, 2, 10), |
| 9067 | GEN_VXFORM(vsrab, 2, 12), |
| 9068 | GEN_VXFORM(vsrah, 2, 13), |
| 9069 | GEN_VXFORM(vsraw, 2, 14), |
| 9070 | GEN_VXFORM(vslo, 6, 16), |
| 9071 | GEN_VXFORM(vsro, 6, 17), |
| 9072 | GEN_VXFORM(vaddcuw, 0, 6), |
| 9073 | GEN_VXFORM(vsubcuw, 0, 22), |
| 9074 | GEN_VXFORM(vaddubs, 0, 8), |
| 9075 | GEN_VXFORM(vadduhs, 0, 9), |
| 9076 | GEN_VXFORM(vadduws, 0, 10), |
| 9077 | GEN_VXFORM(vaddsbs, 0, 12), |
| 9078 | GEN_VXFORM(vaddshs, 0, 13), |
| 9079 | GEN_VXFORM(vaddsws, 0, 14), |
| 9080 | GEN_VXFORM(vsububs, 0, 24), |
| 9081 | GEN_VXFORM(vsubuhs, 0, 25), |
| 9082 | GEN_VXFORM(vsubuws, 0, 26), |
| 9083 | GEN_VXFORM(vsubsbs, 0, 28), |
| 9084 | GEN_VXFORM(vsubshs, 0, 29), |
| 9085 | GEN_VXFORM(vsubsws, 0, 30), |
| 9086 | GEN_VXFORM(vrlb, 2, 0), |
| 9087 | GEN_VXFORM(vrlh, 2, 1), |
| 9088 | GEN_VXFORM(vrlw, 2, 2), |
| 9089 | GEN_VXFORM(vsl, 2, 7), |
| 9090 | GEN_VXFORM(vsr, 2, 11), |
| 9091 | GEN_VXFORM(vpkuhum, 7, 0), |
| 9092 | GEN_VXFORM(vpkuwum, 7, 1), |
| 9093 | GEN_VXFORM(vpkuhus, 7, 2), |
| 9094 | GEN_VXFORM(vpkuwus, 7, 3), |
| 9095 | GEN_VXFORM(vpkshus, 7, 4), |
| 9096 | GEN_VXFORM(vpkswus, 7, 5), |
| 9097 | GEN_VXFORM(vpkshss, 7, 6), |
| 9098 | GEN_VXFORM(vpkswss, 7, 7), |
| 9099 | GEN_VXFORM(vpkpx, 7, 12), |
| 9100 | GEN_VXFORM(vsum4ubs, 4, 24), |
| 9101 | GEN_VXFORM(vsum4sbs, 4, 28), |
| 9102 | GEN_VXFORM(vsum4shs, 4, 25), |
| 9103 | GEN_VXFORM(vsum2sws, 4, 26), |
| 9104 | GEN_VXFORM(vsumsws, 4, 30), |
| 9105 | GEN_VXFORM(vaddfp, 5, 0), |
| 9106 | GEN_VXFORM(vsubfp, 5, 1), |
| 9107 | GEN_VXFORM(vmaxfp, 5, 16), |
| 9108 | GEN_VXFORM(vminfp, 5, 17), |
| 9109 | |
| 9110 | #undef GEN_VXRFORM1 |
| 9111 | #undef GEN_VXRFORM |
| 9112 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
| 9113 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), |
| 9114 | #define GEN_VXRFORM(name, opc2, opc3) \ |
| 9115 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ |
| 9116 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
| 9117 | GEN_VXRFORM(vcmpequb, 3, 0) |
| 9118 | GEN_VXRFORM(vcmpequh, 3, 1) |
| 9119 | GEN_VXRFORM(vcmpequw, 3, 2) |
| 9120 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
| 9121 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
| 9122 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
| 9123 | GEN_VXRFORM(vcmpgtub, 3, 8) |
| 9124 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
| 9125 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
| 9126 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
| 9127 | GEN_VXRFORM(vcmpgefp, 3, 7) |
| 9128 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
| 9129 | GEN_VXRFORM(vcmpbfp, 3, 15) |
| 9130 | |
| 9131 | #undef GEN_VXFORM_SIMM |
| 9132 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
| 9133 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
| 9134 | GEN_VXFORM_SIMM(vspltisb, 6, 12), |
| 9135 | GEN_VXFORM_SIMM(vspltish, 6, 13), |
| 9136 | GEN_VXFORM_SIMM(vspltisw, 6, 14), |
| 9137 | |
| 9138 | #undef GEN_VXFORM_NOA |
| 9139 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
| 9140 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) |
| 9141 | GEN_VXFORM_NOA(vupkhsb, 7, 8), |
| 9142 | GEN_VXFORM_NOA(vupkhsh, 7, 9), |
| 9143 | GEN_VXFORM_NOA(vupklsb, 7, 10), |
| 9144 | GEN_VXFORM_NOA(vupklsh, 7, 11), |
| 9145 | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
| 9146 | GEN_VXFORM_NOA(vupklpx, 7, 15), |
| 9147 | GEN_VXFORM_NOA(vrefp, 5, 4), |
| 9148 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), |
Aurelien Jarno | 0bffbc6 | 2009-02-09 12:20:50 +0100 | [diff] [blame] | 9149 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 9150 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
| 9151 | GEN_VXFORM_NOA(vrfim, 5, 8), |
| 9152 | GEN_VXFORM_NOA(vrfin, 5, 9), |
| 9153 | GEN_VXFORM_NOA(vrfip, 5, 10), |
| 9154 | GEN_VXFORM_NOA(vrfiz, 5, 11), |
| 9155 | |
| 9156 | #undef GEN_VXFORM_UIMM |
| 9157 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
| 9158 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
| 9159 | GEN_VXFORM_UIMM(vspltb, 6, 8), |
| 9160 | GEN_VXFORM_UIMM(vsplth, 6, 9), |
| 9161 | GEN_VXFORM_UIMM(vspltw, 6, 10), |
| 9162 | GEN_VXFORM_UIMM(vcfux, 5, 12), |
| 9163 | GEN_VXFORM_UIMM(vcfsx, 5, 13), |
| 9164 | GEN_VXFORM_UIMM(vctuxs, 5, 14), |
| 9165 | GEN_VXFORM_UIMM(vctsxs, 5, 15), |
| 9166 | |
| 9167 | #undef GEN_VAFORM_PAIRED |
| 9168 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
| 9169 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) |
| 9170 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), |
| 9171 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), |
| 9172 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), |
| 9173 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), |
| 9174 | GEN_VAFORM_PAIRED(vsel, vperm, 21), |
| 9175 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), |
| 9176 | |
| 9177 | #undef GEN_SPE |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9178 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
| 9179 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) |
| 9180 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9181 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9182 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9183 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9184 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
| 9185 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
| 9186 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
| 9187 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), |
| 9188 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), |
| 9189 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), |
| 9190 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9191 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9192 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9193 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), |
| 9194 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), |
| 9195 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), |
| 9196 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), |
| 9197 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9198 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9199 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9200 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9201 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
| 9202 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), |
| 9203 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), |
| 9204 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9205 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
| 9206 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), |
| 9207 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), |
| 9208 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 9209 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9210 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
| 9211 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), |
| 9212 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9213 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
| 9214 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
| 9215 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9216 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9217 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9218 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9219 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9220 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9221 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9222 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
| 9223 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 9224 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9225 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
| 9226 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), |
| 9227 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9228 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
| 9229 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
| 9230 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), |
| 9231 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9232 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9233 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9234 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
| 9235 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9236 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
| 9237 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
| 9238 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 9239 | |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9240 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), |
| 9241 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9242 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), |
| 9243 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
| 9244 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), |
| 9245 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9246 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), |
| 9247 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), |
| 9248 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9249 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9250 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9251 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
| 9252 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
| 9253 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
| 9254 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), |
| 9255 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
Blue Swirl | 5c55ff9 | 2009-06-17 15:22:31 +0000 | [diff] [blame] | 9256 | |
| 9257 | #undef GEN_SPEOP_LDST |
| 9258 | #define GEN_SPEOP_LDST(name, opc2, sh) \ |
| 9259 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) |
| 9260 | GEN_SPEOP_LDST(evldd, 0x00, 3), |
| 9261 | GEN_SPEOP_LDST(evldw, 0x01, 3), |
| 9262 | GEN_SPEOP_LDST(evldh, 0x02, 3), |
| 9263 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), |
| 9264 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), |
| 9265 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), |
| 9266 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), |
| 9267 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), |
| 9268 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), |
| 9269 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), |
| 9270 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), |
| 9271 | |
| 9272 | GEN_SPEOP_LDST(evstdd, 0x10, 3), |
| 9273 | GEN_SPEOP_LDST(evstdw, 0x11, 3), |
| 9274 | GEN_SPEOP_LDST(evstdh, 0x12, 3), |
| 9275 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), |
| 9276 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), |
| 9277 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), |
| 9278 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), |
| 9279 | }; |
| 9280 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9281 | #include "translate_init.c" |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 9282 | #include "helper_regs.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9283 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9284 | /*****************************************************************************/ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9285 | /* Misc PowerPC helpers */ |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 9286 | void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 9287 | int flags) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9288 | { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9289 | #define RGPL 4 |
| 9290 | #define RFPL 4 |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9291 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9292 | int i; |
| 9293 | |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9294 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 9295 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
| 9296 | env->nip, env->lr, env->ctr, env->xer); |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9297 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
| 9298 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], |
| 9299 | env->hflags, env->mmu_idx); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 9300 | #if !defined(NO_TIMER_DUMP) |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 9301 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9302 | #if !defined(CONFIG_USER_ONLY) |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 9303 | " DECR %08" PRIu32 |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9304 | #endif |
| 9305 | "\n", |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 9306 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9307 | #if !defined(CONFIG_USER_ONLY) |
| 9308 | , cpu_ppc_load_decr(env) |
| 9309 | #endif |
| 9310 | ); |
j_mayer | 077fc20 | 2007-11-04 01:57:29 +0000 | [diff] [blame] | 9311 | #endif |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9312 | for (i = 0; i < 32; i++) { |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9313 | if ((i & (RGPL - 1)) == 0) |
| 9314 | cpu_fprintf(f, "GPR%02d", i); |
Blue Swirl | b11ebf6 | 2009-08-16 11:54:37 +0000 | [diff] [blame] | 9315 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9316 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 9317 | cpu_fprintf(f, "\n"); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9318 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9319 | cpu_fprintf(f, "CR "); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9320 | for (i = 0; i < 8; i++) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 9321 | cpu_fprintf(f, "%01x", env->crf[i]); |
| 9322 | cpu_fprintf(f, " ["); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9323 | for (i = 0; i < 8; i++) { |
| 9324 | char a = '-'; |
| 9325 | if (env->crf[i] & 0x08) |
| 9326 | a = 'L'; |
| 9327 | else if (env->crf[i] & 0x04) |
| 9328 | a = 'G'; |
| 9329 | else if (env->crf[i] & 0x02) |
| 9330 | a = 'E'; |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 9331 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9332 | } |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9333 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
| 9334 | env->reserve_addr); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9335 | for (i = 0; i < 32; i++) { |
| 9336 | if ((i & (RFPL - 1)) == 0) |
| 9337 | cpu_fprintf(f, "FPR%02d", i); |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 9338 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9339 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 9340 | cpu_fprintf(f, "\n"); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9341 | } |
aurel32 | 7889270 | 2008-12-14 18:40:49 +0000 | [diff] [blame] | 9342 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr); |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 9343 | #if !defined(CONFIG_USER_ONLY) |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 9344 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
| 9345 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", |
| 9346 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
| 9347 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); |
| 9348 | |
| 9349 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
| 9350 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", |
| 9351 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], |
| 9352 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); |
| 9353 | |
| 9354 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
| 9355 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", |
| 9356 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], |
| 9357 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); |
| 9358 | |
| 9359 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
| 9360 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
| 9361 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", |
| 9362 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], |
| 9363 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
| 9364 | |
| 9365 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx |
| 9366 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", |
| 9367 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], |
| 9368 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); |
| 9369 | |
| 9370 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx |
| 9371 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", |
| 9372 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], |
| 9373 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); |
| 9374 | |
| 9375 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx |
| 9376 | " EPR " TARGET_FMT_lx "\n", |
| 9377 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], |
| 9378 | env->spr[SPR_BOOKE_EPR]); |
| 9379 | |
| 9380 | /* FSL-specific */ |
| 9381 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
| 9382 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", |
| 9383 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], |
| 9384 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); |
| 9385 | |
| 9386 | /* |
| 9387 | * IVORs are left out as they are large and do not change often -- |
| 9388 | * they can be read with "p $ivor0", "p $ivor1", etc. |
| 9389 | */ |
| 9390 | } |
| 9391 | |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 9392 | #if defined(TARGET_PPC64) |
| 9393 | if (env->flags & POWERPC_FLAG_CFAR) { |
| 9394 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); |
| 9395 | } |
| 9396 | #endif |
| 9397 | |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 9398 | switch (env->mmu_model) { |
| 9399 | case POWERPC_MMU_32B: |
| 9400 | case POWERPC_MMU_601: |
| 9401 | case POWERPC_MMU_SOFT_6xx: |
| 9402 | case POWERPC_MMU_SOFT_74xx: |
| 9403 | #if defined(TARGET_PPC64) |
| 9404 | case POWERPC_MMU_620: |
| 9405 | case POWERPC_MMU_64B: |
| 9406 | #endif |
| 9407 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]); |
| 9408 | break; |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 9409 | case POWERPC_MMU_BOOKE206: |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 9410 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
| 9411 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", |
| 9412 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], |
| 9413 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); |
| 9414 | |
| 9415 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx |
| 9416 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", |
| 9417 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], |
| 9418 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); |
| 9419 | |
| 9420 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx |
| 9421 | " TLB1CFG " TARGET_FMT_lx "\n", |
| 9422 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], |
| 9423 | env->spr[SPR_BOOKE_TLB1CFG]); |
| 9424 | break; |
| 9425 | default: |
| 9426 | break; |
| 9427 | } |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 9428 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9429 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9430 | #undef RGPL |
| 9431 | #undef RFPL |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9432 | } |
| 9433 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 9434 | void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf, |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9435 | int flags) |
| 9436 | { |
| 9437 | #if defined(DO_PPC_STATISTICS) |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 9438 | opc_handler_t **t1, **t2, **t3, *handler; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9439 | int op1, op2, op3; |
| 9440 | |
| 9441 | t1 = env->opcodes; |
| 9442 | for (op1 = 0; op1 < 64; op1++) { |
| 9443 | handler = t1[op1]; |
| 9444 | if (is_indirect_opcode(handler)) { |
| 9445 | t2 = ind_table(handler); |
| 9446 | for (op2 = 0; op2 < 32; op2++) { |
| 9447 | handler = t2[op2]; |
| 9448 | if (is_indirect_opcode(handler)) { |
| 9449 | t3 = ind_table(handler); |
| 9450 | for (op3 = 0; op3 < 32; op3++) { |
| 9451 | handler = t3[op3]; |
| 9452 | if (handler->count == 0) |
| 9453 | continue; |
| 9454 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " |
Blue Swirl | 0bfcd59 | 2010-05-22 08:02:12 +0000 | [diff] [blame] | 9455 | "%016" PRIx64 " %" PRId64 "\n", |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9456 | op1, op2, op3, op1, (op3 << 5) | op2, |
| 9457 | handler->oname, |
| 9458 | handler->count, handler->count); |
| 9459 | } |
| 9460 | } else { |
| 9461 | if (handler->count == 0) |
| 9462 | continue; |
| 9463 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " |
Blue Swirl | 0bfcd59 | 2010-05-22 08:02:12 +0000 | [diff] [blame] | 9464 | "%016" PRIx64 " %" PRId64 "\n", |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9465 | op1, op2, op1, op2, handler->oname, |
| 9466 | handler->count, handler->count); |
| 9467 | } |
| 9468 | } |
| 9469 | } else { |
| 9470 | if (handler->count == 0) |
| 9471 | continue; |
Blue Swirl | 0bfcd59 | 2010-05-22 08:02:12 +0000 | [diff] [blame] | 9472 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
| 9473 | " %" PRId64 "\n", |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9474 | op1, op1, handler->oname, |
| 9475 | handler->count, handler->count); |
| 9476 | } |
| 9477 | } |
| 9478 | #endif |
| 9479 | } |
| 9480 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9481 | /*****************************************************************************/ |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 9482 | static inline void gen_intermediate_code_internal(CPUState *env, |
| 9483 | TranslationBlock *tb, |
| 9484 | int search_pc) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9485 | { |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 9486 | DisasContext ctx, *ctxp = &ctx; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 9487 | opc_handler_t **table, *handler; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 9488 | target_ulong pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9489 | uint16_t *gen_opc_end; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 9490 | CPUBreakpoint *bp; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9491 | int j, lj = -1; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9492 | int num_insns; |
| 9493 | int max_insns; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9494 | |
| 9495 | pc_start = tb->pc; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9496 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 9497 | ctx.nip = pc_start; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9498 | ctx.tb = tb; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 9499 | ctx.exception = POWERPC_EXCP_NONE; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9500 | ctx.spr_cb = env->spr_cb; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 9501 | ctx.mem_idx = env->mmu_idx; |
| 9502 | ctx.access_type = -1; |
| 9503 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 9504 | #if defined(TARGET_PPC64) |
| 9505 | ctx.sf_mode = msr_sf; |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 9506 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9507 | #endif |
bellard | 3cc6237 | 2005-02-15 23:06:19 +0000 | [diff] [blame] | 9508 | ctx.fpu_enabled = msr_fp; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 9509 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9510 | ctx.spe_enabled = msr_spe; |
| 9511 | else |
| 9512 | ctx.spe_enabled = 0; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 9513 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
| 9514 | ctx.altivec_enabled = msr_vr; |
| 9515 | else |
| 9516 | ctx.altivec_enabled = 0; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9517 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9518 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9519 | else |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9520 | ctx.singlestep_enabled = 0; |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9521 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9522 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
| 9523 | if (unlikely(env->singlestep_enabled)) |
| 9524 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9525 | #if defined (DO_SINGLE_STEP) && 0 |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9526 | /* Single step trace mode */ |
| 9527 | msr_se = 1; |
| 9528 | #endif |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9529 | num_insns = 0; |
| 9530 | max_insns = tb->cflags & CF_COUNT_MASK; |
| 9531 | if (max_insns == 0) |
| 9532 | max_insns = CF_COUNT_MASK; |
| 9533 | |
| 9534 | gen_icount_start(); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9535 | /* Set env in case of segfault during code fetch */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 9536 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
Blue Swirl | 72cf2d4 | 2009-09-12 07:36:22 +0000 | [diff] [blame] | 9537 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { |
| 9538 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 9539 | if (bp->pc == ctx.nip) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 9540 | gen_debug_exception(ctxp); |
bellard | ea4e754 | 2006-05-22 21:50:20 +0000 | [diff] [blame] | 9541 | break; |
| 9542 | } |
| 9543 | } |
| 9544 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9545 | if (unlikely(search_pc)) { |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9546 | j = gen_opc_ptr - gen_opc_buf; |
| 9547 | if (lj < j) { |
| 9548 | lj++; |
| 9549 | while (lj < j) |
| 9550 | gen_opc_instr_start[lj++] = 0; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9551 | } |
aurel32 | af4b6c5 | 2009-03-29 01:18:03 +0000 | [diff] [blame] | 9552 | gen_opc_pc[lj] = ctx.nip; |
| 9553 | gen_opc_instr_start[lj] = 1; |
| 9554 | gen_opc_icount[lj] = num_insns; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9555 | } |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 9556 | LOG_DISAS("----------------\n"); |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9557 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 9558 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9559 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
| 9560 | gen_io_start(); |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 9561 | if (unlikely(ctx.le_mode)) { |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 9562 | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
| 9563 | } else { |
| 9564 | ctx.opcode = ldl_code(ctx.nip); |
bellard | 111bfab | 2005-04-23 18:16:07 +0000 | [diff] [blame] | 9565 | } |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 9566 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9567 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 9568 | opc3(ctx.opcode), little_endian ? "little" : "big"); |
Aurelien Jarno | 731c54f | 2009-09-28 13:39:08 +0200 | [diff] [blame] | 9569 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) |
| 9570 | tcg_gen_debug_insn_start(ctx.nip); |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 9571 | ctx.nip += 4; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9572 | table = env->opcodes; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9573 | num_insns++; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9574 | handler = table[opc1(ctx.opcode)]; |
| 9575 | if (is_indirect_opcode(handler)) { |
| 9576 | table = ind_table(handler); |
| 9577 | handler = table[opc2(ctx.opcode)]; |
| 9578 | if (is_indirect_opcode(handler)) { |
| 9579 | table = ind_table(handler); |
| 9580 | handler = table[opc3(ctx.opcode)]; |
| 9581 | } |
| 9582 | } |
| 9583 | /* Is opcode *REALLY* valid ? */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9584 | if (unlikely(handler->handler == &gen_invalid)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 9585 | if (qemu_log_enabled()) { |
| 9586 | qemu_log("invalid/unsupported opcode: " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9587 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
| 9588 | opc1(ctx.opcode), opc2(ctx.opcode), |
| 9589 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 9590 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9591 | } else { |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9592 | uint32_t inval; |
| 9593 | |
| 9594 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { |
| 9595 | inval = handler->inval2; |
| 9596 | } else { |
| 9597 | inval = handler->inval1; |
| 9598 | } |
| 9599 | |
| 9600 | if (unlikely((ctx.opcode & inval) != 0)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 9601 | if (qemu_log_enabled()) { |
| 9602 | qemu_log("invalid bits: %08x for opcode: " |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9603 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
Fabien Chouteau | 70560da | 2011-09-28 05:54:05 +0000 | [diff] [blame] | 9604 | ctx.opcode & inval, opc1(ctx.opcode), |
Blue Swirl | 90e189e | 2009-08-16 11:13:18 +0000 | [diff] [blame] | 9605 | opc2(ctx.opcode), opc3(ctx.opcode), |
| 9606 | ctx.opcode, ctx.nip - 4); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9607 | } |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 9608 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 9609 | break; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9610 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9611 | } |
bellard | 4b3686f | 2004-05-23 22:18:12 +0000 | [diff] [blame] | 9612 | (*(handler->handler))(&ctx); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9613 | #if defined(DO_PPC_STATISTICS) |
| 9614 | handler->count++; |
| 9615 | #endif |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9616 | /* Check trace mode exceptions */ |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9617 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
| 9618 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
| 9619 | ctx.exception != POWERPC_SYSCALL && |
| 9620 | ctx.exception != POWERPC_EXCP_TRAP && |
| 9621 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 9622 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9623 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9624 | (env->singlestep_enabled) || |
aurel32 | 1b530a6 | 2009-04-05 20:08:59 +0000 | [diff] [blame] | 9625 | singlestep || |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9626 | num_insns >= max_insns)) { |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 9627 | /* if we reach a page boundary or are single stepping, stop |
| 9628 | * generation |
| 9629 | */ |
bellard | 8dd4983 | 2005-06-04 22:22:27 +0000 | [diff] [blame] | 9630 | break; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9631 | } |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 9632 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9633 | if (tb->cflags & CF_LAST_IO) |
| 9634 | gen_io_end(); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 9635 | if (ctx.exception == POWERPC_EXCP_NONE) { |
bellard | c194236 | 2005-11-20 10:31:08 +0000 | [diff] [blame] | 9636 | gen_goto_tb(&ctx, 0, ctx.nip); |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 9637 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9638 | if (unlikely(env->singlestep_enabled)) { |
aurel32 | e06fcd7 | 2008-12-11 22:42:14 +0000 | [diff] [blame] | 9639 | gen_debug_exception(ctxp); |
aurel32 | 8cbcb4f | 2008-05-10 23:28:14 +0000 | [diff] [blame] | 9640 | } |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9641 | /* Generate the return instruction */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 9642 | tcg_gen_exit_tb(0); |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9643 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9644 | gen_icount_end(tb, num_insns); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9645 | *gen_opc_ptr = INDEX_op_end; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9646 | if (unlikely(search_pc)) { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9647 | j = gen_opc_ptr - gen_opc_buf; |
| 9648 | lj++; |
| 9649 | while (lj <= j) |
| 9650 | gen_opc_instr_start[lj++] = 0; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9651 | } else { |
bellard | 046d667 | 2004-04-25 21:15:35 +0000 | [diff] [blame] | 9652 | tb->size = ctx.nip - pc_start; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 9653 | tb->icount = num_insns; |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 9654 | } |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 9655 | #if defined(DEBUG_DISAS) |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 9656 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 9657 | int flags; |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 9658 | flags = env->bfd_mach; |
aurel32 | 76db3ba | 2008-12-08 18:11:21 +0000 | [diff] [blame] | 9659 | flags |= ctx.le_mode << 16; |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 9660 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
| 9661 | log_target_disas(pc_start, ctx.nip - pc_start, flags); |
| 9662 | qemu_log("\n"); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 9663 | } |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9664 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9665 | } |
| 9666 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 9667 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9668 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 9669 | gen_intermediate_code_internal(env, tb, 0); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9670 | } |
| 9671 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 9672 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9673 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 9674 | gen_intermediate_code_internal(env, tb, 1); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 9675 | } |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 9676 | |
Stefan Weil | e87b7cb | 2011-04-18 06:39:52 +0000 | [diff] [blame] | 9677 | void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 9678 | { |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 9679 | env->nip = gen_opc_pc[pc_pos]; |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 9680 | } |