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bellard79aceca2003-11-23 14:55:54 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation for qemu: main translation routines.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
Scott Wood90dc8812011-04-29 17:10:23 -05005 * Copyright (C) 2011 Freescale Semiconductor, Inc.
bellard79aceca2003-11-23 14:55:54 +00006 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard79aceca2003-11-23 14:55:54 +000019 */
bellardc6a1c222004-05-20 13:10:49 +000020#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
bellard79aceca2003-11-23 14:55:54 +000026#include "cpu.h"
bellard79aceca2003-11-23 14:55:54 +000027#include "disas.h"
bellard57fec1f2008-02-01 10:50:11 +000028#include "tcg-op.h"
aurel32ca10f862008-04-11 21:35:42 +000029#include "qemu-common.h"
aurel320cfe11e2009-03-03 06:12:14 +000030#include "host-utils.h"
bellard79aceca2003-11-23 14:55:54 +000031
pbrooka7812ae2008-11-17 14:43:54 +000032#include "helper.h"
33#define GEN_HELPER 1
34#include "helper.h"
35
aurel328cbcb4f2008-05-10 23:28:14 +000036#define CPU_SINGLE_STEP 0x1
37#define CPU_BRANCH_STEP 0x2
38#define GDBSTUB_SINGLE_STEP 0x4
39
j_mayera750fc02007-09-26 23:54:22 +000040/* Include definitions for instructions classes and implementations flags */
bellard9fddaa02004-05-21 12:59:32 +000041//#define PPC_DEBUG_DISAS
j_mayer76a66252007-03-07 08:32:30 +000042//#define DO_PPC_STATISTICS
bellard79aceca2003-11-23 14:55:54 +000043
aliguorid12d51d2009-01-15 21:48:06 +000044#ifdef PPC_DEBUG_DISAS
aliguori93fcfe32009-01-15 22:34:14 +000045# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
aliguorid12d51d2009-01-15 21:48:06 +000046#else
47# define LOG_DISAS(...) do { } while (0)
48#endif
j_mayera750fc02007-09-26 23:54:22 +000049/*****************************************************************************/
50/* Code translation helpers */
bellardc53be332005-10-30 21:39:19 +000051
aurel32f78fb442008-09-04 05:25:47 +000052/* global register indexes */
pbrooka7812ae2008-11-17 14:43:54 +000053static TCGv_ptr cpu_env;
aurel321d542692008-09-04 14:43:45 +000054static char cpu_reg_names[10*3 + 22*4 /* GPR */
aurel32f78fb442008-09-04 05:25:47 +000055#if !defined(TARGET_PPC64)
aurel321d542692008-09-04 14:43:45 +000056 + 10*4 + 22*5 /* SPE GPRh */
aurel32f78fb442008-09-04 05:25:47 +000057#endif
aurel32a5e26af2008-09-04 14:43:54 +000058 + 10*4 + 22*5 /* FPR */
aurel3247e46612008-09-04 17:06:47 +000059 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 8*5 /* CRF */];
aurel32f78fb442008-09-04 05:25:47 +000061static TCGv cpu_gpr[32];
62#if !defined(TARGET_PPC64)
63static TCGv cpu_gprh[32];
64#endif
pbrooka7812ae2008-11-17 14:43:54 +000065static TCGv_i64 cpu_fpr[32];
66static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
67static TCGv_i32 cpu_crf[8];
aurel32bd568f12008-09-04 18:06:03 +000068static TCGv cpu_nip;
aurel326527f6e2008-12-06 13:03:35 +000069static TCGv cpu_msr;
aurel32cfdcd372008-09-14 18:30:23 +000070static TCGv cpu_ctr;
71static TCGv cpu_lr;
David Gibson697ab892011-08-31 15:45:10 +000072#if defined(TARGET_PPC64)
73static TCGv cpu_cfar;
74#endif
aurel323d7b4172008-10-21 11:28:46 +000075static TCGv cpu_xer;
aurel32cf360a32008-11-30 16:24:39 +000076static TCGv cpu_reserve;
pbrooka7812ae2008-11-17 14:43:54 +000077static TCGv_i32 cpu_fpscr;
aurel32a7859e82008-11-23 16:30:40 +000078static TCGv_i32 cpu_access_type;
aurel32f78fb442008-09-04 05:25:47 +000079
pbrook2e70f6e2008-06-29 01:03:05 +000080#include "gen-icount.h"
81
82void ppc_translate_init(void)
83{
aurel32f78fb442008-09-04 05:25:47 +000084 int i;
85 char* p;
blueswir12dc766d2009-04-13 16:06:19 +000086 size_t cpu_reg_names_size;
pbrookb2437bf2008-06-29 12:29:56 +000087 static int done_init = 0;
aurel32f78fb442008-09-04 05:25:47 +000088
pbrook2e70f6e2008-06-29 01:03:05 +000089 if (done_init)
90 return;
aurel32f78fb442008-09-04 05:25:47 +000091
pbrooka7812ae2008-11-17 14:43:54 +000092 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
aurel32a5e26af2008-09-04 14:43:54 +000093
aurel32f78fb442008-09-04 05:25:47 +000094 p = cpu_reg_names;
blueswir12dc766d2009-04-13 16:06:19 +000095 cpu_reg_names_size = sizeof(cpu_reg_names);
aurel3247e46612008-09-04 17:06:47 +000096
97 for (i = 0; i < 8; i++) {
blueswir12dc766d2009-04-13 16:06:19 +000098 snprintf(p, cpu_reg_names_size, "crf%d", i);
pbrooka7812ae2008-11-17 14:43:54 +000099 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
100 offsetof(CPUState, crf[i]), p);
aurel3247e46612008-09-04 17:06:47 +0000101 p += 5;
blueswir12dc766d2009-04-13 16:06:19 +0000102 cpu_reg_names_size -= 5;
aurel3247e46612008-09-04 17:06:47 +0000103 }
104
aurel32f78fb442008-09-04 05:25:47 +0000105 for (i = 0; i < 32; i++) {
blueswir12dc766d2009-04-13 16:06:19 +0000106 snprintf(p, cpu_reg_names_size, "r%d", i);
pbrooka7812ae2008-11-17 14:43:54 +0000107 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
aurel32f78fb442008-09-04 05:25:47 +0000108 offsetof(CPUState, gpr[i]), p);
109 p += (i < 10) ? 3 : 4;
blueswir12dc766d2009-04-13 16:06:19 +0000110 cpu_reg_names_size -= (i < 10) ? 3 : 4;
aurel32f78fb442008-09-04 05:25:47 +0000111#if !defined(TARGET_PPC64)
blueswir12dc766d2009-04-13 16:06:19 +0000112 snprintf(p, cpu_reg_names_size, "r%dH", i);
pbrooka7812ae2008-11-17 14:43:54 +0000113 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUState, gprh[i]), p);
aurel32f78fb442008-09-04 05:25:47 +0000115 p += (i < 10) ? 4 : 5;
blueswir12dc766d2009-04-13 16:06:19 +0000116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
aurel32f78fb442008-09-04 05:25:47 +0000117#endif
aurel321d542692008-09-04 14:43:45 +0000118
blueswir12dc766d2009-04-13 16:06:19 +0000119 snprintf(p, cpu_reg_names_size, "fp%d", i);
pbrooka7812ae2008-11-17 14:43:54 +0000120 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, fpr[i]), p);
aurel32ec1ac722008-09-04 15:49:12 +0000122 p += (i < 10) ? 4 : 5;
blueswir12dc766d2009-04-13 16:06:19 +0000123 cpu_reg_names_size -= (i < 10) ? 4 : 5;
aurel32a5e26af2008-09-04 14:43:54 +0000124
blueswir12dc766d2009-04-13 16:06:19 +0000125 snprintf(p, cpu_reg_names_size, "avr%dH", i);
Juan Quintelae2542fe2009-07-27 16:13:06 +0200126#ifdef HOST_WORDS_BIGENDIAN
pbrooka7812ae2008-11-17 14:43:54 +0000127 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
aurel32fe1e5c52008-11-24 08:47:21 +0000128 offsetof(CPUState, avr[i].u64[0]), p);
129#else
130 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132#endif
aurel321d542692008-09-04 14:43:45 +0000133 p += (i < 10) ? 6 : 7;
blueswir12dc766d2009-04-13 16:06:19 +0000134 cpu_reg_names_size -= (i < 10) ? 6 : 7;
aurel32ec1ac722008-09-04 15:49:12 +0000135
blueswir12dc766d2009-04-13 16:06:19 +0000136 snprintf(p, cpu_reg_names_size, "avr%dL", i);
Juan Quintelae2542fe2009-07-27 16:13:06 +0200137#ifdef HOST_WORDS_BIGENDIAN
pbrooka7812ae2008-11-17 14:43:54 +0000138 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
aurel32fe1e5c52008-11-24 08:47:21 +0000139 offsetof(CPUState, avr[i].u64[1]), p);
140#else
141 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
142 offsetof(CPUState, avr[i].u64[0]), p);
143#endif
aurel321d542692008-09-04 14:43:45 +0000144 p += (i < 10) ? 6 : 7;
blueswir12dc766d2009-04-13 16:06:19 +0000145 cpu_reg_names_size -= (i < 10) ? 6 : 7;
aurel32f78fb442008-09-04 05:25:47 +0000146 }
aurel32f10dc082008-08-28 21:01:45 +0000147
pbrooka7812ae2008-11-17 14:43:54 +0000148 cpu_nip = tcg_global_mem_new(TCG_AREG0,
aurel32bd568f12008-09-04 18:06:03 +0000149 offsetof(CPUState, nip), "nip");
150
aurel326527f6e2008-12-06 13:03:35 +0000151 cpu_msr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, msr), "msr");
153
pbrooka7812ae2008-11-17 14:43:54 +0000154 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
aurel32cfdcd372008-09-14 18:30:23 +0000155 offsetof(CPUState, ctr), "ctr");
156
pbrooka7812ae2008-11-17 14:43:54 +0000157 cpu_lr = tcg_global_mem_new(TCG_AREG0,
aurel32cfdcd372008-09-14 18:30:23 +0000158 offsetof(CPUState, lr), "lr");
159
David Gibson697ab892011-08-31 15:45:10 +0000160#if defined(TARGET_PPC64)
161 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUState, cfar), "cfar");
163#endif
164
pbrooka7812ae2008-11-17 14:43:54 +0000165 cpu_xer = tcg_global_mem_new(TCG_AREG0,
aurel323d7b4172008-10-21 11:28:46 +0000166 offsetof(CPUState, xer), "xer");
167
aurel32cf360a32008-11-30 16:24:39 +0000168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
Nathan Froyd18b21a22009-08-03 08:43:25 -0700169 offsetof(CPUState, reserve_addr),
170 "reserve_addr");
aurel32cf360a32008-11-30 16:24:39 +0000171
pbrooka7812ae2008-11-17 14:43:54 +0000172 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
173 offsetof(CPUState, fpscr), "fpscr");
aurel32e1571902008-10-21 11:31:14 +0000174
aurel32a7859e82008-11-23 16:30:40 +0000175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUState, access_type), "access_type");
177
aurel32f10dc082008-08-28 21:01:45 +0000178 /* register helpers */
pbrooka7812ae2008-11-17 14:43:54 +0000179#define GEN_HELPER 2
aurel32f10dc082008-08-28 21:01:45 +0000180#include "helper.h"
181
pbrook2e70f6e2008-06-29 01:03:05 +0000182 done_init = 1;
183}
184
bellard79aceca2003-11-23 14:55:54 +0000185/* internal defines */
186typedef struct DisasContext {
187 struct TranslationBlock *tb;
bellard0fa85d42005-01-03 23:43:32 +0000188 target_ulong nip;
bellard79aceca2003-11-23 14:55:54 +0000189 uint32_t opcode;
bellard9a64fbe2004-01-04 22:58:38 +0000190 uint32_t exception;
bellard3cc62372005-02-15 23:06:19 +0000191 /* Routine used to access memory */
192 int mem_idx;
aurel3276db3ba2008-12-08 18:11:21 +0000193 int access_type;
bellard3cc62372005-02-15 23:06:19 +0000194 /* Translation flags */
aurel3276db3ba2008-12-08 18:11:21 +0000195 int le_mode;
j_mayerd9bce9d2007-03-17 14:02:15 +0000196#if defined(TARGET_PPC64)
197 int sf_mode;
David Gibson697ab892011-08-31 15:45:10 +0000198 int has_cfar;
j_mayerd9bce9d2007-03-17 14:02:15 +0000199#endif
bellard3cc62372005-02-15 23:06:19 +0000200 int fpu_enabled;
j_mayera9d9eb82007-10-07 18:19:26 +0000201 int altivec_enabled;
j_mayer0487d6a2007-03-20 22:11:31 +0000202 int spe_enabled;
Anthony Liguoric227f092009-10-01 16:12:16 -0500203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
bellardea4e7542006-05-22 21:50:20 +0000204 int singlestep_enabled;
bellard79aceca2003-11-23 14:55:54 +0000205} DisasContext;
206
Anthony Liguoric227f092009-10-01 16:12:16 -0500207struct opc_handler_t {
Fabien Chouteau70560da2011-09-28 05:54:05 +0000208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
bellard9a64fbe2004-01-04 22:58:38 +0000212 /* instruction type */
j_mayer0487d6a2007-03-20 22:11:31 +0000213 uint64_t type;
Alexander Grafa5858d72011-05-01 00:00:58 +0200214 /* extended instruction type */
215 uint64_t type2;
bellard79aceca2003-11-23 14:55:54 +0000216 /* handler */
217 void (*handler)(DisasContext *ctx);
j_mayera750fc02007-09-26 23:54:22 +0000218#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
blueswir1b55266b2008-09-20 08:07:15 +0000219 const char *oname;
j_mayera750fc02007-09-26 23:54:22 +0000220#endif
221#if defined(DO_PPC_STATISTICS)
j_mayer76a66252007-03-07 08:32:30 +0000222 uint64_t count;
223#endif
bellard3fc6c082005-07-02 20:59:34 +0000224};
bellard79aceca2003-11-23 14:55:54 +0000225
Blue Swirl636aa202009-08-16 09:06:54 +0000226static inline void gen_reset_fpstatus(void)
j_mayer7c580442007-10-27 17:54:30 +0000227{
aurel32a44d2ce2008-12-13 11:46:27 +0000228 gen_helper_reset_fpstatus();
j_mayer7c580442007-10-27 17:54:30 +0000229}
230
Blue Swirl636aa202009-08-16 09:06:54 +0000231static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
j_mayer7c580442007-10-27 17:54:30 +0000232{
aurel320f2f39c2008-11-19 17:54:49 +0000233 TCGv_i32 t0 = tcg_temp_new_i32();
aurel32af129062008-11-19 16:10:23 +0000234
j_mayer7c580442007-10-27 17:54:30 +0000235 if (set_fprf != 0) {
236 /* This case might be optimized later */
aurel320f2f39c2008-11-19 17:54:49 +0000237 tcg_gen_movi_i32(t0, 1);
aurel32af129062008-11-19 16:10:23 +0000238 gen_helper_compute_fprf(t0, arg, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000239 if (unlikely(set_rc)) {
aurel320f2f39c2008-11-19 17:54:49 +0000240 tcg_gen_mov_i32(cpu_crf[1], t0);
pbrooka7812ae2008-11-17 14:43:54 +0000241 }
aurel32af129062008-11-19 16:10:23 +0000242 gen_helper_float_check_status();
j_mayer7c580442007-10-27 17:54:30 +0000243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
aurel320f2f39c2008-11-19 17:54:49 +0000245 tcg_gen_movi_i32(t0, 0);
aurel32af129062008-11-19 16:10:23 +0000246 gen_helper_compute_fprf(t0, arg, t0);
aurel320f2f39c2008-11-19 17:54:49 +0000247 tcg_gen_mov_i32(cpu_crf[1], t0);
j_mayer7c580442007-10-27 17:54:30 +0000248 }
aurel32af129062008-11-19 16:10:23 +0000249
aurel320f2f39c2008-11-19 17:54:49 +0000250 tcg_temp_free_i32(t0);
j_mayer7c580442007-10-27 17:54:30 +0000251}
252
Blue Swirl636aa202009-08-16 09:06:54 +0000253static inline void gen_set_access_type(DisasContext *ctx, int access_type)
aurel32a7859e82008-11-23 16:30:40 +0000254{
aurel3276db3ba2008-12-08 18:11:21 +0000255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
aurel32a7859e82008-11-23 16:30:40 +0000259}
260
Blue Swirl636aa202009-08-16 09:06:54 +0000261static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
j_mayerd9bce9d2007-03-17 14:02:15 +0000262{
263#if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
aurel32bd568f12008-09-04 18:06:03 +0000265 tcg_gen_movi_tl(cpu_nip, nip);
j_mayerd9bce9d2007-03-17 14:02:15 +0000266 else
267#endif
aurel32bd568f12008-09-04 18:06:03 +0000268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
j_mayerd9bce9d2007-03-17 14:02:15 +0000269}
270
Blue Swirl636aa202009-08-16 09:06:54 +0000271static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
aurel32e06fcd72008-12-11 22:42:14 +0000272{
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283}
bellard79aceca2003-11-23 14:55:54 +0000284
Blue Swirl636aa202009-08-16 09:06:54 +0000285static inline void gen_exception(DisasContext *ctx, uint32_t excp)
aurel32e06fcd72008-12-11 22:42:14 +0000286{
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295}
bellard9a64fbe2004-01-04 22:58:38 +0000296
Blue Swirl636aa202009-08-16 09:06:54 +0000297static inline void gen_debug_exception(DisasContext *ctx)
aurel32e06fcd72008-12-11 22:42:14 +0000298{
299 TCGv_i32 t0;
blueswir15518f3a2009-02-19 20:17:09 +0000300
Sebastian Baueree2b3992011-08-10 01:41:48 +0000301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
blueswir15518f3a2009-02-19 20:17:09 +0000303 gen_update_nip(ctx, ctx->nip);
Sebastian Baueree2b3992011-08-10 01:41:48 +0000304 }
aurel32e06fcd72008-12-11 22:42:14 +0000305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(t0);
307 tcg_temp_free_i32(t0);
308}
bellard9a64fbe2004-01-04 22:58:38 +0000309
Blue Swirl636aa202009-08-16 09:06:54 +0000310static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
aurel32e06fcd72008-12-11 22:42:14 +0000311{
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313}
j_mayera9d9eb82007-10-07 18:19:26 +0000314
bellardf24e5692005-11-23 21:36:30 +0000315/* Stop translation */
Blue Swirl636aa202009-08-16 09:06:54 +0000316static inline void gen_stop_exception(DisasContext *ctx)
bellard3fc6c082005-07-02 20:59:34 +0000317{
j_mayerd9bce9d2007-03-17 14:02:15 +0000318 gen_update_nip(ctx, ctx->nip);
j_mayere1833e12007-09-29 13:06:16 +0000319 ctx->exception = POWERPC_EXCP_STOP;
bellard3fc6c082005-07-02 20:59:34 +0000320}
321
bellardf24e5692005-11-23 21:36:30 +0000322/* No need to update nip here, as execution flow will change */
Blue Swirl636aa202009-08-16 09:06:54 +0000323static inline void gen_sync_exception(DisasContext *ctx)
bellard2be00712005-07-02 22:09:27 +0000324{
j_mayere1833e12007-09-29 13:06:16 +0000325 ctx->exception = POWERPC_EXCP_SYNC;
bellard2be00712005-07-02 22:09:27 +0000326}
327
bellard79aceca2003-11-23 14:55:54 +0000328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
Alexander Grafa5858d72011-05-01 00:00:58 +0200329GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
bellard79aceca2003-11-23 14:55:54 +0000333
j_mayerc7697e12007-10-26 00:46:07 +0000334#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
Alexander Grafa5858d72011-05-01 00:00:58 +0200335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
j_mayerc7697e12007-10-26 00:46:07 +0000339
Anthony Liguoric227f092009-10-01 16:12:16 -0500340typedef struct opcode_t {
bellard79aceca2003-11-23 14:55:54 +0000341 unsigned char opc1, opc2, opc3;
ths1235fc02008-06-03 19:51:57 +0000342#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
bellard18fba282005-02-08 21:24:36 +0000343 unsigned char pad[5];
344#else
345 unsigned char pad[1];
346#endif
Anthony Liguoric227f092009-10-01 16:12:16 -0500347 opc_handler_t handler;
blueswir1b55266b2008-09-20 08:07:15 +0000348 const char *oname;
Anthony Liguoric227f092009-10-01 16:12:16 -0500349} opcode_t;
bellard79aceca2003-11-23 14:55:54 +0000350
j_mayera750fc02007-09-26 23:54:22 +0000351/*****************************************************************************/
bellard79aceca2003-11-23 14:55:54 +0000352/*** Instruction decoding ***/
353#define EXTRACT_HELPER(name, shift, nb) \
Blue Swirl636aa202009-08-16 09:06:54 +0000354static inline uint32_t name(uint32_t opcode) \
bellard79aceca2003-11-23 14:55:54 +0000355{ \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357}
358
359#define EXTRACT_SHELPER(name, shift, nb) \
Blue Swirl636aa202009-08-16 09:06:54 +0000360static inline int32_t name(uint32_t opcode) \
bellard79aceca2003-11-23 14:55:54 +0000361{ \
bellard18fba282005-02-08 21:24:36 +0000362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
bellard79aceca2003-11-23 14:55:54 +0000363}
364
365/* Opcode part 1 */
366EXTRACT_HELPER(opc1, 26, 6);
367/* Opcode part 2 */
368EXTRACT_HELPER(opc2, 1, 5);
369/* Opcode part 3 */
370EXTRACT_HELPER(opc3, 6, 5);
371/* Update Cr0 flags */
372EXTRACT_HELPER(Rc, 0, 1);
373/* Destination */
374EXTRACT_HELPER(rD, 21, 5);
375/* Source */
376EXTRACT_HELPER(rS, 21, 5);
377/* First operand */
378EXTRACT_HELPER(rA, 16, 5);
379/* Second operand */
380EXTRACT_HELPER(rB, 11, 5);
381/* Third operand */
382EXTRACT_HELPER(rC, 6, 5);
383/*** Get CRn ***/
384EXTRACT_HELPER(crfD, 23, 3);
385EXTRACT_HELPER(crfS, 18, 3);
386EXTRACT_HELPER(crbD, 21, 5);
387EXTRACT_HELPER(crbA, 16, 5);
388EXTRACT_HELPER(crbB, 11, 5);
389/* SPR / TBL */
bellard3fc6c082005-07-02 20:59:34 +0000390EXTRACT_HELPER(_SPR, 11, 10);
Blue Swirl636aa202009-08-16 09:06:54 +0000391static inline uint32_t SPR(uint32_t opcode)
bellard3fc6c082005-07-02 20:59:34 +0000392{
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396}
bellard79aceca2003-11-23 14:55:54 +0000397/*** Get constants ***/
398EXTRACT_HELPER(IMM, 12, 8);
399/* 16 bits signed immediate value */
400EXTRACT_SHELPER(SIMM, 0, 16);
401/* 16 bits unsigned immediate value */
402EXTRACT_HELPER(UIMM, 0, 16);
aurel3221d21582009-01-04 22:10:28 +0000403/* 5 bits signed immediate value */
404EXTRACT_HELPER(SIMM5, 16, 5);
aurel3227a4edb2009-01-04 22:10:40 +0000405/* 5 bits signed immediate value */
406EXTRACT_HELPER(UIMM5, 16, 5);
bellard79aceca2003-11-23 14:55:54 +0000407/* Bit count */
408EXTRACT_HELPER(NB, 11, 5);
409/* Shift count */
410EXTRACT_HELPER(SH, 11, 5);
aurel32cd633b12009-01-04 22:10:09 +0000411/* Vector shift count */
412EXTRACT_HELPER(VSH, 6, 4);
bellard79aceca2003-11-23 14:55:54 +0000413/* Mask start */
414EXTRACT_HELPER(MB, 6, 5);
415/* Mask end */
416EXTRACT_HELPER(ME, 1, 5);
bellardfb0eaff2004-01-04 14:57:11 +0000417/* Trap operand */
418EXTRACT_HELPER(TO, 21, 5);
bellard79aceca2003-11-23 14:55:54 +0000419
420EXTRACT_HELPER(CRM, 12, 8);
421EXTRACT_HELPER(FM, 17, 8);
422EXTRACT_HELPER(SR, 16, 4);
aurel32e4bb9972008-06-18 22:10:12 +0000423EXTRACT_HELPER(FPIMM, 12, 4);
bellardfb0eaff2004-01-04 14:57:11 +0000424
bellard79aceca2003-11-23 14:55:54 +0000425/*** Jump target decoding ***/
426/* Displacement */
427EXTRACT_SHELPER(d, 0, 16);
428/* Immediate address */
Blue Swirl636aa202009-08-16 09:06:54 +0000429static inline target_ulong LI(uint32_t opcode)
bellard79aceca2003-11-23 14:55:54 +0000430{
431 return (opcode >> 0) & 0x03FFFFFC;
432}
433
Blue Swirl636aa202009-08-16 09:06:54 +0000434static inline uint32_t BD(uint32_t opcode)
bellard79aceca2003-11-23 14:55:54 +0000435{
436 return (opcode >> 0) & 0xFFFC;
437}
438
439EXTRACT_HELPER(BO, 21, 5);
440EXTRACT_HELPER(BI, 16, 5);
441/* Absolute/relative address */
442EXTRACT_HELPER(AA, 1, 1);
443/* Link */
444EXTRACT_HELPER(LK, 0, 1);
445
446/* Create a mask between <start> and <end> bits */
Blue Swirl636aa202009-08-16 09:06:54 +0000447static inline target_ulong MASK(uint32_t start, uint32_t end)
bellard79aceca2003-11-23 14:55:54 +0000448{
j_mayer76a66252007-03-07 08:32:30 +0000449 target_ulong ret;
bellard79aceca2003-11-23 14:55:54 +0000450
j_mayer76a66252007-03-07 08:32:30 +0000451#if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000453 ret = UINT64_MAX << (63 - end);
j_mayer76a66252007-03-07 08:32:30 +0000454 } else if (likely(end == 63)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000455 ret = UINT64_MAX >> start;
j_mayer76a66252007-03-07 08:32:30 +0000456 }
457#else
458 if (likely(start == 0)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000459 ret = UINT32_MAX << (31 - end);
j_mayer76a66252007-03-07 08:32:30 +0000460 } else if (likely(end == 31)) {
j_mayer6f2d8972007-11-12 00:04:48 +0000461 ret = UINT32_MAX >> start;
j_mayer76a66252007-03-07 08:32:30 +0000462 }
463#endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
bellard79aceca2003-11-23 14:55:54 +0000470
471 return ret;
472}
473
j_mayera750fc02007-09-26 23:54:22 +0000474/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +0000475/* PowerPC instructions table */
bellard933dc6e2004-07-10 15:33:29 +0000476
j_mayer76a66252007-03-07 08:32:30 +0000477#if defined(DO_PPC_STATISTICS)
Alexander Grafa5858d72011-05-01 00:00:58 +0200478#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
Blue Swirl5c55ff92009-06-17 15:22:31 +0000479{ \
j_mayer76a66252007-03-07 08:32:30 +0000480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
Fabien Chouteau70560da2011-09-28 05:54:05 +0000485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492}
493#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494{ \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
j_mayer76a66252007-03-07 08:32:30 +0000502 .type = _typ, \
Alexander Grafa5858d72011-05-01 00:00:58 +0200503 .type2 = _typ2, \
j_mayer76a66252007-03-07 08:32:30 +0000504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508}
Alexander Grafa5858d72011-05-01 00:00:58 +0200509#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
Blue Swirl5c55ff92009-06-17 15:22:31 +0000510{ \
j_mayerc7697e12007-10-26 00:46:07 +0000511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
Fabien Chouteau70560da2011-09-28 05:54:05 +0000516 .inval1 = invl, \
j_mayerc7697e12007-10-26 00:46:07 +0000517 .type = _typ, \
Alexander Grafa5858d72011-05-01 00:00:58 +0200518 .type2 = _typ2, \
j_mayerc7697e12007-10-26 00:46:07 +0000519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523}
j_mayer76a66252007-03-07 08:32:30 +0000524#else
Alexander Grafa5858d72011-05-01 00:00:58 +0200525#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
Blue Swirl5c55ff92009-06-17 15:22:31 +0000526{ \
bellard79aceca2003-11-23 14:55:54 +0000527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
bellard18fba282005-02-08 21:24:36 +0000530 .pad = { 0, }, \
bellard79aceca2003-11-23 14:55:54 +0000531 .handler = { \
Fabien Chouteau70560da2011-09-28 05:54:05 +0000532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538}
539#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540{ \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
bellard9a64fbe2004-01-04 22:58:38 +0000548 .type = _typ, \
Alexander Grafa5858d72011-05-01 00:00:58 +0200549 .type2 = _typ2, \
bellard79aceca2003-11-23 14:55:54 +0000550 .handler = &gen_##name, \
551 }, \
bellard3fc6c082005-07-02 20:59:34 +0000552 .oname = stringify(name), \
bellard79aceca2003-11-23 14:55:54 +0000553}
Alexander Grafa5858d72011-05-01 00:00:58 +0200554#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
Blue Swirl5c55ff92009-06-17 15:22:31 +0000555{ \
j_mayerc7697e12007-10-26 00:46:07 +0000556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
Fabien Chouteau70560da2011-09-28 05:54:05 +0000561 .inval1 = invl, \
j_mayerc7697e12007-10-26 00:46:07 +0000562 .type = _typ, \
Alexander Grafa5858d72011-05-01 00:00:58 +0200563 .type2 = _typ2, \
j_mayerc7697e12007-10-26 00:46:07 +0000564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567}
j_mayer76a66252007-03-07 08:32:30 +0000568#endif
bellard79aceca2003-11-23 14:55:54 +0000569
aurel3254cdcae2008-12-05 07:21:31 +0000570/* SPR load/store helpers */
Blue Swirl636aa202009-08-16 09:06:54 +0000571static inline void gen_load_spr(TCGv t, int reg)
aurel3254cdcae2008-12-05 07:21:31 +0000572{
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
574}
575
Blue Swirl636aa202009-08-16 09:06:54 +0000576static inline void gen_store_spr(int reg, TCGv t)
aurel3254cdcae2008-12-05 07:21:31 +0000577{
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
579}
580
bellard79aceca2003-11-23 14:55:54 +0000581/* Invalid instruction */
Blue Swirl99e300e2009-06-17 15:22:09 +0000582static void gen_invalid(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +0000583{
aurel32e06fcd72008-12-11 22:42:14 +0000584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
bellard9a64fbe2004-01-04 22:58:38 +0000585}
586
Anthony Liguoric227f092009-10-01 16:12:16 -0500587static opc_handler_t invalid_handler = {
Fabien Chouteau70560da2011-09-28 05:54:05 +0000588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
bellard9a64fbe2004-01-04 22:58:38 +0000590 .type = PPC_NONE,
Alexander Grafa5858d72011-05-01 00:00:58 +0200591 .type2 = PPC_NONE,
bellard79aceca2003-11-23 14:55:54 +0000592 .handler = gen_invalid,
593};
594
aurel32e1571902008-10-21 11:31:14 +0000595/*** Integer comparison ***/
596
Blue Swirl636aa202009-08-16 09:06:54 +0000597static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000598{
599 int l1, l2, l3;
600
aurel32269f3e92008-11-01 00:53:48 +0000601 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
602 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
aurel32e1571902008-10-21 11:31:14 +0000603 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
604
605 l1 = gen_new_label();
606 l2 = gen_new_label();
607 l3 = gen_new_label();
608 if (s) {
aurel32ea363692008-10-27 22:50:39 +0000609 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
610 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
aurel32e1571902008-10-21 11:31:14 +0000611 } else {
aurel32ea363692008-10-27 22:50:39 +0000612 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
613 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
aurel32e1571902008-10-21 11:31:14 +0000614 }
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
616 tcg_gen_br(l3);
617 gen_set_label(l1);
618 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
619 tcg_gen_br(l3);
620 gen_set_label(l2);
621 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
622 gen_set_label(l3);
623}
624
Blue Swirl636aa202009-08-16 09:06:54 +0000625static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000626{
aurel32ea363692008-10-27 22:50:39 +0000627 TCGv t0 = tcg_const_local_tl(arg1);
628 gen_op_cmp(arg0, t0, s, crf);
629 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000630}
631
632#if defined(TARGET_PPC64)
Blue Swirl636aa202009-08-16 09:06:54 +0000633static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000634{
aurel32ea363692008-10-27 22:50:39 +0000635 TCGv t0, t1;
pbrooka7812ae2008-11-17 14:43:54 +0000636 t0 = tcg_temp_local_new();
637 t1 = tcg_temp_local_new();
aurel32e1571902008-10-21 11:31:14 +0000638 if (s) {
aurel32ea363692008-10-27 22:50:39 +0000639 tcg_gen_ext32s_tl(t0, arg0);
640 tcg_gen_ext32s_tl(t1, arg1);
aurel32e1571902008-10-21 11:31:14 +0000641 } else {
aurel32ea363692008-10-27 22:50:39 +0000642 tcg_gen_ext32u_tl(t0, arg0);
643 tcg_gen_ext32u_tl(t1, arg1);
aurel32e1571902008-10-21 11:31:14 +0000644 }
aurel32ea363692008-10-27 22:50:39 +0000645 gen_op_cmp(t0, t1, s, crf);
646 tcg_temp_free(t1);
647 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000648}
649
Blue Swirl636aa202009-08-16 09:06:54 +0000650static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
aurel32e1571902008-10-21 11:31:14 +0000651{
aurel32ea363692008-10-27 22:50:39 +0000652 TCGv t0 = tcg_const_local_tl(arg1);
653 gen_op_cmp32(arg0, t0, s, crf);
654 tcg_temp_free(t0);
aurel32e1571902008-10-21 11:31:14 +0000655}
656#endif
657
Blue Swirl636aa202009-08-16 09:06:54 +0000658static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
aurel32e1571902008-10-21 11:31:14 +0000659{
660#if defined(TARGET_PPC64)
661 if (!(ctx->sf_mode))
662 gen_op_cmpi32(reg, 0, 1, 0);
663 else
664#endif
665 gen_op_cmpi(reg, 0, 1, 0);
666}
667
668/* cmp */
Blue Swirl99e300e2009-06-17 15:22:09 +0000669static void gen_cmp(DisasContext *ctx)
aurel32e1571902008-10-21 11:31:14 +0000670{
671#if defined(TARGET_PPC64)
672 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
674 1, crfD(ctx->opcode));
675 else
676#endif
677 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
678 1, crfD(ctx->opcode));
679}
680
681/* cmpi */
Blue Swirl99e300e2009-06-17 15:22:09 +0000682static void gen_cmpi(DisasContext *ctx)
aurel32e1571902008-10-21 11:31:14 +0000683{
684#if defined(TARGET_PPC64)
685 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
686 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
687 1, crfD(ctx->opcode));
688 else
689#endif
690 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
691 1, crfD(ctx->opcode));
692}
693
694/* cmpl */
Blue Swirl99e300e2009-06-17 15:22:09 +0000695static void gen_cmpl(DisasContext *ctx)
aurel32e1571902008-10-21 11:31:14 +0000696{
697#if defined(TARGET_PPC64)
698 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
699 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
700 0, crfD(ctx->opcode));
701 else
702#endif
703 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
704 0, crfD(ctx->opcode));
705}
706
707/* cmpli */
Blue Swirl99e300e2009-06-17 15:22:09 +0000708static void gen_cmpli(DisasContext *ctx)
aurel32e1571902008-10-21 11:31:14 +0000709{
710#if defined(TARGET_PPC64)
711 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
713 0, crfD(ctx->opcode));
714 else
715#endif
716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
717 0, crfD(ctx->opcode));
718}
719
720/* isel (PowerPC 2.03 specification) */
Blue Swirl99e300e2009-06-17 15:22:09 +0000721static void gen_isel(DisasContext *ctx)
aurel32e1571902008-10-21 11:31:14 +0000722{
723 int l1, l2;
724 uint32_t bi = rC(ctx->opcode);
725 uint32_t mask;
pbrooka7812ae2008-11-17 14:43:54 +0000726 TCGv_i32 t0;
aurel32e1571902008-10-21 11:31:14 +0000727
728 l1 = gen_new_label();
729 l2 = gen_new_label();
730
731 mask = 1 << (3 - (bi & 0x03));
pbrooka7812ae2008-11-17 14:43:54 +0000732 t0 = tcg_temp_new_i32();
aurel32fea0c502008-11-02 08:22:34 +0000733 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
734 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
aurel32e1571902008-10-21 11:31:14 +0000735 if (rA(ctx->opcode) == 0)
736 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
737 else
738 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
739 tcg_gen_br(l2);
740 gen_set_label(l1);
741 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
742 gen_set_label(l2);
pbrooka7812ae2008-11-17 14:43:54 +0000743 tcg_temp_free_i32(t0);
aurel32e1571902008-10-21 11:31:14 +0000744}
745
bellard79aceca2003-11-23 14:55:54 +0000746/*** Integer arithmetic ***/
aurel3274637402008-11-01 00:54:12 +0000747
Blue Swirl636aa202009-08-16 09:06:54 +0000748static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
749 TCGv arg1, TCGv arg2, int sub)
aurel3274637402008-11-01 00:54:12 +0000750{
751 int l1;
752 TCGv t0;
753
754 l1 = gen_new_label();
755 /* Start with XER OV disabled, the most likely case */
756 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
pbrooka7812ae2008-11-17 14:43:54 +0000757 t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +0000758 tcg_gen_xor_tl(t0, arg0, arg1);
759#if defined(TARGET_PPC64)
760 if (!ctx->sf_mode)
761 tcg_gen_ext32s_tl(t0, t0);
762#endif
763 if (sub)
764 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
765 else
766 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
767 tcg_gen_xor_tl(t0, arg1, arg2);
768#if defined(TARGET_PPC64)
769 if (!ctx->sf_mode)
770 tcg_gen_ext32s_tl(t0, t0);
771#endif
772 if (sub)
773 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
774 else
775 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
776 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
777 gen_set_label(l1);
778 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +0000779}
780
Blue Swirl636aa202009-08-16 09:06:54 +0000781static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
782 TCGv arg2, int sub)
aurel3274637402008-11-01 00:54:12 +0000783{
784 int l1 = gen_new_label();
j_mayerd9bce9d2007-03-17 14:02:15 +0000785
786#if defined(TARGET_PPC64)
aurel3274637402008-11-01 00:54:12 +0000787 if (!(ctx->sf_mode)) {
788 TCGv t0, t1;
pbrooka7812ae2008-11-17 14:43:54 +0000789 t0 = tcg_temp_new();
790 t1 = tcg_temp_new();
j_mayerd9bce9d2007-03-17 14:02:15 +0000791
aurel3274637402008-11-01 00:54:12 +0000792 tcg_gen_ext32u_tl(t0, arg1);
793 tcg_gen_ext32u_tl(t1, arg2);
794 if (sub) {
795 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
aurel32bdc4e052008-11-09 17:27:03 +0000796 } else {
aurel3274637402008-11-01 00:54:12 +0000797 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
798 }
aurel32a9730012008-11-09 17:27:36 +0000799 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
800 gen_set_label(l1);
801 tcg_temp_free(t0);
802 tcg_temp_free(t1);
aurel3274637402008-11-01 00:54:12 +0000803 } else
j_mayerd9bce9d2007-03-17 14:02:15 +0000804#endif
aurel32a9730012008-11-09 17:27:36 +0000805 {
806 if (sub) {
807 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
808 } else {
809 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
810 }
811 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
812 gen_set_label(l1);
aurel3274637402008-11-01 00:54:12 +0000813 }
aurel3274637402008-11-01 00:54:12 +0000814}
bellard79aceca2003-11-23 14:55:54 +0000815
aurel3274637402008-11-01 00:54:12 +0000816/* Common add function */
Blue Swirl636aa202009-08-16 09:06:54 +0000817static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
818 TCGv arg2, int add_ca, int compute_ca,
819 int compute_ov)
aurel3239dd32e2008-09-05 14:19:43 +0000820{
aurel3274637402008-11-01 00:54:12 +0000821 TCGv t0, t1;
822
823 if ((!compute_ca && !compute_ov) ||
pbrooka7812ae2008-11-17 14:43:54 +0000824 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
aurel3274637402008-11-01 00:54:12 +0000825 t0 = ret;
826 } else {
pbrooka7812ae2008-11-17 14:43:54 +0000827 t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +0000828 }
829
830 if (add_ca) {
pbrooka7812ae2008-11-17 14:43:54 +0000831 t1 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +0000832 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
833 tcg_gen_shri_tl(t1, t1, XER_CA);
malcd2e9fd82009-06-20 05:51:47 +0400834 } else {
835 TCGV_UNUSED(t1);
aurel3274637402008-11-01 00:54:12 +0000836 }
837
838 if (compute_ca && compute_ov) {
839 /* Start with XER CA and OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
841 } else if (compute_ca) {
842 /* Start with XER CA disabled, the most likely case */
843 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
844 } else if (compute_ov) {
845 /* Start with XER OV disabled, the most likely case */
846 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
847 }
848
849 tcg_gen_add_tl(t0, arg1, arg2);
850
851 if (compute_ca) {
852 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
853 }
854 if (add_ca) {
855 tcg_gen_add_tl(t0, t0, t1);
856 gen_op_arith_compute_ca(ctx, t0, t1, 0);
857 tcg_temp_free(t1);
858 }
859 if (compute_ov) {
860 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
861 }
862
863 if (unlikely(Rc(ctx->opcode) != 0))
864 gen_set_Rc0(ctx, t0);
865
pbrooka7812ae2008-11-17 14:43:54 +0000866 if (!TCGV_EQUAL(t0, ret)) {
aurel3274637402008-11-01 00:54:12 +0000867 tcg_gen_mov_tl(ret, t0);
868 tcg_temp_free(t0);
869 }
aurel3239dd32e2008-09-05 14:19:43 +0000870}
aurel3274637402008-11-01 00:54:12 +0000871/* Add functions with two operands */
872#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +0000873static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +0000874{ \
875 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
876 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
877 add_ca, compute_ca, compute_ov); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000878}
aurel3274637402008-11-01 00:54:12 +0000879/* Add functions with one operand and one immediate */
880#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
881 add_ca, compute_ca, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +0000882static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +0000883{ \
884 TCGv t0 = tcg_const_local_tl(const_val); \
885 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
886 cpu_gpr[rA(ctx->opcode)], t0, \
887 add_ca, compute_ca, compute_ov); \
888 tcg_temp_free(t0); \
j_mayerd9bce9d2007-03-17 14:02:15 +0000889}
aurel3274637402008-11-01 00:54:12 +0000890
891/* add add. addo addo. */
892GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
893GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
894/* addc addc. addco addco. */
895GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
896GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
897/* adde adde. addeo addeo. */
898GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
899GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
bellard79aceca2003-11-23 14:55:54 +0000900/* addme addme. addmeo addmeo. */
aurel3274637402008-11-01 00:54:12 +0000901GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
902GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
903/* addze addze. addzeo addzeo.*/
904GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
905GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
bellard79aceca2003-11-23 14:55:54 +0000906/* addi */
Blue Swirl99e300e2009-06-17 15:22:09 +0000907static void gen_addi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +0000908{
j_mayer76a66252007-03-07 08:32:30 +0000909 target_long simm = SIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +0000910
911 if (rA(ctx->opcode) == 0) {
j_mayer76a66252007-03-07 08:32:30 +0000912 /* li case */
aurel3274637402008-11-01 00:54:12 +0000913 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
bellard79aceca2003-11-23 14:55:54 +0000914 } else {
aurel3274637402008-11-01 00:54:12 +0000915 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
bellard79aceca2003-11-23 14:55:54 +0000916 }
bellard79aceca2003-11-23 14:55:54 +0000917}
aurel3274637402008-11-01 00:54:12 +0000918/* addic addic.*/
Blue Swirl636aa202009-08-16 09:06:54 +0000919static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
920 int compute_Rc0)
aurel3274637402008-11-01 00:54:12 +0000921{
922 target_long simm = SIMM(ctx->opcode);
923
924 /* Start with XER CA and OV disabled, the most likely case */
925 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
926
927 if (likely(simm != 0)) {
pbrooka7812ae2008-11-17 14:43:54 +0000928 TCGv t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +0000929 tcg_gen_addi_tl(t0, arg1, simm);
930 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
931 tcg_gen_mov_tl(ret, t0);
932 tcg_temp_free(t0);
933 } else {
934 tcg_gen_mov_tl(ret, arg1);
935 }
936 if (compute_Rc0) {
937 gen_set_Rc0(ctx, ret);
938 }
939}
Blue Swirl99e300e2009-06-17 15:22:09 +0000940
941static void gen_addic(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +0000942{
aurel3274637402008-11-01 00:54:12 +0000943 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
bellard79aceca2003-11-23 14:55:54 +0000944}
Blue Swirle8eaa2c2009-06-17 15:22:14 +0000945
946static void gen_addic_(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +0000947{
aurel3274637402008-11-01 00:54:12 +0000948 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
bellard79aceca2003-11-23 14:55:54 +0000949}
Blue Swirl99e300e2009-06-17 15:22:09 +0000950
Blue Swirl54623272009-06-17 15:22:19 +0000951/* addis */
Blue Swirl99e300e2009-06-17 15:22:09 +0000952static void gen_addis(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +0000953{
j_mayer76a66252007-03-07 08:32:30 +0000954 target_long simm = SIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +0000955
956 if (rA(ctx->opcode) == 0) {
j_mayer76a66252007-03-07 08:32:30 +0000957 /* lis case */
aurel3274637402008-11-01 00:54:12 +0000958 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
bellard79aceca2003-11-23 14:55:54 +0000959 } else {
aurel3274637402008-11-01 00:54:12 +0000960 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
bellard79aceca2003-11-23 14:55:54 +0000961 }
aurel3274637402008-11-01 00:54:12 +0000962}
963
Blue Swirl636aa202009-08-16 09:06:54 +0000964static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
965 TCGv arg2, int sign, int compute_ov)
aurel3274637402008-11-01 00:54:12 +0000966{
aurel322ef1b122008-11-09 17:27:19 +0000967 int l1 = gen_new_label();
968 int l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +0000969 TCGv_i32 t0 = tcg_temp_local_new_i32();
970 TCGv_i32 t1 = tcg_temp_local_new_i32();
aurel3274637402008-11-01 00:54:12 +0000971
aurel322ef1b122008-11-09 17:27:19 +0000972 tcg_gen_trunc_tl_i32(t0, arg1);
973 tcg_gen_trunc_tl_i32(t1, arg2);
974 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
aurel3274637402008-11-01 00:54:12 +0000975 if (sign) {
aurel322ef1b122008-11-09 17:27:19 +0000976 int l3 = gen_new_label();
977 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
978 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
aurel3274637402008-11-01 00:54:12 +0000979 gen_set_label(l3);
aurel322ef1b122008-11-09 17:27:19 +0000980 tcg_gen_div_i32(t0, t0, t1);
aurel3274637402008-11-01 00:54:12 +0000981 } else {
aurel322ef1b122008-11-09 17:27:19 +0000982 tcg_gen_divu_i32(t0, t0, t1);
aurel3274637402008-11-01 00:54:12 +0000983 }
984 if (compute_ov) {
985 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
986 }
987 tcg_gen_br(l2);
988 gen_set_label(l1);
989 if (sign) {
aurel322ef1b122008-11-09 17:27:19 +0000990 tcg_gen_sari_i32(t0, t0, 31);
aurel3274637402008-11-01 00:54:12 +0000991 } else {
992 tcg_gen_movi_i32(t0, 0);
993 }
994 if (compute_ov) {
995 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
996 }
997 gen_set_label(l2);
aurel322ef1b122008-11-09 17:27:19 +0000998 tcg_gen_extu_i32_tl(ret, t0);
pbrooka7812ae2008-11-17 14:43:54 +0000999 tcg_temp_free_i32(t0);
1000 tcg_temp_free_i32(t1);
aurel3274637402008-11-01 00:54:12 +00001001 if (unlikely(Rc(ctx->opcode) != 0))
1002 gen_set_Rc0(ctx, ret);
1003}
1004/* Div functions */
1005#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001006static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +00001007{ \
1008 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1009 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1010 sign, compute_ov); \
1011}
1012/* divwu divwu. divwuo divwuo. */
1013GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1014GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1015/* divw divw. divwo divwo. */
1016GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1017GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1018#if defined(TARGET_PPC64)
Blue Swirl636aa202009-08-16 09:06:54 +00001019static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1020 TCGv arg2, int sign, int compute_ov)
aurel3274637402008-11-01 00:54:12 +00001021{
aurel322ef1b122008-11-09 17:27:19 +00001022 int l1 = gen_new_label();
1023 int l2 = gen_new_label();
aurel3274637402008-11-01 00:54:12 +00001024
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1026 if (sign) {
aurel322ef1b122008-11-09 17:27:19 +00001027 int l3 = gen_new_label();
aurel3274637402008-11-01 00:54:12 +00001028 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1030 gen_set_label(l3);
aurel3274637402008-11-01 00:54:12 +00001031 tcg_gen_div_i64(ret, arg1, arg2);
1032 } else {
1033 tcg_gen_divu_i64(ret, arg1, arg2);
1034 }
1035 if (compute_ov) {
1036 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1037 }
1038 tcg_gen_br(l2);
1039 gen_set_label(l1);
1040 if (sign) {
1041 tcg_gen_sari_i64(ret, arg1, 63);
1042 } else {
1043 tcg_gen_movi_i64(ret, 0);
1044 }
1045 if (compute_ov) {
1046 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1047 }
1048 gen_set_label(l2);
1049 if (unlikely(Rc(ctx->opcode) != 0))
1050 gen_set_Rc0(ctx, ret);
1051}
1052#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001053static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +00001054{ \
aurel322ef1b122008-11-09 17:27:19 +00001055 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1056 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1057 sign, compute_ov); \
aurel3274637402008-11-01 00:54:12 +00001058}
1059/* divwu divwu. divwuo divwuo. */
1060GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1061GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1062/* divw divw. divwo divwo. */
1063GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1064GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1065#endif
1066
1067/* mulhw mulhw. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001068static void gen_mulhw(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001069{
pbrooka7812ae2008-11-17 14:43:54 +00001070 TCGv_i64 t0, t1;
aurel3274637402008-11-01 00:54:12 +00001071
pbrooka7812ae2008-11-17 14:43:54 +00001072 t0 = tcg_temp_new_i64();
1073 t1 = tcg_temp_new_i64();
aurel3274637402008-11-01 00:54:12 +00001074#if defined(TARGET_PPC64)
1075 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1076 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1077 tcg_gen_mul_i64(t0, t0, t1);
1078 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1079#else
1080 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1081 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1082 tcg_gen_mul_i64(t0, t0, t1);
1083 tcg_gen_shri_i64(t0, t0, 32);
1084 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1085#endif
pbrooka7812ae2008-11-17 14:43:54 +00001086 tcg_temp_free_i64(t0);
1087 tcg_temp_free_i64(t1);
aurel3274637402008-11-01 00:54:12 +00001088 if (unlikely(Rc(ctx->opcode) != 0))
1089 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1090}
Blue Swirl99e300e2009-06-17 15:22:09 +00001091
Blue Swirl54623272009-06-17 15:22:19 +00001092/* mulhwu mulhwu. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001093static void gen_mulhwu(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001094{
pbrooka7812ae2008-11-17 14:43:54 +00001095 TCGv_i64 t0, t1;
aurel3274637402008-11-01 00:54:12 +00001096
pbrooka7812ae2008-11-17 14:43:54 +00001097 t0 = tcg_temp_new_i64();
1098 t1 = tcg_temp_new_i64();
aurel3274637402008-11-01 00:54:12 +00001099#if defined(TARGET_PPC64)
1100 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1101 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1102 tcg_gen_mul_i64(t0, t0, t1);
1103 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1104#else
1105 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1106 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1107 tcg_gen_mul_i64(t0, t0, t1);
1108 tcg_gen_shri_i64(t0, t0, 32);
1109 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1110#endif
pbrooka7812ae2008-11-17 14:43:54 +00001111 tcg_temp_free_i64(t0);
1112 tcg_temp_free_i64(t1);
aurel3274637402008-11-01 00:54:12 +00001113 if (unlikely(Rc(ctx->opcode) != 0))
1114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1115}
Blue Swirl99e300e2009-06-17 15:22:09 +00001116
Blue Swirl54623272009-06-17 15:22:19 +00001117/* mullw mullw. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001118static void gen_mullw(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001119{
aurel3274637402008-11-01 00:54:12 +00001120 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121 cpu_gpr[rB(ctx->opcode)]);
aurel321e4c0902008-11-09 17:27:11 +00001122 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
aurel3274637402008-11-01 00:54:12 +00001123 if (unlikely(Rc(ctx->opcode) != 0))
1124 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125}
Blue Swirl99e300e2009-06-17 15:22:09 +00001126
Blue Swirl54623272009-06-17 15:22:19 +00001127/* mullwo mullwo. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001128static void gen_mullwo(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001129{
1130 int l1;
pbrooka7812ae2008-11-17 14:43:54 +00001131 TCGv_i64 t0, t1;
aurel3274637402008-11-01 00:54:12 +00001132
pbrooka7812ae2008-11-17 14:43:54 +00001133 t0 = tcg_temp_new_i64();
1134 t1 = tcg_temp_new_i64();
aurel3274637402008-11-01 00:54:12 +00001135 l1 = gen_new_label();
1136 /* Start with XER OV disabled, the most likely case */
1137 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1138#if defined(TARGET_PPC64)
1139 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1140 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1141#else
1142 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1143 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1144#endif
1145 tcg_gen_mul_i64(t0, t0, t1);
1146#if defined(TARGET_PPC64)
1147 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1148 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1149#else
1150 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1151 tcg_gen_ext32s_i64(t1, t0);
1152 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1153#endif
1154 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1155 gen_set_label(l1);
pbrooka7812ae2008-11-17 14:43:54 +00001156 tcg_temp_free_i64(t0);
1157 tcg_temp_free_i64(t1);
aurel3274637402008-11-01 00:54:12 +00001158 if (unlikely(Rc(ctx->opcode) != 0))
1159 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001160}
Blue Swirl99e300e2009-06-17 15:22:09 +00001161
Blue Swirl54623272009-06-17 15:22:19 +00001162/* mulli */
Blue Swirl99e300e2009-06-17 15:22:09 +00001163static void gen_mulli(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001164{
aurel3274637402008-11-01 00:54:12 +00001165 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1166 SIMM(ctx->opcode));
bellard79aceca2003-11-23 14:55:54 +00001167}
aurel3274637402008-11-01 00:54:12 +00001168#if defined(TARGET_PPC64)
1169#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001170static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +00001171{ \
pbrooka7812ae2008-11-17 14:43:54 +00001172 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
aurel3274637402008-11-01 00:54:12 +00001173 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1174 if (unlikely(Rc(ctx->opcode) != 0)) \
1175 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1176}
1177/* mulhd mulhd. */
1178GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1179/* mulhdu mulhdu. */
1180GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
Blue Swirl99e300e2009-06-17 15:22:09 +00001181
Blue Swirl54623272009-06-17 15:22:19 +00001182/* mulld mulld. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001183static void gen_mulld(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001184{
1185 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1186 cpu_gpr[rB(ctx->opcode)]);
1187 if (unlikely(Rc(ctx->opcode) != 0))
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189}
1190/* mulldo mulldo. */
1191GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1192#endif
1193
1194/* neg neg. nego nego. */
Blue Swirl636aa202009-08-16 09:06:54 +00001195static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1196 int ov_check)
aurel3274637402008-11-01 00:54:12 +00001197{
aurel32ec6469a2008-11-09 17:27:27 +00001198 int l1 = gen_new_label();
1199 int l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00001200 TCGv t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +00001201#if defined(TARGET_PPC64)
1202 if (ctx->sf_mode) {
aurel32741a7442008-11-09 18:27:28 +00001203 tcg_gen_mov_tl(t0, arg1);
aurel32ec6469a2008-11-09 17:27:27 +00001204 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1205 } else
1206#endif
1207 {
1208 tcg_gen_ext32s_tl(t0, arg1);
aurel3274637402008-11-01 00:54:12 +00001209 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1210 }
aurel3274637402008-11-01 00:54:12 +00001211 tcg_gen_neg_tl(ret, arg1);
1212 if (ov_check) {
1213 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1214 }
1215 tcg_gen_br(l2);
1216 gen_set_label(l1);
aurel32ec6469a2008-11-09 17:27:27 +00001217 tcg_gen_mov_tl(ret, t0);
aurel3274637402008-11-01 00:54:12 +00001218 if (ov_check) {
1219 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1220 }
1221 gen_set_label(l2);
aurel32ec6469a2008-11-09 17:27:27 +00001222 tcg_temp_free(t0);
aurel3274637402008-11-01 00:54:12 +00001223 if (unlikely(Rc(ctx->opcode) != 0))
1224 gen_set_Rc0(ctx, ret);
1225}
Blue Swirl99e300e2009-06-17 15:22:09 +00001226
1227static void gen_neg(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001228{
aurel32ec6469a2008-11-09 17:27:27 +00001229 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
aurel3274637402008-11-01 00:54:12 +00001230}
Blue Swirl99e300e2009-06-17 15:22:09 +00001231
1232static void gen_nego(DisasContext *ctx)
aurel3274637402008-11-01 00:54:12 +00001233{
aurel32ec6469a2008-11-09 17:27:27 +00001234 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
aurel3274637402008-11-01 00:54:12 +00001235}
1236
1237/* Common subf function */
Blue Swirl636aa202009-08-16 09:06:54 +00001238static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1239 TCGv arg2, int add_ca, int compute_ca,
1240 int compute_ov)
aurel3274637402008-11-01 00:54:12 +00001241{
1242 TCGv t0, t1;
1243
1244 if ((!compute_ca && !compute_ov) ||
pbrooka7812ae2008-11-17 14:43:54 +00001245 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
aurel3274637402008-11-01 00:54:12 +00001246 t0 = ret;
1247 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001248 t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +00001249 }
1250
1251 if (add_ca) {
pbrooka7812ae2008-11-17 14:43:54 +00001252 t1 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +00001253 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1254 tcg_gen_shri_tl(t1, t1, XER_CA);
malcd2e9fd82009-06-20 05:51:47 +04001255 } else {
1256 TCGV_UNUSED(t1);
aurel3274637402008-11-01 00:54:12 +00001257 }
1258
1259 if (compute_ca && compute_ov) {
1260 /* Start with XER CA and OV disabled, the most likely case */
1261 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1262 } else if (compute_ca) {
1263 /* Start with XER CA disabled, the most likely case */
1264 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1265 } else if (compute_ov) {
1266 /* Start with XER OV disabled, the most likely case */
1267 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1268 }
1269
1270 if (add_ca) {
1271 tcg_gen_not_tl(t0, arg1);
1272 tcg_gen_add_tl(t0, t0, arg2);
1273 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1274 tcg_gen_add_tl(t0, t0, t1);
1275 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1276 tcg_temp_free(t1);
1277 } else {
1278 tcg_gen_sub_tl(t0, arg2, arg1);
1279 if (compute_ca) {
1280 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1281 }
1282 }
1283 if (compute_ov) {
1284 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1285 }
1286
1287 if (unlikely(Rc(ctx->opcode) != 0))
1288 gen_set_Rc0(ctx, t0);
1289
pbrooka7812ae2008-11-17 14:43:54 +00001290 if (!TCGV_EQUAL(t0, ret)) {
aurel3274637402008-11-01 00:54:12 +00001291 tcg_gen_mov_tl(ret, t0);
1292 tcg_temp_free(t0);
1293 }
1294}
1295/* Sub functions with Two operands functions */
1296#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001297static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +00001298{ \
1299 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1300 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1301 add_ca, compute_ca, compute_ov); \
1302}
1303/* Sub functions with one operand and one immediate */
1304#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1305 add_ca, compute_ca, compute_ov) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001306static void glue(gen_, name)(DisasContext *ctx) \
aurel3274637402008-11-01 00:54:12 +00001307{ \
1308 TCGv t0 = tcg_const_local_tl(const_val); \
1309 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1310 cpu_gpr[rA(ctx->opcode)], t0, \
1311 add_ca, compute_ca, compute_ov); \
1312 tcg_temp_free(t0); \
1313}
1314/* subf subf. subfo subfo. */
1315GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1316GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1317/* subfc subfc. subfco subfco. */
1318GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1319GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1320/* subfe subfe. subfeo subfo. */
1321GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1322GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1323/* subfme subfme. subfmeo subfmeo. */
1324GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1325GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1326/* subfze subfze. subfzeo subfzeo.*/
1327GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1328GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
Blue Swirl99e300e2009-06-17 15:22:09 +00001329
Blue Swirl54623272009-06-17 15:22:19 +00001330/* subfic */
Blue Swirl99e300e2009-06-17 15:22:09 +00001331static void gen_subfic(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001332{
aurel3274637402008-11-01 00:54:12 +00001333 /* Start with XER CA and OV disabled, the most likely case */
1334 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
pbrooka7812ae2008-11-17 14:43:54 +00001335 TCGv t0 = tcg_temp_local_new();
aurel3274637402008-11-01 00:54:12 +00001336 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1337 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1338 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1339 tcg_temp_free(t1);
1340 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1341 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00001342}
1343
bellard79aceca2003-11-23 14:55:54 +00001344/*** Integer logical ***/
aurel3226d67362008-10-21 11:31:27 +00001345#define GEN_LOGICAL2(name, tcg_op, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001346static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00001347{ \
aurel3226d67362008-10-21 11:31:27 +00001348 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1349 cpu_gpr[rB(ctx->opcode)]); \
j_mayer76a66252007-03-07 08:32:30 +00001350 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel3226d67362008-10-21 11:31:27 +00001351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +00001352}
bellard79aceca2003-11-23 14:55:54 +00001353
aurel3226d67362008-10-21 11:31:27 +00001354#define GEN_LOGICAL1(name, tcg_op, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00001355static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00001356{ \
aurel3226d67362008-10-21 11:31:27 +00001357 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
j_mayer76a66252007-03-07 08:32:30 +00001358 if (unlikely(Rc(ctx->opcode) != 0)) \
aurel3226d67362008-10-21 11:31:27 +00001359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
bellard79aceca2003-11-23 14:55:54 +00001360}
1361
1362/* and & and. */
aurel3226d67362008-10-21 11:31:27 +00001363GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001364/* andc & andc. */
aurel3226d67362008-10-21 11:31:27 +00001365GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001366
Blue Swirl54623272009-06-17 15:22:19 +00001367/* andi. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001368static void gen_andi_(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001369{
aurel3226d67362008-10-21 11:31:27 +00001370 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001372}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001373
Blue Swirl54623272009-06-17 15:22:19 +00001374/* andis. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001375static void gen_andis_(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001376{
aurel3226d67362008-10-21 11:31:27 +00001377 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1378 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001379}
Blue Swirl99e300e2009-06-17 15:22:09 +00001380
Blue Swirl54623272009-06-17 15:22:19 +00001381/* cntlzw */
Blue Swirl99e300e2009-06-17 15:22:09 +00001382static void gen_cntlzw(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001383{
pbrooka7812ae2008-11-17 14:43:54 +00001384 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001385 if (unlikely(Rc(ctx->opcode) != 0))
pbrook2e31f5d2008-10-24 12:03:16 +00001386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001387}
bellard79aceca2003-11-23 14:55:54 +00001388/* eqv & eqv. */
aurel3226d67362008-10-21 11:31:27 +00001389GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001390/* extsb & extsb. */
aurel3226d67362008-10-21 11:31:27 +00001391GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001392/* extsh & extsh. */
aurel3226d67362008-10-21 11:31:27 +00001393GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001394/* nand & nand. */
aurel3226d67362008-10-21 11:31:27 +00001395GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00001396/* nor & nor. */
aurel3226d67362008-10-21 11:31:27 +00001397GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
Blue Swirl99e300e2009-06-17 15:22:09 +00001398
Blue Swirl54623272009-06-17 15:22:19 +00001399/* or & or. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001400static void gen_or(DisasContext *ctx)
bellard9a64fbe2004-01-04 22:58:38 +00001401{
j_mayer76a66252007-03-07 08:32:30 +00001402 int rs, ra, rb;
1403
1404 rs = rS(ctx->opcode);
1405 ra = rA(ctx->opcode);
1406 rb = rB(ctx->opcode);
1407 /* Optimisation for mr. ri case */
1408 if (rs != ra || rs != rb) {
aurel3226d67362008-10-21 11:31:27 +00001409 if (rs != rb)
1410 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1411 else
1412 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
j_mayer76a66252007-03-07 08:32:30 +00001413 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001414 gen_set_Rc0(ctx, cpu_gpr[ra]);
j_mayer76a66252007-03-07 08:32:30 +00001415 } else if (unlikely(Rc(ctx->opcode) != 0)) {
aurel3226d67362008-10-21 11:31:27 +00001416 gen_set_Rc0(ctx, cpu_gpr[rs]);
j_mayerc80f84e2007-09-30 01:18:26 +00001417#if defined(TARGET_PPC64)
1418 } else {
aurel3226d67362008-10-21 11:31:27 +00001419 int prio = 0;
1420
j_mayerc80f84e2007-09-30 01:18:26 +00001421 switch (rs) {
1422 case 1:
1423 /* Set process priority to low */
aurel3226d67362008-10-21 11:31:27 +00001424 prio = 2;
j_mayerc80f84e2007-09-30 01:18:26 +00001425 break;
1426 case 6:
1427 /* Set process priority to medium-low */
aurel3226d67362008-10-21 11:31:27 +00001428 prio = 3;
j_mayerc80f84e2007-09-30 01:18:26 +00001429 break;
1430 case 2:
1431 /* Set process priority to normal */
aurel3226d67362008-10-21 11:31:27 +00001432 prio = 4;
j_mayerc80f84e2007-09-30 01:18:26 +00001433 break;
j_mayerbe147d02007-09-30 13:03:23 +00001434#if !defined(CONFIG_USER_ONLY)
1435 case 31:
aurel3276db3ba2008-12-08 18:11:21 +00001436 if (ctx->mem_idx > 0) {
j_mayerbe147d02007-09-30 13:03:23 +00001437 /* Set process priority to very low */
aurel3226d67362008-10-21 11:31:27 +00001438 prio = 1;
j_mayerbe147d02007-09-30 13:03:23 +00001439 }
1440 break;
1441 case 5:
aurel3276db3ba2008-12-08 18:11:21 +00001442 if (ctx->mem_idx > 0) {
j_mayerbe147d02007-09-30 13:03:23 +00001443 /* Set process priority to medium-hight */
aurel3226d67362008-10-21 11:31:27 +00001444 prio = 5;
j_mayerbe147d02007-09-30 13:03:23 +00001445 }
1446 break;
1447 case 3:
aurel3276db3ba2008-12-08 18:11:21 +00001448 if (ctx->mem_idx > 0) {
j_mayerbe147d02007-09-30 13:03:23 +00001449 /* Set process priority to high */
aurel3226d67362008-10-21 11:31:27 +00001450 prio = 6;
j_mayerbe147d02007-09-30 13:03:23 +00001451 }
1452 break;
j_mayerbe147d02007-09-30 13:03:23 +00001453 case 7:
aurel3276db3ba2008-12-08 18:11:21 +00001454 if (ctx->mem_idx > 1) {
j_mayerbe147d02007-09-30 13:03:23 +00001455 /* Set process priority to very high */
aurel3226d67362008-10-21 11:31:27 +00001456 prio = 7;
j_mayerbe147d02007-09-30 13:03:23 +00001457 }
1458 break;
1459#endif
j_mayerc80f84e2007-09-30 01:18:26 +00001460 default:
1461 /* nop */
1462 break;
1463 }
aurel3226d67362008-10-21 11:31:27 +00001464 if (prio) {
pbrooka7812ae2008-11-17 14:43:54 +00001465 TCGv t0 = tcg_temp_new();
aurel3254cdcae2008-12-05 07:21:31 +00001466 gen_load_spr(t0, SPR_PPR);
aurel32ea363692008-10-27 22:50:39 +00001467 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1468 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
aurel3254cdcae2008-12-05 07:21:31 +00001469 gen_store_spr(SPR_PPR, t0);
aurel32ea363692008-10-27 22:50:39 +00001470 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001471 }
j_mayerc80f84e2007-09-30 01:18:26 +00001472#endif
bellard9a64fbe2004-01-04 22:58:38 +00001473 }
bellard9a64fbe2004-01-04 22:58:38 +00001474}
bellard79aceca2003-11-23 14:55:54 +00001475/* orc & orc. */
aurel3226d67362008-10-21 11:31:27 +00001476GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
Blue Swirl99e300e2009-06-17 15:22:09 +00001477
Blue Swirl54623272009-06-17 15:22:19 +00001478/* xor & xor. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001479static void gen_xor(DisasContext *ctx)
bellard9a64fbe2004-01-04 22:58:38 +00001480{
bellard9a64fbe2004-01-04 22:58:38 +00001481 /* Optimisation for "set to zero" case */
aurel3226d67362008-10-21 11:31:27 +00001482 if (rS(ctx->opcode) != rB(ctx->opcode))
aurel32312179c2008-10-27 22:50:31 +00001483 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001484 else
1485 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
j_mayer76a66252007-03-07 08:32:30 +00001486 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard9a64fbe2004-01-04 22:58:38 +00001488}
Blue Swirl99e300e2009-06-17 15:22:09 +00001489
Blue Swirl54623272009-06-17 15:22:19 +00001490/* ori */
Blue Swirl99e300e2009-06-17 15:22:09 +00001491static void gen_ori(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001492{
j_mayer76a66252007-03-07 08:32:30 +00001493 target_ulong uimm = UIMM(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00001494
bellard9a64fbe2004-01-04 22:58:38 +00001495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
j_mayer76a66252007-03-07 08:32:30 +00001497 /* XXX: should handle special NOPs for POWER series */
bellard9a64fbe2004-01-04 22:58:38 +00001498 return;
j_mayer76a66252007-03-07 08:32:30 +00001499 }
aurel3226d67362008-10-21 11:31:27 +00001500 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
bellard79aceca2003-11-23 14:55:54 +00001501}
Blue Swirl99e300e2009-06-17 15:22:09 +00001502
Blue Swirl54623272009-06-17 15:22:19 +00001503/* oris */
Blue Swirl99e300e2009-06-17 15:22:09 +00001504static void gen_oris(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001505{
j_mayer76a66252007-03-07 08:32:30 +00001506 target_ulong uimm = UIMM(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00001507
1508 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1509 /* NOP */
1510 return;
1511 }
aurel3226d67362008-10-21 11:31:27 +00001512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
j_mayer76a66252007-03-07 08:32:30 +00001513}
Blue Swirl99e300e2009-06-17 15:22:09 +00001514
Blue Swirl54623272009-06-17 15:22:19 +00001515/* xori */
Blue Swirl99e300e2009-06-17 15:22:09 +00001516static void gen_xori(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00001517{
1518 target_ulong uimm = UIMM(ctx->opcode);
1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
aurel3226d67362008-10-21 11:31:27 +00001524 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
bellard79aceca2003-11-23 14:55:54 +00001525}
Blue Swirl99e300e2009-06-17 15:22:09 +00001526
Blue Swirl54623272009-06-17 15:22:19 +00001527/* xoris */
Blue Swirl99e300e2009-06-17 15:22:09 +00001528static void gen_xoris(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001529{
j_mayer76a66252007-03-07 08:32:30 +00001530 target_ulong uimm = UIMM(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00001531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
aurel3226d67362008-10-21 11:31:27 +00001536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
bellard79aceca2003-11-23 14:55:54 +00001537}
Blue Swirl99e300e2009-06-17 15:22:09 +00001538
Blue Swirl54623272009-06-17 15:22:19 +00001539/* popcntb : PowerPC 2.03 specification */
Blue Swirl99e300e2009-06-17 15:22:09 +00001540static void gen_popcntb(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00001541{
David Gibsoneaabeef2011-04-01 15:15:13 +11001542 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001543}
1544
David Gibsoneaabeef2011-04-01 15:15:13 +11001545static void gen_popcntw(DisasContext *ctx)
1546{
1547 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1548}
1549
1550#if defined(TARGET_PPC64)
1551/* popcntd: PowerPC 2.06 specification */
1552static void gen_popcntd(DisasContext *ctx)
1553{
1554 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555}
1556#endif
1557
j_mayerd9bce9d2007-03-17 14:02:15 +00001558#if defined(TARGET_PPC64)
1559/* extsw & extsw. */
aurel3226d67362008-10-21 11:31:27 +00001560GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
Blue Swirl99e300e2009-06-17 15:22:09 +00001561
Blue Swirl54623272009-06-17 15:22:19 +00001562/* cntlzd */
Blue Swirl99e300e2009-06-17 15:22:09 +00001563static void gen_cntlzd(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001564{
pbrooka7812ae2008-11-17 14:43:54 +00001565 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001566 if (unlikely(Rc(ctx->opcode) != 0))
1567 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1568}
j_mayerd9bce9d2007-03-17 14:02:15 +00001569#endif
1570
bellard79aceca2003-11-23 14:55:54 +00001571/*** Integer rotate ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00001572
Blue Swirl54623272009-06-17 15:22:19 +00001573/* rlwimi & rlwimi. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001574static void gen_rlwimi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001575{
j_mayer76a66252007-03-07 08:32:30 +00001576 uint32_t mb, me, sh;
bellard79aceca2003-11-23 14:55:54 +00001577
1578 mb = MB(ctx->opcode);
1579 me = ME(ctx->opcode);
j_mayer76a66252007-03-07 08:32:30 +00001580 sh = SH(ctx->opcode);
aurel32d03ef512008-10-27 22:50:22 +00001581 if (likely(sh == 0 && mb == 0 && me == 31)) {
1582 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1583 } else {
aurel32d03ef512008-10-27 22:50:22 +00001584 target_ulong mask;
pbrooka7812ae2008-11-17 14:43:54 +00001585 TCGv t1;
1586 TCGv t0 = tcg_temp_new();
aurel3254843a52008-11-03 07:08:44 +00001587#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00001588 TCGv_i32 t2 = tcg_temp_new_i32();
1589 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1590 tcg_gen_rotli_i32(t2, t2, sh);
1591 tcg_gen_extu_i32_i64(t0, t2);
1592 tcg_temp_free_i32(t2);
aurel3254843a52008-11-03 07:08:44 +00001593#else
1594 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1595#endif
j_mayer76a66252007-03-07 08:32:30 +00001596#if defined(TARGET_PPC64)
aurel32d03ef512008-10-27 22:50:22 +00001597 mb += 32;
1598 me += 32;
j_mayer76a66252007-03-07 08:32:30 +00001599#endif
aurel32d03ef512008-10-27 22:50:22 +00001600 mask = MASK(mb, me);
pbrooka7812ae2008-11-17 14:43:54 +00001601 t1 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001602 tcg_gen_andi_tl(t0, t0, mask);
1603 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1604 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1605 tcg_temp_free(t0);
1606 tcg_temp_free(t1);
1607 }
j_mayer76a66252007-03-07 08:32:30 +00001608 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001609 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001610}
Blue Swirl99e300e2009-06-17 15:22:09 +00001611
Blue Swirl54623272009-06-17 15:22:19 +00001612/* rlwinm & rlwinm. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001613static void gen_rlwinm(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001614{
1615 uint32_t mb, me, sh;
ths3b46e622007-09-17 08:09:54 +00001616
bellard79aceca2003-11-23 14:55:54 +00001617 sh = SH(ctx->opcode);
1618 mb = MB(ctx->opcode);
1619 me = ME(ctx->opcode);
aurel32d03ef512008-10-27 22:50:22 +00001620
1621 if (likely(mb == 0 && me == (31 - sh))) {
1622 if (likely(sh == 0)) {
1623 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1624 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001625 TCGv t0 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001626 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1627 tcg_gen_shli_tl(t0, t0, sh);
1628 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1629 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00001630 }
aurel32d03ef512008-10-27 22:50:22 +00001631 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
pbrooka7812ae2008-11-17 14:43:54 +00001632 TCGv t0 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001633 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1634 tcg_gen_shri_tl(t0, t0, mb);
1635 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1636 tcg_temp_free(t0);
1637 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001638 TCGv t0 = tcg_temp_new();
aurel3254843a52008-11-03 07:08:44 +00001639#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00001640 TCGv_i32 t1 = tcg_temp_new_i32();
aurel3254843a52008-11-03 07:08:44 +00001641 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1642 tcg_gen_rotli_i32(t1, t1, sh);
1643 tcg_gen_extu_i32_i64(t0, t1);
pbrooka7812ae2008-11-17 14:43:54 +00001644 tcg_temp_free_i32(t1);
aurel3254843a52008-11-03 07:08:44 +00001645#else
1646 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1647#endif
j_mayer76a66252007-03-07 08:32:30 +00001648#if defined(TARGET_PPC64)
aurel32d03ef512008-10-27 22:50:22 +00001649 mb += 32;
1650 me += 32;
j_mayer76a66252007-03-07 08:32:30 +00001651#endif
aurel32d03ef512008-10-27 22:50:22 +00001652 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1653 tcg_temp_free(t0);
1654 }
j_mayer76a66252007-03-07 08:32:30 +00001655 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001656 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001657}
Blue Swirl99e300e2009-06-17 15:22:09 +00001658
Blue Swirl54623272009-06-17 15:22:19 +00001659/* rlwnm & rlwnm. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001660static void gen_rlwnm(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001661{
1662 uint32_t mb, me;
aurel3254843a52008-11-03 07:08:44 +00001663 TCGv t0;
1664#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00001665 TCGv_i32 t1, t2;
aurel3254843a52008-11-03 07:08:44 +00001666#endif
bellard79aceca2003-11-23 14:55:54 +00001667
1668 mb = MB(ctx->opcode);
1669 me = ME(ctx->opcode);
pbrooka7812ae2008-11-17 14:43:54 +00001670 t0 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001671 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
aurel3254843a52008-11-03 07:08:44 +00001672#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00001673 t1 = tcg_temp_new_i32();
1674 t2 = tcg_temp_new_i32();
aurel3254843a52008-11-03 07:08:44 +00001675 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1676 tcg_gen_trunc_i64_i32(t2, t0);
1677 tcg_gen_rotl_i32(t1, t1, t2);
1678 tcg_gen_extu_i32_i64(t0, t1);
pbrooka7812ae2008-11-17 14:43:54 +00001679 tcg_temp_free_i32(t1);
1680 tcg_temp_free_i32(t2);
aurel3254843a52008-11-03 07:08:44 +00001681#else
1682 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1683#endif
j_mayer76a66252007-03-07 08:32:30 +00001684 if (unlikely(mb != 0 || me != 31)) {
1685#if defined(TARGET_PPC64)
1686 mb += 32;
1687 me += 32;
1688#endif
aurel3254843a52008-11-03 07:08:44 +00001689 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
aurel32d03ef512008-10-27 22:50:22 +00001690 } else {
aurel3254843a52008-11-03 07:08:44 +00001691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
bellard79aceca2003-11-23 14:55:54 +00001692 }
aurel3254843a52008-11-03 07:08:44 +00001693 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00001694 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001695 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001696}
1697
j_mayerd9bce9d2007-03-17 14:02:15 +00001698#if defined(TARGET_PPC64)
1699#define GEN_PPC64_R2(name, opc1, opc2) \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001700static void glue(gen_, name##0)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001701{ \
1702 gen_##name(ctx, 0); \
1703} \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001704 \
1705static void glue(gen_, name##1)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001706{ \
1707 gen_##name(ctx, 1); \
1708}
1709#define GEN_PPC64_R4(name, opc1, opc2) \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001710static void glue(gen_, name##0)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001711{ \
1712 gen_##name(ctx, 0, 0); \
1713} \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001714 \
1715static void glue(gen_, name##1)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001716{ \
1717 gen_##name(ctx, 0, 1); \
1718} \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001719 \
1720static void glue(gen_, name##2)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001721{ \
1722 gen_##name(ctx, 1, 0); \
1723} \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001724 \
1725static void glue(gen_, name##3)(DisasContext *ctx) \
j_mayerd9bce9d2007-03-17 14:02:15 +00001726{ \
1727 gen_##name(ctx, 1, 1); \
1728}
j_mayer51789c42007-03-22 22:41:50 +00001729
Blue Swirl636aa202009-08-16 09:06:54 +00001730static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1731 uint32_t sh)
j_mayer51789c42007-03-22 22:41:50 +00001732{
aurel32d03ef512008-10-27 22:50:22 +00001733 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1734 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1735 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1736 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1737 } else {
pbrooka7812ae2008-11-17 14:43:54 +00001738 TCGv t0 = tcg_temp_new();
aurel3254843a52008-11-03 07:08:44 +00001739 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
aurel32d03ef512008-10-27 22:50:22 +00001740 if (likely(mb == 0 && me == 63)) {
aurel3254843a52008-11-03 07:08:44 +00001741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
aurel32d03ef512008-10-27 22:50:22 +00001742 } else {
1743 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
j_mayer51789c42007-03-22 22:41:50 +00001744 }
aurel32d03ef512008-10-27 22:50:22 +00001745 tcg_temp_free(t0);
j_mayer51789c42007-03-22 22:41:50 +00001746 }
j_mayer51789c42007-03-22 22:41:50 +00001747 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001748 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer51789c42007-03-22 22:41:50 +00001749}
j_mayerd9bce9d2007-03-17 14:02:15 +00001750/* rldicl - rldicl. */
Blue Swirl636aa202009-08-16 09:06:54 +00001751static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001752{
j_mayer51789c42007-03-22 22:41:50 +00001753 uint32_t sh, mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001754
j_mayer9d53c752007-04-06 07:59:47 +00001755 sh = SH(ctx->opcode) | (shn << 5);
1756 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001757 gen_rldinm(ctx, mb, 63, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001758}
j_mayer51789c42007-03-22 22:41:50 +00001759GEN_PPC64_R4(rldicl, 0x1E, 0x00);
j_mayerd9bce9d2007-03-17 14:02:15 +00001760/* rldicr - rldicr. */
Blue Swirl636aa202009-08-16 09:06:54 +00001761static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001762{
j_mayer51789c42007-03-22 22:41:50 +00001763 uint32_t sh, me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001764
j_mayer9d53c752007-04-06 07:59:47 +00001765 sh = SH(ctx->opcode) | (shn << 5);
1766 me = MB(ctx->opcode) | (men << 5);
j_mayer51789c42007-03-22 22:41:50 +00001767 gen_rldinm(ctx, 0, me, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001768}
j_mayer51789c42007-03-22 22:41:50 +00001769GEN_PPC64_R4(rldicr, 0x1E, 0x02);
j_mayerd9bce9d2007-03-17 14:02:15 +00001770/* rldic - rldic. */
Blue Swirl636aa202009-08-16 09:06:54 +00001771static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001772{
j_mayer51789c42007-03-22 22:41:50 +00001773 uint32_t sh, mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001774
j_mayer9d53c752007-04-06 07:59:47 +00001775 sh = SH(ctx->opcode) | (shn << 5);
1776 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001777 gen_rldinm(ctx, mb, 63 - sh, sh);
j_mayerd9bce9d2007-03-17 14:02:15 +00001778}
j_mayer51789c42007-03-22 22:41:50 +00001779GEN_PPC64_R4(rldic, 0x1E, 0x04);
1780
Blue Swirl636aa202009-08-16 09:06:54 +00001781static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
j_mayer51789c42007-03-22 22:41:50 +00001782{
aurel3254843a52008-11-03 07:08:44 +00001783 TCGv t0;
aurel32d03ef512008-10-27 22:50:22 +00001784
1785 mb = MB(ctx->opcode);
1786 me = ME(ctx->opcode);
pbrooka7812ae2008-11-17 14:43:54 +00001787 t0 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
aurel3254843a52008-11-03 07:08:44 +00001789 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
j_mayer51789c42007-03-22 22:41:50 +00001790 if (unlikely(mb != 0 || me != 63)) {
aurel3254843a52008-11-03 07:08:44 +00001791 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1792 } else {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 }
1795 tcg_temp_free(t0);
j_mayer51789c42007-03-22 22:41:50 +00001796 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer51789c42007-03-22 22:41:50 +00001798}
1799
j_mayerd9bce9d2007-03-17 14:02:15 +00001800/* rldcl - rldcl. */
Blue Swirl636aa202009-08-16 09:06:54 +00001801static inline void gen_rldcl(DisasContext *ctx, int mbn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001802{
j_mayer51789c42007-03-22 22:41:50 +00001803 uint32_t mb;
j_mayerd9bce9d2007-03-17 14:02:15 +00001804
j_mayer9d53c752007-04-06 07:59:47 +00001805 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer51789c42007-03-22 22:41:50 +00001806 gen_rldnm(ctx, mb, 63);
j_mayerd9bce9d2007-03-17 14:02:15 +00001807}
j_mayer36081602007-09-17 08:21:54 +00001808GEN_PPC64_R2(rldcl, 0x1E, 0x08);
j_mayerd9bce9d2007-03-17 14:02:15 +00001809/* rldcr - rldcr. */
Blue Swirl636aa202009-08-16 09:06:54 +00001810static inline void gen_rldcr(DisasContext *ctx, int men)
j_mayerd9bce9d2007-03-17 14:02:15 +00001811{
j_mayer51789c42007-03-22 22:41:50 +00001812 uint32_t me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001813
j_mayer9d53c752007-04-06 07:59:47 +00001814 me = MB(ctx->opcode) | (men << 5);
j_mayer51789c42007-03-22 22:41:50 +00001815 gen_rldnm(ctx, 0, me);
j_mayerd9bce9d2007-03-17 14:02:15 +00001816}
j_mayer36081602007-09-17 08:21:54 +00001817GEN_PPC64_R2(rldcr, 0x1E, 0x09);
j_mayerd9bce9d2007-03-17 14:02:15 +00001818/* rldimi - rldimi. */
Blue Swirl636aa202009-08-16 09:06:54 +00001819static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
j_mayerd9bce9d2007-03-17 14:02:15 +00001820{
j_mayer271a9162007-11-14 05:26:46 +00001821 uint32_t sh, mb, me;
j_mayerd9bce9d2007-03-17 14:02:15 +00001822
j_mayer9d53c752007-04-06 07:59:47 +00001823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
j_mayer271a9162007-11-14 05:26:46 +00001825 me = 63 - sh;
aurel32d03ef512008-10-27 22:50:22 +00001826 if (unlikely(sh == 0 && mb == 0)) {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 } else {
1829 TCGv t0, t1;
1830 target_ulong mask;
1831
pbrooka7812ae2008-11-17 14:43:54 +00001832 t0 = tcg_temp_new();
aurel3254843a52008-11-03 07:08:44 +00001833 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
pbrooka7812ae2008-11-17 14:43:54 +00001834 t1 = tcg_temp_new();
aurel32d03ef512008-10-27 22:50:22 +00001835 mask = MASK(mb, me);
1836 tcg_gen_andi_tl(t0, t0, mask);
1837 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1839 tcg_temp_free(t0);
1840 tcg_temp_free(t1);
j_mayer51789c42007-03-22 22:41:50 +00001841 }
j_mayer51789c42007-03-22 22:41:50 +00001842 if (unlikely(Rc(ctx->opcode) != 0))
aurel32d03ef512008-10-27 22:50:22 +00001843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001844}
j_mayer36081602007-09-17 08:21:54 +00001845GEN_PPC64_R4(rldimi, 0x1E, 0x06);
j_mayerd9bce9d2007-03-17 14:02:15 +00001846#endif
1847
bellard79aceca2003-11-23 14:55:54 +00001848/*** Integer shift ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00001849
Blue Swirl54623272009-06-17 15:22:19 +00001850/* slw & slw. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001851static void gen_slw(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001852{
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001853 TCGv t0, t1;
aurel3226d67362008-10-21 11:31:27 +00001854
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001855 t0 = tcg_temp_new();
1856 /* AND rS with a mask that is 0 when rB >= 0x20 */
1857#if defined(TARGET_PPC64)
1858 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859 tcg_gen_sari_tl(t0, t0, 0x3f);
1860#else
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862 tcg_gen_sari_tl(t0, t0, 0x1f);
1863#endif
1864 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865 t1 = tcg_temp_new();
1866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1867 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1868 tcg_temp_free(t1);
aurel32fea0c502008-11-02 08:22:34 +00001869 tcg_temp_free(t0);
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001870 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873}
Blue Swirl99e300e2009-06-17 15:22:09 +00001874
Blue Swirl54623272009-06-17 15:22:19 +00001875/* sraw & sraw. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001876static void gen_sraw(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001877{
pbrooka7812ae2008-11-17 14:43:54 +00001878 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1879 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882}
Blue Swirl99e300e2009-06-17 15:22:09 +00001883
Blue Swirl54623272009-06-17 15:22:19 +00001884/* srawi & srawi. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001885static void gen_srawi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00001886{
aurel3226d67362008-10-21 11:31:27 +00001887 int sh = SH(ctx->opcode);
1888 if (sh != 0) {
1889 int l1, l2;
aurel32fea0c502008-11-02 08:22:34 +00001890 TCGv t0;
aurel3226d67362008-10-21 11:31:27 +00001891 l1 = gen_new_label();
1892 l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00001893 t0 = tcg_temp_local_new();
aurel32fea0c502008-11-02 08:22:34 +00001894 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1895 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1896 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1897 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
aurel32269f3e92008-11-01 00:53:48 +00001898 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +00001899 tcg_gen_br(l2);
1900 gen_set_label(l1);
aurel32269f3e92008-11-01 00:53:48 +00001901 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
aurel3226d67362008-10-21 11:31:27 +00001902 gen_set_label(l2);
aurel32fea0c502008-11-02 08:22:34 +00001903 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1904 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1905 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001906 } else {
1907 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel32269f3e92008-11-01 00:53:48 +00001908 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001909 }
j_mayer76a66252007-03-07 08:32:30 +00001910 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001911 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00001912}
Blue Swirl99e300e2009-06-17 15:22:09 +00001913
Blue Swirl54623272009-06-17 15:22:19 +00001914/* srw & srw. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001915static void gen_srw(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001916{
aurel32fea0c502008-11-02 08:22:34 +00001917 TCGv t0, t1;
j_mayerd9bce9d2007-03-17 14:02:15 +00001918
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001919 t0 = tcg_temp_new();
1920 /* AND rS with a mask that is 0 when rB >= 0x20 */
1921#if defined(TARGET_PPC64)
1922 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1923 tcg_gen_sari_tl(t0, t0, 0x3f);
1924#else
1925 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1926 tcg_gen_sari_tl(t0, t0, 0x1f);
1927#endif
1928 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1929 tcg_gen_ext32u_tl(t0, t0);
pbrooka7812ae2008-11-17 14:43:54 +00001930 t1 = tcg_temp_new();
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001931 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1932 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
aurel32fea0c502008-11-02 08:22:34 +00001933 tcg_temp_free(t1);
aurel32fea0c502008-11-02 08:22:34 +00001934 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001935 if (unlikely(Rc(ctx->opcode) != 0))
1936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1937}
Blue Swirl54623272009-06-17 15:22:19 +00001938
j_mayerd9bce9d2007-03-17 14:02:15 +00001939#if defined(TARGET_PPC64)
1940/* sld & sld. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001941static void gen_sld(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001942{
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001943 TCGv t0, t1;
aurel3226d67362008-10-21 11:31:27 +00001944
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02001945 t0 = tcg_temp_new();
1946 /* AND rS with a mask that is 0 when rB >= 0x40 */
1947 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1948 tcg_gen_sari_tl(t0, t0, 0x3f);
1949 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1950 t1 = tcg_temp_new();
1951 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1952 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1953 tcg_temp_free(t1);
aurel32fea0c502008-11-02 08:22:34 +00001954 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957}
Blue Swirl99e300e2009-06-17 15:22:09 +00001958
Blue Swirl54623272009-06-17 15:22:19 +00001959/* srad & srad. */
Blue Swirl99e300e2009-06-17 15:22:09 +00001960static void gen_srad(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00001961{
pbrooka7812ae2008-11-17 14:43:54 +00001962 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
1963 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3226d67362008-10-21 11:31:27 +00001964 if (unlikely(Rc(ctx->opcode) != 0))
1965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1966}
j_mayerd9bce9d2007-03-17 14:02:15 +00001967/* sradi & sradi. */
Blue Swirl636aa202009-08-16 09:06:54 +00001968static inline void gen_sradi(DisasContext *ctx, int n)
j_mayerd9bce9d2007-03-17 14:02:15 +00001969{
aurel3226d67362008-10-21 11:31:27 +00001970 int sh = SH(ctx->opcode) + (n << 5);
j_mayerd9bce9d2007-03-17 14:02:15 +00001971 if (sh != 0) {
aurel3226d67362008-10-21 11:31:27 +00001972 int l1, l2;
aurel32fea0c502008-11-02 08:22:34 +00001973 TCGv t0;
aurel3226d67362008-10-21 11:31:27 +00001974 l1 = gen_new_label();
1975 l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00001976 t0 = tcg_temp_local_new();
aurel3226d67362008-10-21 11:31:27 +00001977 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
aurel32fea0c502008-11-02 08:22:34 +00001978 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1979 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
aurel32269f3e92008-11-01 00:53:48 +00001980 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +00001981 tcg_gen_br(l2);
1982 gen_set_label(l1);
aurel32269f3e92008-11-01 00:53:48 +00001983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
aurel3226d67362008-10-21 11:31:27 +00001984 gen_set_label(l2);
aurel32a9730012008-11-09 17:27:36 +00001985 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00001986 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1987 } else {
1988 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
aurel32269f3e92008-11-01 00:53:48 +00001989 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
j_mayerd9bce9d2007-03-17 14:02:15 +00001990 }
j_mayerd9bce9d2007-03-17 14:02:15 +00001991 if (unlikely(Rc(ctx->opcode) != 0))
aurel3226d67362008-10-21 11:31:27 +00001992 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00001993}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001994
1995static void gen_sradi0(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00001996{
1997 gen_sradi(ctx, 0);
1998}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00001999
2000static void gen_sradi1(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00002001{
2002 gen_sradi(ctx, 1);
2003}
Blue Swirl99e300e2009-06-17 15:22:09 +00002004
Blue Swirl54623272009-06-17 15:22:19 +00002005/* srd & srd. */
Blue Swirl99e300e2009-06-17 15:22:09 +00002006static void gen_srd(DisasContext *ctx)
aurel3226d67362008-10-21 11:31:27 +00002007{
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02002008 TCGv t0, t1;
aurel3226d67362008-10-21 11:31:27 +00002009
Aurelien Jarno7fd6bf72009-09-18 16:56:30 +02002010 t0 = tcg_temp_new();
2011 /* AND rS with a mask that is 0 when rB >= 0x40 */
2012 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2013 tcg_gen_sari_tl(t0, t0, 0x3f);
2014 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2015 t1 = tcg_temp_new();
2016 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2017 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2018 tcg_temp_free(t1);
aurel32fea0c502008-11-02 08:22:34 +00002019 tcg_temp_free(t0);
aurel3226d67362008-10-21 11:31:27 +00002020 if (unlikely(Rc(ctx->opcode) != 0))
2021 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2022}
j_mayerd9bce9d2007-03-17 14:02:15 +00002023#endif
bellard79aceca2003-11-23 14:55:54 +00002024
2025/*** Floating-Point arithmetic ***/
j_mayer7c580442007-10-27 17:54:30 +00002026#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002027static void gen_f##name(DisasContext *ctx) \
bellard9a64fbe2004-01-04 22:58:38 +00002028{ \
j_mayer76a66252007-03-07 08:32:30 +00002029 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002030 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard3cc62372005-02-15 23:06:19 +00002031 return; \
2032 } \
aurel32eb44b952008-12-15 17:13:39 +00002033 /* NIP cannot be restored if the memory exception comes from an helper */ \
2034 gen_update_nip(ctx, ctx->nip - 4); \
j_mayer7c580442007-10-27 17:54:30 +00002035 gen_reset_fpstatus(); \
aurel32af129062008-11-19 16:10:23 +00002036 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2037 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002038 if (isfloat) { \
aurel32af129062008-11-19 16:10:23 +00002039 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002040 } \
aurel32af129062008-11-19 16:10:23 +00002041 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2042 Rc(ctx->opcode) != 0); \
bellard79aceca2003-11-23 14:55:54 +00002043}
2044
j_mayer7c580442007-10-27 17:54:30 +00002045#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2046_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2047_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00002048
j_mayer7c580442007-10-27 17:54:30 +00002049#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002050static void gen_f##name(DisasContext *ctx) \
bellard9a64fbe2004-01-04 22:58:38 +00002051{ \
j_mayer76a66252007-03-07 08:32:30 +00002052 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002053 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard3cc62372005-02-15 23:06:19 +00002054 return; \
2055 } \
aurel32eb44b952008-12-15 17:13:39 +00002056 /* NIP cannot be restored if the memory exception comes from an helper */ \
2057 gen_update_nip(ctx, ctx->nip - 4); \
j_mayer7c580442007-10-27 17:54:30 +00002058 gen_reset_fpstatus(); \
aurel32af129062008-11-19 16:10:23 +00002059 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2060 cpu_fpr[rB(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002061 if (isfloat) { \
aurel32af129062008-11-19 16:10:23 +00002062 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002063 } \
aurel32af129062008-11-19 16:10:23 +00002064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2065 set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00002066}
j_mayer7c580442007-10-27 17:54:30 +00002067#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2068_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2069_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00002070
j_mayer7c580442007-10-27 17:54:30 +00002071#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002072static void gen_f##name(DisasContext *ctx) \
bellard9a64fbe2004-01-04 22:58:38 +00002073{ \
j_mayer76a66252007-03-07 08:32:30 +00002074 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002075 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard3cc62372005-02-15 23:06:19 +00002076 return; \
2077 } \
aurel32eb44b952008-12-15 17:13:39 +00002078 /* NIP cannot be restored if the memory exception comes from an helper */ \
2079 gen_update_nip(ctx, ctx->nip - 4); \
j_mayer7c580442007-10-27 17:54:30 +00002080 gen_reset_fpstatus(); \
aurel32af129062008-11-19 16:10:23 +00002081 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2082 cpu_fpr[rC(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002083 if (isfloat) { \
aurel32af129062008-11-19 16:10:23 +00002084 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
bellard4ecc3192005-03-13 17:01:22 +00002085 } \
aurel32af129062008-11-19 16:10:23 +00002086 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2087 set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00002088}
j_mayer7c580442007-10-27 17:54:30 +00002089#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2090_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2091_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
bellard9a64fbe2004-01-04 22:58:38 +00002092
j_mayer7c580442007-10-27 17:54:30 +00002093#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002094static void gen_f##name(DisasContext *ctx) \
bellard9a64fbe2004-01-04 22:58:38 +00002095{ \
j_mayer76a66252007-03-07 08:32:30 +00002096 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002097 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard3cc62372005-02-15 23:06:19 +00002098 return; \
2099 } \
aurel32eb44b952008-12-15 17:13:39 +00002100 /* NIP cannot be restored if the memory exception comes from an helper */ \
2101 gen_update_nip(ctx, ctx->nip - 4); \
j_mayer7c580442007-10-27 17:54:30 +00002102 gen_reset_fpstatus(); \
aurel32af129062008-11-19 16:10:23 +00002103 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2104 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2105 set_fprf, Rc(ctx->opcode) != 0); \
bellard79aceca2003-11-23 14:55:54 +00002106}
2107
j_mayer7c580442007-10-27 17:54:30 +00002108#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002109static void gen_f##name(DisasContext *ctx) \
bellard9a64fbe2004-01-04 22:58:38 +00002110{ \
j_mayer76a66252007-03-07 08:32:30 +00002111 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002112 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard3cc62372005-02-15 23:06:19 +00002113 return; \
2114 } \
aurel32eb44b952008-12-15 17:13:39 +00002115 /* NIP cannot be restored if the memory exception comes from an helper */ \
2116 gen_update_nip(ctx, ctx->nip - 4); \
j_mayer7c580442007-10-27 17:54:30 +00002117 gen_reset_fpstatus(); \
aurel32af129062008-11-19 16:10:23 +00002118 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2119 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2120 set_fprf, Rc(ctx->opcode) != 0); \
bellard9a64fbe2004-01-04 22:58:38 +00002121}
2122
2123/* fadd - fadds */
j_mayer7c580442007-10-27 17:54:30 +00002124GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002125/* fdiv - fdivs */
j_mayer7c580442007-10-27 17:54:30 +00002126GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002127/* fmul - fmuls */
j_mayer7c580442007-10-27 17:54:30 +00002128GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002129
j_mayerd7e4b872007-09-30 01:11:48 +00002130/* fre */
j_mayer7c580442007-10-27 17:54:30 +00002131GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002132
j_mayera750fc02007-09-26 23:54:22 +00002133/* fres */
j_mayer7c580442007-10-27 17:54:30 +00002134GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
bellard79aceca2003-11-23 14:55:54 +00002135
j_mayera750fc02007-09-26 23:54:22 +00002136/* frsqrte */
j_mayer7c580442007-10-27 17:54:30 +00002137GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2138
2139/* frsqrtes */
Blue Swirl99e300e2009-06-17 15:22:09 +00002140static void gen_frsqrtes(DisasContext *ctx)
j_mayer7c580442007-10-27 17:54:30 +00002141{
aurel32af129062008-11-19 16:10:23 +00002142 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002143 gen_exception(ctx, POWERPC_EXCP_FPU);
aurel32af129062008-11-19 16:10:23 +00002144 return;
2145 }
aurel32eb44b952008-12-15 17:13:39 +00002146 /* NIP cannot be restored if the memory exception comes from an helper */
2147 gen_update_nip(ctx, ctx->nip - 4);
aurel32af129062008-11-19 16:10:23 +00002148 gen_reset_fpstatus();
2149 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2151 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
j_mayer7c580442007-10-27 17:54:30 +00002152}
bellard79aceca2003-11-23 14:55:54 +00002153
j_mayera750fc02007-09-26 23:54:22 +00002154/* fsel */
j_mayer7c580442007-10-27 17:54:30 +00002155_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
bellard4ecc3192005-03-13 17:01:22 +00002156/* fsub - fsubs */
j_mayer7c580442007-10-27 17:54:30 +00002157GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002158/* Optional: */
Blue Swirl99e300e2009-06-17 15:22:09 +00002159
Blue Swirl54623272009-06-17 15:22:19 +00002160/* fsqrt */
Blue Swirl99e300e2009-06-17 15:22:09 +00002161static void gen_fsqrt(DisasContext *ctx)
bellardc7d344a2005-04-23 18:05:46 +00002162{
j_mayer76a66252007-03-07 08:32:30 +00002163 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002164 gen_exception(ctx, POWERPC_EXCP_FPU);
bellardc7d344a2005-04-23 18:05:46 +00002165 return;
2166 }
aurel32eb44b952008-12-15 17:13:39 +00002167 /* NIP cannot be restored if the memory exception comes from an helper */
2168 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002169 gen_reset_fpstatus();
aurel32af129062008-11-19 16:10:23 +00002170 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2171 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
bellardc7d344a2005-04-23 18:05:46 +00002172}
bellard79aceca2003-11-23 14:55:54 +00002173
Blue Swirl99e300e2009-06-17 15:22:09 +00002174static void gen_fsqrts(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002175{
j_mayer76a66252007-03-07 08:32:30 +00002176 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002177 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002178 return;
2179 }
aurel32eb44b952008-12-15 17:13:39 +00002180 /* NIP cannot be restored if the memory exception comes from an helper */
2181 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002182 gen_reset_fpstatus();
aurel32af129062008-11-19 16:10:23 +00002183 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2184 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
bellard79aceca2003-11-23 14:55:54 +00002186}
2187
2188/*** Floating-Point multiply-and-add ***/
bellard4ecc3192005-03-13 17:01:22 +00002189/* fmadd - fmadds */
j_mayer7c580442007-10-27 17:54:30 +00002190GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002191/* fmsub - fmsubs */
j_mayer7c580442007-10-27 17:54:30 +00002192GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002193/* fnmadd - fnmadds */
j_mayer7c580442007-10-27 17:54:30 +00002194GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
bellard4ecc3192005-03-13 17:01:22 +00002195/* fnmsub - fnmsubs */
j_mayer7c580442007-10-27 17:54:30 +00002196GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002197
2198/*** Floating-Point round & convert ***/
2199/* fctiw */
j_mayer7c580442007-10-27 17:54:30 +00002200GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002201/* fctiwz */
j_mayer7c580442007-10-27 17:54:30 +00002202GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00002203/* frsp */
j_mayer7c580442007-10-27 17:54:30 +00002204GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
j_mayer426613d2007-03-23 09:45:27 +00002205#if defined(TARGET_PPC64)
2206/* fcfid */
j_mayer7c580442007-10-27 17:54:30 +00002207GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002208/* fctid */
j_mayer7c580442007-10-27 17:54:30 +00002209GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002210/* fctidz */
j_mayer7c580442007-10-27 17:54:30 +00002211GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
j_mayer426613d2007-03-23 09:45:27 +00002212#endif
bellard79aceca2003-11-23 14:55:54 +00002213
j_mayerd7e4b872007-09-30 01:11:48 +00002214/* frin */
j_mayer7c580442007-10-27 17:54:30 +00002215GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002216/* friz */
j_mayer7c580442007-10-27 17:54:30 +00002217GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002218/* frip */
j_mayer7c580442007-10-27 17:54:30 +00002219GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002220/* frim */
j_mayer7c580442007-10-27 17:54:30 +00002221GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
j_mayerd7e4b872007-09-30 01:11:48 +00002222
bellard79aceca2003-11-23 14:55:54 +00002223/*** Floating-Point compare ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00002224
Blue Swirl54623272009-06-17 15:22:19 +00002225/* fcmpo */
Blue Swirl99e300e2009-06-17 15:22:09 +00002226static void gen_fcmpo(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002227{
aurel32330c4832008-12-15 17:13:31 +00002228 TCGv_i32 crf;
j_mayer76a66252007-03-07 08:32:30 +00002229 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002230 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002231 return;
2232 }
aurel32eb44b952008-12-15 17:13:39 +00002233 /* NIP cannot be restored if the memory exception comes from an helper */
2234 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002235 gen_reset_fpstatus();
aurel329a819372008-12-14 19:34:09 +00002236 crf = tcg_const_i32(crfD(ctx->opcode));
2237 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
aurel32330c4832008-12-15 17:13:31 +00002238 tcg_temp_free_i32(crf);
aurel32af129062008-11-19 16:10:23 +00002239 gen_helper_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002240}
2241
2242/* fcmpu */
Blue Swirl99e300e2009-06-17 15:22:09 +00002243static void gen_fcmpu(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002244{
aurel32330c4832008-12-15 17:13:31 +00002245 TCGv_i32 crf;
j_mayer76a66252007-03-07 08:32:30 +00002246 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002247 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002248 return;
2249 }
aurel32eb44b952008-12-15 17:13:39 +00002250 /* NIP cannot be restored if the memory exception comes from an helper */
2251 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002252 gen_reset_fpstatus();
aurel329a819372008-12-14 19:34:09 +00002253 crf = tcg_const_i32(crfD(ctx->opcode));
2254 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
aurel32330c4832008-12-15 17:13:31 +00002255 tcg_temp_free_i32(crf);
aurel32af129062008-11-19 16:10:23 +00002256 gen_helper_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002257}
2258
bellard9a64fbe2004-01-04 22:58:38 +00002259/*** Floating-point move ***/
2260/* fabs */
j_mayer7c580442007-10-27 17:54:30 +00002261/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2262GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002263
2264/* fmr - fmr. */
j_mayer7c580442007-10-27 17:54:30 +00002265/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
Blue Swirl99e300e2009-06-17 15:22:09 +00002266static void gen_fmr(DisasContext *ctx)
bellard9a64fbe2004-01-04 22:58:38 +00002267{
j_mayer76a66252007-03-07 08:32:30 +00002268 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002269 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002270 return;
2271 }
aurel32af129062008-11-19 16:10:23 +00002272 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2273 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
bellard9a64fbe2004-01-04 22:58:38 +00002274}
2275
2276/* fnabs */
j_mayer7c580442007-10-27 17:54:30 +00002277/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2278GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002279/* fneg */
j_mayer7c580442007-10-27 17:54:30 +00002280/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2281GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
bellard9a64fbe2004-01-04 22:58:38 +00002282
bellard79aceca2003-11-23 14:55:54 +00002283/*** Floating-Point status & ctrl register ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00002284
Blue Swirl54623272009-06-17 15:22:19 +00002285/* mcrfs */
Blue Swirl99e300e2009-06-17 15:22:09 +00002286static void gen_mcrfs(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002287{
j_mayer7c580442007-10-27 17:54:30 +00002288 int bfa;
2289
j_mayer76a66252007-03-07 08:32:30 +00002290 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002291 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002292 return;
2293 }
j_mayer7c580442007-10-27 17:54:30 +00002294 bfa = 4 * (7 - crfS(ctx->opcode));
aurel32e1571902008-10-21 11:31:14 +00002295 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2296 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
aurel32af129062008-11-19 16:10:23 +00002297 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
bellard79aceca2003-11-23 14:55:54 +00002298}
2299
2300/* mffs */
Blue Swirl99e300e2009-06-17 15:22:09 +00002301static void gen_mffs(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002302{
j_mayer76a66252007-03-07 08:32:30 +00002303 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002304 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002305 return;
2306 }
j_mayer7c580442007-10-27 17:54:30 +00002307 gen_reset_fpstatus();
aurel32af129062008-11-19 16:10:23 +00002308 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2309 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
bellard79aceca2003-11-23 14:55:54 +00002310}
2311
2312/* mtfsb0 */
Blue Swirl99e300e2009-06-17 15:22:09 +00002313static void gen_mtfsb0(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002314{
bellardfb0eaff2004-01-04 14:57:11 +00002315 uint8_t crb;
ths3b46e622007-09-17 08:09:54 +00002316
j_mayer76a66252007-03-07 08:32:30 +00002317 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002318 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002319 return;
2320 }
aurel326e35d522008-12-14 18:40:58 +00002321 crb = 31 - crbD(ctx->opcode);
j_mayer7c580442007-10-27 17:54:30 +00002322 gen_reset_fpstatus();
aurel326e35d522008-12-14 18:40:58 +00002323 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
aurel32eb44b952008-12-15 17:13:39 +00002324 TCGv_i32 t0;
2325 /* NIP cannot be restored if the memory exception comes from an helper */
2326 gen_update_nip(ctx, ctx->nip - 4);
2327 t0 = tcg_const_i32(crb);
aurel326e35d522008-12-14 18:40:58 +00002328 gen_helper_fpscr_clrbit(t0);
2329 tcg_temp_free_i32(t0);
2330 }
j_mayer7c580442007-10-27 17:54:30 +00002331 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002332 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002333 }
bellard79aceca2003-11-23 14:55:54 +00002334}
2335
2336/* mtfsb1 */
Blue Swirl99e300e2009-06-17 15:22:09 +00002337static void gen_mtfsb1(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002338{
bellardfb0eaff2004-01-04 14:57:11 +00002339 uint8_t crb;
ths3b46e622007-09-17 08:09:54 +00002340
j_mayer76a66252007-03-07 08:32:30 +00002341 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002342 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002343 return;
2344 }
aurel326e35d522008-12-14 18:40:58 +00002345 crb = 31 - crbD(ctx->opcode);
j_mayer7c580442007-10-27 17:54:30 +00002346 gen_reset_fpstatus();
2347 /* XXX: we pretend we can only do IEEE floating-point computations */
aurel32af129062008-11-19 16:10:23 +00002348 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
aurel32eb44b952008-12-15 17:13:39 +00002349 TCGv_i32 t0;
2350 /* NIP cannot be restored if the memory exception comes from an helper */
2351 gen_update_nip(ctx, ctx->nip - 4);
2352 t0 = tcg_const_i32(crb);
aurel32af129062008-11-19 16:10:23 +00002353 gen_helper_fpscr_setbit(t0);
aurel320f2f39c2008-11-19 17:54:49 +00002354 tcg_temp_free_i32(t0);
aurel32af129062008-11-19 16:10:23 +00002355 }
j_mayer7c580442007-10-27 17:54:30 +00002356 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002357 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002358 }
2359 /* We can raise a differed exception */
aurel32af129062008-11-19 16:10:23 +00002360 gen_helper_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002361}
2362
2363/* mtfsf */
Blue Swirl99e300e2009-06-17 15:22:09 +00002364static void gen_mtfsf(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002365{
aurel320f2f39c2008-11-19 17:54:49 +00002366 TCGv_i32 t0;
blueswir149110122009-03-07 20:55:31 +00002367 int L = ctx->opcode & 0x02000000;
aurel32af129062008-11-19 16:10:23 +00002368
j_mayer76a66252007-03-07 08:32:30 +00002369 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002370 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002371 return;
2372 }
aurel32eb44b952008-12-15 17:13:39 +00002373 /* NIP cannot be restored if the memory exception comes from an helper */
2374 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002375 gen_reset_fpstatus();
blueswir149110122009-03-07 20:55:31 +00002376 if (L)
2377 t0 = tcg_const_i32(0xff);
2378 else
2379 t0 = tcg_const_i32(FM(ctx->opcode));
aurel32af129062008-11-19 16:10:23 +00002380 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
aurel320f2f39c2008-11-19 17:54:49 +00002381 tcg_temp_free_i32(t0);
j_mayer7c580442007-10-27 17:54:30 +00002382 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002383 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002384 }
2385 /* We can raise a differed exception */
aurel32af129062008-11-19 16:10:23 +00002386 gen_helper_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002387}
2388
2389/* mtfsfi */
Blue Swirl99e300e2009-06-17 15:22:09 +00002390static void gen_mtfsfi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002391{
j_mayer7c580442007-10-27 17:54:30 +00002392 int bf, sh;
aurel320f2f39c2008-11-19 17:54:49 +00002393 TCGv_i64 t0;
2394 TCGv_i32 t1;
j_mayer7c580442007-10-27 17:54:30 +00002395
j_mayer76a66252007-03-07 08:32:30 +00002396 if (unlikely(!ctx->fpu_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00002397 gen_exception(ctx, POWERPC_EXCP_FPU);
bellard3cc62372005-02-15 23:06:19 +00002398 return;
2399 }
j_mayer7c580442007-10-27 17:54:30 +00002400 bf = crbD(ctx->opcode) >> 2;
2401 sh = 7 - bf;
aurel32eb44b952008-12-15 17:13:39 +00002402 /* NIP cannot be restored if the memory exception comes from an helper */
2403 gen_update_nip(ctx, ctx->nip - 4);
j_mayer7c580442007-10-27 17:54:30 +00002404 gen_reset_fpstatus();
aurel320f2f39c2008-11-19 17:54:49 +00002405 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
aurel32af129062008-11-19 16:10:23 +00002406 t1 = tcg_const_i32(1 << sh);
2407 gen_helper_store_fpscr(t0, t1);
aurel320f2f39c2008-11-19 17:54:49 +00002408 tcg_temp_free_i64(t0);
2409 tcg_temp_free_i32(t1);
j_mayer7c580442007-10-27 17:54:30 +00002410 if (unlikely(Rc(ctx->opcode) != 0)) {
aurel32e1571902008-10-21 11:31:14 +00002411 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
j_mayer7c580442007-10-27 17:54:30 +00002412 }
2413 /* We can raise a differed exception */
aurel32af129062008-11-19 16:10:23 +00002414 gen_helper_float_check_status();
bellard79aceca2003-11-23 14:55:54 +00002415}
2416
j_mayer76a66252007-03-07 08:32:30 +00002417/*** Addressing modes ***/
2418/* Register indirect with immediate index : EA = (rA|0) + SIMM */
Blue Swirl636aa202009-08-16 09:06:54 +00002419static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2420 target_long maskl)
j_mayer76a66252007-03-07 08:32:30 +00002421{
2422 target_long simm = SIMM(ctx->opcode);
2423
j_mayerbe147d02007-09-30 13:03:23 +00002424 simm &= ~maskl;
aurel3276db3ba2008-12-08 18:11:21 +00002425 if (rA(ctx->opcode) == 0) {
2426#if defined(TARGET_PPC64)
2427 if (!ctx->sf_mode) {
2428 tcg_gen_movi_tl(EA, (uint32_t)simm);
2429 } else
2430#endif
aurel32e2be8d82008-10-14 19:55:54 +00002431 tcg_gen_movi_tl(EA, simm);
aurel3276db3ba2008-12-08 18:11:21 +00002432 } else if (likely(simm != 0)) {
aurel32e2be8d82008-10-14 19:55:54 +00002433 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
aurel3276db3ba2008-12-08 18:11:21 +00002434#if defined(TARGET_PPC64)
2435 if (!ctx->sf_mode) {
2436 tcg_gen_ext32u_tl(EA, EA);
2437 }
2438#endif
2439 } else {
2440#if defined(TARGET_PPC64)
2441 if (!ctx->sf_mode) {
2442 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2443 } else
2444#endif
aurel32e2be8d82008-10-14 19:55:54 +00002445 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
aurel3276db3ba2008-12-08 18:11:21 +00002446 }
j_mayer76a66252007-03-07 08:32:30 +00002447}
2448
Blue Swirl636aa202009-08-16 09:06:54 +00002449static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
j_mayer76a66252007-03-07 08:32:30 +00002450{
aurel3276db3ba2008-12-08 18:11:21 +00002451 if (rA(ctx->opcode) == 0) {
2452#if defined(TARGET_PPC64)
2453 if (!ctx->sf_mode) {
2454 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2455 } else
2456#endif
aurel32e2be8d82008-10-14 19:55:54 +00002457 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
aurel3276db3ba2008-12-08 18:11:21 +00002458 } else {
aurel32e2be8d82008-10-14 19:55:54 +00002459 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3276db3ba2008-12-08 18:11:21 +00002460#if defined(TARGET_PPC64)
2461 if (!ctx->sf_mode) {
2462 tcg_gen_ext32u_tl(EA, EA);
2463 }
2464#endif
2465 }
j_mayer76a66252007-03-07 08:32:30 +00002466}
2467
Blue Swirl636aa202009-08-16 09:06:54 +00002468static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
j_mayer76a66252007-03-07 08:32:30 +00002469{
aurel3276db3ba2008-12-08 18:11:21 +00002470 if (rA(ctx->opcode) == 0) {
aurel32e2be8d82008-10-14 19:55:54 +00002471 tcg_gen_movi_tl(EA, 0);
aurel3276db3ba2008-12-08 18:11:21 +00002472 } else {
2473#if defined(TARGET_PPC64)
2474 if (!ctx->sf_mode) {
2475 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2476 } else
2477#endif
2478 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2479 }
2480}
2481
Blue Swirl636aa202009-08-16 09:06:54 +00002482static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2483 target_long val)
aurel3276db3ba2008-12-08 18:11:21 +00002484{
2485 tcg_gen_addi_tl(ret, arg1, val);
2486#if defined(TARGET_PPC64)
2487 if (!ctx->sf_mode) {
2488 tcg_gen_ext32u_tl(ret, ret);
2489 }
2490#endif
j_mayer76a66252007-03-07 08:32:30 +00002491}
2492
Blue Swirl636aa202009-08-16 09:06:54 +00002493static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
aurel32cf360a32008-11-30 16:24:39 +00002494{
2495 int l1 = gen_new_label();
2496 TCGv t0 = tcg_temp_new();
2497 TCGv_i32 t1, t2;
2498 /* NIP cannot be restored if the memory exception comes from an helper */
2499 gen_update_nip(ctx, ctx->nip - 4);
2500 tcg_gen_andi_tl(t0, EA, mask);
2501 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2502 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2503 t2 = tcg_const_i32(0);
2504 gen_helper_raise_exception_err(t1, t2);
2505 tcg_temp_free_i32(t1);
2506 tcg_temp_free_i32(t2);
2507 gen_set_label(l1);
2508 tcg_temp_free(t0);
2509}
2510
j_mayer78636672007-11-16 14:11:28 +00002511/*** Integer load ***/
Blue Swirl636aa202009-08-16 09:06:54 +00002512static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002513{
2514 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2515}
2516
Blue Swirl636aa202009-08-16 09:06:54 +00002517static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002518{
2519 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2520}
2521
Blue Swirl636aa202009-08-16 09:06:54 +00002522static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002523{
2524 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2525 if (unlikely(ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002526 tcg_gen_bswap16_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002527 }
aurel32b61f2752008-10-15 17:00:37 +00002528}
2529
Blue Swirl636aa202009-08-16 09:06:54 +00002530static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002531{
aurel3276db3ba2008-12-08 18:11:21 +00002532 if (unlikely(ctx->le_mode)) {
aurel3276db3ba2008-12-08 18:11:21 +00002533 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
aurel32fa3966a2009-03-13 09:35:34 +00002534 tcg_gen_bswap16_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002535 tcg_gen_ext16s_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002536 } else {
2537 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2538 }
aurel32b61f2752008-10-15 17:00:37 +00002539}
2540
Blue Swirl636aa202009-08-16 09:06:54 +00002541static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002542{
aurel3276db3ba2008-12-08 18:11:21 +00002543 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2544 if (unlikely(ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002545 tcg_gen_bswap32_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002546 }
aurel32b61f2752008-10-15 17:00:37 +00002547}
2548
aurel3276db3ba2008-12-08 18:11:21 +00002549#if defined(TARGET_PPC64)
Blue Swirl636aa202009-08-16 09:06:54 +00002550static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002551{
blueswir1a457e7e2009-02-28 08:25:29 +00002552 if (unlikely(ctx->le_mode)) {
aurel3276db3ba2008-12-08 18:11:21 +00002553 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
aurel32fa3966a2009-03-13 09:35:34 +00002554 tcg_gen_bswap32_tl(arg1, arg1);
2555 tcg_gen_ext32s_tl(arg1, arg1);
aurel32b61f2752008-10-15 17:00:37 +00002556 } else
aurel3276db3ba2008-12-08 18:11:21 +00002557 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
aurel32a0d7d5a2008-11-23 16:30:50 +00002558}
aurel32b61f2752008-10-15 17:00:37 +00002559#endif
2560
Blue Swirl636aa202009-08-16 09:06:54 +00002561static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002562{
2563 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2564 if (unlikely(ctx->le_mode)) {
aurel3266896cb2009-03-13 09:34:48 +00002565 tcg_gen_bswap64_i64(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002566 }
2567}
2568
Blue Swirl636aa202009-08-16 09:06:54 +00002569static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002570{
2571 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2572}
2573
Blue Swirl636aa202009-08-16 09:06:54 +00002574static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002575{
2576 if (unlikely(ctx->le_mode)) {
aurel3276db3ba2008-12-08 18:11:21 +00002577 TCGv t0 = tcg_temp_new();
2578 tcg_gen_ext16u_tl(t0, arg1);
aurel32fa3966a2009-03-13 09:35:34 +00002579 tcg_gen_bswap16_tl(t0, t0);
aurel3276db3ba2008-12-08 18:11:21 +00002580 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2581 tcg_temp_free(t0);
aurel3276db3ba2008-12-08 18:11:21 +00002582 } else {
2583 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2584 }
2585}
2586
Blue Swirl636aa202009-08-16 09:06:54 +00002587static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002588{
2589 if (unlikely(ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002590 TCGv t0 = tcg_temp_new();
2591 tcg_gen_ext32u_tl(t0, arg1);
2592 tcg_gen_bswap32_tl(t0, t0);
aurel3276db3ba2008-12-08 18:11:21 +00002593 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2594 tcg_temp_free(t0);
aurel3276db3ba2008-12-08 18:11:21 +00002595 } else {
2596 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2597 }
2598}
2599
Blue Swirl636aa202009-08-16 09:06:54 +00002600static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
aurel3276db3ba2008-12-08 18:11:21 +00002601{
2602 if (unlikely(ctx->le_mode)) {
2603 TCGv_i64 t0 = tcg_temp_new_i64();
aurel3266896cb2009-03-13 09:34:48 +00002604 tcg_gen_bswap64_i64(t0, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002605 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2606 tcg_temp_free_i64(t0);
2607 } else
2608 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2609}
2610
aurel320c8aacd2008-11-23 16:30:28 +00002611#define GEN_LD(name, ldop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002612static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002613{ \
aurel3276db3ba2008-12-08 18:11:21 +00002614 TCGv EA; \
2615 gen_set_access_type(ctx, ACCESS_INT); \
2616 EA = tcg_temp_new(); \
2617 gen_addr_imm_index(ctx, EA, 0); \
2618 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002619 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002620}
2621
aurel320c8aacd2008-11-23 16:30:28 +00002622#define GEN_LDU(name, ldop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002623static void glue(gen_, name##u)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002624{ \
aurel32b61f2752008-10-15 17:00:37 +00002625 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002626 if (unlikely(rA(ctx->opcode) == 0 || \
2627 rA(ctx->opcode) == rD(ctx->opcode))) { \
aurel32e06fcd72008-12-11 22:42:14 +00002628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00002629 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002630 } \
aurel3276db3ba2008-12-08 18:11:21 +00002631 gen_set_access_type(ctx, ACCESS_INT); \
aurel320c8aacd2008-11-23 16:30:28 +00002632 EA = tcg_temp_new(); \
j_mayer9d53c752007-04-06 07:59:47 +00002633 if (type == PPC_64B) \
aurel3276db3ba2008-12-08 18:11:21 +00002634 gen_addr_imm_index(ctx, EA, 0x03); \
j_mayer9d53c752007-04-06 07:59:47 +00002635 else \
aurel3276db3ba2008-12-08 18:11:21 +00002636 gen_addr_imm_index(ctx, EA, 0); \
2637 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002638 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2639 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002640}
2641
aurel320c8aacd2008-11-23 16:30:28 +00002642#define GEN_LDUX(name, ldop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002643static void glue(gen_, name##ux)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002644{ \
aurel32b61f2752008-10-15 17:00:37 +00002645 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002646 if (unlikely(rA(ctx->opcode) == 0 || \
2647 rA(ctx->opcode) == rD(ctx->opcode))) { \
aurel32e06fcd72008-12-11 22:42:14 +00002648 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00002649 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002650 } \
aurel3276db3ba2008-12-08 18:11:21 +00002651 gen_set_access_type(ctx, ACCESS_INT); \
aurel320c8aacd2008-11-23 16:30:28 +00002652 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00002653 gen_addr_reg_index(ctx, EA); \
2654 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002655 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2656 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002657}
2658
aurel320c8aacd2008-11-23 16:30:28 +00002659#define GEN_LDX(name, ldop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002660static void glue(gen_, name##x)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002661{ \
aurel3276db3ba2008-12-08 18:11:21 +00002662 TCGv EA; \
2663 gen_set_access_type(ctx, ACCESS_INT); \
2664 EA = tcg_temp_new(); \
2665 gen_addr_reg_index(ctx, EA); \
2666 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002667 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002668}
2669
aurel320c8aacd2008-11-23 16:30:28 +00002670#define GEN_LDS(name, ldop, op, type) \
2671GEN_LD(name, ldop, op | 0x20, type); \
2672GEN_LDU(name, ldop, op | 0x21, type); \
2673GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2674GEN_LDX(name, ldop, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00002675
2676/* lbz lbzu lbzux lbzx */
aurel320c8aacd2008-11-23 16:30:28 +00002677GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002678/* lha lhau lhaux lhax */
aurel320c8aacd2008-11-23 16:30:28 +00002679GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002680/* lhz lhzu lhzux lhzx */
aurel320c8aacd2008-11-23 16:30:28 +00002681GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002682/* lwz lwzu lwzux lwzx */
aurel320c8aacd2008-11-23 16:30:28 +00002683GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
j_mayerd9bce9d2007-03-17 14:02:15 +00002684#if defined(TARGET_PPC64)
j_mayerd9bce9d2007-03-17 14:02:15 +00002685/* lwaux */
aurel320c8aacd2008-11-23 16:30:28 +00002686GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002687/* lwax */
aurel320c8aacd2008-11-23 16:30:28 +00002688GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002689/* ldux */
aurel320c8aacd2008-11-23 16:30:28 +00002690GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
j_mayerd9bce9d2007-03-17 14:02:15 +00002691/* ldx */
aurel320c8aacd2008-11-23 16:30:28 +00002692GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
Blue Swirl99e300e2009-06-17 15:22:09 +00002693
2694static void gen_ld(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00002695{
aurel32b61f2752008-10-15 17:00:37 +00002696 TCGv EA;
j_mayerd9bce9d2007-03-17 14:02:15 +00002697 if (Rc(ctx->opcode)) {
2698 if (unlikely(rA(ctx->opcode) == 0 ||
2699 rA(ctx->opcode) == rD(ctx->opcode))) {
aurel32e06fcd72008-12-11 22:42:14 +00002700 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayerd9bce9d2007-03-17 14:02:15 +00002701 return;
2702 }
2703 }
aurel3276db3ba2008-12-08 18:11:21 +00002704 gen_set_access_type(ctx, ACCESS_INT);
pbrooka7812ae2008-11-17 14:43:54 +00002705 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00002706 gen_addr_imm_index(ctx, EA, 0x03);
j_mayerd9bce9d2007-03-17 14:02:15 +00002707 if (ctx->opcode & 0x02) {
2708 /* lwa (lwau is undefined) */
aurel3276db3ba2008-12-08 18:11:21 +00002709 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002710 } else {
2711 /* ld - ldu */
aurel3276db3ba2008-12-08 18:11:21 +00002712 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002713 }
j_mayerd9bce9d2007-03-17 14:02:15 +00002714 if (Rc(ctx->opcode))
aurel32b61f2752008-10-15 17:00:37 +00002715 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2716 tcg_temp_free(EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002717}
Blue Swirl99e300e2009-06-17 15:22:09 +00002718
Blue Swirl54623272009-06-17 15:22:19 +00002719/* lq */
Blue Swirl99e300e2009-06-17 15:22:09 +00002720static void gen_lq(DisasContext *ctx)
j_mayerbe147d02007-09-30 13:03:23 +00002721{
2722#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00002723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00002724#else
2725 int ra, rd;
aurel32b61f2752008-10-15 17:00:37 +00002726 TCGv EA;
j_mayerbe147d02007-09-30 13:03:23 +00002727
2728 /* Restore CPU state */
aurel3276db3ba2008-12-08 18:11:21 +00002729 if (unlikely(ctx->mem_idx == 0)) {
aurel32e06fcd72008-12-11 22:42:14 +00002730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00002731 return;
2732 }
2733 ra = rA(ctx->opcode);
2734 rd = rD(ctx->opcode);
2735 if (unlikely((rd & 1) || rd == ra)) {
aurel32e06fcd72008-12-11 22:42:14 +00002736 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayerbe147d02007-09-30 13:03:23 +00002737 return;
2738 }
aurel3276db3ba2008-12-08 18:11:21 +00002739 if (unlikely(ctx->le_mode)) {
j_mayerbe147d02007-09-30 13:03:23 +00002740 /* Little-endian mode is not handled */
aurel32e06fcd72008-12-11 22:42:14 +00002741 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
j_mayerbe147d02007-09-30 13:03:23 +00002742 return;
2743 }
aurel3276db3ba2008-12-08 18:11:21 +00002744 gen_set_access_type(ctx, ACCESS_INT);
pbrooka7812ae2008-11-17 14:43:54 +00002745 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00002746 gen_addr_imm_index(ctx, EA, 0x0F);
2747 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2748 gen_addr_add(ctx, EA, EA, 8);
2749 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
aurel32b61f2752008-10-15 17:00:37 +00002750 tcg_temp_free(EA);
j_mayerbe147d02007-09-30 13:03:23 +00002751#endif
2752}
j_mayerd9bce9d2007-03-17 14:02:15 +00002753#endif
bellard79aceca2003-11-23 14:55:54 +00002754
2755/*** Integer store ***/
aurel320c8aacd2008-11-23 16:30:28 +00002756#define GEN_ST(name, stop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002757static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002758{ \
aurel3276db3ba2008-12-08 18:11:21 +00002759 TCGv EA; \
2760 gen_set_access_type(ctx, ACCESS_INT); \
2761 EA = tcg_temp_new(); \
2762 gen_addr_imm_index(ctx, EA, 0); \
2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002764 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002765}
2766
aurel320c8aacd2008-11-23 16:30:28 +00002767#define GEN_STU(name, stop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002768static void glue(gen_, stop##u)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002769{ \
aurel32b61f2752008-10-15 17:00:37 +00002770 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002771 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002772 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00002773 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002774 } \
aurel3276db3ba2008-12-08 18:11:21 +00002775 gen_set_access_type(ctx, ACCESS_INT); \
aurel320c8aacd2008-11-23 16:30:28 +00002776 EA = tcg_temp_new(); \
j_mayer9d53c752007-04-06 07:59:47 +00002777 if (type == PPC_64B) \
aurel3276db3ba2008-12-08 18:11:21 +00002778 gen_addr_imm_index(ctx, EA, 0x03); \
j_mayer9d53c752007-04-06 07:59:47 +00002779 else \
aurel3276db3ba2008-12-08 18:11:21 +00002780 gen_addr_imm_index(ctx, EA, 0); \
2781 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002782 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2783 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002784}
2785
aurel320c8aacd2008-11-23 16:30:28 +00002786#define GEN_STUX(name, stop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002787static void glue(gen_, name##ux)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002788{ \
aurel32b61f2752008-10-15 17:00:37 +00002789 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00002790 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00002791 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00002792 return; \
bellard9a64fbe2004-01-04 22:58:38 +00002793 } \
aurel3276db3ba2008-12-08 18:11:21 +00002794 gen_set_access_type(ctx, ACCESS_INT); \
aurel320c8aacd2008-11-23 16:30:28 +00002795 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00002796 gen_addr_reg_index(ctx, EA); \
2797 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002800}
2801
aurel320c8aacd2008-11-23 16:30:28 +00002802#define GEN_STX(name, stop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00002803static void glue(gen_, name##x)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00002804{ \
aurel3276db3ba2008-12-08 18:11:21 +00002805 TCGv EA; \
2806 gen_set_access_type(ctx, ACCESS_INT); \
2807 EA = tcg_temp_new(); \
2808 gen_addr_reg_index(ctx, EA); \
2809 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
aurel32b61f2752008-10-15 17:00:37 +00002810 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00002811}
2812
aurel320c8aacd2008-11-23 16:30:28 +00002813#define GEN_STS(name, stop, op, type) \
2814GEN_ST(name, stop, op | 0x20, type); \
2815GEN_STU(name, stop, op | 0x21, type); \
2816GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2817GEN_STX(name, stop, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00002818
2819/* stb stbu stbux stbx */
aurel320c8aacd2008-11-23 16:30:28 +00002820GEN_STS(stb, st8, 0x06, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002821/* sth sthu sthux sthx */
aurel320c8aacd2008-11-23 16:30:28 +00002822GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002823/* stw stwu stwux stwx */
aurel320c8aacd2008-11-23 16:30:28 +00002824GEN_STS(stw, st32, 0x04, PPC_INTEGER);
j_mayerd9bce9d2007-03-17 14:02:15 +00002825#if defined(TARGET_PPC64)
aurel320c8aacd2008-11-23 16:30:28 +00002826GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2827GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
Blue Swirl99e300e2009-06-17 15:22:09 +00002828
2829static void gen_std(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00002830{
j_mayerbe147d02007-09-30 13:03:23 +00002831 int rs;
aurel32b61f2752008-10-15 17:00:37 +00002832 TCGv EA;
j_mayerbe147d02007-09-30 13:03:23 +00002833
2834 rs = rS(ctx->opcode);
2835 if ((ctx->opcode & 0x3) == 0x2) {
2836#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00002837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00002838#else
2839 /* stq */
aurel3276db3ba2008-12-08 18:11:21 +00002840 if (unlikely(ctx->mem_idx == 0)) {
aurel32e06fcd72008-12-11 22:42:14 +00002841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00002842 return;
2843 }
2844 if (unlikely(rs & 1)) {
aurel32e06fcd72008-12-11 22:42:14 +00002845 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayerd9bce9d2007-03-17 14:02:15 +00002846 return;
2847 }
aurel3276db3ba2008-12-08 18:11:21 +00002848 if (unlikely(ctx->le_mode)) {
j_mayerbe147d02007-09-30 13:03:23 +00002849 /* Little-endian mode is not handled */
aurel32e06fcd72008-12-11 22:42:14 +00002850 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
j_mayerbe147d02007-09-30 13:03:23 +00002851 return;
2852 }
aurel3276db3ba2008-12-08 18:11:21 +00002853 gen_set_access_type(ctx, ACCESS_INT);
pbrooka7812ae2008-11-17 14:43:54 +00002854 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00002855 gen_addr_imm_index(ctx, EA, 0x03);
2856 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2857 gen_addr_add(ctx, EA, EA, 8);
2858 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
aurel32b61f2752008-10-15 17:00:37 +00002859 tcg_temp_free(EA);
j_mayerbe147d02007-09-30 13:03:23 +00002860#endif
2861 } else {
2862 /* std / stdu */
2863 if (Rc(ctx->opcode)) {
2864 if (unlikely(rA(ctx->opcode) == 0)) {
aurel32e06fcd72008-12-11 22:42:14 +00002865 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayerbe147d02007-09-30 13:03:23 +00002866 return;
2867 }
2868 }
aurel3276db3ba2008-12-08 18:11:21 +00002869 gen_set_access_type(ctx, ACCESS_INT);
pbrooka7812ae2008-11-17 14:43:54 +00002870 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00002871 gen_addr_imm_index(ctx, EA, 0x03);
2872 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
j_mayerbe147d02007-09-30 13:03:23 +00002873 if (Rc(ctx->opcode))
aurel32b61f2752008-10-15 17:00:37 +00002874 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2875 tcg_temp_free(EA);
j_mayerd9bce9d2007-03-17 14:02:15 +00002876 }
j_mayerd9bce9d2007-03-17 14:02:15 +00002877}
2878#endif
bellard79aceca2003-11-23 14:55:54 +00002879/*** Integer load and store with byte reverse ***/
2880/* lhbrx */
Juan Quintela86178a52009-09-23 01:19:00 +02002881static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002882{
aurel3276db3ba2008-12-08 18:11:21 +00002883 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2884 if (likely(!ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002885 tcg_gen_bswap16_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002886 }
aurel32b61f2752008-10-15 17:00:37 +00002887}
aurel320c8aacd2008-11-23 16:30:28 +00002888GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
aurel32b61f2752008-10-15 17:00:37 +00002889
bellard79aceca2003-11-23 14:55:54 +00002890/* lwbrx */
Juan Quintela86178a52009-09-23 01:19:00 +02002891static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002892{
aurel3276db3ba2008-12-08 18:11:21 +00002893 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2894 if (likely(!ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002895 tcg_gen_bswap32_tl(arg1, arg1);
aurel3276db3ba2008-12-08 18:11:21 +00002896 }
aurel32b61f2752008-10-15 17:00:37 +00002897}
aurel320c8aacd2008-11-23 16:30:28 +00002898GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
aurel32b61f2752008-10-15 17:00:37 +00002899
bellard79aceca2003-11-23 14:55:54 +00002900/* sthbrx */
Juan Quintela86178a52009-09-23 01:19:00 +02002901static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002902{
aurel3276db3ba2008-12-08 18:11:21 +00002903 if (likely(!ctx->le_mode)) {
aurel3276db3ba2008-12-08 18:11:21 +00002904 TCGv t0 = tcg_temp_new();
2905 tcg_gen_ext16u_tl(t0, arg1);
aurel32fa3966a2009-03-13 09:35:34 +00002906 tcg_gen_bswap16_tl(t0, t0);
aurel3276db3ba2008-12-08 18:11:21 +00002907 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2908 tcg_temp_free(t0);
aurel3276db3ba2008-12-08 18:11:21 +00002909 } else {
2910 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2911 }
aurel32b61f2752008-10-15 17:00:37 +00002912}
aurel320c8aacd2008-11-23 16:30:28 +00002913GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
aurel32b61f2752008-10-15 17:00:37 +00002914
bellard79aceca2003-11-23 14:55:54 +00002915/* stwbrx */
Juan Quintela86178a52009-09-23 01:19:00 +02002916static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
aurel32b61f2752008-10-15 17:00:37 +00002917{
aurel3276db3ba2008-12-08 18:11:21 +00002918 if (likely(!ctx->le_mode)) {
aurel32fa3966a2009-03-13 09:35:34 +00002919 TCGv t0 = tcg_temp_new();
2920 tcg_gen_ext32u_tl(t0, arg1);
2921 tcg_gen_bswap32_tl(t0, t0);
aurel3276db3ba2008-12-08 18:11:21 +00002922 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2923 tcg_temp_free(t0);
aurel3276db3ba2008-12-08 18:11:21 +00002924 } else {
2925 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2926 }
aurel32b61f2752008-10-15 17:00:37 +00002927}
aurel320c8aacd2008-11-23 16:30:28 +00002928GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
bellard79aceca2003-11-23 14:55:54 +00002929
2930/*** Integer load and store multiple ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00002931
Blue Swirl54623272009-06-17 15:22:19 +00002932/* lmw */
Blue Swirl99e300e2009-06-17 15:22:09 +00002933static void gen_lmw(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002934{
aurel3276db3ba2008-12-08 18:11:21 +00002935 TCGv t0;
2936 TCGv_i32 t1;
2937 gen_set_access_type(ctx, ACCESS_INT);
j_mayer76a66252007-03-07 08:32:30 +00002938 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00002939 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00002940 t0 = tcg_temp_new();
2941 t1 = tcg_const_i32(rD(ctx->opcode));
2942 gen_addr_imm_index(ctx, t0, 0);
aurel32ff4a62c2008-11-30 16:23:56 +00002943 gen_helper_lmw(t0, t1);
2944 tcg_temp_free(t0);
2945 tcg_temp_free_i32(t1);
bellard79aceca2003-11-23 14:55:54 +00002946}
2947
2948/* stmw */
Blue Swirl99e300e2009-06-17 15:22:09 +00002949static void gen_stmw(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002950{
aurel3276db3ba2008-12-08 18:11:21 +00002951 TCGv t0;
2952 TCGv_i32 t1;
2953 gen_set_access_type(ctx, ACCESS_INT);
j_mayer76a66252007-03-07 08:32:30 +00002954 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00002955 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00002956 t0 = tcg_temp_new();
2957 t1 = tcg_const_i32(rS(ctx->opcode));
2958 gen_addr_imm_index(ctx, t0, 0);
aurel32ff4a62c2008-11-30 16:23:56 +00002959 gen_helper_stmw(t0, t1);
2960 tcg_temp_free(t0);
2961 tcg_temp_free_i32(t1);
bellard79aceca2003-11-23 14:55:54 +00002962}
2963
2964/*** Integer load and store strings ***/
Blue Swirl54623272009-06-17 15:22:19 +00002965
bellard79aceca2003-11-23 14:55:54 +00002966/* lswi */
bellard3fc6c082005-07-02 20:59:34 +00002967/* PowerPC32 specification says we must generate an exception if
bellard9a64fbe2004-01-04 22:58:38 +00002968 * rA is in the range of registers to be loaded.
2969 * In an other hand, IBM says this is valid, but rA won't be loaded.
2970 * For now, I'll follow the spec...
2971 */
Blue Swirl99e300e2009-06-17 15:22:09 +00002972static void gen_lswi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00002973{
aurel32dfbc7992008-11-30 16:24:21 +00002974 TCGv t0;
2975 TCGv_i32 t1, t2;
bellard79aceca2003-11-23 14:55:54 +00002976 int nb = NB(ctx->opcode);
2977 int start = rD(ctx->opcode);
bellard9a64fbe2004-01-04 22:58:38 +00002978 int ra = rA(ctx->opcode);
bellard79aceca2003-11-23 14:55:54 +00002979 int nr;
2980
2981 if (nb == 0)
2982 nb = 32;
2983 nr = nb / 4;
j_mayer76a66252007-03-07 08:32:30 +00002984 if (unlikely(((start + nr) > 32 &&
2985 start <= ra && (start + nr - 32) > ra) ||
2986 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
aurel32e06fcd72008-12-11 22:42:14 +00002987 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
bellard9fddaa02004-05-21 12:59:32 +00002988 return;
bellard297d8e62004-02-21 14:11:27 +00002989 }
aurel3276db3ba2008-12-08 18:11:21 +00002990 gen_set_access_type(ctx, ACCESS_INT);
bellard8dd49832005-06-04 22:22:27 +00002991 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00002992 gen_update_nip(ctx, ctx->nip - 4);
aurel32dfbc7992008-11-30 16:24:21 +00002993 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00002994 gen_addr_register(ctx, t0);
aurel32dfbc7992008-11-30 16:24:21 +00002995 t1 = tcg_const_i32(nb);
2996 t2 = tcg_const_i32(start);
2997 gen_helper_lsw(t0, t1, t2);
2998 tcg_temp_free(t0);
2999 tcg_temp_free_i32(t1);
3000 tcg_temp_free_i32(t2);
bellard79aceca2003-11-23 14:55:54 +00003001}
3002
3003/* lswx */
Blue Swirl99e300e2009-06-17 15:22:09 +00003004static void gen_lswx(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003005{
aurel3276db3ba2008-12-08 18:11:21 +00003006 TCGv t0;
3007 TCGv_i32 t1, t2, t3;
3008 gen_set_access_type(ctx, ACCESS_INT);
j_mayer76a66252007-03-07 08:32:30 +00003009 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00003010 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00003011 t0 = tcg_temp_new();
3012 gen_addr_reg_index(ctx, t0);
3013 t1 = tcg_const_i32(rD(ctx->opcode));
3014 t2 = tcg_const_i32(rA(ctx->opcode));
3015 t3 = tcg_const_i32(rB(ctx->opcode));
aurel32dfbc7992008-11-30 16:24:21 +00003016 gen_helper_lswx(t0, t1, t2, t3);
3017 tcg_temp_free(t0);
3018 tcg_temp_free_i32(t1);
3019 tcg_temp_free_i32(t2);
3020 tcg_temp_free_i32(t3);
bellard79aceca2003-11-23 14:55:54 +00003021}
3022
3023/* stswi */
Blue Swirl99e300e2009-06-17 15:22:09 +00003024static void gen_stswi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003025{
aurel3276db3ba2008-12-08 18:11:21 +00003026 TCGv t0;
3027 TCGv_i32 t1, t2;
bellard4b3686f2004-05-23 22:18:12 +00003028 int nb = NB(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00003029 gen_set_access_type(ctx, ACCESS_INT);
j_mayer76a66252007-03-07 08:32:30 +00003030 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00003031 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00003032 t0 = tcg_temp_new();
3033 gen_addr_register(ctx, t0);
bellard4b3686f2004-05-23 22:18:12 +00003034 if (nb == 0)
3035 nb = 32;
aurel32dfbc7992008-11-30 16:24:21 +00003036 t1 = tcg_const_i32(nb);
aurel3276db3ba2008-12-08 18:11:21 +00003037 t2 = tcg_const_i32(rS(ctx->opcode));
aurel32dfbc7992008-11-30 16:24:21 +00003038 gen_helper_stsw(t0, t1, t2);
3039 tcg_temp_free(t0);
3040 tcg_temp_free_i32(t1);
3041 tcg_temp_free_i32(t2);
bellard79aceca2003-11-23 14:55:54 +00003042}
3043
3044/* stswx */
Blue Swirl99e300e2009-06-17 15:22:09 +00003045static void gen_stswx(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003046{
aurel3276db3ba2008-12-08 18:11:21 +00003047 TCGv t0;
3048 TCGv_i32 t1, t2;
3049 gen_set_access_type(ctx, ACCESS_INT);
bellard8dd49832005-06-04 22:22:27 +00003050 /* NIP cannot be restored if the memory exception comes from an helper */
ths5fafdf22007-09-16 21:08:06 +00003051 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00003052 t0 = tcg_temp_new();
3053 gen_addr_reg_index(ctx, t0);
3054 t1 = tcg_temp_new_i32();
aurel32dfbc7992008-11-30 16:24:21 +00003055 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3056 tcg_gen_andi_i32(t1, t1, 0x7F);
aurel3276db3ba2008-12-08 18:11:21 +00003057 t2 = tcg_const_i32(rS(ctx->opcode));
aurel32dfbc7992008-11-30 16:24:21 +00003058 gen_helper_stsw(t0, t1, t2);
3059 tcg_temp_free(t0);
3060 tcg_temp_free_i32(t1);
3061 tcg_temp_free_i32(t2);
bellard79aceca2003-11-23 14:55:54 +00003062}
3063
3064/*** Memory synchronisation ***/
3065/* eieio */
Blue Swirl99e300e2009-06-17 15:22:09 +00003066static void gen_eieio(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003067{
bellard79aceca2003-11-23 14:55:54 +00003068}
3069
3070/* isync */
Blue Swirl99e300e2009-06-17 15:22:09 +00003071static void gen_isync(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003072{
aurel32e06fcd72008-12-11 22:42:14 +00003073 gen_stop_exception(ctx);
bellard79aceca2003-11-23 14:55:54 +00003074}
3075
bellard111bfab2005-04-23 18:16:07 +00003076/* lwarx */
Blue Swirl99e300e2009-06-17 15:22:09 +00003077static void gen_lwarx(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003078{
aurel3276db3ba2008-12-08 18:11:21 +00003079 TCGv t0;
Nathan Froyd18b21a22009-08-03 08:43:25 -07003080 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
aurel3276db3ba2008-12-08 18:11:21 +00003081 gen_set_access_type(ctx, ACCESS_RES);
3082 t0 = tcg_temp_local_new();
3083 gen_addr_reg_index(ctx, t0);
aurel32cf360a32008-11-30 16:24:39 +00003084 gen_check_align(ctx, t0, 0x03);
Nathan Froyd18b21a22009-08-03 08:43:25 -07003085 gen_qemu_ld32u(ctx, gpr, t0);
aurel32cf360a32008-11-30 16:24:39 +00003086 tcg_gen_mov_tl(cpu_reserve, t0);
Nathan Froyd18b21a22009-08-03 08:43:25 -07003087 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
aurel32cf360a32008-11-30 16:24:39 +00003088 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00003089}
3090
Nathan Froyd44252652009-08-03 08:43:26 -07003091#if defined(CONFIG_USER_ONLY)
3092static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3093 int reg, int size)
3094{
3095 TCGv t0 = tcg_temp_new();
3096 uint32_t save_exception = ctx->exception;
3097
3098 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUState, reserve_ea));
3099 tcg_gen_movi_tl(t0, (size << 5) | reg);
3100 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, reserve_info));
3101 tcg_temp_free(t0);
3102 gen_update_nip(ctx, ctx->nip-4);
3103 ctx->exception = POWERPC_EXCP_BRANCH;
3104 gen_exception(ctx, POWERPC_EXCP_STCX);
3105 ctx->exception = save_exception;
3106}
3107#endif
3108
bellard79aceca2003-11-23 14:55:54 +00003109/* stwcx. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00003110static void gen_stwcx_(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003111{
aurel3276db3ba2008-12-08 18:11:21 +00003112 TCGv t0;
3113 gen_set_access_type(ctx, ACCESS_RES);
3114 t0 = tcg_temp_local_new();
3115 gen_addr_reg_index(ctx, t0);
aurel32cf360a32008-11-30 16:24:39 +00003116 gen_check_align(ctx, t0, 0x03);
Nathan Froyd44252652009-08-03 08:43:26 -07003117#if defined(CONFIG_USER_ONLY)
3118 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3119#else
3120 {
3121 int l1;
3122
3123 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3124 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3125 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3126 l1 = gen_new_label();
3127 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3128 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3129 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3130 gen_set_label(l1);
3131 tcg_gen_movi_tl(cpu_reserve, -1);
3132 }
3133#endif
aurel32cf360a32008-11-30 16:24:39 +00003134 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00003135}
3136
j_mayer426613d2007-03-23 09:45:27 +00003137#if defined(TARGET_PPC64)
j_mayer426613d2007-03-23 09:45:27 +00003138/* ldarx */
Blue Swirl99e300e2009-06-17 15:22:09 +00003139static void gen_ldarx(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00003140{
aurel3276db3ba2008-12-08 18:11:21 +00003141 TCGv t0;
Nathan Froyd18b21a22009-08-03 08:43:25 -07003142 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
aurel3276db3ba2008-12-08 18:11:21 +00003143 gen_set_access_type(ctx, ACCESS_RES);
3144 t0 = tcg_temp_local_new();
3145 gen_addr_reg_index(ctx, t0);
aurel32cf360a32008-11-30 16:24:39 +00003146 gen_check_align(ctx, t0, 0x07);
Nathan Froyd18b21a22009-08-03 08:43:25 -07003147 gen_qemu_ld64(ctx, gpr, t0);
aurel32cf360a32008-11-30 16:24:39 +00003148 tcg_gen_mov_tl(cpu_reserve, t0);
Nathan Froyd18b21a22009-08-03 08:43:25 -07003149 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUState, reserve_val));
aurel32cf360a32008-11-30 16:24:39 +00003150 tcg_temp_free(t0);
j_mayer426613d2007-03-23 09:45:27 +00003151}
3152
3153/* stdcx. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00003154static void gen_stdcx_(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00003155{
aurel3276db3ba2008-12-08 18:11:21 +00003156 TCGv t0;
3157 gen_set_access_type(ctx, ACCESS_RES);
3158 t0 = tcg_temp_local_new();
3159 gen_addr_reg_index(ctx, t0);
aurel32cf360a32008-11-30 16:24:39 +00003160 gen_check_align(ctx, t0, 0x07);
Nathan Froyd44252652009-08-03 08:43:26 -07003161#if defined(CONFIG_USER_ONLY)
3162 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3163#else
3164 {
3165 int l1;
3166 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3167 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3168 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3169 l1 = gen_new_label();
3170 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3171 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3172 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3173 gen_set_label(l1);
3174 tcg_gen_movi_tl(cpu_reserve, -1);
3175 }
3176#endif
aurel32cf360a32008-11-30 16:24:39 +00003177 tcg_temp_free(t0);
j_mayer426613d2007-03-23 09:45:27 +00003178}
3179#endif /* defined(TARGET_PPC64) */
3180
bellard79aceca2003-11-23 14:55:54 +00003181/* sync */
Blue Swirl99e300e2009-06-17 15:22:09 +00003182static void gen_sync(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003183{
bellard79aceca2003-11-23 14:55:54 +00003184}
3185
j_mayer0db1b202007-09-30 03:46:38 +00003186/* wait */
Blue Swirl99e300e2009-06-17 15:22:09 +00003187static void gen_wait(DisasContext *ctx)
j_mayer0db1b202007-09-30 03:46:38 +00003188{
aurel32931ff272008-11-30 16:23:46 +00003189 TCGv_i32 t0 = tcg_temp_new_i32();
3190 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3191 tcg_temp_free_i32(t0);
j_mayer0db1b202007-09-30 03:46:38 +00003192 /* Stop translation, as the CPU is supposed to sleep from now */
aurel32e06fcd72008-12-11 22:42:14 +00003193 gen_exception_err(ctx, EXCP_HLT, 1);
j_mayer0db1b202007-09-30 03:46:38 +00003194}
3195
bellard79aceca2003-11-23 14:55:54 +00003196/*** Floating-point load ***/
aurel32a0d7d5a2008-11-23 16:30:50 +00003197#define GEN_LDF(name, ldop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003198static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003199{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003200 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003201 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003202 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003203 return; \
3204 } \
aurel3276db3ba2008-12-08 18:11:21 +00003205 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003206 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003207 gen_addr_imm_index(ctx, EA, 0); \
3208 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003209 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003210}
3211
aurel32a0d7d5a2008-11-23 16:30:50 +00003212#define GEN_LDUF(name, ldop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003213static void glue(gen_, name##u)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003214{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003215 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003216 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003217 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003218 return; \
3219 } \
j_mayer76a66252007-03-07 08:32:30 +00003220 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003221 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00003222 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003223 } \
aurel3276db3ba2008-12-08 18:11:21 +00003224 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003225 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003226 gen_addr_imm_index(ctx, EA, 0); \
3227 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003228 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3229 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003230}
3231
aurel32a0d7d5a2008-11-23 16:30:50 +00003232#define GEN_LDUXF(name, ldop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003233static void glue(gen_, name##ux)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003234{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003235 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003236 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003237 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003238 return; \
3239 } \
j_mayer76a66252007-03-07 08:32:30 +00003240 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003241 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00003242 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003243 } \
aurel3276db3ba2008-12-08 18:11:21 +00003244 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003245 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003246 gen_addr_reg_index(ctx, EA); \
3247 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003248 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3249 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003250}
3251
aurel32a0d7d5a2008-11-23 16:30:50 +00003252#define GEN_LDXF(name, ldop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003253static void glue(gen_, name##x)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003254{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003255 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003256 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003257 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003258 return; \
3259 } \
aurel3276db3ba2008-12-08 18:11:21 +00003260 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003261 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003262 gen_addr_reg_index(ctx, EA); \
3263 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003264 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003265}
3266
aurel32a0d7d5a2008-11-23 16:30:50 +00003267#define GEN_LDFS(name, ldop, op, type) \
3268GEN_LDF(name, ldop, op | 0x20, type); \
3269GEN_LDUF(name, ldop, op | 0x21, type); \
3270GEN_LDUXF(name, ldop, op | 0x01, type); \
3271GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
bellard79aceca2003-11-23 14:55:54 +00003272
Blue Swirl636aa202009-08-16 09:06:54 +00003273static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
aurel32a0d7d5a2008-11-23 16:30:50 +00003274{
3275 TCGv t0 = tcg_temp_new();
3276 TCGv_i32 t1 = tcg_temp_new_i32();
aurel3276db3ba2008-12-08 18:11:21 +00003277 gen_qemu_ld32u(ctx, t0, arg2);
aurel32a0d7d5a2008-11-23 16:30:50 +00003278 tcg_gen_trunc_tl_i32(t1, t0);
3279 tcg_temp_free(t0);
3280 gen_helper_float32_to_float64(arg1, t1);
3281 tcg_temp_free_i32(t1);
3282}
3283
3284 /* lfd lfdu lfdux lfdx */
3285GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3286 /* lfs lfsu lfsux lfsx */
3287GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003288
3289/*** Floating-point store ***/
aurel32a0d7d5a2008-11-23 16:30:50 +00003290#define GEN_STF(name, stop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003291static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003292{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003293 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003294 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003295 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003296 return; \
3297 } \
aurel3276db3ba2008-12-08 18:11:21 +00003298 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003299 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003300 gen_addr_imm_index(ctx, EA, 0); \
3301 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003302 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003303}
3304
aurel32a0d7d5a2008-11-23 16:30:50 +00003305#define GEN_STUF(name, stop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003306static void glue(gen_, name##u)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003307{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003308 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003309 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003310 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003311 return; \
3312 } \
j_mayer76a66252007-03-07 08:32:30 +00003313 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003314 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00003315 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003316 } \
aurel3276db3ba2008-12-08 18:11:21 +00003317 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003318 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003319 gen_addr_imm_index(ctx, EA, 0); \
3320 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003321 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3322 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003323}
3324
aurel32a0d7d5a2008-11-23 16:30:50 +00003325#define GEN_STUXF(name, stop, opc, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003326static void glue(gen_, name##ux)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003327{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003328 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003329 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003330 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003331 return; \
3332 } \
j_mayer76a66252007-03-07 08:32:30 +00003333 if (unlikely(rA(ctx->opcode) == 0)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003334 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
bellard9fddaa02004-05-21 12:59:32 +00003335 return; \
bellard9a64fbe2004-01-04 22:58:38 +00003336 } \
aurel3276db3ba2008-12-08 18:11:21 +00003337 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003338 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003339 gen_addr_reg_index(ctx, EA); \
3340 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003341 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3342 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003343}
3344
aurel32a0d7d5a2008-11-23 16:30:50 +00003345#define GEN_STXF(name, stop, opc2, opc3, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003346static void glue(gen_, name##x)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003347{ \
aurel32a0d7d5a2008-11-23 16:30:50 +00003348 TCGv EA; \
j_mayer76a66252007-03-07 08:32:30 +00003349 if (unlikely(!ctx->fpu_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00003350 gen_exception(ctx, POWERPC_EXCP_FPU); \
bellard4ecc3192005-03-13 17:01:22 +00003351 return; \
3352 } \
aurel3276db3ba2008-12-08 18:11:21 +00003353 gen_set_access_type(ctx, ACCESS_FLOAT); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003354 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00003355 gen_addr_reg_index(ctx, EA); \
3356 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
aurel32a0d7d5a2008-11-23 16:30:50 +00003357 tcg_temp_free(EA); \
bellard79aceca2003-11-23 14:55:54 +00003358}
3359
aurel32a0d7d5a2008-11-23 16:30:50 +00003360#define GEN_STFS(name, stop, op, type) \
3361GEN_STF(name, stop, op | 0x20, type); \
3362GEN_STUF(name, stop, op | 0x21, type); \
3363GEN_STUXF(name, stop, op | 0x01, type); \
3364GEN_STXF(name, stop, 0x17, op | 0x00, type)
3365
Blue Swirl636aa202009-08-16 09:06:54 +00003366static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
aurel32a0d7d5a2008-11-23 16:30:50 +00003367{
3368 TCGv_i32 t0 = tcg_temp_new_i32();
3369 TCGv t1 = tcg_temp_new();
3370 gen_helper_float64_to_float32(t0, arg1);
3371 tcg_gen_extu_i32_tl(t1, t0);
3372 tcg_temp_free_i32(t0);
aurel3276db3ba2008-12-08 18:11:21 +00003373 gen_qemu_st32(ctx, t1, arg2);
aurel32a0d7d5a2008-11-23 16:30:50 +00003374 tcg_temp_free(t1);
3375}
bellard79aceca2003-11-23 14:55:54 +00003376
3377/* stfd stfdu stfdux stfdx */
aurel32a0d7d5a2008-11-23 16:30:50 +00003378GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003379/* stfs stfsu stfsux stfsx */
aurel32a0d7d5a2008-11-23 16:30:50 +00003380GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
bellard79aceca2003-11-23 14:55:54 +00003381
3382/* Optional: */
Blue Swirl636aa202009-08-16 09:06:54 +00003383static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
aurel32a0d7d5a2008-11-23 16:30:50 +00003384{
3385 TCGv t0 = tcg_temp_new();
3386 tcg_gen_trunc_i64_tl(t0, arg1),
aurel3276db3ba2008-12-08 18:11:21 +00003387 gen_qemu_st32(ctx, t0, arg2);
aurel32a0d7d5a2008-11-23 16:30:50 +00003388 tcg_temp_free(t0);
3389}
bellard79aceca2003-11-23 14:55:54 +00003390/* stfiwx */
aurel32a0d7d5a2008-11-23 16:30:50 +00003391GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
bellard79aceca2003-11-23 14:55:54 +00003392
David Gibson697ab892011-08-31 15:45:10 +00003393static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3394{
3395#if defined(TARGET_PPC64)
3396 if (ctx->has_cfar)
3397 tcg_gen_movi_tl(cpu_cfar, nip);
3398#endif
3399}
3400
bellard79aceca2003-11-23 14:55:54 +00003401/*** Branch ***/
Blue Swirl636aa202009-08-16 09:06:54 +00003402static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
bellardc53be332005-10-30 21:39:19 +00003403{
bellardc1942362005-11-20 10:31:08 +00003404 TranslationBlock *tb;
3405 tb = ctx->tb;
aurel32a2ffb812008-10-21 16:31:31 +00003406#if defined(TARGET_PPC64)
3407 if (!ctx->sf_mode)
3408 dest = (uint32_t) dest;
3409#endif
bellard57fec1f2008-02-01 10:50:11 +00003410 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
aurel328cbcb4f2008-05-10 23:28:14 +00003411 likely(!ctx->singlestep_enabled)) {
bellard57fec1f2008-02-01 10:50:11 +00003412 tcg_gen_goto_tb(n);
aurel32a2ffb812008-10-21 16:31:31 +00003413 tcg_gen_movi_tl(cpu_nip, dest & ~3);
Stefan Weil4b4a72e2011-04-02 13:36:31 +02003414 tcg_gen_exit_tb((tcg_target_long)tb + n);
bellardc1942362005-11-20 10:31:08 +00003415 } else {
aurel32a2ffb812008-10-21 16:31:31 +00003416 tcg_gen_movi_tl(cpu_nip, dest & ~3);
aurel328cbcb4f2008-05-10 23:28:14 +00003417 if (unlikely(ctx->singlestep_enabled)) {
3418 if ((ctx->singlestep_enabled &
aurel32bdc4e052008-11-09 17:27:03 +00003419 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
aurel328cbcb4f2008-05-10 23:28:14 +00003420 ctx->exception == POWERPC_EXCP_BRANCH) {
3421 target_ulong tmp = ctx->nip;
3422 ctx->nip = dest;
aurel32e06fcd72008-12-11 22:42:14 +00003423 gen_exception(ctx, POWERPC_EXCP_TRACE);
aurel328cbcb4f2008-05-10 23:28:14 +00003424 ctx->nip = tmp;
3425 }
3426 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
aurel32e06fcd72008-12-11 22:42:14 +00003427 gen_debug_exception(ctx);
aurel328cbcb4f2008-05-10 23:28:14 +00003428 }
3429 }
bellard57fec1f2008-02-01 10:50:11 +00003430 tcg_gen_exit_tb(0);
bellardc1942362005-11-20 10:31:08 +00003431 }
bellardc53be332005-10-30 21:39:19 +00003432}
3433
Blue Swirl636aa202009-08-16 09:06:54 +00003434static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
j_mayere1833e12007-09-29 13:06:16 +00003435{
3436#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003437 if (ctx->sf_mode == 0)
3438 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
j_mayere1833e12007-09-29 13:06:16 +00003439 else
3440#endif
aurel32a2ffb812008-10-21 16:31:31 +00003441 tcg_gen_movi_tl(cpu_lr, nip);
j_mayere1833e12007-09-29 13:06:16 +00003442}
3443
bellard79aceca2003-11-23 14:55:54 +00003444/* b ba bl bla */
Blue Swirl99e300e2009-06-17 15:22:09 +00003445static void gen_b(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003446{
j_mayer76a66252007-03-07 08:32:30 +00003447 target_ulong li, target;
bellard38a64f92004-07-07 22:06:01 +00003448
aurel328cbcb4f2008-05-10 23:28:14 +00003449 ctx->exception = POWERPC_EXCP_BRANCH;
bellard38a64f92004-07-07 22:06:01 +00003450 /* sign extend LI */
j_mayer76a66252007-03-07 08:32:30 +00003451#if defined(TARGET_PPC64)
j_mayerd9bce9d2007-03-17 14:02:15 +00003452 if (ctx->sf_mode)
3453 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3454 else
j_mayer76a66252007-03-07 08:32:30 +00003455#endif
j_mayerd9bce9d2007-03-17 14:02:15 +00003456 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
j_mayer76a66252007-03-07 08:32:30 +00003457 if (likely(AA(ctx->opcode) == 0))
bellard046d6672004-04-25 21:15:35 +00003458 target = ctx->nip + li - 4;
bellard79aceca2003-11-23 14:55:54 +00003459 else
bellard9a64fbe2004-01-04 22:58:38 +00003460 target = li;
j_mayere1833e12007-09-29 13:06:16 +00003461 if (LK(ctx->opcode))
3462 gen_setlr(ctx, ctx->nip);
David Gibson697ab892011-08-31 15:45:10 +00003463 gen_update_cfar(ctx, ctx->nip);
bellardc1942362005-11-20 10:31:08 +00003464 gen_goto_tb(ctx, 0, target);
bellard79aceca2003-11-23 14:55:54 +00003465}
3466
bellarde98a6e42004-02-21 15:35:00 +00003467#define BCOND_IM 0
3468#define BCOND_LR 1
3469#define BCOND_CTR 2
bellard79aceca2003-11-23 14:55:54 +00003470
Blue Swirl636aa202009-08-16 09:06:54 +00003471static inline void gen_bcond(DisasContext *ctx, int type)
j_mayerd9bce9d2007-03-17 14:02:15 +00003472{
j_mayerd9bce9d2007-03-17 14:02:15 +00003473 uint32_t bo = BO(ctx->opcode);
Blue Swirl05f92402010-04-25 20:32:49 +00003474 int l1;
aurel32a2ffb812008-10-21 16:31:31 +00003475 TCGv target;
bellard79aceca2003-11-23 14:55:54 +00003476
aurel328cbcb4f2008-05-10 23:28:14 +00003477 ctx->exception = POWERPC_EXCP_BRANCH;
aurel32a2ffb812008-10-21 16:31:31 +00003478 if (type == BCOND_LR || type == BCOND_CTR) {
pbrooka7812ae2008-11-17 14:43:54 +00003479 target = tcg_temp_local_new();
aurel32a2ffb812008-10-21 16:31:31 +00003480 if (type == BCOND_CTR)
3481 tcg_gen_mov_tl(target, cpu_ctr);
3482 else
3483 tcg_gen_mov_tl(target, cpu_lr);
malcd2e9fd82009-06-20 05:51:47 +04003484 } else {
3485 TCGV_UNUSED(target);
bellarde98a6e42004-02-21 15:35:00 +00003486 }
j_mayere1833e12007-09-29 13:06:16 +00003487 if (LK(ctx->opcode))
3488 gen_setlr(ctx, ctx->nip);
aurel32a2ffb812008-10-21 16:31:31 +00003489 l1 = gen_new_label();
3490 if ((bo & 0x4) == 0) {
3491 /* Decrement and test CTR */
pbrooka7812ae2008-11-17 14:43:54 +00003492 TCGv temp = tcg_temp_new();
aurel32a2ffb812008-10-21 16:31:31 +00003493 if (unlikely(type == BCOND_CTR)) {
aurel32e06fcd72008-12-11 22:42:14 +00003494 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
aurel32a2ffb812008-10-21 16:31:31 +00003495 return;
bellarde98a6e42004-02-21 15:35:00 +00003496 }
aurel32a2ffb812008-10-21 16:31:31 +00003497 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003498#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003499 if (!ctx->sf_mode)
3500 tcg_gen_ext32u_tl(temp, cpu_ctr);
3501 else
j_mayerd9bce9d2007-03-17 14:02:15 +00003502#endif
aurel32a2ffb812008-10-21 16:31:31 +00003503 tcg_gen_mov_tl(temp, cpu_ctr);
3504 if (bo & 0x2) {
3505 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003506 } else {
aurel32a2ffb812008-10-21 16:31:31 +00003507 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3508 }
pbrooka7812ae2008-11-17 14:43:54 +00003509 tcg_temp_free(temp);
aurel32a2ffb812008-10-21 16:31:31 +00003510 }
3511 if ((bo & 0x10) == 0) {
3512 /* Test CR */
3513 uint32_t bi = BI(ctx->opcode);
3514 uint32_t mask = 1 << (3 - (bi & 0x03));
pbrooka7812ae2008-11-17 14:43:54 +00003515 TCGv_i32 temp = tcg_temp_new_i32();
aurel32a2ffb812008-10-21 16:31:31 +00003516
3517 if (bo & 0x8) {
3518 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3519 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3520 } else {
3521 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3522 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003523 }
pbrooka7812ae2008-11-17 14:43:54 +00003524 tcg_temp_free_i32(temp);
j_mayerd9bce9d2007-03-17 14:02:15 +00003525 }
David Gibson697ab892011-08-31 15:45:10 +00003526 gen_update_cfar(ctx, ctx->nip);
bellarde98a6e42004-02-21 15:35:00 +00003527 if (type == BCOND_IM) {
aurel32a2ffb812008-10-21 16:31:31 +00003528 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3529 if (likely(AA(ctx->opcode) == 0)) {
3530 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3531 } else {
3532 gen_goto_tb(ctx, 0, li);
3533 }
bellardc53be332005-10-30 21:39:19 +00003534 gen_set_label(l1);
bellardc1942362005-11-20 10:31:08 +00003535 gen_goto_tb(ctx, 1, ctx->nip);
bellarde98a6e42004-02-21 15:35:00 +00003536 } else {
j_mayerd9bce9d2007-03-17 14:02:15 +00003537#if defined(TARGET_PPC64)
aurel32a2ffb812008-10-21 16:31:31 +00003538 if (!(ctx->sf_mode))
3539 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
j_mayerd9bce9d2007-03-17 14:02:15 +00003540 else
3541#endif
aurel32a2ffb812008-10-21 16:31:31 +00003542 tcg_gen_andi_tl(cpu_nip, target, ~3);
3543 tcg_gen_exit_tb(0);
3544 gen_set_label(l1);
3545#if defined(TARGET_PPC64)
3546 if (!(ctx->sf_mode))
3547 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3548 else
3549#endif
3550 tcg_gen_movi_tl(cpu_nip, ctx->nip);
bellard57fec1f2008-02-01 10:50:11 +00003551 tcg_gen_exit_tb(0);
j_mayer08e46e52007-04-16 07:18:42 +00003552 }
bellarde98a6e42004-02-21 15:35:00 +00003553}
3554
Blue Swirl99e300e2009-06-17 15:22:09 +00003555static void gen_bc(DisasContext *ctx)
ths3b46e622007-09-17 08:09:54 +00003556{
bellarde98a6e42004-02-21 15:35:00 +00003557 gen_bcond(ctx, BCOND_IM);
3558}
3559
Blue Swirl99e300e2009-06-17 15:22:09 +00003560static void gen_bcctr(DisasContext *ctx)
ths3b46e622007-09-17 08:09:54 +00003561{
bellarde98a6e42004-02-21 15:35:00 +00003562 gen_bcond(ctx, BCOND_CTR);
3563}
3564
Blue Swirl99e300e2009-06-17 15:22:09 +00003565static void gen_bclr(DisasContext *ctx)
ths3b46e622007-09-17 08:09:54 +00003566{
bellarde98a6e42004-02-21 15:35:00 +00003567 gen_bcond(ctx, BCOND_LR);
3568}
bellard79aceca2003-11-23 14:55:54 +00003569
3570/*** Condition register logical ***/
aurel32e1571902008-10-21 11:31:14 +00003571#define GEN_CRLOGIC(name, tcg_op, opc) \
Blue Swirl99e300e2009-06-17 15:22:09 +00003572static void glue(gen_, name)(DisasContext *ctx) \
bellard79aceca2003-11-23 14:55:54 +00003573{ \
j_mayerfc0d4412007-10-31 22:02:17 +00003574 uint8_t bitmask; \
3575 int sh; \
pbrooka7812ae2008-11-17 14:43:54 +00003576 TCGv_i32 t0, t1; \
j_mayerfc0d4412007-10-31 22:02:17 +00003577 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
pbrooka7812ae2008-11-17 14:43:54 +00003578 t0 = tcg_temp_new_i32(); \
j_mayerfc0d4412007-10-31 22:02:17 +00003579 if (sh > 0) \
aurel32fea0c502008-11-02 08:22:34 +00003580 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
j_mayerfc0d4412007-10-31 22:02:17 +00003581 else if (sh < 0) \
aurel32fea0c502008-11-02 08:22:34 +00003582 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
aurel32e1571902008-10-21 11:31:14 +00003583 else \
aurel32fea0c502008-11-02 08:22:34 +00003584 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
pbrooka7812ae2008-11-17 14:43:54 +00003585 t1 = tcg_temp_new_i32(); \
j_mayerfc0d4412007-10-31 22:02:17 +00003586 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3587 if (sh > 0) \
aurel32fea0c502008-11-02 08:22:34 +00003588 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
j_mayerfc0d4412007-10-31 22:02:17 +00003589 else if (sh < 0) \
aurel32fea0c502008-11-02 08:22:34 +00003590 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
aurel32e1571902008-10-21 11:31:14 +00003591 else \
aurel32fea0c502008-11-02 08:22:34 +00003592 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3593 tcg_op(t0, t0, t1); \
j_mayerfc0d4412007-10-31 22:02:17 +00003594 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
aurel32fea0c502008-11-02 08:22:34 +00003595 tcg_gen_andi_i32(t0, t0, bitmask); \
3596 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3597 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
pbrooka7812ae2008-11-17 14:43:54 +00003598 tcg_temp_free_i32(t0); \
3599 tcg_temp_free_i32(t1); \
bellard79aceca2003-11-23 14:55:54 +00003600}
3601
3602/* crand */
aurel32e1571902008-10-21 11:31:14 +00003603GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
bellard79aceca2003-11-23 14:55:54 +00003604/* crandc */
aurel32e1571902008-10-21 11:31:14 +00003605GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
bellard79aceca2003-11-23 14:55:54 +00003606/* creqv */
aurel32e1571902008-10-21 11:31:14 +00003607GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
bellard79aceca2003-11-23 14:55:54 +00003608/* crnand */
aurel32e1571902008-10-21 11:31:14 +00003609GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
bellard79aceca2003-11-23 14:55:54 +00003610/* crnor */
aurel32e1571902008-10-21 11:31:14 +00003611GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
bellard79aceca2003-11-23 14:55:54 +00003612/* cror */
aurel32e1571902008-10-21 11:31:14 +00003613GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
bellard79aceca2003-11-23 14:55:54 +00003614/* crorc */
aurel32e1571902008-10-21 11:31:14 +00003615GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
bellard79aceca2003-11-23 14:55:54 +00003616/* crxor */
aurel32e1571902008-10-21 11:31:14 +00003617GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
Blue Swirl99e300e2009-06-17 15:22:09 +00003618
Blue Swirl54623272009-06-17 15:22:19 +00003619/* mcrf */
Blue Swirl99e300e2009-06-17 15:22:09 +00003620static void gen_mcrf(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003621{
aurel3247e46612008-09-04 17:06:47 +00003622 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
bellard79aceca2003-11-23 14:55:54 +00003623}
3624
3625/*** System linkage ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00003626
Blue Swirl54623272009-06-17 15:22:19 +00003627/* rfi (mem_idx only) */
Blue Swirl99e300e2009-06-17 15:22:09 +00003628static void gen_rfi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003629{
bellard9a64fbe2004-01-04 22:58:38 +00003630#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9a64fbe2004-01-04 22:58:38 +00003632#else
3633 /* Restore CPU state */
aurel3276db3ba2008-12-08 18:11:21 +00003634 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00003635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9fddaa02004-05-21 12:59:32 +00003636 return;
bellard9a64fbe2004-01-04 22:58:38 +00003637 }
David Gibson697ab892011-08-31 15:45:10 +00003638 gen_update_cfar(ctx, ctx->nip);
aurel32d72a19f2008-11-30 16:24:55 +00003639 gen_helper_rfi();
aurel32e06fcd72008-12-11 22:42:14 +00003640 gen_sync_exception(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00003641#endif
bellard79aceca2003-11-23 14:55:54 +00003642}
3643
j_mayer426613d2007-03-23 09:45:27 +00003644#if defined(TARGET_PPC64)
Blue Swirl99e300e2009-06-17 15:22:09 +00003645static void gen_rfid(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00003646{
3647#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00003649#else
3650 /* Restore CPU state */
aurel3276db3ba2008-12-08 18:11:21 +00003651 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00003652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00003653 return;
3654 }
David Gibson697ab892011-08-31 15:45:10 +00003655 gen_update_cfar(ctx, ctx->nip);
aurel32d72a19f2008-11-30 16:24:55 +00003656 gen_helper_rfid();
aurel32e06fcd72008-12-11 22:42:14 +00003657 gen_sync_exception(ctx);
j_mayer426613d2007-03-23 09:45:27 +00003658#endif
3659}
j_mayer426613d2007-03-23 09:45:27 +00003660
Blue Swirl99e300e2009-06-17 15:22:09 +00003661static void gen_hrfid(DisasContext *ctx)
j_mayerbe147d02007-09-30 13:03:23 +00003662{
3663#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00003665#else
3666 /* Restore CPU state */
aurel3276db3ba2008-12-08 18:11:21 +00003667 if (unlikely(ctx->mem_idx <= 1)) {
aurel32e06fcd72008-12-11 22:42:14 +00003668 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayerbe147d02007-09-30 13:03:23 +00003669 return;
3670 }
aurel32d72a19f2008-11-30 16:24:55 +00003671 gen_helper_hrfid();
aurel32e06fcd72008-12-11 22:42:14 +00003672 gen_sync_exception(ctx);
j_mayerbe147d02007-09-30 13:03:23 +00003673#endif
3674}
3675#endif
3676
bellard79aceca2003-11-23 14:55:54 +00003677/* sc */
j_mayer417bf012007-10-07 23:10:08 +00003678#if defined(CONFIG_USER_ONLY)
3679#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3680#else
3681#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3682#endif
Blue Swirl99e300e2009-06-17 15:22:09 +00003683static void gen_sc(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003684{
j_mayere1833e12007-09-29 13:06:16 +00003685 uint32_t lev;
3686
3687 lev = (ctx->opcode >> 5) & 0x7F;
aurel32e06fcd72008-12-11 22:42:14 +00003688 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
bellard79aceca2003-11-23 14:55:54 +00003689}
3690
3691/*** Trap ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00003692
Blue Swirl54623272009-06-17 15:22:19 +00003693/* tw */
Blue Swirl99e300e2009-06-17 15:22:09 +00003694static void gen_tw(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003695{
aurel32cab3bee2008-11-24 11:28:19 +00003696 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
Aurelien Jarnodb9a2312010-02-28 16:02:28 +01003697 /* Update the nip since this might generate a trap exception */
3698 gen_update_nip(ctx, ctx->nip);
aurel32cab3bee2008-11-24 11:28:19 +00003699 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3700 tcg_temp_free_i32(t0);
bellard79aceca2003-11-23 14:55:54 +00003701}
3702
3703/* twi */
Blue Swirl99e300e2009-06-17 15:22:09 +00003704static void gen_twi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003705{
aurel32cab3bee2008-11-24 11:28:19 +00003706 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3707 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
Aurelien Jarnodb9a2312010-02-28 16:02:28 +01003708 /* Update the nip since this might generate a trap exception */
3709 gen_update_nip(ctx, ctx->nip);
aurel32cab3bee2008-11-24 11:28:19 +00003710 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3711 tcg_temp_free(t0);
3712 tcg_temp_free_i32(t1);
bellard79aceca2003-11-23 14:55:54 +00003713}
3714
j_mayerd9bce9d2007-03-17 14:02:15 +00003715#if defined(TARGET_PPC64)
3716/* td */
Blue Swirl99e300e2009-06-17 15:22:09 +00003717static void gen_td(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00003718{
aurel32cab3bee2008-11-24 11:28:19 +00003719 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
Aurelien Jarnodb9a2312010-02-28 16:02:28 +01003720 /* Update the nip since this might generate a trap exception */
3721 gen_update_nip(ctx, ctx->nip);
aurel32cab3bee2008-11-24 11:28:19 +00003722 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3723 tcg_temp_free_i32(t0);
j_mayerd9bce9d2007-03-17 14:02:15 +00003724}
3725
3726/* tdi */
Blue Swirl99e300e2009-06-17 15:22:09 +00003727static void gen_tdi(DisasContext *ctx)
j_mayerd9bce9d2007-03-17 14:02:15 +00003728{
aurel32cab3bee2008-11-24 11:28:19 +00003729 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3730 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
Aurelien Jarnodb9a2312010-02-28 16:02:28 +01003731 /* Update the nip since this might generate a trap exception */
3732 gen_update_nip(ctx, ctx->nip);
aurel32cab3bee2008-11-24 11:28:19 +00003733 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3734 tcg_temp_free(t0);
3735 tcg_temp_free_i32(t1);
j_mayerd9bce9d2007-03-17 14:02:15 +00003736}
3737#endif
3738
bellard79aceca2003-11-23 14:55:54 +00003739/*** Processor control ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00003740
Blue Swirl54623272009-06-17 15:22:19 +00003741/* mcrxr */
Blue Swirl99e300e2009-06-17 15:22:09 +00003742static void gen_mcrxr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003743{
aurel323d7b4172008-10-21 11:28:46 +00003744 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3745 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
aurel32269f3e92008-11-01 00:53:48 +00003746 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
bellard79aceca2003-11-23 14:55:54 +00003747}
3748
aurel320cfe11e2009-03-03 06:12:14 +00003749/* mfcr mfocrf */
Blue Swirl99e300e2009-06-17 15:22:09 +00003750static void gen_mfcr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003751{
j_mayer76a66252007-03-07 08:32:30 +00003752 uint32_t crm, crn;
ths3b46e622007-09-17 08:09:54 +00003753
j_mayer76a66252007-03-07 08:32:30 +00003754 if (likely(ctx->opcode & 0x00100000)) {
3755 crm = CRM(ctx->opcode);
malc8dd640e2009-03-02 22:39:39 +00003756 if (likely(crm && ((crm & (crm - 1)) == 0))) {
aurel320cfe11e2009-03-03 06:12:14 +00003757 crn = ctz32 (crm);
aurel32e1571902008-10-21 11:31:14 +00003758 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
aurel320497d2f2009-03-07 20:57:47 +00003759 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3760 cpu_gpr[rD(ctx->opcode)], crn * 4);
j_mayer76a66252007-03-07 08:32:30 +00003761 }
j_mayerd9bce9d2007-03-17 14:02:15 +00003762 } else {
aurel32651721b2009-03-09 18:50:24 +00003763 TCGv_i32 t0 = tcg_temp_new_i32();
3764 tcg_gen_mov_i32(t0, cpu_crf[0]);
3765 tcg_gen_shli_i32(t0, t0, 4);
3766 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3767 tcg_gen_shli_i32(t0, t0, 4);
3768 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3769 tcg_gen_shli_i32(t0, t0, 4);
3770 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3771 tcg_gen_shli_i32(t0, t0, 4);
3772 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3773 tcg_gen_shli_i32(t0, t0, 4);
3774 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3775 tcg_gen_shli_i32(t0, t0, 4);
3776 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3777 tcg_gen_shli_i32(t0, t0, 4);
3778 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3779 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3780 tcg_temp_free_i32(t0);
j_mayerd9bce9d2007-03-17 14:02:15 +00003781 }
bellard79aceca2003-11-23 14:55:54 +00003782}
3783
3784/* mfmsr */
Blue Swirl99e300e2009-06-17 15:22:09 +00003785static void gen_mfmsr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003786{
bellard9a64fbe2004-01-04 22:58:38 +00003787#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003788 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00003789#else
aurel3276db3ba2008-12-08 18:11:21 +00003790 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00003791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00003792 return;
bellard9a64fbe2004-01-04 22:58:38 +00003793 }
aurel326527f6e2008-12-06 13:03:35 +00003794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
bellard9a64fbe2004-01-04 22:58:38 +00003795#endif
bellard79aceca2003-11-23 14:55:54 +00003796}
3797
Blue Swirl7b134482010-04-18 14:26:51 +00003798static void spr_noaccess(void *opaque, int gprn, int sprn)
bellard79aceca2003-11-23 14:55:54 +00003799{
Blue Swirl7b134482010-04-18 14:26:51 +00003800#if 0
bellard3fc6c082005-07-02 20:59:34 +00003801 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3802 printf("ERROR: try to access SPR %d !\n", sprn);
Blue Swirl7b134482010-04-18 14:26:51 +00003803#endif
bellard3fc6c082005-07-02 20:59:34 +00003804}
3805#define SPR_NOACCESS (&spr_noaccess)
bellard3fc6c082005-07-02 20:59:34 +00003806
3807/* mfspr */
Blue Swirl636aa202009-08-16 09:06:54 +00003808static inline void gen_op_mfspr(DisasContext *ctx)
bellard3fc6c082005-07-02 20:59:34 +00003809{
aurel3245d827d2008-12-07 13:40:29 +00003810 void (*read_cb)(void *opaque, int gprn, int sprn);
bellard79aceca2003-11-23 14:55:54 +00003811 uint32_t sprn = SPR(ctx->opcode);
3812
bellard3fc6c082005-07-02 20:59:34 +00003813#if !defined(CONFIG_USER_ONLY)
aurel3276db3ba2008-12-08 18:11:21 +00003814 if (ctx->mem_idx == 2)
j_mayerbe147d02007-09-30 13:03:23 +00003815 read_cb = ctx->spr_cb[sprn].hea_read;
aurel3276db3ba2008-12-08 18:11:21 +00003816 else if (ctx->mem_idx)
bellard3fc6c082005-07-02 20:59:34 +00003817 read_cb = ctx->spr_cb[sprn].oea_read;
3818 else
bellard9a64fbe2004-01-04 22:58:38 +00003819#endif
bellard3fc6c082005-07-02 20:59:34 +00003820 read_cb = ctx->spr_cb[sprn].uea_read;
j_mayer76a66252007-03-07 08:32:30 +00003821 if (likely(read_cb != NULL)) {
3822 if (likely(read_cb != SPR_NOACCESS)) {
aurel3245d827d2008-12-07 13:40:29 +00003823 (*read_cb)(ctx, rD(ctx->opcode), sprn);
bellard3fc6c082005-07-02 20:59:34 +00003824 } else {
3825 /* Privilege exception */
j_mayer9fceefa2007-11-02 22:47:50 +00003826 /* This is a hack to avoid warnings when running Linux:
3827 * this OS breaks the PowerPC virtualisation model,
3828 * allowing userland application to read the PVR
3829 */
3830 if (sprn != SPR_PVR) {
aliguori93fcfe32009-01-15 22:34:14 +00003831 qemu_log("Trying to read privileged spr %d %03x at "
Blue Swirl90e189e2009-08-16 11:13:18 +00003832 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3833 printf("Trying to read privileged spr %d %03x at "
3834 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
bellardf24e5692005-11-23 21:36:30 +00003835 }
aurel32e06fcd72008-12-11 22:42:14 +00003836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard79aceca2003-11-23 14:55:54 +00003837 }
bellard3fc6c082005-07-02 20:59:34 +00003838 } else {
3839 /* Not defined */
aliguori93fcfe32009-01-15 22:34:14 +00003840 qemu_log("Trying to read invalid spr %d %03x at "
Blue Swirl90e189e2009-08-16 11:13:18 +00003841 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3842 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
j_mayer077fc202007-11-04 01:57:29 +00003843 sprn, sprn, ctx->nip);
aurel32e06fcd72008-12-11 22:42:14 +00003844 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
bellard79aceca2003-11-23 14:55:54 +00003845 }
bellard79aceca2003-11-23 14:55:54 +00003846}
3847
Blue Swirl99e300e2009-06-17 15:22:09 +00003848static void gen_mfspr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003849{
bellard3fc6c082005-07-02 20:59:34 +00003850 gen_op_mfspr(ctx);
j_mayer76a66252007-03-07 08:32:30 +00003851}
bellard3fc6c082005-07-02 20:59:34 +00003852
3853/* mftb */
Blue Swirl99e300e2009-06-17 15:22:09 +00003854static void gen_mftb(DisasContext *ctx)
bellard3fc6c082005-07-02 20:59:34 +00003855{
3856 gen_op_mfspr(ctx);
bellard79aceca2003-11-23 14:55:54 +00003857}
3858
aurel320cfe11e2009-03-03 06:12:14 +00003859/* mtcrf mtocrf*/
Blue Swirl99e300e2009-06-17 15:22:09 +00003860static void gen_mtcrf(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003861{
j_mayer76a66252007-03-07 08:32:30 +00003862 uint32_t crm, crn;
ths3b46e622007-09-17 08:09:54 +00003863
j_mayer76a66252007-03-07 08:32:30 +00003864 crm = CRM(ctx->opcode);
malc8dd640e2009-03-02 22:39:39 +00003865 if (likely((ctx->opcode & 0x00100000))) {
3866 if (crm && ((crm & (crm - 1)) == 0)) {
3867 TCGv_i32 temp = tcg_temp_new_i32();
aurel320cfe11e2009-03-03 06:12:14 +00003868 crn = ctz32 (crm);
malc8dd640e2009-03-02 22:39:39 +00003869 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
aurel320cfe11e2009-03-03 06:12:14 +00003870 tcg_gen_shri_i32(temp, temp, crn * 4);
3871 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
malc8dd640e2009-03-02 22:39:39 +00003872 tcg_temp_free_i32(temp);
3873 }
j_mayer76a66252007-03-07 08:32:30 +00003874 } else {
aurel32651721b2009-03-09 18:50:24 +00003875 TCGv_i32 temp = tcg_temp_new_i32();
3876 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3877 for (crn = 0 ; crn < 8 ; crn++) {
3878 if (crm & (1 << crn)) {
3879 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3880 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3881 }
3882 }
pbrooka7812ae2008-11-17 14:43:54 +00003883 tcg_temp_free_i32(temp);
j_mayer76a66252007-03-07 08:32:30 +00003884 }
bellard79aceca2003-11-23 14:55:54 +00003885}
3886
3887/* mtmsr */
j_mayer426613d2007-03-23 09:45:27 +00003888#if defined(TARGET_PPC64)
Blue Swirl99e300e2009-06-17 15:22:09 +00003889static void gen_mtmsrd(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00003890{
3891#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003892 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer426613d2007-03-23 09:45:27 +00003893#else
aurel3276db3ba2008-12-08 18:11:21 +00003894 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00003895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer426613d2007-03-23 09:45:27 +00003896 return;
3897 }
j_mayerbe147d02007-09-30 13:03:23 +00003898 if (ctx->opcode & 0x00010000) {
3899 /* Special form that does not need any synchronisation */
aurel326527f6e2008-12-06 13:03:35 +00003900 TCGv t0 = tcg_temp_new();
3901 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3902 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3903 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3904 tcg_temp_free(t0);
j_mayerbe147d02007-09-30 13:03:23 +00003905 } else {
j_mayer056b05f2007-10-01 03:03:51 +00003906 /* XXX: we need to update nip before the store
3907 * if we enter power saving mode, we will exit the loop
3908 * directly from ppc_store_msr
3909 */
j_mayerbe147d02007-09-30 13:03:23 +00003910 gen_update_nip(ctx, ctx->nip);
aurel326527f6e2008-12-06 13:03:35 +00003911 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
j_mayerbe147d02007-09-30 13:03:23 +00003912 /* Must stop the translation as machine state (may have) changed */
3913 /* Note that mtmsr is not always defined as context-synchronizing */
aurel32e06fcd72008-12-11 22:42:14 +00003914 gen_stop_exception(ctx);
j_mayerbe147d02007-09-30 13:03:23 +00003915 }
j_mayer426613d2007-03-23 09:45:27 +00003916#endif
3917}
3918#endif
3919
Blue Swirl99e300e2009-06-17 15:22:09 +00003920static void gen_mtmsr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003921{
bellard9a64fbe2004-01-04 22:58:38 +00003922#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00003923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00003924#else
aurel3276db3ba2008-12-08 18:11:21 +00003925 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00003926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00003927 return;
bellard9a64fbe2004-01-04 22:58:38 +00003928 }
j_mayerbe147d02007-09-30 13:03:23 +00003929 if (ctx->opcode & 0x00010000) {
3930 /* Special form that does not need any synchronisation */
aurel326527f6e2008-12-06 13:03:35 +00003931 TCGv t0 = tcg_temp_new();
3932 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3933 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3934 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3935 tcg_temp_free(t0);
j_mayerbe147d02007-09-30 13:03:23 +00003936 } else {
Alexander Graf8018dc62011-06-16 10:44:23 +02003937 TCGv msr = tcg_temp_new();
3938
j_mayer056b05f2007-10-01 03:03:51 +00003939 /* XXX: we need to update nip before the store
3940 * if we enter power saving mode, we will exit the loop
3941 * directly from ppc_store_msr
3942 */
j_mayerbe147d02007-09-30 13:03:23 +00003943 gen_update_nip(ctx, ctx->nip);
j_mayerd9bce9d2007-03-17 14:02:15 +00003944#if defined(TARGET_PPC64)
Alexander Graf8018dc62011-06-16 10:44:23 +02003945 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3946#else
3947 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
j_mayerd9bce9d2007-03-17 14:02:15 +00003948#endif
Alexander Graf8018dc62011-06-16 10:44:23 +02003949 gen_helper_store_msr(msr);
j_mayerbe147d02007-09-30 13:03:23 +00003950 /* Must stop the translation as machine state (may have) changed */
aurel326527f6e2008-12-06 13:03:35 +00003951 /* Note that mtmsr is not always defined as context-synchronizing */
aurel32e06fcd72008-12-11 22:42:14 +00003952 gen_stop_exception(ctx);
j_mayerbe147d02007-09-30 13:03:23 +00003953 }
bellard9a64fbe2004-01-04 22:58:38 +00003954#endif
bellard79aceca2003-11-23 14:55:54 +00003955}
3956
3957/* mtspr */
Blue Swirl99e300e2009-06-17 15:22:09 +00003958static void gen_mtspr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003959{
aurel3245d827d2008-12-07 13:40:29 +00003960 void (*write_cb)(void *opaque, int sprn, int gprn);
bellard79aceca2003-11-23 14:55:54 +00003961 uint32_t sprn = SPR(ctx->opcode);
3962
bellard3fc6c082005-07-02 20:59:34 +00003963#if !defined(CONFIG_USER_ONLY)
aurel3276db3ba2008-12-08 18:11:21 +00003964 if (ctx->mem_idx == 2)
j_mayerbe147d02007-09-30 13:03:23 +00003965 write_cb = ctx->spr_cb[sprn].hea_write;
aurel3276db3ba2008-12-08 18:11:21 +00003966 else if (ctx->mem_idx)
bellard3fc6c082005-07-02 20:59:34 +00003967 write_cb = ctx->spr_cb[sprn].oea_write;
3968 else
bellard9a64fbe2004-01-04 22:58:38 +00003969#endif
bellard3fc6c082005-07-02 20:59:34 +00003970 write_cb = ctx->spr_cb[sprn].uea_write;
j_mayer76a66252007-03-07 08:32:30 +00003971 if (likely(write_cb != NULL)) {
3972 if (likely(write_cb != SPR_NOACCESS)) {
aurel3245d827d2008-12-07 13:40:29 +00003973 (*write_cb)(ctx, sprn, rS(ctx->opcode));
bellard3fc6c082005-07-02 20:59:34 +00003974 } else {
3975 /* Privilege exception */
aliguori93fcfe32009-01-15 22:34:14 +00003976 qemu_log("Trying to write privileged spr %d %03x at "
Blue Swirl90e189e2009-08-16 11:13:18 +00003977 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3978 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3979 "\n", sprn, sprn, ctx->nip);
aurel32e06fcd72008-12-11 22:42:14 +00003980 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer76a66252007-03-07 08:32:30 +00003981 }
bellard3fc6c082005-07-02 20:59:34 +00003982 } else {
3983 /* Not defined */
aliguori93fcfe32009-01-15 22:34:14 +00003984 qemu_log("Trying to write invalid spr %d %03x at "
Blue Swirl90e189e2009-08-16 11:13:18 +00003985 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3986 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
j_mayer077fc202007-11-04 01:57:29 +00003987 sprn, sprn, ctx->nip);
aurel32e06fcd72008-12-11 22:42:14 +00003988 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
bellard9a64fbe2004-01-04 22:58:38 +00003989 }
bellard79aceca2003-11-23 14:55:54 +00003990}
3991
3992/*** Cache management ***/
Blue Swirl99e300e2009-06-17 15:22:09 +00003993
Blue Swirl54623272009-06-17 15:22:19 +00003994/* dcbf */
Blue Swirl99e300e2009-06-17 15:22:09 +00003995static void gen_dcbf(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00003996{
j_mayerdac454a2007-10-26 00:48:00 +00003997 /* XXX: specification says this is treated as a load by the MMU */
aurel3276db3ba2008-12-08 18:11:21 +00003998 TCGv t0;
3999 gen_set_access_type(ctx, ACCESS_CACHE);
4000 t0 = tcg_temp_new();
4001 gen_addr_reg_index(ctx, t0);
4002 gen_qemu_ld8u(ctx, t0, t0);
aurel32fea0c502008-11-02 08:22:34 +00004003 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004004}
4005
4006/* dcbi (Supervisor only) */
Blue Swirl99e300e2009-06-17 15:22:09 +00004007static void gen_dcbi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004008{
bellarda541f292004-04-12 20:39:29 +00004009#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellarda541f292004-04-12 20:39:29 +00004011#else
aurel32b61f2752008-10-15 17:00:37 +00004012 TCGv EA, val;
aurel3276db3ba2008-12-08 18:11:21 +00004013 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004014 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9fddaa02004-05-21 12:59:32 +00004015 return;
bellard9a64fbe2004-01-04 22:58:38 +00004016 }
pbrooka7812ae2008-11-17 14:43:54 +00004017 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00004018 gen_set_access_type(ctx, ACCESS_CACHE);
4019 gen_addr_reg_index(ctx, EA);
pbrooka7812ae2008-11-17 14:43:54 +00004020 val = tcg_temp_new();
j_mayer76a66252007-03-07 08:32:30 +00004021 /* XXX: specification says this should be treated as a store by the MMU */
aurel3276db3ba2008-12-08 18:11:21 +00004022 gen_qemu_ld8u(ctx, val, EA);
4023 gen_qemu_st8(ctx, val, EA);
aurel32b61f2752008-10-15 17:00:37 +00004024 tcg_temp_free(val);
4025 tcg_temp_free(EA);
bellarda541f292004-04-12 20:39:29 +00004026#endif
bellard79aceca2003-11-23 14:55:54 +00004027}
4028
4029/* dcdst */
Blue Swirl99e300e2009-06-17 15:22:09 +00004030static void gen_dcbst(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004031{
j_mayer76a66252007-03-07 08:32:30 +00004032 /* XXX: specification say this is treated as a load by the MMU */
aurel3276db3ba2008-12-08 18:11:21 +00004033 TCGv t0;
4034 gen_set_access_type(ctx, ACCESS_CACHE);
4035 t0 = tcg_temp_new();
4036 gen_addr_reg_index(ctx, t0);
4037 gen_qemu_ld8u(ctx, t0, t0);
aurel32fea0c502008-11-02 08:22:34 +00004038 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004039}
4040
4041/* dcbt */
Blue Swirl99e300e2009-06-17 15:22:09 +00004042static void gen_dcbt(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004043{
j_mayer0db1b202007-09-30 03:46:38 +00004044 /* interpreted as no-op */
j_mayer76a66252007-03-07 08:32:30 +00004045 /* XXX: specification say this is treated as a load by the MMU
4046 * but does not generate any exception
4047 */
bellard79aceca2003-11-23 14:55:54 +00004048}
4049
4050/* dcbtst */
Blue Swirl99e300e2009-06-17 15:22:09 +00004051static void gen_dcbtst(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004052{
j_mayer0db1b202007-09-30 03:46:38 +00004053 /* interpreted as no-op */
j_mayer76a66252007-03-07 08:32:30 +00004054 /* XXX: specification say this is treated as a load by the MMU
4055 * but does not generate any exception
4056 */
bellard79aceca2003-11-23 14:55:54 +00004057}
4058
4059/* dcbz */
Blue Swirl99e300e2009-06-17 15:22:09 +00004060static void gen_dcbz(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004061{
aurel3276db3ba2008-12-08 18:11:21 +00004062 TCGv t0;
4063 gen_set_access_type(ctx, ACCESS_CACHE);
aurel32799a8c82008-11-30 16:24:05 +00004064 /* NIP cannot be restored if the memory exception comes from an helper */
4065 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00004066 t0 = tcg_temp_new();
4067 gen_addr_reg_index(ctx, t0);
aurel32799a8c82008-11-30 16:24:05 +00004068 gen_helper_dcbz(t0);
4069 tcg_temp_free(t0);
j_mayerd63001d2007-10-04 00:51:58 +00004070}
4071
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004072static void gen_dcbz_970(DisasContext *ctx)
j_mayerd63001d2007-10-04 00:51:58 +00004073{
aurel3276db3ba2008-12-08 18:11:21 +00004074 TCGv t0;
4075 gen_set_access_type(ctx, ACCESS_CACHE);
aurel32799a8c82008-11-30 16:24:05 +00004076 /* NIP cannot be restored if the memory exception comes from an helper */
4077 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00004078 t0 = tcg_temp_new();
4079 gen_addr_reg_index(ctx, t0);
j_mayerd63001d2007-10-04 00:51:58 +00004080 if (ctx->opcode & 0x00200000)
aurel32799a8c82008-11-30 16:24:05 +00004081 gen_helper_dcbz(t0);
j_mayerd63001d2007-10-04 00:51:58 +00004082 else
aurel32799a8c82008-11-30 16:24:05 +00004083 gen_helper_dcbz_970(t0);
4084 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004085}
4086
aurel32ae1c1a32009-01-12 21:33:02 +00004087/* dst / dstt */
Blue Swirl99e300e2009-06-17 15:22:09 +00004088static void gen_dst(DisasContext *ctx)
aurel32ae1c1a32009-01-12 21:33:02 +00004089{
4090 if (rA(ctx->opcode) == 0) {
4091 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4092 } else {
4093 /* interpreted as no-op */
4094 }
4095}
4096
4097/* dstst /dststt */
Blue Swirl99e300e2009-06-17 15:22:09 +00004098static void gen_dstst(DisasContext *ctx)
aurel32ae1c1a32009-01-12 21:33:02 +00004099{
4100 if (rA(ctx->opcode) == 0) {
4101 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4102 } else {
4103 /* interpreted as no-op */
4104 }
4105
4106}
4107
4108/* dss / dssall */
Blue Swirl99e300e2009-06-17 15:22:09 +00004109static void gen_dss(DisasContext *ctx)
aurel32ae1c1a32009-01-12 21:33:02 +00004110{
4111 /* interpreted as no-op */
4112}
4113
bellard79aceca2003-11-23 14:55:54 +00004114/* icbi */
Blue Swirl99e300e2009-06-17 15:22:09 +00004115static void gen_icbi(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004116{
aurel3276db3ba2008-12-08 18:11:21 +00004117 TCGv t0;
4118 gen_set_access_type(ctx, ACCESS_CACHE);
j_mayer30032c92007-10-01 05:22:17 +00004119 /* NIP cannot be restored if the memory exception comes from an helper */
4120 gen_update_nip(ctx, ctx->nip - 4);
aurel3276db3ba2008-12-08 18:11:21 +00004121 t0 = tcg_temp_new();
4122 gen_addr_reg_index(ctx, t0);
aurel3237d269d2008-11-30 16:24:13 +00004123 gen_helper_icbi(t0);
4124 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004125}
4126
4127/* Optional: */
4128/* dcba */
Blue Swirl99e300e2009-06-17 15:22:09 +00004129static void gen_dcba(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004130{
j_mayer0db1b202007-09-30 03:46:38 +00004131 /* interpreted as no-op */
4132 /* XXX: specification say this is treated as a store by the MMU
4133 * but does not generate any exception
4134 */
bellard79aceca2003-11-23 14:55:54 +00004135}
4136
4137/*** Segment register manipulation ***/
4138/* Supervisor only: */
Blue Swirl99e300e2009-06-17 15:22:09 +00004139
Blue Swirl54623272009-06-17 15:22:19 +00004140/* mfsr */
Blue Swirl99e300e2009-06-17 15:22:09 +00004141static void gen_mfsr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004142{
bellard9a64fbe2004-01-04 22:58:38 +00004143#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00004145#else
aurel3274d37792008-12-06 21:46:17 +00004146 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004147 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004148 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00004149 return;
bellard9a64fbe2004-01-04 22:58:38 +00004150 }
aurel3274d37792008-12-06 21:46:17 +00004151 t0 = tcg_const_tl(SR(ctx->opcode));
4152 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4153 tcg_temp_free(t0);
bellard9a64fbe2004-01-04 22:58:38 +00004154#endif
bellard79aceca2003-11-23 14:55:54 +00004155}
4156
4157/* mfsrin */
Blue Swirl99e300e2009-06-17 15:22:09 +00004158static void gen_mfsrin(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004159{
bellard9a64fbe2004-01-04 22:58:38 +00004160#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004161 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00004162#else
aurel3274d37792008-12-06 21:46:17 +00004163 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004164 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00004166 return;
bellard9a64fbe2004-01-04 22:58:38 +00004167 }
aurel3274d37792008-12-06 21:46:17 +00004168 t0 = tcg_temp_new();
4169 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4170 tcg_gen_andi_tl(t0, t0, 0xF);
4171 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4172 tcg_temp_free(t0);
bellard9a64fbe2004-01-04 22:58:38 +00004173#endif
bellard79aceca2003-11-23 14:55:54 +00004174}
4175
4176/* mtsr */
Blue Swirl99e300e2009-06-17 15:22:09 +00004177static void gen_mtsr(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004178{
bellard9a64fbe2004-01-04 22:58:38 +00004179#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00004181#else
aurel3274d37792008-12-06 21:46:17 +00004182 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004183 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00004185 return;
bellard9a64fbe2004-01-04 22:58:38 +00004186 }
aurel3274d37792008-12-06 21:46:17 +00004187 t0 = tcg_const_tl(SR(ctx->opcode));
4188 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4189 tcg_temp_free(t0);
bellard9a64fbe2004-01-04 22:58:38 +00004190#endif
bellard79aceca2003-11-23 14:55:54 +00004191}
4192
4193/* mtsrin */
Blue Swirl99e300e2009-06-17 15:22:09 +00004194static void gen_mtsrin(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004195{
bellard9a64fbe2004-01-04 22:58:38 +00004196#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9a64fbe2004-01-04 22:58:38 +00004198#else
aurel3274d37792008-12-06 21:46:17 +00004199 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004200 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
bellard9fddaa02004-05-21 12:59:32 +00004202 return;
bellard9a64fbe2004-01-04 22:58:38 +00004203 }
aurel3274d37792008-12-06 21:46:17 +00004204 t0 = tcg_temp_new();
4205 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4206 tcg_gen_andi_tl(t0, t0, 0xF);
4207 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4208 tcg_temp_free(t0);
bellard9a64fbe2004-01-04 22:58:38 +00004209#endif
bellard79aceca2003-11-23 14:55:54 +00004210}
4211
j_mayer12de9a32007-10-05 22:06:02 +00004212#if defined(TARGET_PPC64)
4213/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004214
Blue Swirl54623272009-06-17 15:22:19 +00004215/* mfsr */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004216static void gen_mfsr_64b(DisasContext *ctx)
j_mayer12de9a32007-10-05 22:06:02 +00004217{
4218#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004220#else
aurel3274d37792008-12-06 21:46:17 +00004221 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004222 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004224 return;
4225 }
aurel3274d37792008-12-06 21:46:17 +00004226 t0 = tcg_const_tl(SR(ctx->opcode));
blueswir1f6b868fc2009-03-07 20:50:01 +00004227 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
aurel3274d37792008-12-06 21:46:17 +00004228 tcg_temp_free(t0);
j_mayer12de9a32007-10-05 22:06:02 +00004229#endif
4230}
4231
4232/* mfsrin */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004233static void gen_mfsrin_64b(DisasContext *ctx)
j_mayer12de9a32007-10-05 22:06:02 +00004234{
4235#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004237#else
aurel3274d37792008-12-06 21:46:17 +00004238 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004239 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004240 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004241 return;
4242 }
aurel3274d37792008-12-06 21:46:17 +00004243 t0 = tcg_temp_new();
4244 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4245 tcg_gen_andi_tl(t0, t0, 0xF);
blueswir1f6b868fc2009-03-07 20:50:01 +00004246 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
aurel3274d37792008-12-06 21:46:17 +00004247 tcg_temp_free(t0);
j_mayer12de9a32007-10-05 22:06:02 +00004248#endif
4249}
4250
4251/* mtsr */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004252static void gen_mtsr_64b(DisasContext *ctx)
j_mayer12de9a32007-10-05 22:06:02 +00004253{
4254#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004256#else
aurel3274d37792008-12-06 21:46:17 +00004257 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004258 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004260 return;
4261 }
aurel3274d37792008-12-06 21:46:17 +00004262 t0 = tcg_const_tl(SR(ctx->opcode));
blueswir1f6b868fc2009-03-07 20:50:01 +00004263 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
aurel3274d37792008-12-06 21:46:17 +00004264 tcg_temp_free(t0);
j_mayer12de9a32007-10-05 22:06:02 +00004265#endif
4266}
4267
4268/* mtsrin */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004269static void gen_mtsrin_64b(DisasContext *ctx)
j_mayer12de9a32007-10-05 22:06:02 +00004270{
4271#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004273#else
aurel3274d37792008-12-06 21:46:17 +00004274 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00004275 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer12de9a32007-10-05 22:06:02 +00004277 return;
4278 }
aurel3274d37792008-12-06 21:46:17 +00004279 t0 = tcg_temp_new();
4280 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4281 tcg_gen_andi_tl(t0, t0, 0xF);
blueswir1f6b868fc2009-03-07 20:50:01 +00004282 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
aurel3274d37792008-12-06 21:46:17 +00004283 tcg_temp_free(t0);
j_mayer12de9a32007-10-05 22:06:02 +00004284#endif
4285}
blueswir1f6b868fc2009-03-07 20:50:01 +00004286
4287/* slbmte */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00004288static void gen_slbmte(DisasContext *ctx)
blueswir1f6b868fc2009-03-07 20:50:01 +00004289{
4290#if defined(CONFIG_USER_ONLY)
4291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4292#else
4293 if (unlikely(!ctx->mem_idx)) {
4294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4295 return;
4296 }
4297 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4298#endif
4299}
4300
David Gibsonefdef952011-04-01 15:15:11 +11004301static void gen_slbmfee(DisasContext *ctx)
4302{
4303#if defined(CONFIG_USER_ONLY)
4304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4305#else
4306 if (unlikely(!ctx->mem_idx)) {
4307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4308 return;
4309 }
4310 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)],
4311 cpu_gpr[rB(ctx->opcode)]);
4312#endif
4313}
4314
4315static void gen_slbmfev(DisasContext *ctx)
4316{
4317#if defined(CONFIG_USER_ONLY)
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4319#else
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)],
4325 cpu_gpr[rB(ctx->opcode)]);
4326#endif
4327}
j_mayer12de9a32007-10-05 22:06:02 +00004328#endif /* defined(TARGET_PPC64) */
4329
bellard79aceca2003-11-23 14:55:54 +00004330/*** Lookaside buffer management ***/
aurel3276db3ba2008-12-08 18:11:21 +00004331/* Optional & mem_idx only: */
Blue Swirl99e300e2009-06-17 15:22:09 +00004332
Blue Swirl54623272009-06-17 15:22:19 +00004333/* tlbia */
Blue Swirl99e300e2009-06-17 15:22:09 +00004334static void gen_tlbia(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004335{
bellard9a64fbe2004-01-04 22:58:38 +00004336#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9a64fbe2004-01-04 22:58:38 +00004338#else
aurel3276db3ba2008-12-08 18:11:21 +00004339 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9fddaa02004-05-21 12:59:32 +00004341 return;
bellard9a64fbe2004-01-04 22:58:38 +00004342 }
aurel3274d37792008-12-06 21:46:17 +00004343 gen_helper_tlbia();
bellard9a64fbe2004-01-04 22:58:38 +00004344#endif
bellard79aceca2003-11-23 14:55:54 +00004345}
4346
blueswir1bf14b1c2009-03-07 20:52:22 +00004347/* tlbiel */
Blue Swirl99e300e2009-06-17 15:22:09 +00004348static void gen_tlbiel(DisasContext *ctx)
blueswir1bf14b1c2009-03-07 20:52:22 +00004349{
4350#if defined(CONFIG_USER_ONLY)
4351 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4352#else
4353 if (unlikely(!ctx->mem_idx)) {
4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4355 return;
4356 }
4357 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4358#endif
4359}
4360
bellard79aceca2003-11-23 14:55:54 +00004361/* tlbie */
Blue Swirl99e300e2009-06-17 15:22:09 +00004362static void gen_tlbie(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004363{
bellard9a64fbe2004-01-04 22:58:38 +00004364#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004365 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9a64fbe2004-01-04 22:58:38 +00004366#else
aurel3276db3ba2008-12-08 18:11:21 +00004367 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9fddaa02004-05-21 12:59:32 +00004369 return;
bellard9a64fbe2004-01-04 22:58:38 +00004370 }
j_mayerd9bce9d2007-03-17 14:02:15 +00004371#if defined(TARGET_PPC64)
aurel3274d37792008-12-06 21:46:17 +00004372 if (!ctx->sf_mode) {
4373 TCGv t0 = tcg_temp_new();
4374 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4375 gen_helper_tlbie(t0);
4376 tcg_temp_free(t0);
4377 } else
j_mayerd9bce9d2007-03-17 14:02:15 +00004378#endif
aurel3274d37792008-12-06 21:46:17 +00004379 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
bellard9a64fbe2004-01-04 22:58:38 +00004380#endif
bellard79aceca2003-11-23 14:55:54 +00004381}
4382
4383/* tlbsync */
Blue Swirl99e300e2009-06-17 15:22:09 +00004384static void gen_tlbsync(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004385{
bellard9a64fbe2004-01-04 22:58:38 +00004386#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9a64fbe2004-01-04 22:58:38 +00004388#else
aurel3276db3ba2008-12-08 18:11:21 +00004389 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004390 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
bellard9fddaa02004-05-21 12:59:32 +00004391 return;
bellard9a64fbe2004-01-04 22:58:38 +00004392 }
4393 /* This has no effect: it should ensure that all previous
4394 * tlbie have completed
4395 */
aurel32e06fcd72008-12-11 22:42:14 +00004396 gen_stop_exception(ctx);
bellard9a64fbe2004-01-04 22:58:38 +00004397#endif
bellard79aceca2003-11-23 14:55:54 +00004398}
4399
j_mayer426613d2007-03-23 09:45:27 +00004400#if defined(TARGET_PPC64)
4401/* slbia */
Blue Swirl99e300e2009-06-17 15:22:09 +00004402static void gen_slbia(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00004403{
4404#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004405 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00004406#else
aurel3276db3ba2008-12-08 18:11:21 +00004407 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004408 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00004409 return;
4410 }
aurel3274d37792008-12-06 21:46:17 +00004411 gen_helper_slbia();
j_mayer426613d2007-03-23 09:45:27 +00004412#endif
4413}
4414
4415/* slbie */
Blue Swirl99e300e2009-06-17 15:22:09 +00004416static void gen_slbie(DisasContext *ctx)
j_mayer426613d2007-03-23 09:45:27 +00004417{
4418#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00004419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00004420#else
aurel3276db3ba2008-12-08 18:11:21 +00004421 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00004422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer426613d2007-03-23 09:45:27 +00004423 return;
4424 }
aurel3274d37792008-12-06 21:46:17 +00004425 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
j_mayer426613d2007-03-23 09:45:27 +00004426#endif
4427}
4428#endif
4429
bellard79aceca2003-11-23 14:55:54 +00004430/*** External control ***/
4431/* Optional: */
Blue Swirl99e300e2009-06-17 15:22:09 +00004432
Blue Swirl54623272009-06-17 15:22:19 +00004433/* eciwx */
Blue Swirl99e300e2009-06-17 15:22:09 +00004434static void gen_eciwx(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004435{
aurel3276db3ba2008-12-08 18:11:21 +00004436 TCGv t0;
aurel32fa407c02008-11-30 16:24:47 +00004437 /* Should check EAR[E] ! */
aurel3276db3ba2008-12-08 18:11:21 +00004438 gen_set_access_type(ctx, ACCESS_EXT);
4439 t0 = tcg_temp_new();
4440 gen_addr_reg_index(ctx, t0);
aurel32fa407c02008-11-30 16:24:47 +00004441 gen_check_align(ctx, t0, 0x03);
aurel3276db3ba2008-12-08 18:11:21 +00004442 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
aurel32fa407c02008-11-30 16:24:47 +00004443 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004444}
4445
4446/* ecowx */
Blue Swirl99e300e2009-06-17 15:22:09 +00004447static void gen_ecowx(DisasContext *ctx)
bellard79aceca2003-11-23 14:55:54 +00004448{
aurel3276db3ba2008-12-08 18:11:21 +00004449 TCGv t0;
aurel32fa407c02008-11-30 16:24:47 +00004450 /* Should check EAR[E] ! */
aurel3276db3ba2008-12-08 18:11:21 +00004451 gen_set_access_type(ctx, ACCESS_EXT);
4452 t0 = tcg_temp_new();
4453 gen_addr_reg_index(ctx, t0);
aurel32fa407c02008-11-30 16:24:47 +00004454 gen_check_align(ctx, t0, 0x03);
aurel3276db3ba2008-12-08 18:11:21 +00004455 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
aurel32fa407c02008-11-30 16:24:47 +00004456 tcg_temp_free(t0);
bellard79aceca2003-11-23 14:55:54 +00004457}
4458
j_mayer76a66252007-03-07 08:32:30 +00004459/* PowerPC 601 specific instructions */
Blue Swirl99e300e2009-06-17 15:22:09 +00004460
Blue Swirl54623272009-06-17 15:22:19 +00004461/* abs - abs. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004462static void gen_abs(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004463{
aurel3222e0e172008-12-06 12:19:14 +00004464 int l1 = gen_new_label();
4465 int l2 = gen_new_label();
4466 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4467 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 tcg_gen_br(l2);
4469 gen_set_label(l1);
4470 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4471 gen_set_label(l2);
j_mayer76a66252007-03-07 08:32:30 +00004472 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004473 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004474}
4475
4476/* abso - abso. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004477static void gen_abso(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004478{
aurel3222e0e172008-12-06 12:19:14 +00004479 int l1 = gen_new_label();
4480 int l2 = gen_new_label();
4481 int l3 = gen_new_label();
4482 /* Start with XER OV disabled, the most likely case */
4483 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4484 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4485 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4486 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4487 tcg_gen_br(l2);
4488 gen_set_label(l1);
4489 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4490 tcg_gen_br(l3);
4491 gen_set_label(l2);
4492 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4493 gen_set_label(l3);
j_mayer76a66252007-03-07 08:32:30 +00004494 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004495 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004496}
4497
4498/* clcs */
Blue Swirl99e300e2009-06-17 15:22:09 +00004499static void gen_clcs(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004500{
aurel3222e0e172008-12-06 12:19:14 +00004501 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4502 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4503 tcg_temp_free_i32(t0);
j_mayerc7697e12007-10-26 00:46:07 +00004504 /* Rc=1 sets CR0 to an undefined state */
j_mayer76a66252007-03-07 08:32:30 +00004505}
4506
4507/* div - div. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004508static void gen_div(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004509{
aurel3222e0e172008-12-06 12:19:14 +00004510 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004511 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004512 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004513}
4514
4515/* divo - divo. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004516static void gen_divo(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004517{
aurel3222e0e172008-12-06 12:19:14 +00004518 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004519 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004520 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004521}
4522
4523/* divs - divs. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004524static void gen_divs(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004525{
aurel3222e0e172008-12-06 12:19:14 +00004526 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004527 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004528 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004529}
4530
4531/* divso - divso. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004532static void gen_divso(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004533{
aurel3222e0e172008-12-06 12:19:14 +00004534 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004535 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004536 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004537}
4538
4539/* doz - doz. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004540static void gen_doz(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004541{
aurel3222e0e172008-12-06 12:19:14 +00004542 int l1 = gen_new_label();
4543 int l2 = gen_new_label();
4544 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4545 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 tcg_gen_br(l2);
4547 gen_set_label(l1);
4548 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4549 gen_set_label(l2);
j_mayer76a66252007-03-07 08:32:30 +00004550 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004551 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004552}
4553
4554/* dozo - dozo. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004555static void gen_dozo(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004556{
aurel3222e0e172008-12-06 12:19:14 +00004557 int l1 = gen_new_label();
4558 int l2 = gen_new_label();
4559 TCGv t0 = tcg_temp_new();
4560 TCGv t1 = tcg_temp_new();
4561 TCGv t2 = tcg_temp_new();
4562 /* Start with XER OV disabled, the most likely case */
4563 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4564 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4565 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4566 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4567 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4568 tcg_gen_andc_tl(t1, t1, t2);
4569 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4570 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4571 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4572 tcg_gen_br(l2);
4573 gen_set_label(l1);
4574 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4575 gen_set_label(l2);
4576 tcg_temp_free(t0);
4577 tcg_temp_free(t1);
4578 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004579 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004580 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004581}
4582
4583/* dozi */
Blue Swirl99e300e2009-06-17 15:22:09 +00004584static void gen_dozi(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004585{
aurel3222e0e172008-12-06 12:19:14 +00004586 target_long simm = SIMM(ctx->opcode);
4587 int l1 = gen_new_label();
4588 int l2 = gen_new_label();
4589 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4590 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4591 tcg_gen_br(l2);
4592 gen_set_label(l1);
4593 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4594 gen_set_label(l2);
4595 if (unlikely(Rc(ctx->opcode) != 0))
4596 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004597}
4598
j_mayer76a66252007-03-07 08:32:30 +00004599/* lscbx - lscbx. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004600static void gen_lscbx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004601{
aurel32bdb4b682008-11-30 16:24:30 +00004602 TCGv t0 = tcg_temp_new();
4603 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4604 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4605 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
j_mayer76a66252007-03-07 08:32:30 +00004606
aurel3276db3ba2008-12-08 18:11:21 +00004607 gen_addr_reg_index(ctx, t0);
j_mayer76a66252007-03-07 08:32:30 +00004608 /* NIP cannot be restored if the memory exception comes from an helper */
j_mayerd9bce9d2007-03-17 14:02:15 +00004609 gen_update_nip(ctx, ctx->nip - 4);
aurel32bdb4b682008-11-30 16:24:30 +00004610 gen_helper_lscbx(t0, t0, t1, t2, t3);
4611 tcg_temp_free_i32(t1);
4612 tcg_temp_free_i32(t2);
4613 tcg_temp_free_i32(t3);
aurel323d7b4172008-10-21 11:28:46 +00004614 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
aurel32bdb4b682008-11-30 16:24:30 +00004615 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
j_mayer76a66252007-03-07 08:32:30 +00004616 if (unlikely(Rc(ctx->opcode) != 0))
aurel32bdb4b682008-11-30 16:24:30 +00004617 gen_set_Rc0(ctx, t0);
4618 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00004619}
4620
4621/* maskg - maskg. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004622static void gen_maskg(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004623{
aurel3222e0e172008-12-06 12:19:14 +00004624 int l1 = gen_new_label();
4625 TCGv t0 = tcg_temp_new();
4626 TCGv t1 = tcg_temp_new();
4627 TCGv t2 = tcg_temp_new();
4628 TCGv t3 = tcg_temp_new();
4629 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4630 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4631 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4632 tcg_gen_addi_tl(t2, t0, 1);
4633 tcg_gen_shr_tl(t2, t3, t2);
4634 tcg_gen_shr_tl(t3, t3, t1);
4635 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4636 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4637 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4638 gen_set_label(l1);
4639 tcg_temp_free(t0);
4640 tcg_temp_free(t1);
4641 tcg_temp_free(t2);
4642 tcg_temp_free(t3);
j_mayer76a66252007-03-07 08:32:30 +00004643 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004645}
4646
4647/* maskir - maskir. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004648static void gen_maskir(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004649{
aurel3222e0e172008-12-06 12:19:14 +00004650 TCGv t0 = tcg_temp_new();
4651 TCGv t1 = tcg_temp_new();
4652 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4653 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4654 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4655 tcg_temp_free(t0);
4656 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004657 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004659}
4660
4661/* mul - mul. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004662static void gen_mul(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004663{
aurel3222e0e172008-12-06 12:19:14 +00004664 TCGv_i64 t0 = tcg_temp_new_i64();
4665 TCGv_i64 t1 = tcg_temp_new_i64();
4666 TCGv t2 = tcg_temp_new();
4667 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4668 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4669 tcg_gen_mul_i64(t0, t0, t1);
4670 tcg_gen_trunc_i64_tl(t2, t0);
4671 gen_store_spr(SPR_MQ, t2);
4672 tcg_gen_shri_i64(t1, t0, 32);
4673 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4674 tcg_temp_free_i64(t0);
4675 tcg_temp_free_i64(t1);
4676 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004677 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004678 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004679}
4680
4681/* mulo - mulo. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004682static void gen_mulo(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004683{
aurel3222e0e172008-12-06 12:19:14 +00004684 int l1 = gen_new_label();
4685 TCGv_i64 t0 = tcg_temp_new_i64();
4686 TCGv_i64 t1 = tcg_temp_new_i64();
4687 TCGv t2 = tcg_temp_new();
4688 /* Start with XER OV disabled, the most likely case */
4689 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4690 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4691 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4692 tcg_gen_mul_i64(t0, t0, t1);
4693 tcg_gen_trunc_i64_tl(t2, t0);
4694 gen_store_spr(SPR_MQ, t2);
4695 tcg_gen_shri_i64(t1, t0, 32);
4696 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4697 tcg_gen_ext32s_i64(t1, t0);
4698 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4699 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4700 gen_set_label(l1);
4701 tcg_temp_free_i64(t0);
4702 tcg_temp_free_i64(t1);
4703 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004704 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004705 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004706}
4707
4708/* nabs - nabs. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004709static void gen_nabs(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004710{
aurel3222e0e172008-12-06 12:19:14 +00004711 int l1 = gen_new_label();
4712 int l2 = gen_new_label();
4713 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4714 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4715 tcg_gen_br(l2);
4716 gen_set_label(l1);
4717 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4718 gen_set_label(l2);
j_mayer76a66252007-03-07 08:32:30 +00004719 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004720 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004721}
4722
4723/* nabso - nabso. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004724static void gen_nabso(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004725{
aurel3222e0e172008-12-06 12:19:14 +00004726 int l1 = gen_new_label();
4727 int l2 = gen_new_label();
4728 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4729 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4730 tcg_gen_br(l2);
4731 gen_set_label(l1);
4732 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4733 gen_set_label(l2);
4734 /* nabs never overflows */
4735 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
j_mayer76a66252007-03-07 08:32:30 +00004736 if (unlikely(Rc(ctx->opcode) != 0))
aurel3222e0e172008-12-06 12:19:14 +00004737 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004738}
4739
4740/* rlmi - rlmi. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004741static void gen_rlmi(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004742{
aurel3274879532008-12-05 07:21:44 +00004743 uint32_t mb = MB(ctx->opcode);
4744 uint32_t me = ME(ctx->opcode);
4745 TCGv t0 = tcg_temp_new();
4746 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4747 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4748 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4749 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4750 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4751 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00004752 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004753 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004754}
4755
4756/* rrib - rrib. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004757static void gen_rrib(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004758{
aurel3274879532008-12-05 07:21:44 +00004759 TCGv t0 = tcg_temp_new();
4760 TCGv t1 = tcg_temp_new();
4761 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4762 tcg_gen_movi_tl(t1, 0x80000000);
4763 tcg_gen_shr_tl(t1, t1, t0);
4764 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4765 tcg_gen_and_tl(t0, t0, t1);
4766 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4767 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4768 tcg_temp_free(t0);
4769 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004770 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004771 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004772}
4773
4774/* sle - sle. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004775static void gen_sle(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004776{
aurel3274879532008-12-05 07:21:44 +00004777 TCGv t0 = tcg_temp_new();
4778 TCGv t1 = tcg_temp_new();
4779 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4780 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4781 tcg_gen_subfi_tl(t1, 32, t1);
4782 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4783 tcg_gen_or_tl(t1, t0, t1);
4784 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4785 gen_store_spr(SPR_MQ, t1);
4786 tcg_temp_free(t0);
4787 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004788 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004789 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004790}
4791
4792/* sleq - sleq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004793static void gen_sleq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004794{
aurel3274879532008-12-05 07:21:44 +00004795 TCGv t0 = tcg_temp_new();
4796 TCGv t1 = tcg_temp_new();
4797 TCGv t2 = tcg_temp_new();
4798 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4799 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4800 tcg_gen_shl_tl(t2, t2, t0);
4801 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4802 gen_load_spr(t1, SPR_MQ);
4803 gen_store_spr(SPR_MQ, t0);
4804 tcg_gen_and_tl(t0, t0, t2);
4805 tcg_gen_andc_tl(t1, t1, t2);
4806 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4807 tcg_temp_free(t0);
4808 tcg_temp_free(t1);
4809 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004810 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004811 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004812}
4813
4814/* sliq - sliq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004815static void gen_sliq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004816{
aurel3274879532008-12-05 07:21:44 +00004817 int sh = SH(ctx->opcode);
4818 TCGv t0 = tcg_temp_new();
4819 TCGv t1 = tcg_temp_new();
4820 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4821 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4822 tcg_gen_or_tl(t1, t0, t1);
4823 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4824 gen_store_spr(SPR_MQ, t1);
4825 tcg_temp_free(t0);
4826 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004827 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004829}
4830
4831/* slliq - slliq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004832static void gen_slliq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004833{
aurel3274879532008-12-05 07:21:44 +00004834 int sh = SH(ctx->opcode);
4835 TCGv t0 = tcg_temp_new();
4836 TCGv t1 = tcg_temp_new();
4837 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4838 gen_load_spr(t1, SPR_MQ);
4839 gen_store_spr(SPR_MQ, t0);
4840 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4841 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004845 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004847}
4848
4849/* sllq - sllq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004850static void gen_sllq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004851{
aurel3274879532008-12-05 07:21:44 +00004852 int l1 = gen_new_label();
4853 int l2 = gen_new_label();
4854 TCGv t0 = tcg_temp_local_new();
4855 TCGv t1 = tcg_temp_local_new();
4856 TCGv t2 = tcg_temp_local_new();
4857 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4858 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4859 tcg_gen_shl_tl(t1, t1, t2);
4860 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4861 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4862 gen_load_spr(t0, SPR_MQ);
4863 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4864 tcg_gen_br(l2);
4865 gen_set_label(l1);
4866 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4867 gen_load_spr(t2, SPR_MQ);
4868 tcg_gen_andc_tl(t1, t2, t1);
4869 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4870 gen_set_label(l2);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
4873 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004874 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004876}
4877
4878/* slq - slq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004879static void gen_slq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004880{
aurel3274879532008-12-05 07:21:44 +00004881 int l1 = gen_new_label();
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4885 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4886 tcg_gen_subfi_tl(t1, 32, t1);
4887 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4888 tcg_gen_or_tl(t1, t0, t1);
4889 gen_store_spr(SPR_MQ, t1);
4890 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4892 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4893 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4894 gen_set_label(l1);
4895 tcg_temp_free(t0);
4896 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004897 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004899}
4900
j_mayerd9bce9d2007-03-17 14:02:15 +00004901/* sraiq - sraiq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004902static void gen_sraiq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004903{
aurel3274879532008-12-05 07:21:44 +00004904 int sh = SH(ctx->opcode);
4905 int l1 = gen_new_label();
4906 TCGv t0 = tcg_temp_new();
4907 TCGv t1 = tcg_temp_new();
4908 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4909 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4910 tcg_gen_or_tl(t0, t0, t1);
4911 gen_store_spr(SPR_MQ, t0);
4912 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4913 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4914 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4915 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4916 gen_set_label(l1);
4917 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004920 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004922}
4923
4924/* sraq - sraq. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004925static void gen_sraq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004926{
aurel3274879532008-12-05 07:21:44 +00004927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4934 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4935 tcg_gen_subfi_tl(t2, 32, t2);
4936 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4937 tcg_gen_or_tl(t0, t0, t2);
4938 gen_store_spr(SPR_MQ, t0);
4939 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4940 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4941 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4942 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4943 gen_set_label(l1);
4944 tcg_temp_free(t0);
4945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4946 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4947 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4948 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4949 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4950 gen_set_label(l2);
4951 tcg_temp_free(t1);
4952 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00004953 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004954 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004955}
4956
4957/* sre - sre. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004958static void gen_sre(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004959{
aurel3274879532008-12-05 07:21:44 +00004960 TCGv t0 = tcg_temp_new();
4961 TCGv t1 = tcg_temp_new();
4962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4963 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4964 tcg_gen_subfi_tl(t1, 32, t1);
4965 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4966 tcg_gen_or_tl(t1, t0, t1);
4967 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4968 gen_store_spr(SPR_MQ, t1);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004971 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004973}
4974
4975/* srea - srea. */
Blue Swirl99e300e2009-06-17 15:22:09 +00004976static void gen_srea(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004977{
aurel3274879532008-12-05 07:21:44 +00004978 TCGv t0 = tcg_temp_new();
4979 TCGv t1 = tcg_temp_new();
4980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4981 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4982 gen_store_spr(SPR_MQ, t0);
4983 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4984 tcg_temp_free(t0);
4985 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00004986 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00004987 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00004988}
4989
4990/* sreq */
Blue Swirl99e300e2009-06-17 15:22:09 +00004991static void gen_sreq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00004992{
aurel3274879532008-12-05 07:21:44 +00004993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_new();
4995 TCGv t2 = tcg_temp_new();
4996 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4998 tcg_gen_shr_tl(t1, t1, t0);
4999 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5000 gen_load_spr(t2, SPR_MQ);
5001 gen_store_spr(SPR_MQ, t0);
5002 tcg_gen_and_tl(t0, t0, t1);
5003 tcg_gen_andc_tl(t2, t2, t1);
5004 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5005 tcg_temp_free(t0);
5006 tcg_temp_free(t1);
5007 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00005008 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00005009 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005010}
5011
5012/* sriq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005013static void gen_sriq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005014{
aurel3274879532008-12-05 07:21:44 +00005015 int sh = SH(ctx->opcode);
5016 TCGv t0 = tcg_temp_new();
5017 TCGv t1 = tcg_temp_new();
5018 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5019 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5020 tcg_gen_or_tl(t1, t0, t1);
5021 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5022 gen_store_spr(SPR_MQ, t1);
5023 tcg_temp_free(t0);
5024 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005025 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00005026 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005027}
5028
5029/* srliq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005030static void gen_srliq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005031{
aurel3274879532008-12-05 07:21:44 +00005032 int sh = SH(ctx->opcode);
5033 TCGv t0 = tcg_temp_new();
5034 TCGv t1 = tcg_temp_new();
5035 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5036 gen_load_spr(t1, SPR_MQ);
5037 gen_store_spr(SPR_MQ, t0);
5038 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5039 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5040 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5041 tcg_temp_free(t0);
5042 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005043 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00005044 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005045}
5046
5047/* srlq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005048static void gen_srlq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005049{
aurel3274879532008-12-05 07:21:44 +00005050 int l1 = gen_new_label();
5051 int l2 = gen_new_label();
5052 TCGv t0 = tcg_temp_local_new();
5053 TCGv t1 = tcg_temp_local_new();
5054 TCGv t2 = tcg_temp_local_new();
5055 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5057 tcg_gen_shr_tl(t2, t1, t2);
5058 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5059 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5060 gen_load_spr(t0, SPR_MQ);
5061 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5062 tcg_gen_br(l2);
5063 gen_set_label(l1);
5064 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5065 tcg_gen_and_tl(t0, t0, t2);
5066 gen_load_spr(t1, SPR_MQ);
5067 tcg_gen_andc_tl(t1, t1, t2);
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5069 gen_set_label(l2);
5070 tcg_temp_free(t0);
5071 tcg_temp_free(t1);
5072 tcg_temp_free(t2);
j_mayer76a66252007-03-07 08:32:30 +00005073 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00005074 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005075}
5076
5077/* srq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005078static void gen_srq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005079{
aurel3274879532008-12-05 07:21:44 +00005080 int l1 = gen_new_label();
5081 TCGv t0 = tcg_temp_new();
5082 TCGv t1 = tcg_temp_new();
5083 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5084 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5085 tcg_gen_subfi_tl(t1, 32, t1);
5086 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5087 tcg_gen_or_tl(t1, t0, t1);
5088 gen_store_spr(SPR_MQ, t1);
5089 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5090 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5091 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5092 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5093 gen_set_label(l1);
5094 tcg_temp_free(t0);
5095 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005096 if (unlikely(Rc(ctx->opcode) != 0))
aurel3274879532008-12-05 07:21:44 +00005097 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005098}
5099
5100/* PowerPC 602 specific instructions */
Blue Swirl99e300e2009-06-17 15:22:09 +00005101
Blue Swirl54623272009-06-17 15:22:19 +00005102/* dsa */
Blue Swirl99e300e2009-06-17 15:22:09 +00005103static void gen_dsa(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005104{
5105 /* XXX: TODO */
aurel32e06fcd72008-12-11 22:42:14 +00005106 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer76a66252007-03-07 08:32:30 +00005107}
5108
5109/* esa */
Blue Swirl99e300e2009-06-17 15:22:09 +00005110static void gen_esa(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005111{
5112 /* XXX: TODO */
aurel32e06fcd72008-12-11 22:42:14 +00005113 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer76a66252007-03-07 08:32:30 +00005114}
5115
5116/* mfrom */
Blue Swirl99e300e2009-06-17 15:22:09 +00005117static void gen_mfrom(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005118{
5119#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005121#else
aurel3276db3ba2008-12-08 18:11:21 +00005122 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005124 return;
5125 }
aurel32cf02a652008-11-30 16:23:35 +00005126 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005127#endif
5128}
5129
5130/* 602 - 603 - G2 TLB management */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005131
Blue Swirl54623272009-06-17 15:22:19 +00005132/* tlbld */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005133static void gen_tlbld_6xx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005134{
5135#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005137#else
aurel3276db3ba2008-12-08 18:11:21 +00005138 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005140 return;
5141 }
aurel3274d37792008-12-06 21:46:17 +00005142 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005143#endif
5144}
5145
5146/* tlbli */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005147static void gen_tlbli_6xx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005148{
5149#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005151#else
aurel3276db3ba2008-12-08 18:11:21 +00005152 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005154 return;
5155 }
aurel3274d37792008-12-06 21:46:17 +00005156 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005157#endif
5158}
5159
j_mayer7dbe11a2007-10-01 05:16:57 +00005160/* 74xx TLB management */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005161
Blue Swirl54623272009-06-17 15:22:19 +00005162/* tlbld */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005163static void gen_tlbld_74xx(DisasContext *ctx)
j_mayer7dbe11a2007-10-01 05:16:57 +00005164{
5165#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer7dbe11a2007-10-01 05:16:57 +00005167#else
aurel3276db3ba2008-12-08 18:11:21 +00005168 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005169 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer7dbe11a2007-10-01 05:16:57 +00005170 return;
5171 }
aurel3274d37792008-12-06 21:46:17 +00005172 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
j_mayer7dbe11a2007-10-01 05:16:57 +00005173#endif
5174}
5175
5176/* tlbli */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005177static void gen_tlbli_74xx(DisasContext *ctx)
j_mayer7dbe11a2007-10-01 05:16:57 +00005178{
5179#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005180 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer7dbe11a2007-10-01 05:16:57 +00005181#else
aurel3276db3ba2008-12-08 18:11:21 +00005182 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer7dbe11a2007-10-01 05:16:57 +00005184 return;
5185 }
aurel3274d37792008-12-06 21:46:17 +00005186 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
j_mayer7dbe11a2007-10-01 05:16:57 +00005187#endif
5188}
5189
j_mayer76a66252007-03-07 08:32:30 +00005190/* POWER instructions not in PowerPC 601 */
Blue Swirl99e300e2009-06-17 15:22:09 +00005191
Blue Swirl54623272009-06-17 15:22:19 +00005192/* clf */
Blue Swirl99e300e2009-06-17 15:22:09 +00005193static void gen_clf(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005194{
5195 /* Cache line flush: implemented as no-op */
5196}
5197
5198/* cli */
Blue Swirl99e300e2009-06-17 15:22:09 +00005199static void gen_cli(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005200{
blueswir17f75ffd2007-05-27 19:39:27 +00005201 /* Cache line invalidate: privileged and treated as no-op */
j_mayer76a66252007-03-07 08:32:30 +00005202#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005204#else
aurel3276db3ba2008-12-08 18:11:21 +00005205 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005207 return;
5208 }
5209#endif
5210}
5211
5212/* dclst */
Blue Swirl99e300e2009-06-17 15:22:09 +00005213static void gen_dclst(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005214{
5215 /* Data cache line store: treated as no-op */
5216}
5217
Blue Swirl99e300e2009-06-17 15:22:09 +00005218static void gen_mfsri(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005219{
5220#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005222#else
aurel3274d37792008-12-06 21:46:17 +00005223 int ra = rA(ctx->opcode);
5224 int rd = rD(ctx->opcode);
5225 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00005226 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005227 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005228 return;
5229 }
aurel3274d37792008-12-06 21:46:17 +00005230 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005231 gen_addr_reg_index(ctx, t0);
aurel3274d37792008-12-06 21:46:17 +00005232 tcg_gen_shri_tl(t0, t0, 28);
5233 tcg_gen_andi_tl(t0, t0, 0xF);
5234 gen_helper_load_sr(cpu_gpr[rd], t0);
5235 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005236 if (ra != 0 && ra != rd)
aurel3274d37792008-12-06 21:46:17 +00005237 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
j_mayer76a66252007-03-07 08:32:30 +00005238#endif
5239}
5240
Blue Swirl99e300e2009-06-17 15:22:09 +00005241static void gen_rac(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005242{
5243#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005245#else
aurel3222e0e172008-12-06 12:19:14 +00005246 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00005247 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005249 return;
5250 }
aurel3222e0e172008-12-06 12:19:14 +00005251 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005252 gen_addr_reg_index(ctx, t0);
aurel3222e0e172008-12-06 12:19:14 +00005253 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5254 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005255#endif
5256}
5257
Blue Swirl99e300e2009-06-17 15:22:09 +00005258static void gen_rfsvc(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005259{
5260#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005262#else
aurel3276db3ba2008-12-08 18:11:21 +00005263 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005265 return;
5266 }
aurel32d72a19f2008-11-30 16:24:55 +00005267 gen_helper_rfsvc();
aurel32e06fcd72008-12-11 22:42:14 +00005268 gen_sync_exception(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005269#endif
5270}
5271
5272/* svc is not implemented for now */
5273
5274/* POWER2 specific instructions */
5275/* Quad manipulation (load/store two floats at a time) */
j_mayer76a66252007-03-07 08:32:30 +00005276
5277/* lfq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005278static void gen_lfq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005279{
aurel3201a4afe2008-11-27 19:30:56 +00005280 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005281 TCGv t0;
5282 gen_set_access_type(ctx, ACCESS_FLOAT);
5283 t0 = tcg_temp_new();
5284 gen_addr_imm_index(ctx, t0, 0);
5285 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5286 gen_addr_add(ctx, t0, t0, 8);
5287 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
aurel3201a4afe2008-11-27 19:30:56 +00005288 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005289}
5290
5291/* lfqu */
Blue Swirl99e300e2009-06-17 15:22:09 +00005292static void gen_lfqu(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005293{
5294 int ra = rA(ctx->opcode);
aurel3201a4afe2008-11-27 19:30:56 +00005295 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005296 TCGv t0, t1;
5297 gen_set_access_type(ctx, ACCESS_FLOAT);
5298 t0 = tcg_temp_new();
5299 t1 = tcg_temp_new();
5300 gen_addr_imm_index(ctx, t0, 0);
5301 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5302 gen_addr_add(ctx, t1, t0, 8);
5303 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
j_mayer76a66252007-03-07 08:32:30 +00005304 if (ra != 0)
aurel3201a4afe2008-11-27 19:30:56 +00005305 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5306 tcg_temp_free(t0);
5307 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005308}
5309
5310/* lfqux */
Blue Swirl99e300e2009-06-17 15:22:09 +00005311static void gen_lfqux(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005312{
5313 int ra = rA(ctx->opcode);
aurel3201a4afe2008-11-27 19:30:56 +00005314 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005315 gen_set_access_type(ctx, ACCESS_FLOAT);
5316 TCGv t0, t1;
5317 t0 = tcg_temp_new();
5318 gen_addr_reg_index(ctx, t0);
5319 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5320 t1 = tcg_temp_new();
5321 gen_addr_add(ctx, t1, t0, 8);
5322 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5323 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005324 if (ra != 0)
aurel3201a4afe2008-11-27 19:30:56 +00005325 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5326 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005327}
5328
5329/* lfqx */
Blue Swirl99e300e2009-06-17 15:22:09 +00005330static void gen_lfqx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005331{
aurel3201a4afe2008-11-27 19:30:56 +00005332 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005333 TCGv t0;
5334 gen_set_access_type(ctx, ACCESS_FLOAT);
5335 t0 = tcg_temp_new();
5336 gen_addr_reg_index(ctx, t0);
5337 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5338 gen_addr_add(ctx, t0, t0, 8);
5339 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
aurel3201a4afe2008-11-27 19:30:56 +00005340 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005341}
5342
5343/* stfq */
Blue Swirl99e300e2009-06-17 15:22:09 +00005344static void gen_stfq(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005345{
aurel3201a4afe2008-11-27 19:30:56 +00005346 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005347 TCGv t0;
5348 gen_set_access_type(ctx, ACCESS_FLOAT);
5349 t0 = tcg_temp_new();
5350 gen_addr_imm_index(ctx, t0, 0);
5351 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5352 gen_addr_add(ctx, t0, t0, 8);
5353 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
aurel3201a4afe2008-11-27 19:30:56 +00005354 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005355}
5356
5357/* stfqu */
Blue Swirl99e300e2009-06-17 15:22:09 +00005358static void gen_stfqu(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005359{
5360 int ra = rA(ctx->opcode);
aurel3201a4afe2008-11-27 19:30:56 +00005361 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005362 TCGv t0, t1;
5363 gen_set_access_type(ctx, ACCESS_FLOAT);
5364 t0 = tcg_temp_new();
5365 gen_addr_imm_index(ctx, t0, 0);
5366 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5367 t1 = tcg_temp_new();
5368 gen_addr_add(ctx, t1, t0, 8);
5369 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5370 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005371 if (ra != 0)
aurel3201a4afe2008-11-27 19:30:56 +00005372 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5373 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005374}
5375
5376/* stfqux */
Blue Swirl99e300e2009-06-17 15:22:09 +00005377static void gen_stfqux(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005378{
5379 int ra = rA(ctx->opcode);
aurel3201a4afe2008-11-27 19:30:56 +00005380 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005381 TCGv t0, t1;
5382 gen_set_access_type(ctx, ACCESS_FLOAT);
5383 t0 = tcg_temp_new();
5384 gen_addr_reg_index(ctx, t0);
5385 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5386 t1 = tcg_temp_new();
5387 gen_addr_add(ctx, t1, t0, 8);
5388 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5389 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005390 if (ra != 0)
aurel3201a4afe2008-11-27 19:30:56 +00005391 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5392 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005393}
5394
5395/* stfqx */
Blue Swirl99e300e2009-06-17 15:22:09 +00005396static void gen_stfqx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005397{
aurel3201a4afe2008-11-27 19:30:56 +00005398 int rd = rD(ctx->opcode);
aurel3276db3ba2008-12-08 18:11:21 +00005399 TCGv t0;
5400 gen_set_access_type(ctx, ACCESS_FLOAT);
5401 t0 = tcg_temp_new();
5402 gen_addr_reg_index(ctx, t0);
5403 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5404 gen_addr_add(ctx, t0, t0, 8);
5405 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
aurel3201a4afe2008-11-27 19:30:56 +00005406 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005407}
5408
5409/* BookE specific instructions */
Blue Swirl99e300e2009-06-17 15:22:09 +00005410
Blue Swirl54623272009-06-17 15:22:19 +00005411/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005412static void gen_mfapidi(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005413{
5414 /* XXX: TODO */
aurel32e06fcd72008-12-11 22:42:14 +00005415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer76a66252007-03-07 08:32:30 +00005416}
5417
j_mayer2662a052007-09-21 05:50:37 +00005418/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005419static void gen_tlbiva(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005420{
5421#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005423#else
aurel3274d37792008-12-06 21:46:17 +00005424 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00005425 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005427 return;
5428 }
aurel32ec72e272008-12-07 15:45:15 +00005429 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005430 gen_addr_reg_index(ctx, t0);
aurel3274d37792008-12-06 21:46:17 +00005431 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5432 tcg_temp_free(t0);
j_mayer76a66252007-03-07 08:32:30 +00005433#endif
5434}
5435
5436/* All 405 MAC instructions are translated here */
Blue Swirl636aa202009-08-16 09:06:54 +00005437static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5438 int ra, int rb, int rt, int Rc)
j_mayer76a66252007-03-07 08:32:30 +00005439{
aurel32182608d2008-11-01 00:54:23 +00005440 TCGv t0, t1;
5441
pbrooka7812ae2008-11-17 14:43:54 +00005442 t0 = tcg_temp_local_new();
5443 t1 = tcg_temp_local_new();
aurel32182608d2008-11-01 00:54:23 +00005444
j_mayer76a66252007-03-07 08:32:30 +00005445 switch (opc3 & 0x0D) {
5446 case 0x05:
5447 /* macchw - macchw. - macchwo - macchwo. */
5448 /* macchws - macchws. - macchwso - macchwso. */
5449 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5450 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5451 /* mulchw - mulchw. */
aurel32182608d2008-11-01 00:54:23 +00005452 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5453 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5454 tcg_gen_ext16s_tl(t1, t1);
j_mayer76a66252007-03-07 08:32:30 +00005455 break;
5456 case 0x04:
5457 /* macchwu - macchwu. - macchwuo - macchwuo. */
5458 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5459 /* mulchwu - mulchwu. */
aurel32182608d2008-11-01 00:54:23 +00005460 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5461 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5462 tcg_gen_ext16u_tl(t1, t1);
j_mayer76a66252007-03-07 08:32:30 +00005463 break;
5464 case 0x01:
5465 /* machhw - machhw. - machhwo - machhwo. */
5466 /* machhws - machhws. - machhwso - machhwso. */
5467 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5468 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5469 /* mulhhw - mulhhw. */
aurel32182608d2008-11-01 00:54:23 +00005470 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5471 tcg_gen_ext16s_tl(t0, t0);
5472 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5473 tcg_gen_ext16s_tl(t1, t1);
j_mayer76a66252007-03-07 08:32:30 +00005474 break;
5475 case 0x00:
5476 /* machhwu - machhwu. - machhwuo - machhwuo. */
5477 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5478 /* mulhhwu - mulhhwu. */
aurel32182608d2008-11-01 00:54:23 +00005479 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5480 tcg_gen_ext16u_tl(t0, t0);
5481 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5482 tcg_gen_ext16u_tl(t1, t1);
j_mayer76a66252007-03-07 08:32:30 +00005483 break;
5484 case 0x0D:
5485 /* maclhw - maclhw. - maclhwo - maclhwo. */
5486 /* maclhws - maclhws. - maclhwso - maclhwso. */
5487 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5488 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5489 /* mullhw - mullhw. */
aurel32182608d2008-11-01 00:54:23 +00005490 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5491 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
j_mayer76a66252007-03-07 08:32:30 +00005492 break;
5493 case 0x0C:
5494 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5495 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5496 /* mullhwu - mullhwu. */
aurel32182608d2008-11-01 00:54:23 +00005497 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5498 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
j_mayer76a66252007-03-07 08:32:30 +00005499 break;
5500 }
j_mayer76a66252007-03-07 08:32:30 +00005501 if (opc2 & 0x04) {
aurel32182608d2008-11-01 00:54:23 +00005502 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5503 tcg_gen_mul_tl(t1, t0, t1);
5504 if (opc2 & 0x02) {
5505 /* nmultiply-and-accumulate (0x0E) */
5506 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5507 } else {
5508 /* multiply-and-accumulate (0x0C) */
5509 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5510 }
5511
5512 if (opc3 & 0x12) {
5513 /* Check overflow and/or saturate */
5514 int l1 = gen_new_label();
5515
5516 if (opc3 & 0x10) {
5517 /* Start with XER OV disabled, the most likely case */
5518 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5519 }
5520 if (opc3 & 0x01) {
5521 /* Signed */
5522 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5523 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5524 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5525 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
aurel32bdc4e052008-11-09 17:27:03 +00005526 if (opc3 & 0x02) {
aurel32182608d2008-11-01 00:54:23 +00005527 /* Saturate */
5528 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5529 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5530 }
5531 } else {
5532 /* Unsigned */
5533 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
aurel32bdc4e052008-11-09 17:27:03 +00005534 if (opc3 & 0x02) {
aurel32182608d2008-11-01 00:54:23 +00005535 /* Saturate */
5536 tcg_gen_movi_tl(t0, UINT32_MAX);
5537 }
5538 }
5539 if (opc3 & 0x10) {
5540 /* Check overflow */
5541 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5542 }
5543 gen_set_label(l1);
5544 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5545 }
5546 } else {
5547 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
j_mayer76a66252007-03-07 08:32:30 +00005548 }
aurel32182608d2008-11-01 00:54:23 +00005549 tcg_temp_free(t0);
5550 tcg_temp_free(t1);
j_mayer76a66252007-03-07 08:32:30 +00005551 if (unlikely(Rc) != 0) {
5552 /* Update Rc0 */
aurel32182608d2008-11-01 00:54:23 +00005553 gen_set_Rc0(ctx, cpu_gpr[rt]);
j_mayer76a66252007-03-07 08:32:30 +00005554 }
5555}
5556
j_mayera750fc02007-09-26 23:54:22 +00005557#define GEN_MAC_HANDLER(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00005558static void glue(gen_, name)(DisasContext *ctx) \
j_mayer76a66252007-03-07 08:32:30 +00005559{ \
5560 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5561 rD(ctx->opcode), Rc(ctx->opcode)); \
5562}
5563
5564/* macchw - macchw. */
j_mayera750fc02007-09-26 23:54:22 +00005565GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005566/* macchwo - macchwo. */
j_mayera750fc02007-09-26 23:54:22 +00005567GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
j_mayer76a66252007-03-07 08:32:30 +00005568/* macchws - macchws. */
j_mayera750fc02007-09-26 23:54:22 +00005569GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
j_mayer76a66252007-03-07 08:32:30 +00005570/* macchwso - macchwso. */
j_mayera750fc02007-09-26 23:54:22 +00005571GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
j_mayer76a66252007-03-07 08:32:30 +00005572/* macchwsu - macchwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005573GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
j_mayer76a66252007-03-07 08:32:30 +00005574/* macchwsuo - macchwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005575GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
j_mayer76a66252007-03-07 08:32:30 +00005576/* macchwu - macchwu. */
j_mayera750fc02007-09-26 23:54:22 +00005577GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
j_mayer76a66252007-03-07 08:32:30 +00005578/* macchwuo - macchwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005579GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
j_mayer76a66252007-03-07 08:32:30 +00005580/* machhw - machhw. */
j_mayera750fc02007-09-26 23:54:22 +00005581GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005582/* machhwo - machhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005583GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
j_mayer76a66252007-03-07 08:32:30 +00005584/* machhws - machhws. */
j_mayera750fc02007-09-26 23:54:22 +00005585GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
j_mayer76a66252007-03-07 08:32:30 +00005586/* machhwso - machhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005587GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
j_mayer76a66252007-03-07 08:32:30 +00005588/* machhwsu - machhwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005589GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
j_mayer76a66252007-03-07 08:32:30 +00005590/* machhwsuo - machhwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005591GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
j_mayer76a66252007-03-07 08:32:30 +00005592/* machhwu - machhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005593GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
j_mayer76a66252007-03-07 08:32:30 +00005594/* machhwuo - machhwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005595GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
j_mayer76a66252007-03-07 08:32:30 +00005596/* maclhw - maclhw. */
j_mayera750fc02007-09-26 23:54:22 +00005597GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005598/* maclhwo - maclhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005599GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
j_mayer76a66252007-03-07 08:32:30 +00005600/* maclhws - maclhws. */
j_mayera750fc02007-09-26 23:54:22 +00005601GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
j_mayer76a66252007-03-07 08:32:30 +00005602/* maclhwso - maclhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005603GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
j_mayer76a66252007-03-07 08:32:30 +00005604/* maclhwu - maclhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005605GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
j_mayer76a66252007-03-07 08:32:30 +00005606/* maclhwuo - maclhwuo. */
j_mayera750fc02007-09-26 23:54:22 +00005607GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
j_mayer76a66252007-03-07 08:32:30 +00005608/* maclhwsu - maclhwsu. */
j_mayera750fc02007-09-26 23:54:22 +00005609GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
j_mayer76a66252007-03-07 08:32:30 +00005610/* maclhwsuo - maclhwsuo. */
j_mayera750fc02007-09-26 23:54:22 +00005611GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
j_mayer76a66252007-03-07 08:32:30 +00005612/* nmacchw - nmacchw. */
j_mayera750fc02007-09-26 23:54:22 +00005613GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005614/* nmacchwo - nmacchwo. */
j_mayera750fc02007-09-26 23:54:22 +00005615GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
j_mayer76a66252007-03-07 08:32:30 +00005616/* nmacchws - nmacchws. */
j_mayera750fc02007-09-26 23:54:22 +00005617GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
j_mayer76a66252007-03-07 08:32:30 +00005618/* nmacchwso - nmacchwso. */
j_mayera750fc02007-09-26 23:54:22 +00005619GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
j_mayer76a66252007-03-07 08:32:30 +00005620/* nmachhw - nmachhw. */
j_mayera750fc02007-09-26 23:54:22 +00005621GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005622/* nmachhwo - nmachhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005623GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
j_mayer76a66252007-03-07 08:32:30 +00005624/* nmachhws - nmachhws. */
j_mayera750fc02007-09-26 23:54:22 +00005625GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
j_mayer76a66252007-03-07 08:32:30 +00005626/* nmachhwso - nmachhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005627GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
j_mayer76a66252007-03-07 08:32:30 +00005628/* nmaclhw - nmaclhw. */
j_mayera750fc02007-09-26 23:54:22 +00005629GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005630/* nmaclhwo - nmaclhwo. */
j_mayera750fc02007-09-26 23:54:22 +00005631GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
j_mayer76a66252007-03-07 08:32:30 +00005632/* nmaclhws - nmaclhws. */
j_mayera750fc02007-09-26 23:54:22 +00005633GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
j_mayer76a66252007-03-07 08:32:30 +00005634/* nmaclhwso - nmaclhwso. */
j_mayera750fc02007-09-26 23:54:22 +00005635GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
j_mayer76a66252007-03-07 08:32:30 +00005636
5637/* mulchw - mulchw. */
j_mayera750fc02007-09-26 23:54:22 +00005638GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
j_mayer76a66252007-03-07 08:32:30 +00005639/* mulchwu - mulchwu. */
j_mayera750fc02007-09-26 23:54:22 +00005640GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
j_mayer76a66252007-03-07 08:32:30 +00005641/* mulhhw - mulhhw. */
j_mayera750fc02007-09-26 23:54:22 +00005642GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
j_mayer76a66252007-03-07 08:32:30 +00005643/* mulhhwu - mulhhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005644GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
j_mayer76a66252007-03-07 08:32:30 +00005645/* mullhw - mullhw. */
j_mayera750fc02007-09-26 23:54:22 +00005646GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
j_mayer76a66252007-03-07 08:32:30 +00005647/* mullhwu - mullhwu. */
j_mayera750fc02007-09-26 23:54:22 +00005648GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
j_mayer76a66252007-03-07 08:32:30 +00005649
5650/* mfdcr */
Blue Swirl99e300e2009-06-17 15:22:09 +00005651static void gen_mfdcr(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005652{
5653#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer76a66252007-03-07 08:32:30 +00005655#else
aurel3206dca6a2008-12-06 16:37:18 +00005656 TCGv dcrn;
aurel3276db3ba2008-12-08 18:11:21 +00005657 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer76a66252007-03-07 08:32:30 +00005659 return;
5660 }
aurel3206dca6a2008-12-06 16:37:18 +00005661 /* NIP cannot be restored if the memory exception comes from an helper */
5662 gen_update_nip(ctx, ctx->nip - 4);
5663 dcrn = tcg_const_tl(SPR(ctx->opcode));
5664 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5665 tcg_temp_free(dcrn);
j_mayer76a66252007-03-07 08:32:30 +00005666#endif
5667}
5668
5669/* mtdcr */
Blue Swirl99e300e2009-06-17 15:22:09 +00005670static void gen_mtdcr(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005671{
5672#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer76a66252007-03-07 08:32:30 +00005674#else
aurel3206dca6a2008-12-06 16:37:18 +00005675 TCGv dcrn;
aurel3276db3ba2008-12-08 18:11:21 +00005676 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayer76a66252007-03-07 08:32:30 +00005678 return;
5679 }
aurel3206dca6a2008-12-06 16:37:18 +00005680 /* NIP cannot be restored if the memory exception comes from an helper */
5681 gen_update_nip(ctx, ctx->nip - 4);
5682 dcrn = tcg_const_tl(SPR(ctx->opcode));
5683 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5684 tcg_temp_free(dcrn);
j_mayera42bd6c2007-03-30 10:22:46 +00005685#endif
5686}
5687
5688/* mfdcrx */
j_mayer2662a052007-09-21 05:50:37 +00005689/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005690static void gen_mfdcrx(DisasContext *ctx)
j_mayera42bd6c2007-03-30 10:22:46 +00005691{
5692#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayera42bd6c2007-03-30 10:22:46 +00005694#else
aurel3276db3ba2008-12-08 18:11:21 +00005695 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayera42bd6c2007-03-30 10:22:46 +00005697 return;
5698 }
aurel3206dca6a2008-12-06 16:37:18 +00005699 /* NIP cannot be restored if the memory exception comes from an helper */
5700 gen_update_nip(ctx, ctx->nip - 4);
5701 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005702 /* Note: Rc update flag set leads to undefined state of Rc0 */
j_mayera42bd6c2007-03-30 10:22:46 +00005703#endif
5704}
5705
5706/* mtdcrx */
j_mayer2662a052007-09-21 05:50:37 +00005707/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005708static void gen_mtdcrx(DisasContext *ctx)
j_mayera42bd6c2007-03-30 10:22:46 +00005709{
5710#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005711 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayera42bd6c2007-03-30 10:22:46 +00005712#else
aurel3276db3ba2008-12-08 18:11:21 +00005713 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
j_mayera42bd6c2007-03-30 10:22:46 +00005715 return;
5716 }
aurel3206dca6a2008-12-06 16:37:18 +00005717 /* NIP cannot be restored if the memory exception comes from an helper */
5718 gen_update_nip(ctx, ctx->nip - 4);
5719 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005720 /* Note: Rc update flag set leads to undefined state of Rc0 */
j_mayer76a66252007-03-07 08:32:30 +00005721#endif
5722}
5723
j_mayera750fc02007-09-26 23:54:22 +00005724/* mfdcrux (PPC 460) : user-mode access to DCR */
Blue Swirl99e300e2009-06-17 15:22:09 +00005725static void gen_mfdcrux(DisasContext *ctx)
j_mayera750fc02007-09-26 23:54:22 +00005726{
aurel3206dca6a2008-12-06 16:37:18 +00005727 /* NIP cannot be restored if the memory exception comes from an helper */
5728 gen_update_nip(ctx, ctx->nip - 4);
5729 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005730 /* Note: Rc update flag set leads to undefined state of Rc0 */
5731}
5732
5733/* mtdcrux (PPC 460) : user-mode access to DCR */
Blue Swirl99e300e2009-06-17 15:22:09 +00005734static void gen_mtdcrux(DisasContext *ctx)
j_mayera750fc02007-09-26 23:54:22 +00005735{
aurel3206dca6a2008-12-06 16:37:18 +00005736 /* NIP cannot be restored if the memory exception comes from an helper */
5737 gen_update_nip(ctx, ctx->nip - 4);
5738 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayera750fc02007-09-26 23:54:22 +00005739 /* Note: Rc update flag set leads to undefined state of Rc0 */
5740}
5741
j_mayer76a66252007-03-07 08:32:30 +00005742/* dccci */
Blue Swirl99e300e2009-06-17 15:22:09 +00005743static void gen_dccci(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005744{
5745#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005747#else
aurel3276db3ba2008-12-08 18:11:21 +00005748 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005750 return;
5751 }
5752 /* interpreted as no-op */
5753#endif
5754}
5755
5756/* dcread */
Blue Swirl99e300e2009-06-17 15:22:09 +00005757static void gen_dcread(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005758{
5759#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005761#else
aurel32b61f2752008-10-15 17:00:37 +00005762 TCGv EA, val;
aurel3276db3ba2008-12-08 18:11:21 +00005763 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005765 return;
5766 }
aurel3276db3ba2008-12-08 18:11:21 +00005767 gen_set_access_type(ctx, ACCESS_CACHE);
pbrooka7812ae2008-11-17 14:43:54 +00005768 EA = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005769 gen_addr_reg_index(ctx, EA);
pbrooka7812ae2008-11-17 14:43:54 +00005770 val = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005771 gen_qemu_ld32u(ctx, val, EA);
aurel32b61f2752008-10-15 17:00:37 +00005772 tcg_temp_free(val);
5773 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5774 tcg_temp_free(EA);
j_mayer76a66252007-03-07 08:32:30 +00005775#endif
5776}
5777
5778/* icbt */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005779static void gen_icbt_40x(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005780{
5781 /* interpreted as no-op */
5782 /* XXX: specification say this is treated as a load by the MMU
5783 * but does not generate any exception
5784 */
5785}
5786
5787/* iccci */
Blue Swirl99e300e2009-06-17 15:22:09 +00005788static void gen_iccci(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005789{
5790#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005792#else
aurel3276db3ba2008-12-08 18:11:21 +00005793 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005795 return;
5796 }
5797 /* interpreted as no-op */
5798#endif
5799}
5800
5801/* icread */
Blue Swirl99e300e2009-06-17 15:22:09 +00005802static void gen_icread(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005803{
5804#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005806#else
aurel3276db3ba2008-12-08 18:11:21 +00005807 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005809 return;
5810 }
5811 /* interpreted as no-op */
5812#endif
5813}
5814
aurel3276db3ba2008-12-08 18:11:21 +00005815/* rfci (mem_idx only) */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005816static void gen_rfci_40x(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005817{
5818#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005820#else
aurel3276db3ba2008-12-08 18:11:21 +00005821 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005823 return;
5824 }
5825 /* Restore CPU state */
aurel32d72a19f2008-11-30 16:24:55 +00005826 gen_helper_40x_rfci();
aurel32e06fcd72008-12-11 22:42:14 +00005827 gen_sync_exception(ctx);
j_mayer76a66252007-03-07 08:32:30 +00005828#endif
5829}
5830
Blue Swirl99e300e2009-06-17 15:22:09 +00005831static void gen_rfci(DisasContext *ctx)
j_mayera42bd6c2007-03-30 10:22:46 +00005832{
5833#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005835#else
aurel3276db3ba2008-12-08 18:11:21 +00005836 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005838 return;
5839 }
5840 /* Restore CPU state */
aurel32d72a19f2008-11-30 16:24:55 +00005841 gen_helper_rfci();
aurel32e06fcd72008-12-11 22:42:14 +00005842 gen_sync_exception(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005843#endif
5844}
5845
5846/* BookE specific */
Blue Swirl99e300e2009-06-17 15:22:09 +00005847
Blue Swirl54623272009-06-17 15:22:19 +00005848/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005849static void gen_rfdi(DisasContext *ctx)
j_mayera42bd6c2007-03-30 10:22:46 +00005850{
5851#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005853#else
aurel3276db3ba2008-12-08 18:11:21 +00005854 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005855 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005856 return;
5857 }
5858 /* Restore CPU state */
aurel32d72a19f2008-11-30 16:24:55 +00005859 gen_helper_rfdi();
aurel32e06fcd72008-12-11 22:42:14 +00005860 gen_sync_exception(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005861#endif
5862}
5863
j_mayer2662a052007-09-21 05:50:37 +00005864/* XXX: not implemented on 440 ? */
Blue Swirl99e300e2009-06-17 15:22:09 +00005865static void gen_rfmci(DisasContext *ctx)
j_mayera42bd6c2007-03-30 10:22:46 +00005866{
5867#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005869#else
aurel3276db3ba2008-12-08 18:11:21 +00005870 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005871 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayera42bd6c2007-03-30 10:22:46 +00005872 return;
5873 }
5874 /* Restore CPU state */
aurel32d72a19f2008-11-30 16:24:55 +00005875 gen_helper_rfmci();
aurel32e06fcd72008-12-11 22:42:14 +00005876 gen_sync_exception(ctx);
j_mayera42bd6c2007-03-30 10:22:46 +00005877#endif
5878}
j_mayer5eb79952007-09-19 05:44:04 +00005879
j_mayerd9bce9d2007-03-17 14:02:15 +00005880/* TLB management - PowerPC 405 implementation */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005881
Blue Swirl54623272009-06-17 15:22:19 +00005882/* tlbre */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005883static void gen_tlbre_40x(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005884{
5885#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005886 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005887#else
aurel3276db3ba2008-12-08 18:11:21 +00005888 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005890 return;
5891 }
5892 switch (rB(ctx->opcode)) {
5893 case 0:
aurel3274d37792008-12-06 21:46:17 +00005894 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005895 break;
5896 case 1:
aurel3274d37792008-12-06 21:46:17 +00005897 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005898 break;
5899 default:
aurel32e06fcd72008-12-11 22:42:14 +00005900 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer76a66252007-03-07 08:32:30 +00005901 break;
5902 }
5903#endif
5904}
5905
j_mayerd9bce9d2007-03-17 14:02:15 +00005906/* tlbsx - tlbsx. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005907static void gen_tlbsx_40x(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005908{
5909#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005910 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005911#else
aurel3274d37792008-12-06 21:46:17 +00005912 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00005913 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005914 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005915 return;
5916 }
aurel3274d37792008-12-06 21:46:17 +00005917 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005918 gen_addr_reg_index(ctx, t0);
aurel3274d37792008-12-06 21:46:17 +00005919 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5920 tcg_temp_free(t0);
5921 if (Rc(ctx->opcode)) {
5922 int l1 = gen_new_label();
5923 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5924 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5925 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5926 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5927 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5928 gen_set_label(l1);
5929 }
j_mayer76a66252007-03-07 08:32:30 +00005930#endif
5931}
5932
5933/* tlbwe */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005934static void gen_tlbwe_40x(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00005935{
5936#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005938#else
aurel3276db3ba2008-12-08 18:11:21 +00005939 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00005941 return;
5942 }
5943 switch (rB(ctx->opcode)) {
5944 case 0:
aurel3274d37792008-12-06 21:46:17 +00005945 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005946 break;
5947 case 1:
aurel3274d37792008-12-06 21:46:17 +00005948 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
j_mayer76a66252007-03-07 08:32:30 +00005949 break;
5950 default:
aurel32e06fcd72008-12-11 22:42:14 +00005951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer76a66252007-03-07 08:32:30 +00005952 break;
5953 }
5954#endif
5955}
5956
j_mayera4bb6c32007-09-21 05:28:33 +00005957/* TLB management - PowerPC 440 implementation */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005958
Blue Swirl54623272009-06-17 15:22:19 +00005959/* tlbre */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005960static void gen_tlbre_440(DisasContext *ctx)
j_mayer5eb79952007-09-19 05:44:04 +00005961{
5962#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005963 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00005964#else
aurel3276db3ba2008-12-08 18:11:21 +00005965 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005966 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00005967 return;
5968 }
5969 switch (rB(ctx->opcode)) {
5970 case 0:
j_mayer5eb79952007-09-19 05:44:04 +00005971 case 1:
j_mayer5eb79952007-09-19 05:44:04 +00005972 case 2:
aurel3274d37792008-12-06 21:46:17 +00005973 {
5974 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
Edgar E. Iglesias58239472011-01-21 23:12:42 +01005975 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]);
aurel3274d37792008-12-06 21:46:17 +00005976 tcg_temp_free_i32(t0);
5977 }
j_mayer5eb79952007-09-19 05:44:04 +00005978 break;
5979 default:
aurel32e06fcd72008-12-11 22:42:14 +00005980 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer5eb79952007-09-19 05:44:04 +00005981 break;
5982 }
5983#endif
5984}
5985
5986/* tlbsx - tlbsx. */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00005987static void gen_tlbsx_440(DisasContext *ctx)
j_mayer5eb79952007-09-19 05:44:04 +00005988{
5989#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00005990 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00005991#else
aurel3274d37792008-12-06 21:46:17 +00005992 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00005993 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00005994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00005995 return;
5996 }
aurel3274d37792008-12-06 21:46:17 +00005997 t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00005998 gen_addr_reg_index(ctx, t0);
aurel3274d37792008-12-06 21:46:17 +00005999 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6000 tcg_temp_free(t0);
6001 if (Rc(ctx->opcode)) {
6002 int l1 = gen_new_label();
6003 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6004 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6005 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6006 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6007 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6008 gen_set_label(l1);
6009 }
j_mayer5eb79952007-09-19 05:44:04 +00006010#endif
6011}
6012
6013/* tlbwe */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00006014static void gen_tlbwe_440(DisasContext *ctx)
j_mayer5eb79952007-09-19 05:44:04 +00006015{
6016#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00006017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00006018#else
aurel3276db3ba2008-12-08 18:11:21 +00006019 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00006020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer5eb79952007-09-19 05:44:04 +00006021 return;
6022 }
6023 switch (rB(ctx->opcode)) {
6024 case 0:
j_mayer5eb79952007-09-19 05:44:04 +00006025 case 1:
j_mayer5eb79952007-09-19 05:44:04 +00006026 case 2:
aurel3274d37792008-12-06 21:46:17 +00006027 {
6028 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6029 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6030 tcg_temp_free_i32(t0);
6031 }
j_mayer5eb79952007-09-19 05:44:04 +00006032 break;
6033 default:
aurel32e06fcd72008-12-11 22:42:14 +00006034 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer5eb79952007-09-19 05:44:04 +00006035 break;
6036 }
6037#endif
6038}
6039
Alexander Graf01662f32011-04-30 23:34:58 +02006040/* TLB management - PowerPC BookE 2.06 implementation */
6041
6042/* tlbre */
6043static void gen_tlbre_booke206(DisasContext *ctx)
6044{
6045#if defined(CONFIG_USER_ONLY)
6046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6047#else
6048 if (unlikely(!ctx->mem_idx)) {
6049 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6050 return;
6051 }
6052
6053 gen_helper_booke206_tlbre();
6054#endif
6055}
6056
6057/* tlbsx - tlbsx. */
6058static void gen_tlbsx_booke206(DisasContext *ctx)
6059{
6060#if defined(CONFIG_USER_ONLY)
6061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6062#else
6063 TCGv t0;
6064 if (unlikely(!ctx->mem_idx)) {
6065 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6066 return;
6067 }
6068
6069 if (rA(ctx->opcode)) {
6070 t0 = tcg_temp_new();
6071 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6072 } else {
6073 t0 = tcg_const_tl(0);
6074 }
6075
6076 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6077 gen_helper_booke206_tlbsx(t0);
6078#endif
6079}
6080
6081/* tlbwe */
6082static void gen_tlbwe_booke206(DisasContext *ctx)
6083{
6084#if defined(CONFIG_USER_ONLY)
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086#else
6087 if (unlikely(!ctx->mem_idx)) {
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6089 return;
6090 }
Alexander Graf3f162d12012-01-25 16:27:26 +01006091 gen_update_nip(ctx, ctx->nip - 4);
Alexander Graf01662f32011-04-30 23:34:58 +02006092 gen_helper_booke206_tlbwe();
6093#endif
6094}
6095
6096static void gen_tlbivax_booke206(DisasContext *ctx)
6097{
6098#if defined(CONFIG_USER_ONLY)
6099 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6100#else
6101 TCGv t0;
6102 if (unlikely(!ctx->mem_idx)) {
6103 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6104 return;
6105 }
6106
6107 t0 = tcg_temp_new();
6108 gen_addr_reg_index(ctx, t0);
6109
6110 gen_helper_booke206_tlbivax(t0);
6111#endif
6112}
6113
Alexander Graf6d3db822012-01-20 04:09:15 +01006114static void gen_tlbilx_booke206(DisasContext *ctx)
6115{
6116#if defined(CONFIG_USER_ONLY)
6117 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6118#else
6119 TCGv t0;
6120 if (unlikely(!ctx->mem_idx)) {
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6122 return;
6123 }
6124
6125 t0 = tcg_temp_new();
6126 gen_addr_reg_index(ctx, t0);
6127
6128 switch((ctx->opcode >> 21) & 0x3) {
6129 case 0:
6130 gen_helper_booke206_tlbilx0(t0);
6131 break;
6132 case 1:
6133 gen_helper_booke206_tlbilx1(t0);
6134 break;
6135 case 3:
6136 gen_helper_booke206_tlbilx3(t0);
6137 break;
6138 default:
6139 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6140 break;
6141 }
6142
6143 tcg_temp_free(t0);
6144#endif
6145}
6146
Alexander Graf01662f32011-04-30 23:34:58 +02006147
j_mayer76a66252007-03-07 08:32:30 +00006148/* wrtee */
Blue Swirl99e300e2009-06-17 15:22:09 +00006149static void gen_wrtee(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006150{
6151#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00006152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00006153#else
aurel326527f6e2008-12-06 13:03:35 +00006154 TCGv t0;
aurel3276db3ba2008-12-08 18:11:21 +00006155 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00006156 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00006157 return;
6158 }
aurel326527f6e2008-12-06 13:03:35 +00006159 t0 = tcg_temp_new();
6160 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6161 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6162 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6163 tcg_temp_free(t0);
j_mayerdee96f62007-09-29 15:02:38 +00006164 /* Stop translation to have a chance to raise an exception
6165 * if we just set msr_ee to 1
6166 */
aurel32e06fcd72008-12-11 22:42:14 +00006167 gen_stop_exception(ctx);
j_mayer76a66252007-03-07 08:32:30 +00006168#endif
6169}
6170
6171/* wrteei */
Blue Swirl99e300e2009-06-17 15:22:09 +00006172static void gen_wrteei(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006173{
6174#if defined(CONFIG_USER_ONLY)
aurel32e06fcd72008-12-11 22:42:14 +00006175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00006176#else
aurel3276db3ba2008-12-08 18:11:21 +00006177 if (unlikely(!ctx->mem_idx)) {
aurel32e06fcd72008-12-11 22:42:14 +00006178 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
j_mayer76a66252007-03-07 08:32:30 +00006179 return;
6180 }
Baojun Wangfbe73002009-07-03 18:56:57 +08006181 if (ctx->opcode & 0x00008000) {
aurel326527f6e2008-12-06 13:03:35 +00006182 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6183 /* Stop translation to have a chance to raise an exception */
aurel32e06fcd72008-12-11 22:42:14 +00006184 gen_stop_exception(ctx);
aurel326527f6e2008-12-06 13:03:35 +00006185 } else {
aurel321b6e5f92009-01-14 19:40:54 +00006186 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
aurel326527f6e2008-12-06 13:03:35 +00006187 }
j_mayer76a66252007-03-07 08:32:30 +00006188#endif
6189}
6190
j_mayer08e46e52007-04-16 07:18:42 +00006191/* PowerPC 440 specific instructions */
Blue Swirl99e300e2009-06-17 15:22:09 +00006192
Blue Swirl54623272009-06-17 15:22:19 +00006193/* dlmzb */
Blue Swirl99e300e2009-06-17 15:22:09 +00006194static void gen_dlmzb(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006195{
aurel32ef0d51a2008-11-30 17:26:29 +00006196 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6197 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6198 cpu_gpr[rB(ctx->opcode)], t0);
6199 tcg_temp_free_i32(t0);
j_mayer76a66252007-03-07 08:32:30 +00006200}
6201
6202/* mbar replaces eieio on 440 */
Blue Swirl99e300e2009-06-17 15:22:09 +00006203static void gen_mbar(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006204{
6205 /* interpreted as no-op */
6206}
6207
6208/* msync replaces sync on 440 */
Alexander Grafdcb2b9e12012-01-21 03:48:58 +01006209static void gen_msync_4xx(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006210{
6211 /* interpreted as no-op */
6212}
6213
6214/* icbt */
Blue Swirle8eaa2c2009-06-17 15:22:14 +00006215static void gen_icbt_440(DisasContext *ctx)
j_mayer76a66252007-03-07 08:32:30 +00006216{
6217 /* interpreted as no-op */
6218 /* XXX: specification say this is treated as a load by the MMU
6219 * but does not generate any exception
6220 */
6221}
6222
Alexander Graf9e0b5cb2012-01-31 03:18:35 +01006223/* Embedded.Processor Control */
6224
6225static void gen_msgclr(DisasContext *ctx)
6226{
6227#if defined(CONFIG_USER_ONLY)
6228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6229#else
6230 if (unlikely(ctx->mem_idx == 0)) {
6231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6232 return;
6233 }
6234
6235 gen_helper_msgclr(cpu_gpr[rB(ctx->opcode)]);
6236#endif
6237}
6238
Alexander Grafd5d11a32012-01-31 03:19:23 +01006239static void gen_msgsnd(DisasContext *ctx)
6240{
6241#if defined(CONFIG_USER_ONLY)
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6243#else
6244 if (unlikely(ctx->mem_idx == 0)) {
6245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6246 return;
6247 }
6248
6249 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6250#endif
6251}
6252
j_mayera9d9eb82007-10-07 18:19:26 +00006253/*** Altivec vector extension ***/
6254/* Altivec registers moves */
j_mayera9d9eb82007-10-07 18:19:26 +00006255
Blue Swirl636aa202009-08-16 09:06:54 +00006256static inline TCGv_ptr gen_avr_ptr(int reg)
aurel32564e5712008-12-18 22:51:31 +00006257{
aurel32e4704b32009-01-03 13:31:10 +00006258 TCGv_ptr r = tcg_temp_new_ptr();
aurel32564e5712008-12-18 22:51:31 +00006259 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6260 return r;
6261}
6262
j_mayera9d9eb82007-10-07 18:19:26 +00006263#define GEN_VR_LDX(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006264static void glue(gen_, name)(DisasContext *ctx) \
j_mayera9d9eb82007-10-07 18:19:26 +00006265{ \
aurel32fe1e5c52008-11-24 08:47:21 +00006266 TCGv EA; \
j_mayera9d9eb82007-10-07 18:19:26 +00006267 if (unlikely(!ctx->altivec_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00006268 gen_exception(ctx, POWERPC_EXCP_VPU); \
j_mayera9d9eb82007-10-07 18:19:26 +00006269 return; \
6270 } \
aurel3276db3ba2008-12-08 18:11:21 +00006271 gen_set_access_type(ctx, ACCESS_INT); \
aurel32fe1e5c52008-11-24 08:47:21 +00006272 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00006273 gen_addr_reg_index(ctx, EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006274 tcg_gen_andi_tl(EA, EA, ~0xf); \
aurel3276db3ba2008-12-08 18:11:21 +00006275 if (ctx->le_mode) { \
6276 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006277 tcg_gen_addi_tl(EA, EA, 8); \
aurel3276db3ba2008-12-08 18:11:21 +00006278 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006279 } else { \
aurel3276db3ba2008-12-08 18:11:21 +00006280 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006281 tcg_gen_addi_tl(EA, EA, 8); \
aurel3276db3ba2008-12-08 18:11:21 +00006282 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006283 } \
6284 tcg_temp_free(EA); \
j_mayera9d9eb82007-10-07 18:19:26 +00006285}
6286
6287#define GEN_VR_STX(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006288static void gen_st##name(DisasContext *ctx) \
j_mayera9d9eb82007-10-07 18:19:26 +00006289{ \
aurel32fe1e5c52008-11-24 08:47:21 +00006290 TCGv EA; \
j_mayera9d9eb82007-10-07 18:19:26 +00006291 if (unlikely(!ctx->altivec_enabled)) { \
aurel32e06fcd72008-12-11 22:42:14 +00006292 gen_exception(ctx, POWERPC_EXCP_VPU); \
j_mayera9d9eb82007-10-07 18:19:26 +00006293 return; \
6294 } \
aurel3276db3ba2008-12-08 18:11:21 +00006295 gen_set_access_type(ctx, ACCESS_INT); \
aurel32fe1e5c52008-11-24 08:47:21 +00006296 EA = tcg_temp_new(); \
aurel3276db3ba2008-12-08 18:11:21 +00006297 gen_addr_reg_index(ctx, EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006298 tcg_gen_andi_tl(EA, EA, ~0xf); \
aurel3276db3ba2008-12-08 18:11:21 +00006299 if (ctx->le_mode) { \
6300 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006301 tcg_gen_addi_tl(EA, EA, 8); \
aurel3276db3ba2008-12-08 18:11:21 +00006302 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006303 } else { \
aurel3276db3ba2008-12-08 18:11:21 +00006304 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006305 tcg_gen_addi_tl(EA, EA, 8); \
aurel3276db3ba2008-12-08 18:11:21 +00006306 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
aurel32fe1e5c52008-11-24 08:47:21 +00006307 } \
6308 tcg_temp_free(EA); \
j_mayera9d9eb82007-10-07 18:19:26 +00006309}
6310
aurel32cbfb6ae2009-01-04 22:13:10 +00006311#define GEN_VR_LVE(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006312static void gen_lve##name(DisasContext *ctx) \
aurel32cbfb6ae2009-01-04 22:13:10 +00006313 { \
6314 TCGv EA; \
6315 TCGv_ptr rs; \
6316 if (unlikely(!ctx->altivec_enabled)) { \
6317 gen_exception(ctx, POWERPC_EXCP_VPU); \
6318 return; \
6319 } \
6320 gen_set_access_type(ctx, ACCESS_INT); \
6321 EA = tcg_temp_new(); \
6322 gen_addr_reg_index(ctx, EA); \
6323 rs = gen_avr_ptr(rS(ctx->opcode)); \
6324 gen_helper_lve##name (rs, EA); \
6325 tcg_temp_free(EA); \
6326 tcg_temp_free_ptr(rs); \
6327 }
6328
6329#define GEN_VR_STVE(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006330static void gen_stve##name(DisasContext *ctx) \
aurel32cbfb6ae2009-01-04 22:13:10 +00006331 { \
6332 TCGv EA; \
6333 TCGv_ptr rs; \
6334 if (unlikely(!ctx->altivec_enabled)) { \
6335 gen_exception(ctx, POWERPC_EXCP_VPU); \
6336 return; \
6337 } \
6338 gen_set_access_type(ctx, ACCESS_INT); \
6339 EA = tcg_temp_new(); \
6340 gen_addr_reg_index(ctx, EA); \
6341 rs = gen_avr_ptr(rS(ctx->opcode)); \
6342 gen_helper_stve##name (rs, EA); \
6343 tcg_temp_free(EA); \
6344 tcg_temp_free_ptr(rs); \
6345 }
6346
aurel32fe1e5c52008-11-24 08:47:21 +00006347GEN_VR_LDX(lvx, 0x07, 0x03);
j_mayera9d9eb82007-10-07 18:19:26 +00006348/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
aurel32fe1e5c52008-11-24 08:47:21 +00006349GEN_VR_LDX(lvxl, 0x07, 0x0B);
j_mayera9d9eb82007-10-07 18:19:26 +00006350
aurel32cbfb6ae2009-01-04 22:13:10 +00006351GEN_VR_LVE(bx, 0x07, 0x00);
6352GEN_VR_LVE(hx, 0x07, 0x01);
6353GEN_VR_LVE(wx, 0x07, 0x02);
6354
aurel32fe1e5c52008-11-24 08:47:21 +00006355GEN_VR_STX(svx, 0x07, 0x07);
j_mayera9d9eb82007-10-07 18:19:26 +00006356/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
aurel32fe1e5c52008-11-24 08:47:21 +00006357GEN_VR_STX(svxl, 0x07, 0x0F);
j_mayera9d9eb82007-10-07 18:19:26 +00006358
aurel32cbfb6ae2009-01-04 22:13:10 +00006359GEN_VR_STVE(bx, 0x07, 0x04);
6360GEN_VR_STVE(hx, 0x07, 0x05);
6361GEN_VR_STVE(wx, 0x07, 0x06);
6362
Blue Swirl99e300e2009-06-17 15:22:09 +00006363static void gen_lvsl(DisasContext *ctx)
aurel32bf8d8de2009-01-04 22:09:42 +00006364{
6365 TCGv_ptr rd;
6366 TCGv EA;
6367 if (unlikely(!ctx->altivec_enabled)) {
6368 gen_exception(ctx, POWERPC_EXCP_VPU);
6369 return;
6370 }
6371 EA = tcg_temp_new();
6372 gen_addr_reg_index(ctx, EA);
6373 rd = gen_avr_ptr(rD(ctx->opcode));
6374 gen_helper_lvsl(rd, EA);
6375 tcg_temp_free(EA);
6376 tcg_temp_free_ptr(rd);
6377}
6378
Blue Swirl99e300e2009-06-17 15:22:09 +00006379static void gen_lvsr(DisasContext *ctx)
aurel32bf8d8de2009-01-04 22:09:42 +00006380{
6381 TCGv_ptr rd;
6382 TCGv EA;
6383 if (unlikely(!ctx->altivec_enabled)) {
6384 gen_exception(ctx, POWERPC_EXCP_VPU);
6385 return;
6386 }
6387 EA = tcg_temp_new();
6388 gen_addr_reg_index(ctx, EA);
6389 rd = gen_avr_ptr(rD(ctx->opcode));
6390 gen_helper_lvsr(rd, EA);
6391 tcg_temp_free(EA);
6392 tcg_temp_free_ptr(rd);
6393}
6394
Blue Swirl99e300e2009-06-17 15:22:09 +00006395static void gen_mfvscr(DisasContext *ctx)
aurel32785f4512009-01-04 22:51:59 +00006396{
6397 TCGv_i32 t;
6398 if (unlikely(!ctx->altivec_enabled)) {
6399 gen_exception(ctx, POWERPC_EXCP_VPU);
6400 return;
6401 }
6402 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6403 t = tcg_temp_new_i32();
6404 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6405 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
aurel32fce5ecb2009-02-03 19:55:13 +00006406 tcg_temp_free_i32(t);
aurel32785f4512009-01-04 22:51:59 +00006407}
6408
Blue Swirl99e300e2009-06-17 15:22:09 +00006409static void gen_mtvscr(DisasContext *ctx)
aurel32785f4512009-01-04 22:51:59 +00006410{
aurel326e87b7c2009-02-03 19:56:09 +00006411 TCGv_ptr p;
aurel32785f4512009-01-04 22:51:59 +00006412 if (unlikely(!ctx->altivec_enabled)) {
6413 gen_exception(ctx, POWERPC_EXCP_VPU);
6414 return;
6415 }
aurel326e87b7c2009-02-03 19:56:09 +00006416 p = gen_avr_ptr(rD(ctx->opcode));
6417 gen_helper_mtvscr(p);
6418 tcg_temp_free_ptr(p);
aurel32785f4512009-01-04 22:51:59 +00006419}
6420
aurel327a9b96c2008-12-18 22:42:58 +00006421/* Logical operations */
6422#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006423static void glue(gen_, name)(DisasContext *ctx) \
aurel327a9b96c2008-12-18 22:42:58 +00006424{ \
6425 if (unlikely(!ctx->altivec_enabled)) { \
6426 gen_exception(ctx, POWERPC_EXCP_VPU); \
6427 return; \
6428 } \
6429 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6430 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6431}
6432
6433GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6434GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6435GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6436GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6437GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6438
aurel328e27dd62009-01-03 13:31:30 +00006439#define GEN_VXFORM(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006440static void glue(gen_, name)(DisasContext *ctx) \
aurel328e27dd62009-01-03 13:31:30 +00006441{ \
6442 TCGv_ptr ra, rb, rd; \
6443 if (unlikely(!ctx->altivec_enabled)) { \
6444 gen_exception(ctx, POWERPC_EXCP_VPU); \
6445 return; \
6446 } \
6447 ra = gen_avr_ptr(rA(ctx->opcode)); \
6448 rb = gen_avr_ptr(rB(ctx->opcode)); \
6449 rd = gen_avr_ptr(rD(ctx->opcode)); \
6450 gen_helper_##name (rd, ra, rb); \
6451 tcg_temp_free_ptr(ra); \
6452 tcg_temp_free_ptr(rb); \
6453 tcg_temp_free_ptr(rd); \
6454}
6455
aurel327872c512009-01-03 13:31:40 +00006456GEN_VXFORM(vaddubm, 0, 0);
6457GEN_VXFORM(vadduhm, 0, 1);
6458GEN_VXFORM(vadduwm, 0, 2);
6459GEN_VXFORM(vsububm, 0, 16);
6460GEN_VXFORM(vsubuhm, 0, 17);
6461GEN_VXFORM(vsubuwm, 0, 18);
aurel32e4039332009-01-03 13:31:58 +00006462GEN_VXFORM(vmaxub, 1, 0);
6463GEN_VXFORM(vmaxuh, 1, 1);
6464GEN_VXFORM(vmaxuw, 1, 2);
6465GEN_VXFORM(vmaxsb, 1, 4);
6466GEN_VXFORM(vmaxsh, 1, 5);
6467GEN_VXFORM(vmaxsw, 1, 6);
6468GEN_VXFORM(vminub, 1, 8);
6469GEN_VXFORM(vminuh, 1, 9);
6470GEN_VXFORM(vminuw, 1, 10);
6471GEN_VXFORM(vminsb, 1, 12);
6472GEN_VXFORM(vminsh, 1, 13);
6473GEN_VXFORM(vminsw, 1, 14);
aurel32fab3cbe2009-01-03 13:31:49 +00006474GEN_VXFORM(vavgub, 1, 16);
6475GEN_VXFORM(vavguh, 1, 17);
6476GEN_VXFORM(vavguw, 1, 18);
6477GEN_VXFORM(vavgsb, 1, 20);
6478GEN_VXFORM(vavgsh, 1, 21);
6479GEN_VXFORM(vavgsw, 1, 22);
aurel323b430042009-01-04 22:08:38 +00006480GEN_VXFORM(vmrghb, 6, 0);
6481GEN_VXFORM(vmrghh, 6, 1);
6482GEN_VXFORM(vmrghw, 6, 2);
6483GEN_VXFORM(vmrglb, 6, 4);
6484GEN_VXFORM(vmrglh, 6, 5);
6485GEN_VXFORM(vmrglw, 6, 6);
aurel322c277902009-01-04 22:08:48 +00006486GEN_VXFORM(vmuloub, 4, 0);
6487GEN_VXFORM(vmulouh, 4, 1);
6488GEN_VXFORM(vmulosb, 4, 4);
6489GEN_VXFORM(vmulosh, 4, 5);
6490GEN_VXFORM(vmuleub, 4, 8);
6491GEN_VXFORM(vmuleuh, 4, 9);
6492GEN_VXFORM(vmulesb, 4, 12);
6493GEN_VXFORM(vmulesh, 4, 13);
aurel32d79f0802009-01-04 22:09:08 +00006494GEN_VXFORM(vslb, 2, 4);
6495GEN_VXFORM(vslh, 2, 5);
6496GEN_VXFORM(vslw, 2, 6);
aurel3207ef34c2009-01-04 22:08:58 +00006497GEN_VXFORM(vsrb, 2, 8);
6498GEN_VXFORM(vsrh, 2, 9);
6499GEN_VXFORM(vsrw, 2, 10);
6500GEN_VXFORM(vsrab, 2, 12);
6501GEN_VXFORM(vsrah, 2, 13);
6502GEN_VXFORM(vsraw, 2, 14);
aurel327b239be2009-01-04 22:09:19 +00006503GEN_VXFORM(vslo, 6, 16);
6504GEN_VXFORM(vsro, 6, 17);
aurel32e343da72009-01-04 22:09:31 +00006505GEN_VXFORM(vaddcuw, 0, 6);
6506GEN_VXFORM(vsubcuw, 0, 22);
aurel325ab09f32009-01-08 23:19:50 +00006507GEN_VXFORM(vaddubs, 0, 8);
6508GEN_VXFORM(vadduhs, 0, 9);
6509GEN_VXFORM(vadduws, 0, 10);
6510GEN_VXFORM(vaddsbs, 0, 12);
6511GEN_VXFORM(vaddshs, 0, 13);
6512GEN_VXFORM(vaddsws, 0, 14);
6513GEN_VXFORM(vsububs, 0, 24);
6514GEN_VXFORM(vsubuhs, 0, 25);
6515GEN_VXFORM(vsubuws, 0, 26);
6516GEN_VXFORM(vsubsbs, 0, 28);
6517GEN_VXFORM(vsubshs, 0, 29);
6518GEN_VXFORM(vsubsws, 0, 30);
aurel325e1d0982009-01-04 22:09:52 +00006519GEN_VXFORM(vrlb, 2, 0);
6520GEN_VXFORM(vrlh, 2, 1);
6521GEN_VXFORM(vrlw, 2, 2);
aurel32d9430ad2009-01-08 18:54:48 +00006522GEN_VXFORM(vsl, 2, 7);
6523GEN_VXFORM(vsr, 2, 11);
aurel325335a142009-01-04 22:12:09 +00006524GEN_VXFORM(vpkuhum, 7, 0);
6525GEN_VXFORM(vpkuwum, 7, 1);
6526GEN_VXFORM(vpkuhus, 7, 2);
6527GEN_VXFORM(vpkuwus, 7, 3);
6528GEN_VXFORM(vpkshus, 7, 4);
6529GEN_VXFORM(vpkswus, 7, 5);
6530GEN_VXFORM(vpkshss, 7, 6);
6531GEN_VXFORM(vpkswss, 7, 7);
aurel321dd9ffb2009-01-04 22:12:19 +00006532GEN_VXFORM(vpkpx, 7, 12);
aurel328142cdd2009-01-04 22:13:21 +00006533GEN_VXFORM(vsum4ubs, 4, 24);
6534GEN_VXFORM(vsum4sbs, 4, 28);
6535GEN_VXFORM(vsum4shs, 4, 25);
6536GEN_VXFORM(vsum2sws, 4, 26);
6537GEN_VXFORM(vsumsws, 4, 30);
aurel3256fdd212009-02-09 16:48:51 +00006538GEN_VXFORM(vaddfp, 5, 0);
6539GEN_VXFORM(vsubfp, 5, 1);
aurel321536ff62009-02-09 16:48:39 +00006540GEN_VXFORM(vmaxfp, 5, 16);
6541GEN_VXFORM(vminfp, 5, 17);
aurel32fab3cbe2009-01-03 13:31:49 +00006542
aurel320cbcd902009-01-08 18:54:26 +00006543#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
Blue Swirle8eaa2c2009-06-17 15:22:14 +00006544static void glue(gen_, name)(DisasContext *ctx) \
aurel320cbcd902009-01-08 18:54:26 +00006545 { \
6546 TCGv_ptr ra, rb, rd; \
6547 if (unlikely(!ctx->altivec_enabled)) { \
6548 gen_exception(ctx, POWERPC_EXCP_VPU); \
6549 return; \
6550 } \
6551 ra = gen_avr_ptr(rA(ctx->opcode)); \
6552 rb = gen_avr_ptr(rB(ctx->opcode)); \
6553 rd = gen_avr_ptr(rD(ctx->opcode)); \
6554 gen_helper_##opname (rd, ra, rb); \
6555 tcg_temp_free_ptr(ra); \
6556 tcg_temp_free_ptr(rb); \
6557 tcg_temp_free_ptr(rd); \
6558 }
6559
6560#define GEN_VXRFORM(name, opc2, opc3) \
6561 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6562 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6563
aurel321add6e22009-01-08 18:54:38 +00006564GEN_VXRFORM(vcmpequb, 3, 0)
6565GEN_VXRFORM(vcmpequh, 3, 1)
6566GEN_VXRFORM(vcmpequw, 3, 2)
6567GEN_VXRFORM(vcmpgtsb, 3, 12)
6568GEN_VXRFORM(vcmpgtsh, 3, 13)
6569GEN_VXRFORM(vcmpgtsw, 3, 14)
6570GEN_VXRFORM(vcmpgtub, 3, 8)
6571GEN_VXRFORM(vcmpgtuh, 3, 9)
6572GEN_VXRFORM(vcmpgtuw, 3, 10)
aurel32819ca122009-02-09 16:49:10 +00006573GEN_VXRFORM(vcmpeqfp, 3, 3)
6574GEN_VXRFORM(vcmpgefp, 3, 7)
6575GEN_VXRFORM(vcmpgtfp, 3, 11)
6576GEN_VXRFORM(vcmpbfp, 3, 15)
aurel321add6e22009-01-08 18:54:38 +00006577
aurel32c0267662009-01-08 18:54:57 +00006578#define GEN_VXFORM_SIMM(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006579static void glue(gen_, name)(DisasContext *ctx) \
aurel32c0267662009-01-08 18:54:57 +00006580 { \
6581 TCGv_ptr rd; \
6582 TCGv_i32 simm; \
6583 if (unlikely(!ctx->altivec_enabled)) { \
6584 gen_exception(ctx, POWERPC_EXCP_VPU); \
6585 return; \
6586 } \
6587 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6588 rd = gen_avr_ptr(rD(ctx->opcode)); \
6589 gen_helper_##name (rd, simm); \
6590 tcg_temp_free_i32(simm); \
6591 tcg_temp_free_ptr(rd); \
6592 }
6593
6594GEN_VXFORM_SIMM(vspltisb, 6, 12);
6595GEN_VXFORM_SIMM(vspltish, 6, 13);
6596GEN_VXFORM_SIMM(vspltisw, 6, 14);
6597
aurel32de5f2482009-01-04 22:10:59 +00006598#define GEN_VXFORM_NOA(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006599static void glue(gen_, name)(DisasContext *ctx) \
aurel32de5f2482009-01-04 22:10:59 +00006600 { \
6601 TCGv_ptr rb, rd; \
6602 if (unlikely(!ctx->altivec_enabled)) { \
6603 gen_exception(ctx, POWERPC_EXCP_VPU); \
6604 return; \
6605 } \
6606 rb = gen_avr_ptr(rB(ctx->opcode)); \
6607 rd = gen_avr_ptr(rD(ctx->opcode)); \
6608 gen_helper_##name (rd, rb); \
6609 tcg_temp_free_ptr(rb); \
6610 tcg_temp_free_ptr(rd); \
6611 }
6612
aurel326cf1c6e2009-01-04 22:11:20 +00006613GEN_VXFORM_NOA(vupkhsb, 7, 8);
6614GEN_VXFORM_NOA(vupkhsh, 7, 9);
6615GEN_VXFORM_NOA(vupklsb, 7, 10);
6616GEN_VXFORM_NOA(vupklsh, 7, 11);
aurel3279f85c32009-01-04 22:11:10 +00006617GEN_VXFORM_NOA(vupkhpx, 7, 13);
6618GEN_VXFORM_NOA(vupklpx, 7, 15);
aurel32bdfbac32009-02-09 16:49:29 +00006619GEN_VXFORM_NOA(vrefp, 5, 4);
aurel32071fc3b2009-02-09 16:49:40 +00006620GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
Aurelien Jarno0bffbc62009-02-09 12:20:50 +01006621GEN_VXFORM_NOA(vexptefp, 5, 6);
aurel32b5807632009-02-05 22:33:36 +00006622GEN_VXFORM_NOA(vlogefp, 5, 7);
aurel32f6b19642009-02-04 13:52:03 +00006623GEN_VXFORM_NOA(vrfim, 5, 8);
6624GEN_VXFORM_NOA(vrfin, 5, 9);
6625GEN_VXFORM_NOA(vrfip, 5, 10);
6626GEN_VXFORM_NOA(vrfiz, 5, 11);
aurel3279f85c32009-01-04 22:11:10 +00006627
aurel3221d21582009-01-04 22:10:28 +00006628#define GEN_VXFORM_SIMM(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006629static void glue(gen_, name)(DisasContext *ctx) \
aurel3221d21582009-01-04 22:10:28 +00006630 { \
6631 TCGv_ptr rd; \
6632 TCGv_i32 simm; \
6633 if (unlikely(!ctx->altivec_enabled)) { \
6634 gen_exception(ctx, POWERPC_EXCP_VPU); \
6635 return; \
6636 } \
6637 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6638 rd = gen_avr_ptr(rD(ctx->opcode)); \
6639 gen_helper_##name (rd, simm); \
6640 tcg_temp_free_i32(simm); \
6641 tcg_temp_free_ptr(rd); \
6642 }
6643
aurel3227a4edb2009-01-04 22:10:40 +00006644#define GEN_VXFORM_UIMM(name, opc2, opc3) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006645static void glue(gen_, name)(DisasContext *ctx) \
aurel3227a4edb2009-01-04 22:10:40 +00006646 { \
6647 TCGv_ptr rb, rd; \
6648 TCGv_i32 uimm; \
6649 if (unlikely(!ctx->altivec_enabled)) { \
6650 gen_exception(ctx, POWERPC_EXCP_VPU); \
6651 return; \
6652 } \
6653 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6654 rb = gen_avr_ptr(rB(ctx->opcode)); \
6655 rd = gen_avr_ptr(rD(ctx->opcode)); \
6656 gen_helper_##name (rd, rb, uimm); \
6657 tcg_temp_free_i32(uimm); \
6658 tcg_temp_free_ptr(rb); \
6659 tcg_temp_free_ptr(rd); \
6660 }
6661
aurel32e4e6bee2009-01-04 22:10:49 +00006662GEN_VXFORM_UIMM(vspltb, 6, 8);
6663GEN_VXFORM_UIMM(vsplth, 6, 9);
6664GEN_VXFORM_UIMM(vspltw, 6, 10);
aurel32e1406322009-02-04 13:52:17 +00006665GEN_VXFORM_UIMM(vcfux, 5, 12);
6666GEN_VXFORM_UIMM(vcfsx, 5, 13);
aurel32875b31d2009-02-09 16:49:20 +00006667GEN_VXFORM_UIMM(vctuxs, 5, 14);
6668GEN_VXFORM_UIMM(vctsxs, 5, 15);
aurel32e4e6bee2009-01-04 22:10:49 +00006669
Blue Swirl99e300e2009-06-17 15:22:09 +00006670static void gen_vsldoi(DisasContext *ctx)
aurel32cd633b12009-01-04 22:10:09 +00006671{
6672 TCGv_ptr ra, rb, rd;
aurel32fce5ecb2009-02-03 19:55:13 +00006673 TCGv_i32 sh;
aurel32cd633b12009-01-04 22:10:09 +00006674 if (unlikely(!ctx->altivec_enabled)) {
6675 gen_exception(ctx, POWERPC_EXCP_VPU);
6676 return;
6677 }
6678 ra = gen_avr_ptr(rA(ctx->opcode));
6679 rb = gen_avr_ptr(rB(ctx->opcode));
6680 rd = gen_avr_ptr(rD(ctx->opcode));
6681 sh = tcg_const_i32(VSH(ctx->opcode));
6682 gen_helper_vsldoi (rd, ra, rb, sh);
6683 tcg_temp_free_ptr(ra);
6684 tcg_temp_free_ptr(rb);
6685 tcg_temp_free_ptr(rd);
aurel32fce5ecb2009-02-03 19:55:13 +00006686 tcg_temp_free_i32(sh);
aurel32cd633b12009-01-04 22:10:09 +00006687}
6688
aurel32707cec32009-01-04 22:11:29 +00006689#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006690static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
aurel32707cec32009-01-04 22:11:29 +00006691 { \
6692 TCGv_ptr ra, rb, rc, rd; \
6693 if (unlikely(!ctx->altivec_enabled)) { \
6694 gen_exception(ctx, POWERPC_EXCP_VPU); \
6695 return; \
6696 } \
6697 ra = gen_avr_ptr(rA(ctx->opcode)); \
6698 rb = gen_avr_ptr(rB(ctx->opcode)); \
6699 rc = gen_avr_ptr(rC(ctx->opcode)); \
6700 rd = gen_avr_ptr(rD(ctx->opcode)); \
6701 if (Rc(ctx->opcode)) { \
6702 gen_helper_##name1 (rd, ra, rb, rc); \
6703 } else { \
6704 gen_helper_##name0 (rd, ra, rb, rc); \
6705 } \
6706 tcg_temp_free_ptr(ra); \
6707 tcg_temp_free_ptr(rb); \
6708 tcg_temp_free_ptr(rc); \
6709 tcg_temp_free_ptr(rd); \
6710 }
6711
aurel32b161ae22009-01-04 22:12:29 +00006712GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6713
Blue Swirl99e300e2009-06-17 15:22:09 +00006714static void gen_vmladduhm(DisasContext *ctx)
aurel32bcd2ee22009-01-04 22:13:00 +00006715{
6716 TCGv_ptr ra, rb, rc, rd;
6717 if (unlikely(!ctx->altivec_enabled)) {
6718 gen_exception(ctx, POWERPC_EXCP_VPU);
6719 return;
6720 }
6721 ra = gen_avr_ptr(rA(ctx->opcode));
6722 rb = gen_avr_ptr(rB(ctx->opcode));
6723 rc = gen_avr_ptr(rC(ctx->opcode));
6724 rd = gen_avr_ptr(rD(ctx->opcode));
6725 gen_helper_vmladduhm(rd, ra, rb, rc);
6726 tcg_temp_free_ptr(ra);
6727 tcg_temp_free_ptr(rb);
6728 tcg_temp_free_ptr(rc);
6729 tcg_temp_free_ptr(rd);
6730}
6731
aurel32b04ae982009-01-04 22:11:39 +00006732GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
aurel324d9903b2009-01-04 22:12:39 +00006733GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
aurel32eae07262009-01-04 22:12:49 +00006734GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
aurel32d1258692009-01-04 22:11:49 +00006735GEN_VAFORM_PAIRED(vsel, vperm, 21)
aurel3235cf7c72009-02-09 16:48:59 +00006736GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
aurel32b04ae982009-01-04 22:11:39 +00006737
j_mayer0487d6a2007-03-20 22:11:31 +00006738/*** SPE extension ***/
j_mayer0487d6a2007-03-20 22:11:31 +00006739/* Register moves */
j_mayer3cd7d1d2007-11-12 01:56:18 +00006740
Fabien Chouteaua0e13902011-03-16 11:21:22 +01006741
6742static inline void gen_evmra(DisasContext *ctx)
6743{
6744
6745 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02006746 gen_exception(ctx, POWERPC_EXCP_SPEU);
Fabien Chouteaua0e13902011-03-16 11:21:22 +01006747 return;
6748 }
6749
6750#if defined(TARGET_PPC64)
6751 /* rD := rA */
6752 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6753
6754 /* spe_acc := rA */
6755 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6756 cpu_env,
6757 offsetof(CPUState, spe_acc));
6758#else
6759 TCGv_i64 tmp = tcg_temp_new_i64();
6760
6761 /* tmp := rA_lo + rA_hi << 32 */
6762 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6763
6764 /* spe_acc := tmp */
6765 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
6766 tcg_temp_free_i64(tmp);
6767
6768 /* rD := rA */
6769 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6770 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6771#endif
6772}
6773
Blue Swirl636aa202009-08-16 09:06:54 +00006774static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6775{
aurel32f78fb442008-09-04 05:25:47 +00006776#if defined(TARGET_PPC64)
6777 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6778#else
pbrook36aa55d2008-09-21 13:48:32 +00006779 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
j_mayer0487d6a2007-03-20 22:11:31 +00006780#endif
aurel32f78fb442008-09-04 05:25:47 +00006781}
j_mayer0487d6a2007-03-20 22:11:31 +00006782
Blue Swirl636aa202009-08-16 09:06:54 +00006783static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6784{
aurel32f78fb442008-09-04 05:25:47 +00006785#if defined(TARGET_PPC64)
6786 tcg_gen_mov_i64(cpu_gpr[reg], t);
6787#else
pbrooka7812ae2008-11-17 14:43:54 +00006788 TCGv_i64 tmp = tcg_temp_new_i64();
aurel32f78fb442008-09-04 05:25:47 +00006789 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
aurel32f78fb442008-09-04 05:25:47 +00006790 tcg_gen_shri_i64(tmp, t, 32);
6791 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
pbrooka7812ae2008-11-17 14:43:54 +00006792 tcg_temp_free_i64(tmp);
j_mayer0487d6a2007-03-20 22:11:31 +00006793#endif
aurel32f78fb442008-09-04 05:25:47 +00006794}
j_mayer3cd7d1d2007-11-12 01:56:18 +00006795
Fabien Chouteau70560da2011-09-28 05:54:05 +00006796#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
Blue Swirl99e300e2009-06-17 15:22:09 +00006797static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00006798{ \
6799 if (Rc(ctx->opcode)) \
6800 gen_##name1(ctx); \
6801 else \
6802 gen_##name0(ctx); \
6803}
6804
6805/* Handler for undefined SPE opcodes */
Blue Swirl636aa202009-08-16 09:06:54 +00006806static inline void gen_speundef(DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00006807{
aurel32e06fcd72008-12-11 22:42:14 +00006808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
j_mayer0487d6a2007-03-20 22:11:31 +00006809}
6810
aurel3257951c22008-11-10 11:10:23 +00006811/* SPE logic */
6812#if defined(TARGET_PPC64)
6813#define GEN_SPEOP_LOGIC2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006814static inline void gen_##name(DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00006815{ \
6816 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006817 gen_exception(ctx, POWERPC_EXCP_SPEU); \
j_mayer0487d6a2007-03-20 22:11:31 +00006818 return; \
6819 } \
aurel3257951c22008-11-10 11:10:23 +00006820 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6821 cpu_gpr[rB(ctx->opcode)]); \
j_mayer0487d6a2007-03-20 22:11:31 +00006822}
aurel3257951c22008-11-10 11:10:23 +00006823#else
6824#define GEN_SPEOP_LOGIC2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006825static inline void gen_##name(DisasContext *ctx) \
aurel323d3a6a02008-10-15 17:00:45 +00006826{ \
6827 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006828 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel323d3a6a02008-10-15 17:00:45 +00006829 return; \
6830 } \
aurel3257951c22008-11-10 11:10:23 +00006831 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6832 cpu_gpr[rB(ctx->opcode)]); \
6833 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6834 cpu_gprh[rB(ctx->opcode)]); \
6835}
6836#endif
6837
6838GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6839GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6840GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6841GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6842GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6843GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6844GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6845GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6846
6847/* SPE logic immediate */
6848#if defined(TARGET_PPC64)
6849#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
Blue Swirl636aa202009-08-16 09:06:54 +00006850static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00006851{ \
6852 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006853 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00006854 return; \
6855 } \
pbrooka7812ae2008-11-17 14:43:54 +00006856 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6857 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6858 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
aurel3257951c22008-11-10 11:10:23 +00006859 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6860 tcg_opi(t0, t0, rB(ctx->opcode)); \
6861 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6862 tcg_gen_trunc_i64_i32(t1, t2); \
pbrooka7812ae2008-11-17 14:43:54 +00006863 tcg_temp_free_i64(t2); \
aurel3257951c22008-11-10 11:10:23 +00006864 tcg_opi(t1, t1, rB(ctx->opcode)); \
6865 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
pbrooka7812ae2008-11-17 14:43:54 +00006866 tcg_temp_free_i32(t0); \
6867 tcg_temp_free_i32(t1); \
aurel323d3a6a02008-10-15 17:00:45 +00006868}
aurel3257951c22008-11-10 11:10:23 +00006869#else
6870#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
Blue Swirl636aa202009-08-16 09:06:54 +00006871static inline void gen_##name(DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00006872{ \
6873 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006874 gen_exception(ctx, POWERPC_EXCP_SPEU); \
j_mayer0487d6a2007-03-20 22:11:31 +00006875 return; \
6876 } \
aurel3257951c22008-11-10 11:10:23 +00006877 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6878 rB(ctx->opcode)); \
6879 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6880 rB(ctx->opcode)); \
j_mayer0487d6a2007-03-20 22:11:31 +00006881}
aurel3257951c22008-11-10 11:10:23 +00006882#endif
6883GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6884GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6885GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6886GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
j_mayer0487d6a2007-03-20 22:11:31 +00006887
aurel3257951c22008-11-10 11:10:23 +00006888/* SPE arithmetic */
6889#if defined(TARGET_PPC64)
6890#define GEN_SPEOP_ARITH1(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006891static inline void gen_##name(DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00006892{ \
6893 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006894 gen_exception(ctx, POWERPC_EXCP_SPEU); \
j_mayer0487d6a2007-03-20 22:11:31 +00006895 return; \
6896 } \
pbrooka7812ae2008-11-17 14:43:54 +00006897 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6898 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6899 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
aurel3257951c22008-11-10 11:10:23 +00006900 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6901 tcg_op(t0, t0); \
6902 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6903 tcg_gen_trunc_i64_i32(t1, t2); \
pbrooka7812ae2008-11-17 14:43:54 +00006904 tcg_temp_free_i64(t2); \
aurel3257951c22008-11-10 11:10:23 +00006905 tcg_op(t1, t1); \
6906 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
pbrooka7812ae2008-11-17 14:43:54 +00006907 tcg_temp_free_i32(t0); \
6908 tcg_temp_free_i32(t1); \
j_mayer0487d6a2007-03-20 22:11:31 +00006909}
aurel3257951c22008-11-10 11:10:23 +00006910#else
pbrooka7812ae2008-11-17 14:43:54 +00006911#define GEN_SPEOP_ARITH1(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006912static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00006913{ \
6914 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006915 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00006916 return; \
6917 } \
6918 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6919 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6920}
6921#endif
j_mayer0487d6a2007-03-20 22:11:31 +00006922
Blue Swirl636aa202009-08-16 09:06:54 +00006923static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
aurel3257951c22008-11-10 11:10:23 +00006924{
6925 int l1 = gen_new_label();
6926 int l2 = gen_new_label();
j_mayer0487d6a2007-03-20 22:11:31 +00006927
aurel3257951c22008-11-10 11:10:23 +00006928 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6929 tcg_gen_neg_i32(ret, arg1);
6930 tcg_gen_br(l2);
6931 gen_set_label(l1);
pbrooka7812ae2008-11-17 14:43:54 +00006932 tcg_gen_mov_i32(ret, arg1);
aurel3257951c22008-11-10 11:10:23 +00006933 gen_set_label(l2);
6934}
6935GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6936GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6937GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6938GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
Blue Swirl636aa202009-08-16 09:06:54 +00006939static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
aurel3257951c22008-11-10 11:10:23 +00006940{
6941 tcg_gen_addi_i32(ret, arg1, 0x8000);
6942 tcg_gen_ext16u_i32(ret, ret);
6943}
6944GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
pbrooka7812ae2008-11-17 14:43:54 +00006945GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6946GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
aurel3257951c22008-11-10 11:10:23 +00006947
6948#if defined(TARGET_PPC64)
6949#define GEN_SPEOP_ARITH2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006950static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00006951{ \
6952 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006953 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00006954 return; \
6955 } \
pbrooka7812ae2008-11-17 14:43:54 +00006956 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6957 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6958 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
aurel32501e23c2009-01-03 12:35:38 +00006959 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
aurel3257951c22008-11-10 11:10:23 +00006960 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6961 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6962 tcg_op(t0, t0, t2); \
6963 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6964 tcg_gen_trunc_i64_i32(t1, t3); \
6965 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6966 tcg_gen_trunc_i64_i32(t2, t3); \
pbrooka7812ae2008-11-17 14:43:54 +00006967 tcg_temp_free_i64(t3); \
aurel3257951c22008-11-10 11:10:23 +00006968 tcg_op(t1, t1, t2); \
pbrooka7812ae2008-11-17 14:43:54 +00006969 tcg_temp_free_i32(t2); \
aurel3257951c22008-11-10 11:10:23 +00006970 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
pbrooka7812ae2008-11-17 14:43:54 +00006971 tcg_temp_free_i32(t0); \
6972 tcg_temp_free_i32(t1); \
aurel3257951c22008-11-10 11:10:23 +00006973}
6974#else
6975#define GEN_SPEOP_ARITH2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00006976static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00006977{ \
6978 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02006979 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00006980 return; \
6981 } \
6982 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6983 cpu_gpr[rB(ctx->opcode)]); \
6984 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6985 cpu_gprh[rB(ctx->opcode)]); \
6986}
6987#endif
6988
Blue Swirl636aa202009-08-16 09:06:54 +00006989static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3257951c22008-11-10 11:10:23 +00006990{
pbrooka7812ae2008-11-17 14:43:54 +00006991 TCGv_i32 t0;
aurel3257951c22008-11-10 11:10:23 +00006992 int l1, l2;
6993
6994 l1 = gen_new_label();
6995 l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00006996 t0 = tcg_temp_local_new_i32();
aurel3257951c22008-11-10 11:10:23 +00006997 /* No error here: 6 bits are used */
6998 tcg_gen_andi_i32(t0, arg2, 0x3F);
6999 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7000 tcg_gen_shr_i32(ret, arg1, t0);
7001 tcg_gen_br(l2);
7002 gen_set_label(l1);
7003 tcg_gen_movi_i32(ret, 0);
Aurelien Jarno0aef4262010-03-11 21:29:42 +01007004 gen_set_label(l2);
pbrooka7812ae2008-11-17 14:43:54 +00007005 tcg_temp_free_i32(t0);
aurel3257951c22008-11-10 11:10:23 +00007006}
7007GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
Blue Swirl636aa202009-08-16 09:06:54 +00007008static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3257951c22008-11-10 11:10:23 +00007009{
pbrooka7812ae2008-11-17 14:43:54 +00007010 TCGv_i32 t0;
aurel3257951c22008-11-10 11:10:23 +00007011 int l1, l2;
7012
7013 l1 = gen_new_label();
7014 l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00007015 t0 = tcg_temp_local_new_i32();
aurel3257951c22008-11-10 11:10:23 +00007016 /* No error here: 6 bits are used */
7017 tcg_gen_andi_i32(t0, arg2, 0x3F);
7018 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7019 tcg_gen_sar_i32(ret, arg1, t0);
7020 tcg_gen_br(l2);
7021 gen_set_label(l1);
7022 tcg_gen_movi_i32(ret, 0);
Aurelien Jarno0aef4262010-03-11 21:29:42 +01007023 gen_set_label(l2);
pbrooka7812ae2008-11-17 14:43:54 +00007024 tcg_temp_free_i32(t0);
aurel3257951c22008-11-10 11:10:23 +00007025}
7026GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
Blue Swirl636aa202009-08-16 09:06:54 +00007027static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3257951c22008-11-10 11:10:23 +00007028{
pbrooka7812ae2008-11-17 14:43:54 +00007029 TCGv_i32 t0;
aurel3257951c22008-11-10 11:10:23 +00007030 int l1, l2;
7031
7032 l1 = gen_new_label();
7033 l2 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00007034 t0 = tcg_temp_local_new_i32();
aurel3257951c22008-11-10 11:10:23 +00007035 /* No error here: 6 bits are used */
7036 tcg_gen_andi_i32(t0, arg2, 0x3F);
7037 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7038 tcg_gen_shl_i32(ret, arg1, t0);
7039 tcg_gen_br(l2);
7040 gen_set_label(l1);
7041 tcg_gen_movi_i32(ret, 0);
Aurelien Jarnoe29ef9f2010-03-11 21:14:47 +01007042 gen_set_label(l2);
pbrooka7812ae2008-11-17 14:43:54 +00007043 tcg_temp_free_i32(t0);
aurel3257951c22008-11-10 11:10:23 +00007044}
7045GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
Blue Swirl636aa202009-08-16 09:06:54 +00007046static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3257951c22008-11-10 11:10:23 +00007047{
pbrooka7812ae2008-11-17 14:43:54 +00007048 TCGv_i32 t0 = tcg_temp_new_i32();
aurel3257951c22008-11-10 11:10:23 +00007049 tcg_gen_andi_i32(t0, arg2, 0x1F);
7050 tcg_gen_rotl_i32(ret, arg1, t0);
pbrooka7812ae2008-11-17 14:43:54 +00007051 tcg_temp_free_i32(t0);
aurel3257951c22008-11-10 11:10:23 +00007052}
7053GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
Blue Swirl636aa202009-08-16 09:06:54 +00007054static inline void gen_evmergehi(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007055{
7056 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007057 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel3257951c22008-11-10 11:10:23 +00007058 return;
7059 }
7060#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00007061 TCGv t0 = tcg_temp_new();
7062 TCGv t1 = tcg_temp_new();
aurel3257951c22008-11-10 11:10:23 +00007063 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7064 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7065 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7066 tcg_temp_free(t0);
7067 tcg_temp_free(t1);
7068#else
7069 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7070 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7071#endif
7072}
7073GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
Blue Swirl636aa202009-08-16 09:06:54 +00007074static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
aurel3257951c22008-11-10 11:10:23 +00007075{
7076 tcg_gen_sub_i32(ret, arg2, arg1);
7077}
7078GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7079
7080/* SPE arithmetic immediate */
7081#if defined(TARGET_PPC64)
7082#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00007083static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00007084{ \
7085 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02007086 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00007087 return; \
7088 } \
pbrooka7812ae2008-11-17 14:43:54 +00007089 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7090 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7091 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
aurel3257951c22008-11-10 11:10:23 +00007092 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7093 tcg_op(t0, t0, rA(ctx->opcode)); \
7094 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7095 tcg_gen_trunc_i64_i32(t1, t2); \
aurel32e06fcd72008-12-11 22:42:14 +00007096 tcg_temp_free_i64(t2); \
aurel3257951c22008-11-10 11:10:23 +00007097 tcg_op(t1, t1, rA(ctx->opcode)); \
7098 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
pbrooka7812ae2008-11-17 14:43:54 +00007099 tcg_temp_free_i32(t0); \
7100 tcg_temp_free_i32(t1); \
aurel3257951c22008-11-10 11:10:23 +00007101}
7102#else
7103#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
Blue Swirl636aa202009-08-16 09:06:54 +00007104static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00007105{ \
7106 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02007107 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00007108 return; \
7109 } \
7110 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7111 rA(ctx->opcode)); \
7112 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7113 rA(ctx->opcode)); \
7114}
7115#endif
7116GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7117GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7118
7119/* SPE comparison */
7120#if defined(TARGET_PPC64)
7121#define GEN_SPEOP_COMP(name, tcg_cond) \
Blue Swirl636aa202009-08-16 09:06:54 +00007122static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00007123{ \
7124 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02007125 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00007126 return; \
7127 } \
7128 int l1 = gen_new_label(); \
7129 int l2 = gen_new_label(); \
7130 int l3 = gen_new_label(); \
7131 int l4 = gen_new_label(); \
pbrooka7812ae2008-11-17 14:43:54 +00007132 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7133 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7134 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
aurel3257951c22008-11-10 11:10:23 +00007135 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7136 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7137 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
pbrooka7812ae2008-11-17 14:43:54 +00007138 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
aurel3257951c22008-11-10 11:10:23 +00007139 tcg_gen_br(l2); \
7140 gen_set_label(l1); \
7141 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7142 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7143 gen_set_label(l2); \
7144 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7145 tcg_gen_trunc_i64_i32(t0, t2); \
7146 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7147 tcg_gen_trunc_i64_i32(t1, t2); \
pbrooka7812ae2008-11-17 14:43:54 +00007148 tcg_temp_free_i64(t2); \
aurel3257951c22008-11-10 11:10:23 +00007149 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7150 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7151 ~(CRF_CH | CRF_CH_AND_CL)); \
7152 tcg_gen_br(l4); \
7153 gen_set_label(l3); \
7154 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7155 CRF_CH | CRF_CH_OR_CL); \
7156 gen_set_label(l4); \
pbrooka7812ae2008-11-17 14:43:54 +00007157 tcg_temp_free_i32(t0); \
7158 tcg_temp_free_i32(t1); \
aurel3257951c22008-11-10 11:10:23 +00007159}
7160#else
7161#define GEN_SPEOP_COMP(name, tcg_cond) \
Blue Swirl636aa202009-08-16 09:06:54 +00007162static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00007163{ \
7164 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02007165 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00007166 return; \
7167 } \
7168 int l1 = gen_new_label(); \
7169 int l2 = gen_new_label(); \
7170 int l3 = gen_new_label(); \
7171 int l4 = gen_new_label(); \
7172 \
7173 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7174 cpu_gpr[rB(ctx->opcode)], l1); \
7175 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7176 tcg_gen_br(l2); \
7177 gen_set_label(l1); \
7178 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7179 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7180 gen_set_label(l2); \
7181 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7182 cpu_gprh[rB(ctx->opcode)], l3); \
7183 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7184 ~(CRF_CH | CRF_CH_AND_CL)); \
7185 tcg_gen_br(l4); \
7186 gen_set_label(l3); \
7187 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7188 CRF_CH | CRF_CH_OR_CL); \
7189 gen_set_label(l4); \
7190}
7191#endif
7192GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7193GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7194GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7195GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7196GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7197
7198/* SPE misc */
Blue Swirl636aa202009-08-16 09:06:54 +00007199static inline void gen_brinc(DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00007200{
7201 /* Note: brinc is usable even if SPE is disabled */
pbrooka7812ae2008-11-17 14:43:54 +00007202 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7203 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
j_mayer0487d6a2007-03-20 22:11:31 +00007204}
Blue Swirl636aa202009-08-16 09:06:54 +00007205static inline void gen_evmergelo(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007206{
7207 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007208 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel3257951c22008-11-10 11:10:23 +00007209 return;
7210 }
7211#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00007212 TCGv t0 = tcg_temp_new();
7213 TCGv t1 = tcg_temp_new();
Aurelien Jarno17d9b3a2011-03-22 07:41:29 +01007214 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
aurel3257951c22008-11-10 11:10:23 +00007215 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7216 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7217 tcg_temp_free(t0);
7218 tcg_temp_free(t1);
7219#else
aurel3257951c22008-11-10 11:10:23 +00007220 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
Nathan Froyd33890b32009-06-04 13:46:41 -07007221 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
aurel3257951c22008-11-10 11:10:23 +00007222#endif
j_mayer0487d6a2007-03-20 22:11:31 +00007223}
Blue Swirl636aa202009-08-16 09:06:54 +00007224static inline void gen_evmergehilo(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007225{
7226 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007227 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel3257951c22008-11-10 11:10:23 +00007228 return;
7229 }
7230#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00007231 TCGv t0 = tcg_temp_new();
7232 TCGv t1 = tcg_temp_new();
Aurelien Jarno17d9b3a2011-03-22 07:41:29 +01007233 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
aurel3257951c22008-11-10 11:10:23 +00007234 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7235 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7236 tcg_temp_free(t0);
7237 tcg_temp_free(t1);
7238#else
7239 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7240 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7241#endif
j_mayer0487d6a2007-03-20 22:11:31 +00007242}
Blue Swirl636aa202009-08-16 09:06:54 +00007243static inline void gen_evmergelohi(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007244{
7245 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007246 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel3257951c22008-11-10 11:10:23 +00007247 return;
7248 }
7249#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00007250 TCGv t0 = tcg_temp_new();
7251 TCGv t1 = tcg_temp_new();
aurel3257951c22008-11-10 11:10:23 +00007252 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7253 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7254 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7255 tcg_temp_free(t0);
7256 tcg_temp_free(t1);
7257#else
Nathan Froyd33890b32009-06-04 13:46:41 -07007258 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7259 TCGv_i32 tmp = tcg_temp_new_i32();
7260 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7261 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7262 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7263 tcg_temp_free_i32(tmp);
7264 } else {
7265 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7266 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7267 }
aurel3257951c22008-11-10 11:10:23 +00007268#endif
7269}
Blue Swirl636aa202009-08-16 09:06:54 +00007270static inline void gen_evsplati(DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00007271{
Nathan Froydae018472010-02-23 12:21:31 -08007272 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
j_mayer0487d6a2007-03-20 22:11:31 +00007273
aurel3257951c22008-11-10 11:10:23 +00007274#if defined(TARGET_PPC64)
aurel3238d14952008-11-27 19:30:38 +00007275 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
aurel3257951c22008-11-10 11:10:23 +00007276#else
7277 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7278 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7279#endif
j_mayer0487d6a2007-03-20 22:11:31 +00007280}
Blue Swirl636aa202009-08-16 09:06:54 +00007281static inline void gen_evsplatfi(DisasContext *ctx)
j_mayer0487d6a2007-03-20 22:11:31 +00007282{
Nathan Froydae018472010-02-23 12:21:31 -08007283 uint64_t imm = rA(ctx->opcode) << 27;
j_mayer0487d6a2007-03-20 22:11:31 +00007284
aurel3257951c22008-11-10 11:10:23 +00007285#if defined(TARGET_PPC64)
aurel3238d14952008-11-27 19:30:38 +00007286 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
aurel3257951c22008-11-10 11:10:23 +00007287#else
7288 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7289 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7290#endif
j_mayer0487d6a2007-03-20 22:11:31 +00007291}
7292
Blue Swirl636aa202009-08-16 09:06:54 +00007293static inline void gen_evsel(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007294{
7295 int l1 = gen_new_label();
7296 int l2 = gen_new_label();
7297 int l3 = gen_new_label();
7298 int l4 = gen_new_label();
pbrooka7812ae2008-11-17 14:43:54 +00007299 TCGv_i32 t0 = tcg_temp_local_new_i32();
aurel3257951c22008-11-10 11:10:23 +00007300#if defined(TARGET_PPC64)
pbrooka7812ae2008-11-17 14:43:54 +00007301 TCGv t1 = tcg_temp_local_new();
7302 TCGv t2 = tcg_temp_local_new();
aurel3257951c22008-11-10 11:10:23 +00007303#endif
7304 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7305 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7306#if defined(TARGET_PPC64)
7307 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7308#else
7309 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7310#endif
7311 tcg_gen_br(l2);
7312 gen_set_label(l1);
7313#if defined(TARGET_PPC64)
7314 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7315#else
7316 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7317#endif
7318 gen_set_label(l2);
7319 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7320 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7321#if defined(TARGET_PPC64)
Aurelien Jarno17d9b3a2011-03-22 07:41:29 +01007322 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
aurel3257951c22008-11-10 11:10:23 +00007323#else
7324 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7325#endif
7326 tcg_gen_br(l4);
7327 gen_set_label(l3);
7328#if defined(TARGET_PPC64)
Aurelien Jarno17d9b3a2011-03-22 07:41:29 +01007329 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
aurel3257951c22008-11-10 11:10:23 +00007330#else
7331 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7332#endif
7333 gen_set_label(l4);
pbrooka7812ae2008-11-17 14:43:54 +00007334 tcg_temp_free_i32(t0);
aurel3257951c22008-11-10 11:10:23 +00007335#if defined(TARGET_PPC64)
7336 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7337 tcg_temp_free(t1);
7338 tcg_temp_free(t2);
7339#endif
7340}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00007341
7342static void gen_evsel0(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007343{
7344 gen_evsel(ctx);
7345}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00007346
7347static void gen_evsel1(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007348{
7349 gen_evsel(ctx);
7350}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00007351
7352static void gen_evsel2(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007353{
7354 gen_evsel(ctx);
7355}
Blue Swirle8eaa2c2009-06-17 15:22:14 +00007356
7357static void gen_evsel3(DisasContext *ctx)
aurel3257951c22008-11-10 11:10:23 +00007358{
7359 gen_evsel(ctx);
7360}
j_mayer0487d6a2007-03-20 22:11:31 +00007361
Fabien Chouteaua0e13902011-03-16 11:21:22 +01007362/* Multiply */
7363
7364static inline void gen_evmwumi(DisasContext *ctx)
7365{
7366 TCGv_i64 t0, t1;
7367
7368 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007369 gen_exception(ctx, POWERPC_EXCP_SPEU);
Fabien Chouteaua0e13902011-03-16 11:21:22 +01007370 return;
7371 }
7372
7373 t0 = tcg_temp_new_i64();
7374 t1 = tcg_temp_new_i64();
7375
7376 /* t0 := rA; t1 := rB */
7377#if defined(TARGET_PPC64)
7378 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7379 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7380#else
7381 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7382 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7383#endif
7384
7385 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7386
7387 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7388
7389 tcg_temp_free_i64(t0);
7390 tcg_temp_free_i64(t1);
7391}
7392
7393static inline void gen_evmwumia(DisasContext *ctx)
7394{
7395 TCGv_i64 tmp;
7396
7397 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007398 gen_exception(ctx, POWERPC_EXCP_SPEU);
Fabien Chouteaua0e13902011-03-16 11:21:22 +01007399 return;
7400 }
7401
7402 gen_evmwumi(ctx); /* rD := rA * rB */
7403
7404 tmp = tcg_temp_new_i64();
7405
7406 /* acc := rD */
7407 gen_load_gpr64(tmp, rD(ctx->opcode));
7408 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7409 tcg_temp_free_i64(tmp);
7410}
7411
7412static inline void gen_evmwumiaa(DisasContext *ctx)
7413{
7414 TCGv_i64 acc;
7415 TCGv_i64 tmp;
7416
7417 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007418 gen_exception(ctx, POWERPC_EXCP_SPEU);
Fabien Chouteaua0e13902011-03-16 11:21:22 +01007419 return;
7420 }
7421
7422 gen_evmwumi(ctx); /* rD := rA * rB */
7423
7424 acc = tcg_temp_new_i64();
7425 tmp = tcg_temp_new_i64();
7426
7427 /* tmp := rD */
7428 gen_load_gpr64(tmp, rD(ctx->opcode));
7429
7430 /* Load acc */
7431 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7432
7433 /* acc := tmp + acc */
7434 tcg_gen_add_i64(acc, acc, tmp);
7435
7436 /* Store acc */
7437 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7438
7439 /* rD := acc */
7440 gen_store_gpr64(rD(ctx->opcode), acc);
7441
7442 tcg_temp_free_i64(acc);
7443 tcg_temp_free_i64(tmp);
7444}
7445
7446static inline void gen_evmwsmi(DisasContext *ctx)
7447{
7448 TCGv_i64 t0, t1;
7449
7450 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02007451 gen_exception(ctx, POWERPC_EXCP_SPEU);
Fabien Chouteaua0e13902011-03-16 11:21:22 +01007452 return;
7453 }
7454
7455 t0 = tcg_temp_new_i64();
7456 t1 = tcg_temp_new_i64();
7457
7458 /* t0 := rA; t1 := rB */
7459#if defined(TARGET_PPC64)
7460 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7461 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7462#else
7463 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7464 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7465#endif
7466
7467 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7468
7469 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7470
7471 tcg_temp_free_i64(t0);
7472 tcg_temp_free_i64(t1);
7473}
7474
7475static inline void gen_evmwsmia(DisasContext *ctx)
7476{
7477 TCGv_i64 tmp;
7478
7479 gen_evmwsmi(ctx); /* rD := rA * rB */
7480
7481 tmp = tcg_temp_new_i64();
7482
7483 /* acc := rD */
7484 gen_load_gpr64(tmp, rD(ctx->opcode));
7485 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUState, spe_acc));
7486
7487 tcg_temp_free_i64(tmp);
7488}
7489
7490static inline void gen_evmwsmiaa(DisasContext *ctx)
7491{
7492 TCGv_i64 acc = tcg_temp_new_i64();
7493 TCGv_i64 tmp = tcg_temp_new_i64();
7494
7495 gen_evmwsmi(ctx); /* rD := rA * rB */
7496
7497 acc = tcg_temp_new_i64();
7498 tmp = tcg_temp_new_i64();
7499
7500 /* tmp := rD */
7501 gen_load_gpr64(tmp, rD(ctx->opcode));
7502
7503 /* Load acc */
7504 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7505
7506 /* acc := tmp + acc */
7507 tcg_gen_add_i64(acc, acc, tmp);
7508
7509 /* Store acc */
7510 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUState, spe_acc));
7511
7512 /* rD := acc */
7513 gen_store_gpr64(rD(ctx->opcode), acc);
7514
7515 tcg_temp_free_i64(acc);
7516 tcg_temp_free_i64(tmp);
7517}
7518
Fabien Chouteau70560da2011-09-28 05:54:05 +00007519GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7520GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7521GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7522GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7523GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7524GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7525GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7526GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7527GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7528GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7529GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7530GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7531GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7532GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7533GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7534GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7535GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7536GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7537GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7538GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7539GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7540GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7541GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7542GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7543GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7544GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7545GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7546GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7547GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
j_mayer0487d6a2007-03-20 22:11:31 +00007548
aurel326a6ae232008-11-27 19:30:47 +00007549/* SPE load and stores */
Blue Swirl636aa202009-08-16 09:06:54 +00007550static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
aurel326a6ae232008-11-27 19:30:47 +00007551{
7552 target_ulong uimm = rB(ctx->opcode);
j_mayer0487d6a2007-03-20 22:11:31 +00007553
aurel3276db3ba2008-12-08 18:11:21 +00007554 if (rA(ctx->opcode) == 0) {
aurel326a6ae232008-11-27 19:30:47 +00007555 tcg_gen_movi_tl(EA, uimm << sh);
aurel3276db3ba2008-12-08 18:11:21 +00007556 } else {
aurel326a6ae232008-11-27 19:30:47 +00007557 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
aurel3276db3ba2008-12-08 18:11:21 +00007558#if defined(TARGET_PPC64)
7559 if (!ctx->sf_mode) {
7560 tcg_gen_ext32u_tl(EA, EA);
7561 }
7562#endif
7563 }
j_mayer0487d6a2007-03-20 22:11:31 +00007564}
aurel326a6ae232008-11-27 19:30:47 +00007565
Blue Swirl636aa202009-08-16 09:06:54 +00007566static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007567{
j_mayer0487d6a2007-03-20 22:11:31 +00007568#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +00007569 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
j_mayer0487d6a2007-03-20 22:11:31 +00007570#else
aurel326a6ae232008-11-27 19:30:47 +00007571 TCGv_i64 t0 = tcg_temp_new_i64();
aurel3276db3ba2008-12-08 18:11:21 +00007572 gen_qemu_ld64(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007573 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7574 tcg_gen_shri_i64(t0, t0, 32);
7575 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7576 tcg_temp_free_i64(t0);
j_mayer0487d6a2007-03-20 22:11:31 +00007577#endif
j_mayer0487d6a2007-03-20 22:11:31 +00007578}
7579
Blue Swirl636aa202009-08-16 09:06:54 +00007580static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007581{
j_mayer0487d6a2007-03-20 22:11:31 +00007582#if defined(TARGET_PPC64)
aurel326a6ae232008-11-27 19:30:47 +00007583 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007584 gen_qemu_ld32u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007585 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
aurel3276db3ba2008-12-08 18:11:21 +00007586 gen_addr_add(ctx, addr, addr, 4);
7587 gen_qemu_ld32u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007588 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7589 tcg_temp_free(t0);
j_mayer0487d6a2007-03-20 22:11:31 +00007590#else
aurel3276db3ba2008-12-08 18:11:21 +00007591 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7592 gen_addr_add(ctx, addr, addr, 4);
7593 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
j_mayer0487d6a2007-03-20 22:11:31 +00007594#endif
aurel326a6ae232008-11-27 19:30:47 +00007595}
j_mayer0487d6a2007-03-20 22:11:31 +00007596
Blue Swirl636aa202009-08-16 09:06:54 +00007597static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007598{
7599 TCGv t0 = tcg_temp_new();
7600#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +00007601 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007602 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
aurel3276db3ba2008-12-08 18:11:21 +00007603 gen_addr_add(ctx, addr, addr, 2);
7604 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007605 tcg_gen_shli_tl(t0, t0, 32);
7606 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007607 gen_addr_add(ctx, addr, addr, 2);
7608 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007609 tcg_gen_shli_tl(t0, t0, 16);
7610 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007611 gen_addr_add(ctx, addr, addr, 2);
7612 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007613 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7614#else
aurel3276db3ba2008-12-08 18:11:21 +00007615 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007616 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
aurel3276db3ba2008-12-08 18:11:21 +00007617 gen_addr_add(ctx, addr, addr, 2);
7618 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007619 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007620 gen_addr_add(ctx, addr, addr, 2);
7621 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007622 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
aurel3276db3ba2008-12-08 18:11:21 +00007623 gen_addr_add(ctx, addr, addr, 2);
7624 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007625 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7626#endif
7627 tcg_temp_free(t0);
7628}
7629
Blue Swirl636aa202009-08-16 09:06:54 +00007630static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007631{
7632 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007633 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007634#if defined(TARGET_PPC64)
7635 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7636 tcg_gen_shli_tl(t0, t0, 16);
7637 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7638#else
7639 tcg_gen_shli_tl(t0, t0, 16);
7640 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7641 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7642#endif
7643 tcg_temp_free(t0);
7644}
7645
Blue Swirl636aa202009-08-16 09:06:54 +00007646static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007647{
7648 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007649 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007650#if defined(TARGET_PPC64)
7651 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7652 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7653#else
7654 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7655 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7656#endif
7657 tcg_temp_free(t0);
7658}
7659
Blue Swirl636aa202009-08-16 09:06:54 +00007660static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007661{
7662 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007663 gen_qemu_ld16s(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007664#if defined(TARGET_PPC64)
7665 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7666 tcg_gen_ext32u_tl(t0, t0);
7667 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7668#else
7669 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7671#endif
7672 tcg_temp_free(t0);
7673}
7674
Blue Swirl636aa202009-08-16 09:06:54 +00007675static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007676{
7677 TCGv t0 = tcg_temp_new();
7678#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +00007679 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007680 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
aurel3276db3ba2008-12-08 18:11:21 +00007681 gen_addr_add(ctx, addr, addr, 2);
7682 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007683 tcg_gen_shli_tl(t0, t0, 16);
7684 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7685#else
aurel3276db3ba2008-12-08 18:11:21 +00007686 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007687 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
aurel3276db3ba2008-12-08 18:11:21 +00007688 gen_addr_add(ctx, addr, addr, 2);
7689 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007690 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7691#endif
7692 tcg_temp_free(t0);
7693}
7694
Blue Swirl636aa202009-08-16 09:06:54 +00007695static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007696{
7697#if defined(TARGET_PPC64)
7698 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007699 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7700 gen_addr_add(ctx, addr, addr, 2);
7701 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007702 tcg_gen_shli_tl(t0, t0, 32);
7703 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7704 tcg_temp_free(t0);
7705#else
aurel3276db3ba2008-12-08 18:11:21 +00007706 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7707 gen_addr_add(ctx, addr, addr, 2);
7708 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007709#endif
7710}
7711
Blue Swirl636aa202009-08-16 09:06:54 +00007712static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007713{
7714#if defined(TARGET_PPC64)
7715 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007716 gen_qemu_ld16s(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007717 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007718 gen_addr_add(ctx, addr, addr, 2);
7719 gen_qemu_ld16s(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007720 tcg_gen_shli_tl(t0, t0, 32);
7721 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7722 tcg_temp_free(t0);
7723#else
aurel3276db3ba2008-12-08 18:11:21 +00007724 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7725 gen_addr_add(ctx, addr, addr, 2);
7726 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007727#endif
7728}
7729
Blue Swirl636aa202009-08-16 09:06:54 +00007730static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007731{
7732 TCGv t0 = tcg_temp_new();
aurel3276db3ba2008-12-08 18:11:21 +00007733 gen_qemu_ld32u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007734#if defined(TARGET_PPC64)
7735 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7736 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7737#else
7738 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7740#endif
7741 tcg_temp_free(t0);
7742}
7743
Blue Swirl636aa202009-08-16 09:06:54 +00007744static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007745{
7746 TCGv t0 = tcg_temp_new();
7747#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +00007748 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007749 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7750 tcg_gen_shli_tl(t0, t0, 32);
7751 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007752 gen_addr_add(ctx, addr, addr, 2);
7753 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007754 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7755 tcg_gen_shli_tl(t0, t0, 16);
7756 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7757#else
aurel3276db3ba2008-12-08 18:11:21 +00007758 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007759 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7760 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
aurel3276db3ba2008-12-08 18:11:21 +00007761 gen_addr_add(ctx, addr, addr, 2);
7762 gen_qemu_ld16u(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007763 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7764 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7765#endif
7766 tcg_temp_free(t0);
7767}
7768
Blue Swirl636aa202009-08-16 09:06:54 +00007769static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007770{
7771#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +00007772 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007773#else
7774 TCGv_i64 t0 = tcg_temp_new_i64();
7775 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
aurel3276db3ba2008-12-08 18:11:21 +00007776 gen_qemu_st64(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007777 tcg_temp_free_i64(t0);
7778#endif
7779}
7780
Blue Swirl636aa202009-08-16 09:06:54 +00007781static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007782{
7783#if defined(TARGET_PPC64)
7784 TCGv t0 = tcg_temp_new();
7785 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
aurel3276db3ba2008-12-08 18:11:21 +00007786 gen_qemu_st32(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007787 tcg_temp_free(t0);
7788#else
aurel3276db3ba2008-12-08 18:11:21 +00007789 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007790#endif
aurel3276db3ba2008-12-08 18:11:21 +00007791 gen_addr_add(ctx, addr, addr, 4);
7792 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007793}
7794
Blue Swirl636aa202009-08-16 09:06:54 +00007795static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007796{
7797 TCGv t0 = tcg_temp_new();
7798#if defined(TARGET_PPC64)
7799 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7800#else
7801 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7802#endif
aurel3276db3ba2008-12-08 18:11:21 +00007803 gen_qemu_st16(ctx, t0, addr);
7804 gen_addr_add(ctx, addr, addr, 2);
aurel326a6ae232008-11-27 19:30:47 +00007805#if defined(TARGET_PPC64)
7806 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
aurel3276db3ba2008-12-08 18:11:21 +00007807 gen_qemu_st16(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007808#else
aurel3276db3ba2008-12-08 18:11:21 +00007809 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007810#endif
aurel3276db3ba2008-12-08 18:11:21 +00007811 gen_addr_add(ctx, addr, addr, 2);
aurel326a6ae232008-11-27 19:30:47 +00007812 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
aurel3276db3ba2008-12-08 18:11:21 +00007813 gen_qemu_st16(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007814 tcg_temp_free(t0);
aurel3276db3ba2008-12-08 18:11:21 +00007815 gen_addr_add(ctx, addr, addr, 2);
7816 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007817}
7818
Blue Swirl636aa202009-08-16 09:06:54 +00007819static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007820{
7821 TCGv t0 = tcg_temp_new();
7822#if defined(TARGET_PPC64)
7823 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7824#else
7825 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7826#endif
aurel3276db3ba2008-12-08 18:11:21 +00007827 gen_qemu_st16(ctx, t0, addr);
7828 gen_addr_add(ctx, addr, addr, 2);
aurel326a6ae232008-11-27 19:30:47 +00007829 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
aurel3276db3ba2008-12-08 18:11:21 +00007830 gen_qemu_st16(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007831 tcg_temp_free(t0);
7832}
7833
Blue Swirl636aa202009-08-16 09:06:54 +00007834static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007835{
7836#if defined(TARGET_PPC64)
7837 TCGv t0 = tcg_temp_new();
7838 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
aurel3276db3ba2008-12-08 18:11:21 +00007839 gen_qemu_st16(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007840 tcg_temp_free(t0);
7841#else
aurel3276db3ba2008-12-08 18:11:21 +00007842 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007843#endif
aurel3276db3ba2008-12-08 18:11:21 +00007844 gen_addr_add(ctx, addr, addr, 2);
7845 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007846}
7847
Blue Swirl636aa202009-08-16 09:06:54 +00007848static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007849{
7850#if defined(TARGET_PPC64)
7851 TCGv t0 = tcg_temp_new();
7852 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
aurel3276db3ba2008-12-08 18:11:21 +00007853 gen_qemu_st32(ctx, t0, addr);
aurel326a6ae232008-11-27 19:30:47 +00007854 tcg_temp_free(t0);
7855#else
aurel3276db3ba2008-12-08 18:11:21 +00007856 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007857#endif
7858}
7859
Blue Swirl636aa202009-08-16 09:06:54 +00007860static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
aurel326a6ae232008-11-27 19:30:47 +00007861{
aurel3276db3ba2008-12-08 18:11:21 +00007862 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
aurel326a6ae232008-11-27 19:30:47 +00007863}
7864
7865#define GEN_SPEOP_LDST(name, opc2, sh) \
Blue Swirl99e300e2009-06-17 15:22:09 +00007866static void glue(gen_, name)(DisasContext *ctx) \
aurel326a6ae232008-11-27 19:30:47 +00007867{ \
7868 TCGv t0; \
7869 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02007870 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel326a6ae232008-11-27 19:30:47 +00007871 return; \
7872 } \
aurel3276db3ba2008-12-08 18:11:21 +00007873 gen_set_access_type(ctx, ACCESS_INT); \
aurel326a6ae232008-11-27 19:30:47 +00007874 t0 = tcg_temp_new(); \
7875 if (Rc(ctx->opcode)) { \
aurel3276db3ba2008-12-08 18:11:21 +00007876 gen_addr_spe_imm_index(ctx, t0, sh); \
aurel326a6ae232008-11-27 19:30:47 +00007877 } else { \
aurel3276db3ba2008-12-08 18:11:21 +00007878 gen_addr_reg_index(ctx, t0); \
aurel326a6ae232008-11-27 19:30:47 +00007879 } \
7880 gen_op_##name(ctx, t0); \
7881 tcg_temp_free(t0); \
7882}
7883
7884GEN_SPEOP_LDST(evldd, 0x00, 3);
7885GEN_SPEOP_LDST(evldw, 0x01, 3);
7886GEN_SPEOP_LDST(evldh, 0x02, 3);
7887GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7888GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7889GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7890GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7891GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7892GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7893GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7894GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7895
7896GEN_SPEOP_LDST(evstdd, 0x10, 3);
7897GEN_SPEOP_LDST(evstdw, 0x11, 3);
7898GEN_SPEOP_LDST(evstdh, 0x12, 3);
7899GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7900GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7901GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7902GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
j_mayer0487d6a2007-03-20 22:11:31 +00007903
7904/* Multiply and add - TODO */
7905#if 0
Fabien Chouteau70560da2011-09-28 05:54:05 +00007906GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7907GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7908GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7909GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7910GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7911GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7912GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7913GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7914GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7915GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7916GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7917GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007918
Fabien Chouteau70560da2011-09-28 05:54:05 +00007919GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7920GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7921GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7922GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7923GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7924GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7925GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7926GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7927GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7928GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7929GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7930GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007931
Fabien Chouteau70560da2011-09-28 05:54:05 +00007932GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7933GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7934GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7935GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7936GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007937
Fabien Chouteau70560da2011-09-28 05:54:05 +00007938GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7939GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7940GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7941GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7942GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7943GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7945GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7947GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7948GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7949GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007950
Fabien Chouteau70560da2011-09-28 05:54:05 +00007951GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7952GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7953GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7954GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007955
Fabien Chouteau70560da2011-09-28 05:54:05 +00007956GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7957GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7958GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7959GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7960GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7961GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7962GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7963GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7964GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7965GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7966GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7967GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007968
Fabien Chouteau70560da2011-09-28 05:54:05 +00007969GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7970GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7971GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7972GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7973GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
j_mayer0487d6a2007-03-20 22:11:31 +00007974#endif
7975
7976/*** SPE floating-point extension ***/
aurel321c978562008-11-23 10:54:04 +00007977#if defined(TARGET_PPC64)
7978#define GEN_SPEFPUOP_CONV_32_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00007979static inline void gen_##name(DisasContext *ctx) \
j_mayer0487d6a2007-03-20 22:11:31 +00007980{ \
aurel321c978562008-11-23 10:54:04 +00007981 TCGv_i32 t0; \
7982 TCGv t1; \
7983 t0 = tcg_temp_new_i32(); \
7984 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7985 gen_helper_##name(t0, t0); \
7986 t1 = tcg_temp_new(); \
7987 tcg_gen_extu_i32_tl(t1, t0); \
7988 tcg_temp_free_i32(t0); \
7989 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7990 0xFFFFFFFF00000000ULL); \
7991 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7992 tcg_temp_free(t1); \
j_mayer0487d6a2007-03-20 22:11:31 +00007993}
aurel321c978562008-11-23 10:54:04 +00007994#define GEN_SPEFPUOP_CONV_32_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00007995static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00007996{ \
7997 TCGv_i32 t0; \
7998 TCGv t1; \
7999 t0 = tcg_temp_new_i32(); \
8000 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8001 t1 = tcg_temp_new(); \
8002 tcg_gen_extu_i32_tl(t1, t0); \
8003 tcg_temp_free_i32(t0); \
8004 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8005 0xFFFFFFFF00000000ULL); \
8006 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8007 tcg_temp_free(t1); \
8008}
8009#define GEN_SPEFPUOP_CONV_64_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008010static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008011{ \
8012 TCGv_i32 t0 = tcg_temp_new_i32(); \
8013 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8014 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8015 tcg_temp_free_i32(t0); \
8016}
8017#define GEN_SPEFPUOP_CONV_64_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008018static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008019{ \
8020 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8021}
8022#define GEN_SPEFPUOP_ARITH2_32_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008023static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008024{ \
8025 TCGv_i32 t0, t1; \
8026 TCGv_i64 t2; \
8027 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008028 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel321c978562008-11-23 10:54:04 +00008029 return; \
8030 } \
8031 t0 = tcg_temp_new_i32(); \
8032 t1 = tcg_temp_new_i32(); \
8033 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8034 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8035 gen_helper_##name(t0, t0, t1); \
8036 tcg_temp_free_i32(t1); \
8037 t2 = tcg_temp_new(); \
8038 tcg_gen_extu_i32_tl(t2, t0); \
8039 tcg_temp_free_i32(t0); \
8040 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8041 0xFFFFFFFF00000000ULL); \
8042 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8043 tcg_temp_free(t2); \
8044}
8045#define GEN_SPEFPUOP_ARITH2_64_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008046static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00008047{ \
8048 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008049 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00008050 return; \
8051 } \
aurel321c978562008-11-23 10:54:04 +00008052 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8053 cpu_gpr[rB(ctx->opcode)]); \
aurel3257951c22008-11-10 11:10:23 +00008054}
aurel321c978562008-11-23 10:54:04 +00008055#define GEN_SPEFPUOP_COMP_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008056static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008057{ \
8058 TCGv_i32 t0, t1; \
8059 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008060 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel321c978562008-11-23 10:54:04 +00008061 return; \
8062 } \
8063 t0 = tcg_temp_new_i32(); \
8064 t1 = tcg_temp_new_i32(); \
8065 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8066 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8067 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8068 tcg_temp_free_i32(t0); \
8069 tcg_temp_free_i32(t1); \
8070}
8071#define GEN_SPEFPUOP_COMP_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008072static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00008073{ \
8074 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008075 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00008076 return; \
8077 } \
aurel321c978562008-11-23 10:54:04 +00008078 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8079 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
aurel3257951c22008-11-10 11:10:23 +00008080}
aurel321c978562008-11-23 10:54:04 +00008081#else
8082#define GEN_SPEFPUOP_CONV_32_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008083static inline void gen_##name(DisasContext *ctx) \
aurel3257951c22008-11-10 11:10:23 +00008084{ \
aurel321c978562008-11-23 10:54:04 +00008085 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8086}
8087#define GEN_SPEFPUOP_CONV_32_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008088static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008089{ \
8090 TCGv_i64 t0 = tcg_temp_new_i64(); \
8091 gen_load_gpr64(t0, rB(ctx->opcode)); \
8092 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
8093 tcg_temp_free_i64(t0); \
8094}
8095#define GEN_SPEFPUOP_CONV_64_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008096static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008097{ \
8098 TCGv_i64 t0 = tcg_temp_new_i64(); \
8099 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
8100 gen_store_gpr64(rD(ctx->opcode), t0); \
8101 tcg_temp_free_i64(t0); \
8102}
8103#define GEN_SPEFPUOP_CONV_64_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008104static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008105{ \
8106 TCGv_i64 t0 = tcg_temp_new_i64(); \
8107 gen_load_gpr64(t0, rB(ctx->opcode)); \
8108 gen_helper_##name(t0, t0); \
8109 gen_store_gpr64(rD(ctx->opcode), t0); \
8110 tcg_temp_free_i64(t0); \
8111}
8112#define GEN_SPEFPUOP_ARITH2_32_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008113static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008114{ \
aurel3257951c22008-11-10 11:10:23 +00008115 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008116 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel3257951c22008-11-10 11:10:23 +00008117 return; \
8118 } \
aurel321c978562008-11-23 10:54:04 +00008119 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
8120 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
aurel3257951c22008-11-10 11:10:23 +00008121}
aurel321c978562008-11-23 10:54:04 +00008122#define GEN_SPEFPUOP_ARITH2_64_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008123static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008124{ \
8125 TCGv_i64 t0, t1; \
8126 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008127 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel321c978562008-11-23 10:54:04 +00008128 return; \
8129 } \
8130 t0 = tcg_temp_new_i64(); \
8131 t1 = tcg_temp_new_i64(); \
8132 gen_load_gpr64(t0, rA(ctx->opcode)); \
8133 gen_load_gpr64(t1, rB(ctx->opcode)); \
8134 gen_helper_##name(t0, t0, t1); \
8135 gen_store_gpr64(rD(ctx->opcode), t0); \
8136 tcg_temp_free_i64(t0); \
8137 tcg_temp_free_i64(t1); \
8138}
8139#define GEN_SPEFPUOP_COMP_32(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008140static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008141{ \
8142 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008143 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel321c978562008-11-23 10:54:04 +00008144 return; \
8145 } \
8146 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8147 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8148}
8149#define GEN_SPEFPUOP_COMP_64(name) \
Blue Swirl636aa202009-08-16 09:06:54 +00008150static inline void gen_##name(DisasContext *ctx) \
aurel321c978562008-11-23 10:54:04 +00008151{ \
8152 TCGv_i64 t0, t1; \
8153 if (unlikely(!ctx->spe_enabled)) { \
Alexander Graf27a69bb2011-08-23 06:55:43 +02008154 gen_exception(ctx, POWERPC_EXCP_SPEU); \
aurel321c978562008-11-23 10:54:04 +00008155 return; \
8156 } \
8157 t0 = tcg_temp_new_i64(); \
8158 t1 = tcg_temp_new_i64(); \
8159 gen_load_gpr64(t0, rA(ctx->opcode)); \
8160 gen_load_gpr64(t1, rB(ctx->opcode)); \
8161 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
8162 tcg_temp_free_i64(t0); \
8163 tcg_temp_free_i64(t1); \
8164}
8165#endif
aurel3257951c22008-11-10 11:10:23 +00008166
j_mayer0487d6a2007-03-20 22:11:31 +00008167/* Single precision floating-point vectors operations */
8168/* Arithmetic */
aurel321c978562008-11-23 10:54:04 +00008169GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8170GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8171GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8172GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
Blue Swirl636aa202009-08-16 09:06:54 +00008173static inline void gen_evfsabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008174{
8175 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008176 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008177 return;
8178 }
8179#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008180 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
aurel321c978562008-11-23 10:54:04 +00008181#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008182 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8183 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
aurel321c978562008-11-23 10:54:04 +00008184#endif
8185}
Blue Swirl636aa202009-08-16 09:06:54 +00008186static inline void gen_evfsnabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008187{
8188 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008189 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008190 return;
8191 }
8192#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008193 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
aurel321c978562008-11-23 10:54:04 +00008194#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008195 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8196 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008197#endif
8198}
Blue Swirl636aa202009-08-16 09:06:54 +00008199static inline void gen_evfsneg(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008200{
8201 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008202 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008203 return;
8204 }
8205#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008206 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
aurel321c978562008-11-23 10:54:04 +00008207#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008208 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8209 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008210#endif
8211}
8212
j_mayer0487d6a2007-03-20 22:11:31 +00008213/* Conversion */
aurel321c978562008-11-23 10:54:04 +00008214GEN_SPEFPUOP_CONV_64_64(evfscfui);
8215GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8216GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8217GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8218GEN_SPEFPUOP_CONV_64_64(evfsctui);
8219GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8220GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8221GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8222GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8223GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8224
j_mayer0487d6a2007-03-20 22:11:31 +00008225/* Comparison */
aurel321c978562008-11-23 10:54:04 +00008226GEN_SPEFPUOP_COMP_64(evfscmpgt);
8227GEN_SPEFPUOP_COMP_64(evfscmplt);
8228GEN_SPEFPUOP_COMP_64(evfscmpeq);
8229GEN_SPEFPUOP_COMP_64(evfststgt);
8230GEN_SPEFPUOP_COMP_64(evfststlt);
8231GEN_SPEFPUOP_COMP_64(evfststeq);
j_mayer0487d6a2007-03-20 22:11:31 +00008232
8233/* Opcodes definitions */
Fabien Chouteau70560da2011-09-28 05:54:05 +00008234GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8235GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8236GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8237GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8238GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8239GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8240GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8241GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8242GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8243GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8244GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8245GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8246GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8247GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
j_mayer0487d6a2007-03-20 22:11:31 +00008248
8249/* Single precision floating-point operations */
8250/* Arithmetic */
aurel321c978562008-11-23 10:54:04 +00008251GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8252GEN_SPEFPUOP_ARITH2_32_32(efssub);
8253GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8254GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
Blue Swirl636aa202009-08-16 09:06:54 +00008255static inline void gen_efsabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008256{
8257 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008258 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008259 return;
8260 }
Mike Pall6d5c34f2010-12-31 21:17:53 +01008261 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
aurel321c978562008-11-23 10:54:04 +00008262}
Blue Swirl636aa202009-08-16 09:06:54 +00008263static inline void gen_efsnabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008264{
8265 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008266 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008267 return;
8268 }
Mike Pall6d5c34f2010-12-31 21:17:53 +01008269 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008270}
Blue Swirl636aa202009-08-16 09:06:54 +00008271static inline void gen_efsneg(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008272{
8273 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008274 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008275 return;
8276 }
Mike Pall6d5c34f2010-12-31 21:17:53 +01008277 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008278}
8279
j_mayer0487d6a2007-03-20 22:11:31 +00008280/* Conversion */
aurel321c978562008-11-23 10:54:04 +00008281GEN_SPEFPUOP_CONV_32_32(efscfui);
8282GEN_SPEFPUOP_CONV_32_32(efscfsi);
8283GEN_SPEFPUOP_CONV_32_32(efscfuf);
8284GEN_SPEFPUOP_CONV_32_32(efscfsf);
8285GEN_SPEFPUOP_CONV_32_32(efsctui);
8286GEN_SPEFPUOP_CONV_32_32(efsctsi);
8287GEN_SPEFPUOP_CONV_32_32(efsctuf);
8288GEN_SPEFPUOP_CONV_32_32(efsctsf);
8289GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8290GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8291GEN_SPEFPUOP_CONV_32_64(efscfd);
8292
j_mayer0487d6a2007-03-20 22:11:31 +00008293/* Comparison */
aurel321c978562008-11-23 10:54:04 +00008294GEN_SPEFPUOP_COMP_32(efscmpgt);
8295GEN_SPEFPUOP_COMP_32(efscmplt);
8296GEN_SPEFPUOP_COMP_32(efscmpeq);
8297GEN_SPEFPUOP_COMP_32(efststgt);
8298GEN_SPEFPUOP_COMP_32(efststlt);
8299GEN_SPEFPUOP_COMP_32(efststeq);
j_mayer0487d6a2007-03-20 22:11:31 +00008300
8301/* Opcodes definitions */
Fabien Chouteau70560da2011-09-28 05:54:05 +00008302GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8303GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8304GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8305GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8306GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8307GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8308GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8309GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8310GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8311GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8312GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8313GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8314GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8315GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
j_mayer0487d6a2007-03-20 22:11:31 +00008316
8317/* Double precision floating-point operations */
8318/* Arithmetic */
aurel321c978562008-11-23 10:54:04 +00008319GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8320GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8321GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8322GEN_SPEFPUOP_ARITH2_64_64(efddiv);
Blue Swirl636aa202009-08-16 09:06:54 +00008323static inline void gen_efdabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008324{
8325 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008326 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008327 return;
8328 }
8329#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008330 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
aurel321c978562008-11-23 10:54:04 +00008331#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008332 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8333 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
aurel321c978562008-11-23 10:54:04 +00008334#endif
8335}
Blue Swirl636aa202009-08-16 09:06:54 +00008336static inline void gen_efdnabs(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008337{
8338 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008339 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008340 return;
8341 }
8342#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008343 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
aurel321c978562008-11-23 10:54:04 +00008344#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008345 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8346 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008347#endif
8348}
Blue Swirl636aa202009-08-16 09:06:54 +00008349static inline void gen_efdneg(DisasContext *ctx)
aurel321c978562008-11-23 10:54:04 +00008350{
8351 if (unlikely(!ctx->spe_enabled)) {
Alexander Graf27a69bb2011-08-23 06:55:43 +02008352 gen_exception(ctx, POWERPC_EXCP_SPEU);
aurel321c978562008-11-23 10:54:04 +00008353 return;
8354 }
8355#if defined(TARGET_PPC64)
Mike Pall6d5c34f2010-12-31 21:17:53 +01008356 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
aurel321c978562008-11-23 10:54:04 +00008357#else
Mike Pall6d5c34f2010-12-31 21:17:53 +01008358 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8359 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
aurel321c978562008-11-23 10:54:04 +00008360#endif
8361}
j_mayer0487d6a2007-03-20 22:11:31 +00008362
aurel321c978562008-11-23 10:54:04 +00008363/* Conversion */
8364GEN_SPEFPUOP_CONV_64_32(efdcfui);
8365GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8366GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8367GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8368GEN_SPEFPUOP_CONV_32_64(efdctui);
8369GEN_SPEFPUOP_CONV_32_64(efdctsi);
8370GEN_SPEFPUOP_CONV_32_64(efdctuf);
8371GEN_SPEFPUOP_CONV_32_64(efdctsf);
8372GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8373GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8374GEN_SPEFPUOP_CONV_64_32(efdcfs);
8375GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8376GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8377GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8378GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8379
j_mayer0487d6a2007-03-20 22:11:31 +00008380/* Comparison */
aurel321c978562008-11-23 10:54:04 +00008381GEN_SPEFPUOP_COMP_64(efdcmpgt);
8382GEN_SPEFPUOP_COMP_64(efdcmplt);
8383GEN_SPEFPUOP_COMP_64(efdcmpeq);
8384GEN_SPEFPUOP_COMP_64(efdtstgt);
8385GEN_SPEFPUOP_COMP_64(efdtstlt);
8386GEN_SPEFPUOP_COMP_64(efdtsteq);
j_mayer0487d6a2007-03-20 22:11:31 +00008387
8388/* Opcodes definitions */
Fabien Chouteau70560da2011-09-28 05:54:05 +00008389GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8390GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8391GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8392GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8393GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8394GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8395GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8396GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8397GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8398GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8399GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8400GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8401GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8402GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8403GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8404GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
j_mayer0487d6a2007-03-20 22:11:31 +00008405
Anthony Liguoric227f092009-10-01 16:12:16 -05008406static opcode_t opcodes[] = {
Blue Swirl5c55ff92009-06-17 15:22:31 +00008407GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8408GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8409GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8410GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8411GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8412GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8413GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8414GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8415GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8416GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8417GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8418GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8419GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8420GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8421GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8422#if defined(TARGET_PPC64)
8423GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8424#endif
8425GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8426GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8427GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8428GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8429GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8430GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8431GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8432GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8433GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8434GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8435GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8436GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8437GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
David Gibsoneaabeef2011-04-01 15:15:13 +11008438GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008439#if defined(TARGET_PPC64)
David Gibsoneaabeef2011-04-01 15:15:13 +11008440GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008441GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8442#endif
8443GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8444GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8445GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8446GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8447GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8448GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8449GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8450#if defined(TARGET_PPC64)
8451GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8452GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8453GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8454GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8455GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8456#endif
8457GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8458GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8459GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8460GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8461GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8462GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8463GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8464GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8465GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8466GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8467GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8468GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8469#if defined(TARGET_PPC64)
8470GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8471GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8472GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8473#endif
8474GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8475GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8476GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8477GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8478GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8479GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8480GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8481GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
Alexander Graff844c812010-09-10 15:08:33 +00008482GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008483GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8484#if defined(TARGET_PPC64)
Alexander Graff844c812010-09-10 15:08:33 +00008485GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008486GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8487#endif
8488GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8489GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8490GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8491GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8492GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8493GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8494GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8495GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8496#if defined(TARGET_PPC64)
8497GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8498GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8499#endif
8500GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8501GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8502GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8503#if defined(TARGET_PPC64)
8504GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8505GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8506#endif
8507GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8508GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8509GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8510GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8511GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8512GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8513#if defined(TARGET_PPC64)
8514GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8515#endif
8516GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8517GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8518GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8519GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8520GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8521GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8522GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8523GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8524GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8525GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8526GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8527GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8528GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8529GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8530GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8531GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8532GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8533GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8534#if defined(TARGET_PPC64)
8535GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8536GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8537 PPC_SEGMENT_64B),
8538GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8539GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8540 PPC_SEGMENT_64B),
David Gibsonefdef952011-04-01 15:15:11 +11008541GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8542GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8543GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008544#endif
8545GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8546GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8547GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8548GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8549#if defined(TARGET_PPC64)
8550GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8551GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8552#endif
8553GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8554GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8555GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8556GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8557GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8558GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8559GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8560GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8561GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8562GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8563GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8564GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8565GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8566GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8567GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8568GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8569GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8570GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8571GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8572GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8573GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8574GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8575GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8576GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8577GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8578GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8579GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8580GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8581GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8582GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8583GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8584GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8585GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8586GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8587GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8588GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8589GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8590GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8591GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8592GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8593GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8594GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8595GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8596GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8597GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8598GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8599GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8600GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8601GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8602GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8603GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8604GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8605GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8606GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8607GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8608GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8609GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8610GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8611GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8612GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8613GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8614GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8615GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8616GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8617GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8618GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8619GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8620GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8621GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8622GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8623GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
Alexander Graf01662f32011-04-30 23:34:58 +02008624GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008625GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8626GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8627GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8628GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8629GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8630GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8631GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8632GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
Alexander Graf01662f32011-04-30 23:34:58 +02008633GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8634 PPC_NONE, PPC2_BOOKE206),
8635GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8636 PPC_NONE, PPC2_BOOKE206),
8637GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8638 PPC_NONE, PPC2_BOOKE206),
8639GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8640 PPC_NONE, PPC2_BOOKE206),
Alexander Graf6d3db822012-01-20 04:09:15 +01008641GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8642 PPC_NONE, PPC2_BOOKE206),
Alexander Grafd5d11a32012-01-31 03:19:23 +01008643GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8644 PPC_NONE, PPC2_PRCNTL),
Alexander Graf9e0b5cb2012-01-31 03:18:35 +01008645GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8646 PPC_NONE, PPC2_PRCNTL),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008647GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
Baojun Wangfbe73002009-07-03 18:56:57 +08008648GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008649GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
Alexander Graf01662f32011-04-30 23:34:58 +02008650GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8651 PPC_BOOKE, PPC2_BOOKE206),
Alexander Grafdcb2b9e12012-01-21 03:48:58 +01008652GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
Alexander Graf01662f32011-04-30 23:34:58 +02008653GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8654 PPC_BOOKE, PPC2_BOOKE206),
Blue Swirl5c55ff92009-06-17 15:22:31 +00008655GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8656GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8657GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8658GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8659GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8660GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8661GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8662GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8663GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8664GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8665
8666#undef GEN_INT_ARITH_ADD
8667#undef GEN_INT_ARITH_ADD_CONST
8668#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8669GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8670#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8671 add_ca, compute_ca, compute_ov) \
8672GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8673GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8674GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8675GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8676GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8677GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8678GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8679GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8680GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8681GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8682GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8683
8684#undef GEN_INT_ARITH_DIVW
8685#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8686GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8687GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8688GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8689GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8690GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8691
8692#if defined(TARGET_PPC64)
8693#undef GEN_INT_ARITH_DIVD
8694#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8695GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8696GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8697GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8698GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8699GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8700
8701#undef GEN_INT_ARITH_MUL_HELPER
8702#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8703GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8704GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8705GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8706GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8707#endif
8708
8709#undef GEN_INT_ARITH_SUBF
8710#undef GEN_INT_ARITH_SUBF_CONST
8711#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8712GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8713#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8714 add_ca, compute_ca, compute_ov) \
8715GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8716GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8717GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8718GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8719GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8720GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8721GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8722GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8723GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8724GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8725GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8726
8727#undef GEN_LOGICAL1
8728#undef GEN_LOGICAL2
8729#define GEN_LOGICAL2(name, tcg_op, opc, type) \
8730GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8731#define GEN_LOGICAL1(name, tcg_op, opc, type) \
8732GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8733GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8734GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8735GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8736GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8737GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8738GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8739GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8740GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8741#if defined(TARGET_PPC64)
8742GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8743#endif
8744
8745#if defined(TARGET_PPC64)
8746#undef GEN_PPC64_R2
8747#undef GEN_PPC64_R4
8748#define GEN_PPC64_R2(name, opc1, opc2) \
8749GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8750GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8751 PPC_64B)
8752#define GEN_PPC64_R4(name, opc1, opc2) \
8753GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8754GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8755 PPC_64B), \
8756GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8757 PPC_64B), \
8758GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8759 PPC_64B)
8760GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8761GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8762GEN_PPC64_R4(rldic, 0x1E, 0x04),
8763GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8764GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8765GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8766#endif
8767
8768#undef _GEN_FLOAT_ACB
8769#undef GEN_FLOAT_ACB
8770#undef _GEN_FLOAT_AB
8771#undef GEN_FLOAT_AB
8772#undef _GEN_FLOAT_AC
8773#undef GEN_FLOAT_AC
8774#undef GEN_FLOAT_B
8775#undef GEN_FLOAT_BS
8776#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8777GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8778#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8779_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8780_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8781#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8783#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8784_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8785_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8786#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8787GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8788#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8789_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8790_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8791#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8792GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8793#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8794GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8795
8796GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8797GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8798GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8799GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8800GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8801GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8802_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8803GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8804GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8805GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8806GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8807GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8808GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8809GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8810GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8811#if defined(TARGET_PPC64)
8812GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8813GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8814GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8815#endif
8816GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8817GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8818GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8819GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8820GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8821GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8822GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8823
8824#undef GEN_LD
8825#undef GEN_LDU
8826#undef GEN_LDUX
8827#undef GEN_LDX
8828#undef GEN_LDS
8829#define GEN_LD(name, ldop, opc, type) \
8830GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8831#define GEN_LDU(name, ldop, opc, type) \
8832GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8833#define GEN_LDUX(name, ldop, opc2, opc3, type) \
8834GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8835#define GEN_LDX(name, ldop, opc2, opc3, type) \
8836GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8837#define GEN_LDS(name, ldop, op, type) \
8838GEN_LD(name, ldop, op | 0x20, type) \
8839GEN_LDU(name, ldop, op | 0x21, type) \
8840GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8841GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8842
8843GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8844GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8845GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8846GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8847#if defined(TARGET_PPC64)
8848GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8849GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8850GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8851GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8852#endif
8853GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8854GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8855
8856#undef GEN_ST
8857#undef GEN_STU
8858#undef GEN_STUX
8859#undef GEN_STX
8860#undef GEN_STS
8861#define GEN_ST(name, stop, opc, type) \
8862GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8863#define GEN_STU(name, stop, opc, type) \
8864GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8865#define GEN_STUX(name, stop, opc2, opc3, type) \
8866GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8867#define GEN_STX(name, stop, opc2, opc3, type) \
8868GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8869#define GEN_STS(name, stop, op, type) \
8870GEN_ST(name, stop, op | 0x20, type) \
8871GEN_STU(name, stop, op | 0x21, type) \
8872GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8873GEN_STX(name, stop, 0x17, op | 0x00, type)
8874
8875GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8876GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8877GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8878#if defined(TARGET_PPC64)
8879GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8880GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8881#endif
8882GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8883GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8884
8885#undef GEN_LDF
8886#undef GEN_LDUF
8887#undef GEN_LDUXF
8888#undef GEN_LDXF
8889#undef GEN_LDFS
8890#define GEN_LDF(name, ldop, opc, type) \
8891GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8892#define GEN_LDUF(name, ldop, opc, type) \
8893GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8894#define GEN_LDUXF(name, ldop, opc, type) \
8895GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8896#define GEN_LDXF(name, ldop, opc2, opc3, type) \
8897GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8898#define GEN_LDFS(name, ldop, op, type) \
8899GEN_LDF(name, ldop, op | 0x20, type) \
8900GEN_LDUF(name, ldop, op | 0x21, type) \
8901GEN_LDUXF(name, ldop, op | 0x01, type) \
8902GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8903
8904GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8905GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8906
8907#undef GEN_STF
8908#undef GEN_STUF
8909#undef GEN_STUXF
8910#undef GEN_STXF
8911#undef GEN_STFS
8912#define GEN_STF(name, stop, opc, type) \
8913GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8914#define GEN_STUF(name, stop, opc, type) \
8915GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8916#define GEN_STUXF(name, stop, opc, type) \
8917GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8918#define GEN_STXF(name, stop, opc2, opc3, type) \
8919GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8920#define GEN_STFS(name, stop, op, type) \
8921GEN_STF(name, stop, op | 0x20, type) \
8922GEN_STUF(name, stop, op | 0x21, type) \
8923GEN_STUXF(name, stop, op | 0x01, type) \
8924GEN_STXF(name, stop, 0x17, op | 0x00, type)
8925
8926GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8927GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8928GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8929
8930#undef GEN_CRLOGIC
8931#define GEN_CRLOGIC(name, tcg_op, opc) \
8932GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8933GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8934GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8935GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8936GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8937GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8938GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8939GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8940GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8941
8942#undef GEN_MAC_HANDLER
8943#define GEN_MAC_HANDLER(name, opc2, opc3) \
8944GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8945GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8946GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8947GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8948GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8949GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8950GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8951GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8952GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8953GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8954GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8955GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8956GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8957GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8958GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8959GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8960GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8961GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8962GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8963GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8964GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8965GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8966GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8967GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8968GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8969GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8970GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8971GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8972GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8973GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8974GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8975GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
8976GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
8977GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
8978GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
8979GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
8980GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
8981GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
8982GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
8983GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
8984GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
8985GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
8986GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
8987
8988#undef GEN_VR_LDX
8989#undef GEN_VR_STX
8990#undef GEN_VR_LVE
8991#undef GEN_VR_STVE
8992#define GEN_VR_LDX(name, opc2, opc3) \
8993GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8994#define GEN_VR_STX(name, opc2, opc3) \
8995GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8996#define GEN_VR_LVE(name, opc2, opc3) \
8997 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
8998#define GEN_VR_STVE(name, opc2, opc3) \
8999 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9000GEN_VR_LDX(lvx, 0x07, 0x03),
9001GEN_VR_LDX(lvxl, 0x07, 0x0B),
9002GEN_VR_LVE(bx, 0x07, 0x00),
9003GEN_VR_LVE(hx, 0x07, 0x01),
9004GEN_VR_LVE(wx, 0x07, 0x02),
9005GEN_VR_STX(svx, 0x07, 0x07),
9006GEN_VR_STX(svxl, 0x07, 0x0F),
9007GEN_VR_STVE(bx, 0x07, 0x04),
9008GEN_VR_STVE(hx, 0x07, 0x05),
9009GEN_VR_STVE(wx, 0x07, 0x06),
9010
9011#undef GEN_VX_LOGICAL
9012#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9013GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9014GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9015GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9016GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9017GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9018GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9019
9020#undef GEN_VXFORM
9021#define GEN_VXFORM(name, opc2, opc3) \
9022GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9023GEN_VXFORM(vaddubm, 0, 0),
9024GEN_VXFORM(vadduhm, 0, 1),
9025GEN_VXFORM(vadduwm, 0, 2),
9026GEN_VXFORM(vsububm, 0, 16),
9027GEN_VXFORM(vsubuhm, 0, 17),
9028GEN_VXFORM(vsubuwm, 0, 18),
9029GEN_VXFORM(vmaxub, 1, 0),
9030GEN_VXFORM(vmaxuh, 1, 1),
9031GEN_VXFORM(vmaxuw, 1, 2),
9032GEN_VXFORM(vmaxsb, 1, 4),
9033GEN_VXFORM(vmaxsh, 1, 5),
9034GEN_VXFORM(vmaxsw, 1, 6),
9035GEN_VXFORM(vminub, 1, 8),
9036GEN_VXFORM(vminuh, 1, 9),
9037GEN_VXFORM(vminuw, 1, 10),
9038GEN_VXFORM(vminsb, 1, 12),
9039GEN_VXFORM(vminsh, 1, 13),
9040GEN_VXFORM(vminsw, 1, 14),
9041GEN_VXFORM(vavgub, 1, 16),
9042GEN_VXFORM(vavguh, 1, 17),
9043GEN_VXFORM(vavguw, 1, 18),
9044GEN_VXFORM(vavgsb, 1, 20),
9045GEN_VXFORM(vavgsh, 1, 21),
9046GEN_VXFORM(vavgsw, 1, 22),
9047GEN_VXFORM(vmrghb, 6, 0),
9048GEN_VXFORM(vmrghh, 6, 1),
9049GEN_VXFORM(vmrghw, 6, 2),
9050GEN_VXFORM(vmrglb, 6, 4),
9051GEN_VXFORM(vmrglh, 6, 5),
9052GEN_VXFORM(vmrglw, 6, 6),
9053GEN_VXFORM(vmuloub, 4, 0),
9054GEN_VXFORM(vmulouh, 4, 1),
9055GEN_VXFORM(vmulosb, 4, 4),
9056GEN_VXFORM(vmulosh, 4, 5),
9057GEN_VXFORM(vmuleub, 4, 8),
9058GEN_VXFORM(vmuleuh, 4, 9),
9059GEN_VXFORM(vmulesb, 4, 12),
9060GEN_VXFORM(vmulesh, 4, 13),
9061GEN_VXFORM(vslb, 2, 4),
9062GEN_VXFORM(vslh, 2, 5),
9063GEN_VXFORM(vslw, 2, 6),
9064GEN_VXFORM(vsrb, 2, 8),
9065GEN_VXFORM(vsrh, 2, 9),
9066GEN_VXFORM(vsrw, 2, 10),
9067GEN_VXFORM(vsrab, 2, 12),
9068GEN_VXFORM(vsrah, 2, 13),
9069GEN_VXFORM(vsraw, 2, 14),
9070GEN_VXFORM(vslo, 6, 16),
9071GEN_VXFORM(vsro, 6, 17),
9072GEN_VXFORM(vaddcuw, 0, 6),
9073GEN_VXFORM(vsubcuw, 0, 22),
9074GEN_VXFORM(vaddubs, 0, 8),
9075GEN_VXFORM(vadduhs, 0, 9),
9076GEN_VXFORM(vadduws, 0, 10),
9077GEN_VXFORM(vaddsbs, 0, 12),
9078GEN_VXFORM(vaddshs, 0, 13),
9079GEN_VXFORM(vaddsws, 0, 14),
9080GEN_VXFORM(vsububs, 0, 24),
9081GEN_VXFORM(vsubuhs, 0, 25),
9082GEN_VXFORM(vsubuws, 0, 26),
9083GEN_VXFORM(vsubsbs, 0, 28),
9084GEN_VXFORM(vsubshs, 0, 29),
9085GEN_VXFORM(vsubsws, 0, 30),
9086GEN_VXFORM(vrlb, 2, 0),
9087GEN_VXFORM(vrlh, 2, 1),
9088GEN_VXFORM(vrlw, 2, 2),
9089GEN_VXFORM(vsl, 2, 7),
9090GEN_VXFORM(vsr, 2, 11),
9091GEN_VXFORM(vpkuhum, 7, 0),
9092GEN_VXFORM(vpkuwum, 7, 1),
9093GEN_VXFORM(vpkuhus, 7, 2),
9094GEN_VXFORM(vpkuwus, 7, 3),
9095GEN_VXFORM(vpkshus, 7, 4),
9096GEN_VXFORM(vpkswus, 7, 5),
9097GEN_VXFORM(vpkshss, 7, 6),
9098GEN_VXFORM(vpkswss, 7, 7),
9099GEN_VXFORM(vpkpx, 7, 12),
9100GEN_VXFORM(vsum4ubs, 4, 24),
9101GEN_VXFORM(vsum4sbs, 4, 28),
9102GEN_VXFORM(vsum4shs, 4, 25),
9103GEN_VXFORM(vsum2sws, 4, 26),
9104GEN_VXFORM(vsumsws, 4, 30),
9105GEN_VXFORM(vaddfp, 5, 0),
9106GEN_VXFORM(vsubfp, 5, 1),
9107GEN_VXFORM(vmaxfp, 5, 16),
9108GEN_VXFORM(vminfp, 5, 17),
9109
9110#undef GEN_VXRFORM1
9111#undef GEN_VXRFORM
9112#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9113 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9114#define GEN_VXRFORM(name, opc2, opc3) \
9115 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9116 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9117GEN_VXRFORM(vcmpequb, 3, 0)
9118GEN_VXRFORM(vcmpequh, 3, 1)
9119GEN_VXRFORM(vcmpequw, 3, 2)
9120GEN_VXRFORM(vcmpgtsb, 3, 12)
9121GEN_VXRFORM(vcmpgtsh, 3, 13)
9122GEN_VXRFORM(vcmpgtsw, 3, 14)
9123GEN_VXRFORM(vcmpgtub, 3, 8)
9124GEN_VXRFORM(vcmpgtuh, 3, 9)
9125GEN_VXRFORM(vcmpgtuw, 3, 10)
9126GEN_VXRFORM(vcmpeqfp, 3, 3)
9127GEN_VXRFORM(vcmpgefp, 3, 7)
9128GEN_VXRFORM(vcmpgtfp, 3, 11)
9129GEN_VXRFORM(vcmpbfp, 3, 15)
9130
9131#undef GEN_VXFORM_SIMM
9132#define GEN_VXFORM_SIMM(name, opc2, opc3) \
9133 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9134GEN_VXFORM_SIMM(vspltisb, 6, 12),
9135GEN_VXFORM_SIMM(vspltish, 6, 13),
9136GEN_VXFORM_SIMM(vspltisw, 6, 14),
9137
9138#undef GEN_VXFORM_NOA
9139#define GEN_VXFORM_NOA(name, opc2, opc3) \
9140 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9141GEN_VXFORM_NOA(vupkhsb, 7, 8),
9142GEN_VXFORM_NOA(vupkhsh, 7, 9),
9143GEN_VXFORM_NOA(vupklsb, 7, 10),
9144GEN_VXFORM_NOA(vupklsh, 7, 11),
9145GEN_VXFORM_NOA(vupkhpx, 7, 13),
9146GEN_VXFORM_NOA(vupklpx, 7, 15),
9147GEN_VXFORM_NOA(vrefp, 5, 4),
9148GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
Aurelien Jarno0bffbc62009-02-09 12:20:50 +01009149GEN_VXFORM_NOA(vexptefp, 5, 6),
Blue Swirl5c55ff92009-06-17 15:22:31 +00009150GEN_VXFORM_NOA(vlogefp, 5, 7),
9151GEN_VXFORM_NOA(vrfim, 5, 8),
9152GEN_VXFORM_NOA(vrfin, 5, 9),
9153GEN_VXFORM_NOA(vrfip, 5, 10),
9154GEN_VXFORM_NOA(vrfiz, 5, 11),
9155
9156#undef GEN_VXFORM_UIMM
9157#define GEN_VXFORM_UIMM(name, opc2, opc3) \
9158 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9159GEN_VXFORM_UIMM(vspltb, 6, 8),
9160GEN_VXFORM_UIMM(vsplth, 6, 9),
9161GEN_VXFORM_UIMM(vspltw, 6, 10),
9162GEN_VXFORM_UIMM(vcfux, 5, 12),
9163GEN_VXFORM_UIMM(vcfsx, 5, 13),
9164GEN_VXFORM_UIMM(vctuxs, 5, 14),
9165GEN_VXFORM_UIMM(vctsxs, 5, 15),
9166
9167#undef GEN_VAFORM_PAIRED
9168#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9169 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9170GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9171GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9172GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9173GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9174GEN_VAFORM_PAIRED(vsel, vperm, 21),
9175GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9176
9177#undef GEN_SPE
Fabien Chouteau70560da2011-09-28 05:54:05 +00009178#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9179 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9180GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9181GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9182GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9183GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9184GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9185GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9186GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9187GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9188GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9189GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9190GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9191GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9192GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9193GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9194GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9195GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9196GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9197GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9198GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9199GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9200GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9201GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9202GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9203GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9204GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9205GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9206GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9207GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9208GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
Blue Swirl5c55ff92009-06-17 15:22:31 +00009209
Fabien Chouteau70560da2011-09-28 05:54:05 +00009210GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9211GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9212GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9213GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9214GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9215GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9216GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9217GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9218GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9219GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9220GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9221GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9222GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9223GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
Blue Swirl5c55ff92009-06-17 15:22:31 +00009224
Fabien Chouteau70560da2011-09-28 05:54:05 +00009225GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9226GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9227GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9228GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9229GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9230GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9231GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9232GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9233GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9234GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9235GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9236GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9237GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9238GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
Blue Swirl5c55ff92009-06-17 15:22:31 +00009239
Fabien Chouteau70560da2011-09-28 05:54:05 +00009240GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9241GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9242GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9243GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9244GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9245GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9246GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9247GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9248GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9249GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9250GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9251GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9252GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9253GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9254GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9255GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
Blue Swirl5c55ff92009-06-17 15:22:31 +00009256
9257#undef GEN_SPEOP_LDST
9258#define GEN_SPEOP_LDST(name, opc2, sh) \
9259GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9260GEN_SPEOP_LDST(evldd, 0x00, 3),
9261GEN_SPEOP_LDST(evldw, 0x01, 3),
9262GEN_SPEOP_LDST(evldh, 0x02, 3),
9263GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9264GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9265GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9266GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9267GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9268GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9269GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9270GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9271
9272GEN_SPEOP_LDST(evstdd, 0x10, 3),
9273GEN_SPEOP_LDST(evstdw, 0x11, 3),
9274GEN_SPEOP_LDST(evstdh, 0x12, 3),
9275GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9276GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9277GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9278GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9279};
9280
bellard3fc6c082005-07-02 20:59:34 +00009281#include "translate_init.c"
j_mayer0411a972007-10-25 21:35:50 +00009282#include "helper_regs.h"
bellard79aceca2003-11-23 14:55:54 +00009283
bellard9a64fbe2004-01-04 22:58:38 +00009284/*****************************************************************************/
bellard3fc6c082005-07-02 20:59:34 +00009285/* Misc PowerPC helpers */
Stefan Weil9a78eea2010-10-22 23:03:33 +02009286void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
j_mayer36081602007-09-17 08:21:54 +00009287 int flags)
bellard79aceca2003-11-23 14:55:54 +00009288{
bellard3fc6c082005-07-02 20:59:34 +00009289#define RGPL 4
9290#define RFPL 4
bellard3fc6c082005-07-02 20:59:34 +00009291
bellard79aceca2003-11-23 14:55:54 +00009292 int i;
9293
Blue Swirl90e189e2009-08-16 11:13:18 +00009294 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
Stefan Weil9a78eea2010-10-22 23:03:33 +02009295 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9296 env->nip, env->lr, env->ctr, env->xer);
Blue Swirl90e189e2009-08-16 11:13:18 +00009297 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9298 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9299 env->hflags, env->mmu_idx);
j_mayerd9bce9d2007-03-17 14:02:15 +00009300#if !defined(NO_TIMER_DUMP)
Stefan Weil9a78eea2010-10-22 23:03:33 +02009301 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
j_mayer76a66252007-03-07 08:32:30 +00009302#if !defined(CONFIG_USER_ONLY)
Stefan Weil9a78eea2010-10-22 23:03:33 +02009303 " DECR %08" PRIu32
j_mayer76a66252007-03-07 08:32:30 +00009304#endif
9305 "\n",
j_mayer077fc202007-11-04 01:57:29 +00009306 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
j_mayer76a66252007-03-07 08:32:30 +00009307#if !defined(CONFIG_USER_ONLY)
9308 , cpu_ppc_load_decr(env)
9309#endif
9310 );
j_mayer077fc202007-11-04 01:57:29 +00009311#endif
j_mayer76a66252007-03-07 08:32:30 +00009312 for (i = 0; i < 32; i++) {
bellard3fc6c082005-07-02 20:59:34 +00009313 if ((i & (RGPL - 1)) == 0)
9314 cpu_fprintf(f, "GPR%02d", i);
Blue Swirlb11ebf62009-08-16 11:54:37 +00009315 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
bellard3fc6c082005-07-02 20:59:34 +00009316 if ((i & (RGPL - 1)) == (RGPL - 1))
bellard7fe48482004-10-09 18:08:01 +00009317 cpu_fprintf(f, "\n");
j_mayer76a66252007-03-07 08:32:30 +00009318 }
bellard3fc6c082005-07-02 20:59:34 +00009319 cpu_fprintf(f, "CR ");
j_mayer76a66252007-03-07 08:32:30 +00009320 for (i = 0; i < 8; i++)
bellard7fe48482004-10-09 18:08:01 +00009321 cpu_fprintf(f, "%01x", env->crf[i]);
9322 cpu_fprintf(f, " [");
j_mayer76a66252007-03-07 08:32:30 +00009323 for (i = 0; i < 8; i++) {
9324 char a = '-';
9325 if (env->crf[i] & 0x08)
9326 a = 'L';
9327 else if (env->crf[i] & 0x04)
9328 a = 'G';
9329 else if (env->crf[i] & 0x02)
9330 a = 'E';
bellard7fe48482004-10-09 18:08:01 +00009331 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
j_mayer76a66252007-03-07 08:32:30 +00009332 }
Blue Swirl90e189e2009-08-16 11:13:18 +00009333 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9334 env->reserve_addr);
bellard3fc6c082005-07-02 20:59:34 +00009335 for (i = 0; i < 32; i++) {
9336 if ((i & (RFPL - 1)) == 0)
9337 cpu_fprintf(f, "FPR%02d", i);
bellard26a76462006-06-25 18:15:32 +00009338 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
bellard3fc6c082005-07-02 20:59:34 +00009339 if ((i & (RFPL - 1)) == (RFPL - 1))
bellard7fe48482004-10-09 18:08:01 +00009340 cpu_fprintf(f, "\n");
bellard79aceca2003-11-23 14:55:54 +00009341 }
aurel3278892702008-12-14 18:40:49 +00009342 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
j_mayerf2e63a42007-10-07 15:43:50 +00009343#if !defined(CONFIG_USER_ONLY)
Scott Wood90dc8812011-04-29 17:10:23 -05009344 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9345 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9346 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9347 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9348
9349 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9350 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9351 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9352 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9353
9354 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9355 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9356 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9357 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9358
9359 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9360 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9361 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9362 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9363 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9364
9365 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9366 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9367 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9368 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9369
9370 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9371 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9372 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9373 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9374
9375 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9376 " EPR " TARGET_FMT_lx "\n",
9377 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9378 env->spr[SPR_BOOKE_EPR]);
9379
9380 /* FSL-specific */
9381 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9382 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9383 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9384 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9385
9386 /*
9387 * IVORs are left out as they are large and do not change often --
9388 * they can be read with "p $ivor0", "p $ivor1", etc.
9389 */
9390 }
9391
David Gibson697ab892011-08-31 15:45:10 +00009392#if defined(TARGET_PPC64)
9393 if (env->flags & POWERPC_FLAG_CFAR) {
9394 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9395 }
9396#endif
9397
Scott Wood90dc8812011-04-29 17:10:23 -05009398 switch (env->mmu_model) {
9399 case POWERPC_MMU_32B:
9400 case POWERPC_MMU_601:
9401 case POWERPC_MMU_SOFT_6xx:
9402 case POWERPC_MMU_SOFT_74xx:
9403#if defined(TARGET_PPC64)
9404 case POWERPC_MMU_620:
9405 case POWERPC_MMU_64B:
9406#endif
9407 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9408 break;
Alexander Graf01662f32011-04-30 23:34:58 +02009409 case POWERPC_MMU_BOOKE206:
Scott Wood90dc8812011-04-29 17:10:23 -05009410 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9411 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9412 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9413 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9414
9415 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9416 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9417 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9418 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9419
9420 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9421 " TLB1CFG " TARGET_FMT_lx "\n",
9422 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9423 env->spr[SPR_BOOKE_TLB1CFG]);
9424 break;
9425 default:
9426 break;
9427 }
j_mayerf2e63a42007-10-07 15:43:50 +00009428#endif
bellard79aceca2003-11-23 14:55:54 +00009429
bellard3fc6c082005-07-02 20:59:34 +00009430#undef RGPL
9431#undef RFPL
bellard79aceca2003-11-23 14:55:54 +00009432}
9433
Stefan Weil9a78eea2010-10-22 23:03:33 +02009434void cpu_dump_statistics (CPUState *env, FILE*f, fprintf_function cpu_fprintf,
j_mayer76a66252007-03-07 08:32:30 +00009435 int flags)
9436{
9437#if defined(DO_PPC_STATISTICS)
Anthony Liguoric227f092009-10-01 16:12:16 -05009438 opc_handler_t **t1, **t2, **t3, *handler;
j_mayer76a66252007-03-07 08:32:30 +00009439 int op1, op2, op3;
9440
9441 t1 = env->opcodes;
9442 for (op1 = 0; op1 < 64; op1++) {
9443 handler = t1[op1];
9444 if (is_indirect_opcode(handler)) {
9445 t2 = ind_table(handler);
9446 for (op2 = 0; op2 < 32; op2++) {
9447 handler = t2[op2];
9448 if (is_indirect_opcode(handler)) {
9449 t3 = ind_table(handler);
9450 for (op3 = 0; op3 < 32; op3++) {
9451 handler = t3[op3];
9452 if (handler->count == 0)
9453 continue;
9454 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
Blue Swirl0bfcd592010-05-22 08:02:12 +00009455 "%016" PRIx64 " %" PRId64 "\n",
j_mayer76a66252007-03-07 08:32:30 +00009456 op1, op2, op3, op1, (op3 << 5) | op2,
9457 handler->oname,
9458 handler->count, handler->count);
9459 }
9460 } else {
9461 if (handler->count == 0)
9462 continue;
9463 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
Blue Swirl0bfcd592010-05-22 08:02:12 +00009464 "%016" PRIx64 " %" PRId64 "\n",
j_mayer76a66252007-03-07 08:32:30 +00009465 op1, op2, op1, op2, handler->oname,
9466 handler->count, handler->count);
9467 }
9468 }
9469 } else {
9470 if (handler->count == 0)
9471 continue;
Blue Swirl0bfcd592010-05-22 08:02:12 +00009472 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9473 " %" PRId64 "\n",
j_mayer76a66252007-03-07 08:32:30 +00009474 op1, op1, handler->oname,
9475 handler->count, handler->count);
9476 }
9477 }
9478#endif
9479}
9480
bellard9a64fbe2004-01-04 22:58:38 +00009481/*****************************************************************************/
Blue Swirl636aa202009-08-16 09:06:54 +00009482static inline void gen_intermediate_code_internal(CPUState *env,
9483 TranslationBlock *tb,
9484 int search_pc)
bellard79aceca2003-11-23 14:55:54 +00009485{
bellard9fddaa02004-05-21 12:59:32 +00009486 DisasContext ctx, *ctxp = &ctx;
Anthony Liguoric227f092009-10-01 16:12:16 -05009487 opc_handler_t **table, *handler;
bellard0fa85d42005-01-03 23:43:32 +00009488 target_ulong pc_start;
bellard79aceca2003-11-23 14:55:54 +00009489 uint16_t *gen_opc_end;
aliguoria1d1bb32008-11-18 20:07:32 +00009490 CPUBreakpoint *bp;
bellard79aceca2003-11-23 14:55:54 +00009491 int j, lj = -1;
pbrook2e70f6e2008-06-29 01:03:05 +00009492 int num_insns;
9493 int max_insns;
bellard79aceca2003-11-23 14:55:54 +00009494
9495 pc_start = tb->pc;
bellard79aceca2003-11-23 14:55:54 +00009496 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
bellard046d6672004-04-25 21:15:35 +00009497 ctx.nip = pc_start;
bellard79aceca2003-11-23 14:55:54 +00009498 ctx.tb = tb;
j_mayere1833e12007-09-29 13:06:16 +00009499 ctx.exception = POWERPC_EXCP_NONE;
bellard3fc6c082005-07-02 20:59:34 +00009500 ctx.spr_cb = env->spr_cb;
aurel3276db3ba2008-12-08 18:11:21 +00009501 ctx.mem_idx = env->mmu_idx;
9502 ctx.access_type = -1;
9503 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
j_mayerd9bce9d2007-03-17 14:02:15 +00009504#if defined(TARGET_PPC64)
9505 ctx.sf_mode = msr_sf;
David Gibson697ab892011-08-31 15:45:10 +00009506 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
bellard9a64fbe2004-01-04 22:58:38 +00009507#endif
bellard3cc62372005-02-15 23:06:19 +00009508 ctx.fpu_enabled = msr_fp;
j_mayera9d9eb82007-10-07 18:19:26 +00009509 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
j_mayerd26bfc92007-10-07 14:41:00 +00009510 ctx.spe_enabled = msr_spe;
9511 else
9512 ctx.spe_enabled = 0;
j_mayera9d9eb82007-10-07 18:19:26 +00009513 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9514 ctx.altivec_enabled = msr_vr;
9515 else
9516 ctx.altivec_enabled = 0;
j_mayerd26bfc92007-10-07 14:41:00 +00009517 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
aurel328cbcb4f2008-05-10 23:28:14 +00009518 ctx.singlestep_enabled = CPU_SINGLE_STEP;
j_mayerd26bfc92007-10-07 14:41:00 +00009519 else
aurel328cbcb4f2008-05-10 23:28:14 +00009520 ctx.singlestep_enabled = 0;
j_mayerd26bfc92007-10-07 14:41:00 +00009521 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
aurel328cbcb4f2008-05-10 23:28:14 +00009522 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9523 if (unlikely(env->singlestep_enabled))
9524 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
bellard3fc6c082005-07-02 20:59:34 +00009525#if defined (DO_SINGLE_STEP) && 0
bellard9a64fbe2004-01-04 22:58:38 +00009526 /* Single step trace mode */
9527 msr_se = 1;
9528#endif
pbrook2e70f6e2008-06-29 01:03:05 +00009529 num_insns = 0;
9530 max_insns = tb->cflags & CF_COUNT_MASK;
9531 if (max_insns == 0)
9532 max_insns = CF_COUNT_MASK;
9533
9534 gen_icount_start();
bellard9a64fbe2004-01-04 22:58:38 +00009535 /* Set env in case of segfault during code fetch */
j_mayere1833e12007-09-29 13:06:16 +00009536 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
Blue Swirl72cf2d42009-09-12 07:36:22 +00009537 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9538 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
aliguoria1d1bb32008-11-18 20:07:32 +00009539 if (bp->pc == ctx.nip) {
aurel32e06fcd72008-12-11 22:42:14 +00009540 gen_debug_exception(ctxp);
bellardea4e7542006-05-22 21:50:20 +00009541 break;
9542 }
9543 }
9544 }
j_mayer76a66252007-03-07 08:32:30 +00009545 if (unlikely(search_pc)) {
bellard79aceca2003-11-23 14:55:54 +00009546 j = gen_opc_ptr - gen_opc_buf;
9547 if (lj < j) {
9548 lj++;
9549 while (lj < j)
9550 gen_opc_instr_start[lj++] = 0;
bellard79aceca2003-11-23 14:55:54 +00009551 }
aurel32af4b6c52009-03-29 01:18:03 +00009552 gen_opc_pc[lj] = ctx.nip;
9553 gen_opc_instr_start[lj] = 1;
9554 gen_opc_icount[lj] = num_insns;
bellard79aceca2003-11-23 14:55:54 +00009555 }
aliguorid12d51d2009-01-15 21:48:06 +00009556 LOG_DISAS("----------------\n");
Blue Swirl90e189e2009-08-16 11:13:18 +00009557 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
aliguorid12d51d2009-01-15 21:48:06 +00009558 ctx.nip, ctx.mem_idx, (int)msr_ir);
pbrook2e70f6e2008-06-29 01:03:05 +00009559 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9560 gen_io_start();
aurel3276db3ba2008-12-08 18:11:21 +00009561 if (unlikely(ctx.le_mode)) {
j_mayer056401e2007-11-04 02:55:33 +00009562 ctx.opcode = bswap32(ldl_code(ctx.nip));
9563 } else {
9564 ctx.opcode = ldl_code(ctx.nip);
bellard111bfab2005-04-23 18:16:07 +00009565 }
aliguorid12d51d2009-01-15 21:48:06 +00009566 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
bellard9a64fbe2004-01-04 22:58:38 +00009567 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
j_mayer056401e2007-11-04 02:55:33 +00009568 opc3(ctx.opcode), little_endian ? "little" : "big");
Aurelien Jarno731c54f2009-09-28 13:39:08 +02009569 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
9570 tcg_gen_debug_insn_start(ctx.nip);
bellard046d6672004-04-25 21:15:35 +00009571 ctx.nip += 4;
bellard3fc6c082005-07-02 20:59:34 +00009572 table = env->opcodes;
pbrook2e70f6e2008-06-29 01:03:05 +00009573 num_insns++;
bellard79aceca2003-11-23 14:55:54 +00009574 handler = table[opc1(ctx.opcode)];
9575 if (is_indirect_opcode(handler)) {
9576 table = ind_table(handler);
9577 handler = table[opc2(ctx.opcode)];
9578 if (is_indirect_opcode(handler)) {
9579 table = ind_table(handler);
9580 handler = table[opc3(ctx.opcode)];
9581 }
9582 }
9583 /* Is opcode *REALLY* valid ? */
j_mayer76a66252007-03-07 08:32:30 +00009584 if (unlikely(handler->handler == &gen_invalid)) {
aliguori93fcfe32009-01-15 22:34:14 +00009585 if (qemu_log_enabled()) {
9586 qemu_log("invalid/unsupported opcode: "
Blue Swirl90e189e2009-08-16 11:13:18 +00009587 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9588 opc1(ctx.opcode), opc2(ctx.opcode),
9589 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
bellard4b3686f2004-05-23 22:18:12 +00009590 }
j_mayer76a66252007-03-07 08:32:30 +00009591 } else {
Fabien Chouteau70560da2011-09-28 05:54:05 +00009592 uint32_t inval;
9593
9594 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9595 inval = handler->inval2;
9596 } else {
9597 inval = handler->inval1;
9598 }
9599
9600 if (unlikely((ctx.opcode & inval) != 0)) {
aliguori93fcfe32009-01-15 22:34:14 +00009601 if (qemu_log_enabled()) {
9602 qemu_log("invalid bits: %08x for opcode: "
Blue Swirl90e189e2009-08-16 11:13:18 +00009603 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
Fabien Chouteau70560da2011-09-28 05:54:05 +00009604 ctx.opcode & inval, opc1(ctx.opcode),
Blue Swirl90e189e2009-08-16 11:13:18 +00009605 opc2(ctx.opcode), opc3(ctx.opcode),
9606 ctx.opcode, ctx.nip - 4);
j_mayer76a66252007-03-07 08:32:30 +00009607 }
aurel32e06fcd72008-12-11 22:42:14 +00009608 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
bellard4b3686f2004-05-23 22:18:12 +00009609 break;
bellard9a64fbe2004-01-04 22:58:38 +00009610 }
bellard79aceca2003-11-23 14:55:54 +00009611 }
bellard4b3686f2004-05-23 22:18:12 +00009612 (*(handler->handler))(&ctx);
j_mayer76a66252007-03-07 08:32:30 +00009613#if defined(DO_PPC_STATISTICS)
9614 handler->count++;
9615#endif
bellard9a64fbe2004-01-04 22:58:38 +00009616 /* Check trace mode exceptions */
aurel328cbcb4f2008-05-10 23:28:14 +00009617 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9618 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9619 ctx.exception != POWERPC_SYSCALL &&
9620 ctx.exception != POWERPC_EXCP_TRAP &&
9621 ctx.exception != POWERPC_EXCP_BRANCH)) {
aurel32e06fcd72008-12-11 22:42:14 +00009622 gen_exception(ctxp, POWERPC_EXCP_TRACE);
j_mayerd26bfc92007-10-07 14:41:00 +00009623 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
pbrook2e70f6e2008-06-29 01:03:05 +00009624 (env->singlestep_enabled) ||
aurel321b530a62009-04-05 20:08:59 +00009625 singlestep ||
pbrook2e70f6e2008-06-29 01:03:05 +00009626 num_insns >= max_insns)) {
j_mayerd26bfc92007-10-07 14:41:00 +00009627 /* if we reach a page boundary or are single stepping, stop
9628 * generation
9629 */
bellard8dd49832005-06-04 22:22:27 +00009630 break;
j_mayer76a66252007-03-07 08:32:30 +00009631 }
bellard3fc6c082005-07-02 20:59:34 +00009632 }
pbrook2e70f6e2008-06-29 01:03:05 +00009633 if (tb->cflags & CF_LAST_IO)
9634 gen_io_end();
j_mayere1833e12007-09-29 13:06:16 +00009635 if (ctx.exception == POWERPC_EXCP_NONE) {
bellardc1942362005-11-20 10:31:08 +00009636 gen_goto_tb(&ctx, 0, ctx.nip);
j_mayere1833e12007-09-29 13:06:16 +00009637 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
aurel328cbcb4f2008-05-10 23:28:14 +00009638 if (unlikely(env->singlestep_enabled)) {
aurel32e06fcd72008-12-11 22:42:14 +00009639 gen_debug_exception(ctxp);
aurel328cbcb4f2008-05-10 23:28:14 +00009640 }
j_mayer76a66252007-03-07 08:32:30 +00009641 /* Generate the return instruction */
bellard57fec1f2008-02-01 10:50:11 +00009642 tcg_gen_exit_tb(0);
bellard9a64fbe2004-01-04 22:58:38 +00009643 }
pbrook2e70f6e2008-06-29 01:03:05 +00009644 gen_icount_end(tb, num_insns);
bellard79aceca2003-11-23 14:55:54 +00009645 *gen_opc_ptr = INDEX_op_end;
j_mayer76a66252007-03-07 08:32:30 +00009646 if (unlikely(search_pc)) {
bellard9a64fbe2004-01-04 22:58:38 +00009647 j = gen_opc_ptr - gen_opc_buf;
9648 lj++;
9649 while (lj <= j)
9650 gen_opc_instr_start[lj++] = 0;
bellard9a64fbe2004-01-04 22:58:38 +00009651 } else {
bellard046d6672004-04-25 21:15:35 +00009652 tb->size = ctx.nip - pc_start;
pbrook2e70f6e2008-06-29 01:03:05 +00009653 tb->icount = num_insns;
bellard9a64fbe2004-01-04 22:58:38 +00009654 }
j_mayerd9bce9d2007-03-17 14:02:15 +00009655#if defined(DEBUG_DISAS)
aliguori8fec2b82009-01-15 22:36:53 +00009656 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
j_mayer76a66252007-03-07 08:32:30 +00009657 int flags;
j_mayer237c0af2007-09-29 12:01:46 +00009658 flags = env->bfd_mach;
aurel3276db3ba2008-12-08 18:11:21 +00009659 flags |= ctx.le_mode << 16;
aliguori93fcfe32009-01-15 22:34:14 +00009660 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9661 log_target_disas(pc_start, ctx.nip - pc_start, flags);
9662 qemu_log("\n");
bellard9fddaa02004-05-21 12:59:32 +00009663 }
bellard79aceca2003-11-23 14:55:54 +00009664#endif
bellard79aceca2003-11-23 14:55:54 +00009665}
9666
ths2cfc5f12008-07-18 18:01:29 +00009667void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
bellard79aceca2003-11-23 14:55:54 +00009668{
ths2cfc5f12008-07-18 18:01:29 +00009669 gen_intermediate_code_internal(env, tb, 0);
bellard79aceca2003-11-23 14:55:54 +00009670}
9671
ths2cfc5f12008-07-18 18:01:29 +00009672void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
bellard79aceca2003-11-23 14:55:54 +00009673{
ths2cfc5f12008-07-18 18:01:29 +00009674 gen_intermediate_code_internal(env, tb, 1);
bellard79aceca2003-11-23 14:55:54 +00009675}
aurel32d2856f12008-04-28 00:32:32 +00009676
Stefan Weile87b7cb2011-04-18 06:39:52 +00009677void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
aurel32d2856f12008-04-28 00:32:32 +00009678{
aurel32d2856f12008-04-28 00:32:32 +00009679 env->nip = gen_opc_pc[pc_pos];
aurel32d2856f12008-04-28 00:32:32 +00009680}