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balrog02645922007-11-03 12:50:46 +00001/*
2 * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
3 *
4 * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
pbrook87ecb682007-11-17 17:14:51 +000021#include "hw.h"
22#include "i2c.h"
23#include "omap.h"
balrog02645922007-11-03 12:50:46 +000024
25struct omap_i2c_s {
26 target_phys_addr_t base;
27 qemu_irq irq;
28 qemu_irq drq[2];
29 i2c_slave slave;
30 i2c_bus *bus;
31
balrog29885472008-02-10 17:02:23 +000032 uint8_t revision;
balrog02645922007-11-03 12:50:46 +000033 uint8_t mask;
34 uint16_t stat;
35 uint16_t dma;
36 uint16_t count;
37 int count_cur;
38 uint32_t fifo;
39 int rxlen;
40 int txlen;
41 uint16_t control;
42 uint16_t addr[2];
43 uint8_t divider;
44 uint8_t times[2];
45 uint16_t test;
46};
47
balrog29885472008-02-10 17:02:23 +000048#define OMAP2_INTR_REV 0x34
49#define OMAP2_GC_REV 0x34
50
balrog02645922007-11-03 12:50:46 +000051static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
52{
53 qemu_set_irq(s->irq, s->stat & s->mask);
54 if ((s->dma >> 15) & 1) /* RDMA_EN */
55 qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */
56 if ((s->dma >> 7) & 1) /* XDMA_EN */
57 qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
58}
59
60/* These are only stubs now. */
61static void omap_i2c_event(i2c_slave *i2c, enum i2c_event event)
62{
63 struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
64
65 if ((~s->control >> 15) & 1) /* I2C_EN */
66 return;
67
68 switch (event) {
69 case I2C_START_SEND:
70 case I2C_START_RECV:
71 s->stat |= 1 << 9; /* AAS */
72 break;
73 case I2C_FINISH:
74 s->stat |= 1 << 2; /* ARDY */
75 break;
76 case I2C_NACK:
77 s->stat |= 1 << 1; /* NACK */
78 break;
79 }
80
81 omap_i2c_interrupts_update(s);
82}
83
84static int omap_i2c_rx(i2c_slave *i2c)
85{
86 struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
87 uint8_t ret = 0;
88
89 if ((~s->control >> 15) & 1) /* I2C_EN */
90 return -1;
91
92 if (s->txlen)
93 ret = s->fifo >> ((-- s->txlen) << 3) & 0xff;
94 else
95 s->stat |= 1 << 10; /* XUDF */
96 s->stat |= 1 << 4; /* XRDY */
97
98 omap_i2c_interrupts_update(s);
99 return ret;
100}
101
102static int omap_i2c_tx(i2c_slave *i2c, uint8_t data)
103{
104 struct omap_i2c_s *s = (struct omap_i2c_s *) i2c;
105
106 if ((~s->control >> 15) & 1) /* I2C_EN */
107 return 1;
108
109 if (s->rxlen < 4)
110 s->fifo |= data << ((s->rxlen ++) << 3);
111 else
112 s->stat |= 1 << 11; /* ROVR */
113 s->stat |= 1 << 3; /* RRDY */
114
115 omap_i2c_interrupts_update(s);
116 return 1;
117}
118
119static void omap_i2c_fifo_run(struct omap_i2c_s *s)
120{
121 int ack = 1;
122
123 if (!i2c_bus_busy(s->bus))
124 return;
125
126 if ((s->control >> 2) & 1) { /* RM */
127 if ((s->control >> 1) & 1) { /* STP */
128 i2c_end_transfer(s->bus);
129 s->control &= ~(1 << 1); /* STP */
130 s->count_cur = s->count;
balrog29885472008-02-10 17:02:23 +0000131 s->txlen = 0;
balrog02645922007-11-03 12:50:46 +0000132 } else if ((s->control >> 9) & 1) { /* TRX */
133 while (ack && s->txlen)
134 ack = (i2c_send(s->bus,
135 (s->fifo >> ((-- s->txlen) << 3)) &
136 0xff) >= 0);
137 s->stat |= 1 << 4; /* XRDY */
138 } else {
139 while (s->rxlen < 4)
140 s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
141 s->stat |= 1 << 3; /* RRDY */
142 }
143 } else {
144 if ((s->control >> 9) & 1) { /* TRX */
145 while (ack && s->count_cur && s->txlen) {
146 ack = (i2c_send(s->bus,
147 (s->fifo >> ((-- s->txlen) << 3)) &
148 0xff) >= 0);
149 s->count_cur --;
150 }
151 if (ack && s->count_cur)
152 s->stat |= 1 << 4; /* XRDY */
153 if (!s->count_cur) {
154 s->stat |= 1 << 2; /* ARDY */
155 s->control &= ~(1 << 10); /* MST */
156 }
157 } else {
158 while (s->count_cur && s->rxlen < 4) {
159 s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
160 s->count_cur --;
161 }
162 if (s->rxlen)
163 s->stat |= 1 << 3; /* RRDY */
164 }
165 if (!s->count_cur) {
166 if ((s->control >> 1) & 1) { /* STP */
167 i2c_end_transfer(s->bus);
168 s->control &= ~(1 << 1); /* STP */
169 s->count_cur = s->count;
balrog29885472008-02-10 17:02:23 +0000170 s->txlen = 0;
balrog02645922007-11-03 12:50:46 +0000171 } else {
172 s->stat |= 1 << 2; /* ARDY */
173 s->control &= ~(1 << 10); /* MST */
174 }
175 }
176 }
177
178 s->stat |= (!ack) << 1; /* NACK */
179 if (!ack)
180 s->control &= ~(1 << 1); /* STP */
181}
182
183void omap_i2c_reset(struct omap_i2c_s *s)
184{
185 s->mask = 0;
186 s->stat = 0;
187 s->dma = 0;
188 s->count = 0;
189 s->count_cur = 0;
190 s->fifo = 0;
191 s->rxlen = 0;
192 s->txlen = 0;
193 s->control = 0;
194 s->addr[0] = 0;
195 s->addr[1] = 0;
196 s->divider = 0;
197 s->times[0] = 0;
198 s->times[1] = 0;
199 s->test = 0;
200}
201
202static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
203{
204 struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
balrogcf965d22007-11-04 12:19:22 +0000205 int offset = addr & OMAP_MPUI_REG_MASK;
balrog02645922007-11-03 12:50:46 +0000206 uint16_t ret;
207
208 switch (offset) {
209 case 0x00: /* I2C_REV */
balrog29885472008-02-10 17:02:23 +0000210 return s->revision; /* REV */
balrog02645922007-11-03 12:50:46 +0000211
212 case 0x04: /* I2C_IE */
213 return s->mask;
214
215 case 0x08: /* I2C_STAT */
216 return s->stat | (i2c_bus_busy(s->bus) << 12);
217
218 case 0x0c: /* I2C_IV */
balrog29885472008-02-10 17:02:23 +0000219 if (s->revision >= OMAP2_INTR_REV)
220 break;
balrog02645922007-11-03 12:50:46 +0000221 ret = ffs(s->stat & s->mask);
222 if (ret)
223 s->stat ^= 1 << (ret - 1);
224 omap_i2c_interrupts_update(s);
225 return ret;
226
balrog29885472008-02-10 17:02:23 +0000227 case 0x10: /* I2C_SYSS */
228 return (s->control >> 15) & 1; /* I2C_EN */
229
balrog02645922007-11-03 12:50:46 +0000230 case 0x14: /* I2C_BUF */
231 return s->dma;
232
233 case 0x18: /* I2C_CNT */
234 return s->count_cur; /* DCOUNT */
235
236 case 0x1c: /* I2C_DATA */
237 ret = 0;
238 if (s->control & (1 << 14)) { /* BE */
239 ret |= ((s->fifo >> 0) & 0xff) << 8;
240 ret |= ((s->fifo >> 8) & 0xff) << 0;
241 } else {
242 ret |= ((s->fifo >> 8) & 0xff) << 8;
243 ret |= ((s->fifo >> 0) & 0xff) << 0;
244 }
245 if (s->rxlen == 1) {
246 s->stat |= 1 << 15; /* SBD */
247 s->rxlen = 0;
248 } else if (s->rxlen > 1) {
249 if (s->rxlen > 2)
250 s->fifo >>= 16;
251 s->rxlen -= 2;
252 } else
253 /* XXX: remote access (qualifier) error - what's that? */;
254 if (!s->rxlen) {
balrog29885472008-02-10 17:02:23 +0000255 s->stat &= ~(1 << 3); /* RRDY */
balrog02645922007-11-03 12:50:46 +0000256 if (((s->control >> 10) & 1) && /* MST */
257 ((~s->control >> 9) & 1)) { /* TRX */
258 s->stat |= 1 << 2; /* ARDY */
259 s->control &= ~(1 << 10); /* MST */
260 }
261 }
262 s->stat &= ~(1 << 11); /* ROVR */
263 omap_i2c_fifo_run(s);
264 omap_i2c_interrupts_update(s);
265 return ret;
266
balrog29885472008-02-10 17:02:23 +0000267 case 0x20: /* I2C_SYSC */
268 return 0;
269
balrog02645922007-11-03 12:50:46 +0000270 case 0x24: /* I2C_CON */
271 return s->control;
272
273 case 0x28: /* I2C_OA */
274 return s->addr[0];
275
276 case 0x2c: /* I2C_SA */
277 return s->addr[1];
278
279 case 0x30: /* I2C_PSC */
280 return s->divider;
281
282 case 0x34: /* I2C_SCLL */
283 return s->times[0];
284
285 case 0x38: /* I2C_SCLH */
286 return s->times[1];
287
288 case 0x3c: /* I2C_SYSTEST */
289 if (s->test & (1 << 15)) { /* ST_EN */
290 s->test ^= 0xa;
291 return s->test;
292 } else
293 return s->test & ~0x300f;
294 }
295
296 OMAP_BAD_REG(addr);
297 return 0;
298}
299
300static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
301 uint32_t value)
302{
303 struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
balrogcf965d22007-11-04 12:19:22 +0000304 int offset = addr & OMAP_MPUI_REG_MASK;
balrog02645922007-11-03 12:50:46 +0000305 int nack;
306
307 switch (offset) {
308 case 0x00: /* I2C_REV */
balrog02645922007-11-03 12:50:46 +0000309 case 0x0c: /* I2C_IV */
balrog29885472008-02-10 17:02:23 +0000310 case 0x10: /* I2C_SYSS */
311 OMAP_RO_REG(addr);
balrog02645922007-11-03 12:50:46 +0000312 return;
313
314 case 0x04: /* I2C_IE */
balrog29885472008-02-10 17:02:23 +0000315 s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
316 break;
317
318 case 0x08: /* I2C_STAT */
319 if (s->revision < OMAP2_INTR_REV) {
320 OMAP_RO_REG(addr);
321 return;
322 }
323
324 s->stat &= ~(value & 0x3f);
325 omap_i2c_interrupts_update(s);
balrog02645922007-11-03 12:50:46 +0000326 break;
327
328 case 0x14: /* I2C_BUF */
329 s->dma = value & 0x8080;
330 if (value & (1 << 15)) /* RDMA_EN */
331 s->mask &= ~(1 << 3); /* RRDY_IE */
332 if (value & (1 << 7)) /* XDMA_EN */
333 s->mask &= ~(1 << 4); /* XRDY_IE */
334 break;
335
336 case 0x18: /* I2C_CNT */
337 s->count = value; /* DCOUNT */
338 break;
339
340 case 0x1c: /* I2C_DATA */
341 if (s->txlen > 2) {
342 /* XXX: remote access (qualifier) error - what's that? */
343 break;
344 }
345 s->fifo <<= 16;
346 s->txlen += 2;
347 if (s->control & (1 << 14)) { /* BE */
348 s->fifo |= ((value >> 8) & 0xff) << 8;
349 s->fifo |= ((value >> 0) & 0xff) << 0;
350 } else {
351 s->fifo |= ((value >> 0) & 0xff) << 8;
352 s->fifo |= ((value >> 8) & 0xff) << 0;
353 }
354 s->stat &= ~(1 << 10); /* XUDF */
355 if (s->txlen > 2)
356 s->stat &= ~(1 << 4); /* XRDY */
357 omap_i2c_fifo_run(s);
358 omap_i2c_interrupts_update(s);
359 break;
360
balrog29885472008-02-10 17:02:23 +0000361 case 0x20: /* I2C_SYSC */
362 if (s->revision < OMAP2_INTR_REV) {
363 OMAP_BAD_REG(addr);
364 return;
365 }
366
367 if (value & 2)
balrog02645922007-11-03 12:50:46 +0000368 omap_i2c_reset(s);
balrog29885472008-02-10 17:02:23 +0000369 break;
370
371 case 0x24: /* I2C_CON */
372 s->control = value & 0xcf87;
373 if (~value & (1 << 15)) { /* I2C_EN */
374 if (s->revision < OMAP2_INTR_REV)
375 omap_i2c_reset(s);
balrog02645922007-11-03 12:50:46 +0000376 break;
377 }
balrog29885472008-02-10 17:02:23 +0000378 if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
balrog02645922007-11-03 12:50:46 +0000379 printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
380 break;
381 }
balrog29885472008-02-10 17:02:23 +0000382 if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
balrog02645922007-11-03 12:50:46 +0000383 printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
384 break;
385 }
balrog29885472008-02-10 17:02:23 +0000386 if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
balrog02645922007-11-03 12:50:46 +0000387 nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
388 (~value >> 9) & 1); /* TRX */
389 s->stat |= nack << 1; /* NACK */
390 s->control &= ~(1 << 0); /* STT */
391 if (nack)
392 s->control &= ~(1 << 1); /* STP */
balrog29885472008-02-10 17:02:23 +0000393 else {
394 s->count_cur = s->count;
balrog02645922007-11-03 12:50:46 +0000395 omap_i2c_fifo_run(s);
balrog29885472008-02-10 17:02:23 +0000396 }
balrog02645922007-11-03 12:50:46 +0000397 omap_i2c_interrupts_update(s);
398 }
399 break;
400
401 case 0x28: /* I2C_OA */
402 s->addr[0] = value & 0x3ff;
403 i2c_set_slave_address(&s->slave, value & 0x7f);
404 break;
405
406 case 0x2c: /* I2C_SA */
407 s->addr[1] = value & 0x3ff;
408 break;
409
410 case 0x30: /* I2C_PSC */
411 s->divider = value;
412 break;
413
414 case 0x34: /* I2C_SCLL */
415 s->times[0] = value;
416 break;
417
418 case 0x38: /* I2C_SCLH */
419 s->times[1] = value;
420 break;
421
422 case 0x3c: /* I2C_SYSTEST */
balrog29885472008-02-10 17:02:23 +0000423 s->test = value & 0xf80f;
424 if (value & (1 << 11)) /* SBB */
425 if (s->revision >= OMAP2_INTR_REV) {
426 s->stat |= 0x3f;
427 omap_i2c_interrupts_update(s);
428 }
balrog02645922007-11-03 12:50:46 +0000429 if (value & (1 << 15)) /* ST_EN */
430 printf("%s: System Test not supported\n", __FUNCTION__);
431 break;
432
433 default:
434 OMAP_BAD_REG(addr);
435 return;
436 }
437}
438
balrog29885472008-02-10 17:02:23 +0000439static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
440 uint32_t value)
441{
442 struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
443 int offset = addr & OMAP_MPUI_REG_MASK;
444
445 switch (offset) {
446 case 0x1c: /* I2C_DATA */
447 if (s->txlen > 2) {
448 /* XXX: remote access (qualifier) error - what's that? */
449 break;
450 }
451 s->fifo <<= 8;
452 s->txlen += 1;
453 s->fifo |= value & 0xff;
454 s->stat &= ~(1 << 10); /* XUDF */
455 if (s->txlen > 2)
456 s->stat &= ~(1 << 4); /* XRDY */
457 omap_i2c_fifo_run(s);
458 omap_i2c_interrupts_update(s);
459 break;
460
461 default:
462 OMAP_BAD_REG(addr);
463 return;
464 }
465}
466
balrog02645922007-11-03 12:50:46 +0000467static CPUReadMemoryFunc *omap_i2c_readfn[] = {
468 omap_badwidth_read16,
469 omap_i2c_read,
470 omap_badwidth_read16,
471};
472
473static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
balrog29885472008-02-10 17:02:23 +0000474 omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
balrog02645922007-11-03 12:50:46 +0000475 omap_i2c_write,
balrog29885472008-02-10 17:02:23 +0000476 omap_badwidth_write16,
balrog02645922007-11-03 12:50:46 +0000477};
478
479struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
480 qemu_irq irq, qemu_irq *dma, omap_clk clk)
481{
482 int iomemtype;
483 struct omap_i2c_s *s = (struct omap_i2c_s *)
484 qemu_mallocz(sizeof(struct omap_i2c_s));
485
balrog29885472008-02-10 17:02:23 +0000486 /* TODO: set a value greater or equal to real hardware */
487 s->revision = 0x11;
balrog02645922007-11-03 12:50:46 +0000488 s->base = base;
489 s->irq = irq;
490 s->drq[0] = dma[0];
491 s->drq[1] = dma[1];
492 s->slave.event = omap_i2c_event;
493 s->slave.recv = omap_i2c_rx;
494 s->slave.send = omap_i2c_tx;
495 s->bus = i2c_init_bus();
496 omap_i2c_reset(s);
497
498 iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
499 omap_i2c_writefn, s);
500 cpu_register_physical_memory(s->base, 0x800, iomemtype);
501
502 return s;
503}
504
balrog29885472008-02-10 17:02:23 +0000505struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
506 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
507{
508 int iomemtype;
509 struct omap_i2c_s *s = (struct omap_i2c_s *)
510 qemu_mallocz(sizeof(struct omap_i2c_s));
511
512 s->revision = 0x34;
513 s->irq = irq;
514 s->drq[0] = dma[0];
515 s->drq[1] = dma[1];
516 s->slave.event = omap_i2c_event;
517 s->slave.recv = omap_i2c_rx;
518 s->slave.send = omap_i2c_tx;
519 s->bus = i2c_init_bus();
520 omap_i2c_reset(s);
521
522 iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
523 omap_i2c_writefn, s);
524 s->base = omap_l4_attach(ta, 0, iomemtype);
525
526 return s;
527}
528
balrog02645922007-11-03 12:50:46 +0000529i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
530{
531 return s->bus;
532}