Edgar E. Iglesias | d1dbffd | 2020-08-20 21:17:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 Xilinx Inc. |
| 3 | * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>. |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | / { |
| 11 | #address-cells = < 0x01 >; |
| 12 | #size-cells = < 0x01 >; |
| 13 | compatible = "xlnx,microblaze"; |
| 14 | model = "edk131"; |
| 15 | |
| 16 | memory@50000000 { |
| 17 | device_type = "memory"; |
| 18 | reg = < 0x50000000 0x10000000 >; |
| 19 | }; |
| 20 | |
| 21 | aliases { |
| 22 | ethernet0 = "/axi/axi-ethernet@82780000"; |
| 23 | serial0 = "/axi/serial@83e00000"; |
| 24 | }; |
| 25 | |
| 26 | chosen { |
| 27 | bootargs = " console=ttyS0,115200 "; |
| 28 | stdout-path = "/axi/serial@83e00000"; |
| 29 | }; |
| 30 | |
| 31 | cpus { |
| 32 | #address-cells = < 0x01 >; |
| 33 | #cpus = < 0x01 >; |
| 34 | #size-cells = < 0x00 >; |
| 35 | |
| 36 | cpu@0 { |
| 37 | clock-frequency = < 0xbebc200 >; |
| 38 | compatible = "xlnx,microblaze-8.10.a"; |
| 39 | d-cache-baseaddr = < 0x50000000 >; |
| 40 | d-cache-highaddr = < 0x5fffffff >; |
| 41 | d-cache-line-size = < 0x20 >; |
| 42 | d-cache-size = < 0x800 >; |
| 43 | device_type = "cpu"; |
| 44 | i-cache-baseaddr = < 0x50000000 >; |
| 45 | i-cache-highaddr = < 0x5fffffff >; |
| 46 | i-cache-line-size = < 0x20 >; |
| 47 | i-cache-size = < 0x800 >; |
| 48 | model = "microblaze,8.10.a"; |
| 49 | reg = < 0x00 >; |
| 50 | timebase-frequency = < 0xbebc200 >; |
| 51 | xlnx,addr-tag-bits = < 0x11 >; |
| 52 | xlnx,allow-dcache-wr = < 0x01 >; |
| 53 | xlnx,allow-icache-wr = < 0x01 >; |
| 54 | xlnx,area-optimized = < 0x00 >; |
| 55 | xlnx,branch-target-cache-size = < 0x00 >; |
| 56 | xlnx,cache-byte-size = < 0x800 >; |
| 57 | xlnx,d-axi = < 0x01 >; |
| 58 | xlnx,d-lmb = < 0x01 >; |
| 59 | xlnx,d-plb = < 0x00 >; |
| 60 | xlnx,data-size = < 0x20 >; |
| 61 | xlnx,dcache-addr-tag = < 0x11 >; |
| 62 | xlnx,dcache-always-used = < 0x01 >; |
| 63 | xlnx,dcache-byte-size = < 0x800 >; |
| 64 | xlnx,dcache-data-width = < 0x00 >; |
| 65 | xlnx,dcache-force-tag-lutram = < 0x00 >; |
| 66 | xlnx,dcache-interface = < 0x01 >; |
| 67 | xlnx,dcache-line-len = < 0x08 >; |
| 68 | xlnx,dcache-use-fsl = < 0x00 >; |
| 69 | xlnx,dcache-use-writeback = < 0x01 >; |
| 70 | xlnx,dcache-victims = < 0x00 >; |
| 71 | xlnx,debug-enabled = < 0x01 >; |
| 72 | xlnx,div-zero-exception = < 0x01 >; |
| 73 | xlnx,dynamic-bus-sizing = < 0x01 >; |
| 74 | xlnx,ecc-use-ce-exception = < 0x00 >; |
| 75 | xlnx,edge-is-positive = < 0x01 >; |
| 76 | xlnx,endianness = < 0x01 >; |
| 77 | xlnx,family = "virtex6"; |
| 78 | xlnx,fault-tolerant = < 0x00 >; |
| 79 | xlnx,fpu-exception = < 0x01 >; |
| 80 | xlnx,freq = < 0xbebc200 >; |
| 81 | xlnx,fsl-data-size = < 0x20 >; |
| 82 | xlnx,fsl-exception = < 0x00 >; |
| 83 | xlnx,fsl-links = < 0x00 >; |
| 84 | xlnx,i-axi = < 0x01 >; |
| 85 | xlnx,i-lmb = < 0x01 >; |
| 86 | xlnx,i-plb = < 0x00 >; |
| 87 | xlnx,icache-always-used = < 0x01 >; |
| 88 | xlnx,icache-data-width = < 0x00 >; |
| 89 | xlnx,icache-force-tag-lutram = < 0x00 >; |
| 90 | xlnx,icache-interface = < 0x00 >; |
| 91 | xlnx,icache-line-len = < 0x08 >; |
| 92 | xlnx,icache-streams = < 0x00 >; |
| 93 | xlnx,icache-use-fsl = < 0x00 >; |
| 94 | xlnx,icache-victims = < 0x00 >; |
| 95 | xlnx,ill-opcode-exception = < 0x01 >; |
| 96 | xlnx,instance = "microblaze_0"; |
| 97 | xlnx,interconnect = < 0x02 >; |
| 98 | xlnx,interrupt-is-edge = < 0x00 >; |
| 99 | xlnx,mmu-dtlb-size = < 0x04 >; |
| 100 | xlnx,mmu-itlb-size = < 0x02 >; |
| 101 | xlnx,mmu-privileged-instr = < 0x00 >; |
| 102 | xlnx,mmu-tlb-access = < 0x03 >; |
| 103 | xlnx,mmu-zones = < 0x02 >; |
| 104 | xlnx,number-of-pc-brk = < 0x01 >; |
| 105 | xlnx,number-of-rd-addr-brk = < 0x00 >; |
| 106 | xlnx,number-of-wr-addr-brk = < 0x00 >; |
| 107 | xlnx,opcode-0x0-illegal = < 0x01 >; |
| 108 | xlnx,optimization = < 0x00 >; |
| 109 | xlnx,pvr = < 0x02 >; |
| 110 | xlnx,pvr-user1 = < 0x00 >; |
| 111 | xlnx,pvr-user2 = < 0x00 >; |
| 112 | xlnx,reset-msr = < 0x00 >; |
| 113 | xlnx,sco = < 0x00 >; |
| 114 | xlnx,stream-interconnect = < 0x00 >; |
| 115 | xlnx,unaligned-exceptions = < 0x01 >; |
| 116 | xlnx,use-barrel = < 0x01 >; |
| 117 | xlnx,use-branch-target-cache = < 0x00 >; |
| 118 | xlnx,use-dcache = < 0x01 >; |
| 119 | xlnx,use-div = < 0x01 >; |
| 120 | xlnx,use-ext-brk = < 0x01 >; |
| 121 | xlnx,use-ext-nm-brk = < 0x01 >; |
| 122 | xlnx,use-extended-fsl-instr = < 0x00 >; |
| 123 | xlnx,use-fpu = < 0x01 >; |
| 124 | xlnx,use-hw-mul = < 0x02 >; |
| 125 | xlnx,use-icache = < 0x01 >; |
| 126 | xlnx,use-interrupt = < 0x01 >; |
| 127 | xlnx,use-mmu = < 0x03 >; |
| 128 | xlnx,use-msr-instr = < 0x01 >; |
| 129 | xlnx,use-pcmp-instr = < 0x01 >; |
| 130 | xlnx,use-stack-protection = < 0x00 >; |
| 131 | }; |
| 132 | }; |
| 133 | |
| 134 | axi { |
| 135 | #address-cells = < 0x01 >; |
| 136 | #size-cells = < 0x01 >; |
| 137 | compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus"; |
| 138 | ranges; |
| 139 | |
| 140 | axi-ethernet@82780000 { |
| 141 | axistream-connected = < &axi_dma >; |
| 142 | compatible = "xlnx,axi-ethernet-2.01.a\0xlnx,axi-ethernet-1.00.a"; |
| 143 | device_type = "network"; |
| 144 | interrupt-parent = < &intc >; |
| 145 | interrupts = < 0x03 0x02 >; |
| 146 | local-mac-address = [ 00 0a 35 00 22 01 ]; |
| 147 | phy-handle = < &phy7 >; |
| 148 | reg = < 0x82780000 0x40000 >; |
| 149 | xlnx,avb = < 0x00 >; |
| 150 | xlnx,halfdup = < 0x00 >; |
| 151 | xlnx,include-io = < 0x01 >; |
| 152 | xlnx,mcast-extend = < 0x00 >; |
| 153 | xlnx,phy-type = < 0x01 >; |
| 154 | xlnx,phyaddr = "0B00001"; |
| 155 | xlnx,rxcsum = < 0x00 >; |
| 156 | xlnx,rxmem = < 0x1000 >; |
| 157 | xlnx,rxvlan-strp = < 0x00 >; |
| 158 | xlnx,rxvlan-tag = < 0x00 >; |
| 159 | xlnx,rxvlan-tran = < 0x00 >; |
| 160 | xlnx,stats = < 0x00 >; |
| 161 | xlnx,txcsum = < 0x00 >; |
| 162 | xlnx,txmem = < 0x1000 >; |
| 163 | xlnx,txvlan-strp = < 0x00 >; |
| 164 | xlnx,txvlan-tag = < 0x00 >; |
| 165 | xlnx,txvlan-tran = < 0x00 >; |
| 166 | xlnx,type = < 0x02 >; |
| 167 | |
| 168 | mdio { |
| 169 | #address-cells = < 0x01 >; |
| 170 | #size-cells = < 0x00 >; |
| 171 | |
| 172 | phy7: phy@7 { |
| 173 | compatible = "marvell,88e1111"; |
| 174 | device_type = "ethernet-phy"; |
| 175 | reg = < 0x07 >; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | axi_dma: axi-dma@84600000 { |
| 181 | compatible = "xlnx,axi-dma-3.00.a"; |
| 182 | interrupt-parent = < &intc >; |
| 183 | interrupts = < 0x01 0x02 0x00 0x02 >; |
| 184 | reg = < 0x84600000 0x10000 >; |
| 185 | xlnx,dlytmr-resolution = < 0x4e2 >; |
| 186 | xlnx,family = "virtex6"; |
| 187 | xlnx,include-mm2s = < 0x01 >; |
| 188 | xlnx,include-mm2s-dre = < 0x01 >; |
| 189 | xlnx,include-s2mm = < 0x01 >; |
| 190 | xlnx,include-s2mm-dre = < 0x01 >; |
| 191 | xlnx,mm2s-burst-size = < 0x10 >; |
| 192 | xlnx,prmry-is-aclk-async = < 0x00 >; |
| 193 | xlnx,s2mm-burst-size = < 0x10 >; |
| 194 | xlnx,sg-include-desc-queue = < 0x01 >; |
| 195 | xlnx,sg-include-stscntrl-strm = < 0x01 >; |
| 196 | xlnx,sg-length-width = < 0x10 >; |
| 197 | xlnx,sg-use-stsapp-length = < 0x01 >; |
| 198 | }; |
| 199 | |
| 200 | serial@83e00000 { |
| 201 | clock-frequency = < 0x5f5e100 >; |
| 202 | compatible = "xlnx,axi-uart16550-1.01.a\0xlnx,xps-uart16550-2.00.a\0ns16550a"; |
| 203 | current-speed = < 0x2580 >; |
| 204 | device_type = "serial"; |
| 205 | interrupt-parent = < &intc >; |
| 206 | interrupts = < 0x05 0x02 >; |
| 207 | reg = < 0x83e00000 0x10000 >; |
| 208 | reg-offset = < 0x1000 >; |
| 209 | reg-shift = < 0x02 >; |
| 210 | xlnx,external-xin-clk-hz = < 0x17d7840 >; |
| 211 | xlnx,family = "virtex6"; |
| 212 | xlnx,has-external-rclk = < 0x00 >; |
| 213 | xlnx,has-external-xin = < 0x00 >; |
| 214 | xlnx,is-a-16550 = < 0x01 >; |
| 215 | xlnx,use-modem-ports = < 0x00 >; |
| 216 | xlnx,use-user-ports = < 0x00 >; |
| 217 | }; |
| 218 | |
| 219 | system-timer@83c00000 { |
| 220 | clock-frequency = < 0x5f5e100 >; |
| 221 | compatible = "xlnx,axi-timer-1.01.a\0xlnx,xps-timer-1.00.a"; |
| 222 | interrupt-parent = < &intc >; |
| 223 | interrupts = < 0x02 0x00 >; |
| 224 | reg = < 0x83c00000 0x10000 >; |
| 225 | xlnx,count-width = < 0x20 >; |
| 226 | xlnx,family = "virtex6"; |
| 227 | xlnx,gen0-assert = < 0x01 >; |
| 228 | xlnx,gen1-assert = < 0x01 >; |
| 229 | xlnx,one-timer-only = < 0x00 >; |
| 230 | xlnx,trig0-assert = < 0x01 >; |
| 231 | xlnx,trig1-assert = < 0x01 >; |
| 232 | }; |
| 233 | |
| 234 | intc: interrupt-controller@81800000 { |
| 235 | #interrupt-cells = < 0x02 >; |
| 236 | compatible = "xlnx,axi-intc-1.01.a\0xlnx,xps-intc-1.00.a"; |
| 237 | interrupt-controller; |
| 238 | reg = < 0x81800000 0x10000 >; |
| 239 | xlnx,kind-of-intr = < 0x04 >; |
| 240 | xlnx,num-intr-inputs = < 0x06 >; |
| 241 | }; |
| 242 | |
| 243 | flash@86000000 { |
| 244 | #address-cells = < 0x01 >; |
| 245 | #size-cells = < 0x01 >; |
| 246 | bank-width = < 0x02 >; |
| 247 | compatible = "xlnx,axi-emc-1.01.a\0cfi-flash"; |
| 248 | reg = < 0x86000000 0x2000000 >; |
| 249 | xlnx,axi-clk-period-ps = < 0x2710 >; |
| 250 | xlnx,family = "virtex6"; |
| 251 | xlnx,include-datawidth-matching-0 = < 0x01 >; |
| 252 | xlnx,include-datawidth-matching-1 = < 0x00 >; |
| 253 | xlnx,include-datawidth-matching-2 = < 0x00 >; |
| 254 | xlnx,include-datawidth-matching-3 = < 0x00 >; |
| 255 | xlnx,include-negedge-ioregs = < 0x00 >; |
| 256 | xlnx,max-mem-width = < 0x10 >; |
| 257 | xlnx,mem0-type = < 0x02 >; |
| 258 | xlnx,mem0-width = < 0x10 >; |
| 259 | xlnx,mem1-type = < 0x00 >; |
| 260 | xlnx,mem1-width = < 0x20 >; |
| 261 | xlnx,mem2-type = < 0x00 >; |
| 262 | xlnx,mem2-width = < 0x20 >; |
| 263 | xlnx,mem3-type = < 0x00 >; |
| 264 | xlnx,mem3-width = < 0x20 >; |
| 265 | xlnx,num-banks-mem = < 0x01 >; |
| 266 | xlnx,parity-type-mem-0 = < 0x00 >; |
| 267 | xlnx,parity-type-mem-1 = < 0x00 >; |
| 268 | xlnx,parity-type-mem-2 = < 0x00 >; |
| 269 | xlnx,parity-type-mem-3 = < 0x00 >; |
| 270 | xlnx,s-axi-en-reg = < 0x00 >; |
| 271 | xlnx,s-axi-mem-addr-width = < 0x20 >; |
| 272 | xlnx,s-axi-mem-data-width = < 0x20 >; |
| 273 | xlnx,s-axi-mem-id-width = < 0x01 >; |
| 274 | xlnx,s-axi-mem-protocol = "AXI4LITE"; |
| 275 | xlnx,s-axi-reg-addr-width = < 0x20 >; |
| 276 | xlnx,s-axi-reg-data-width = < 0x20 >; |
| 277 | xlnx,s-axi-reg-protocol = "axi4"; |
| 278 | xlnx,synch-pipedelay-0 = < 0x02 >; |
| 279 | xlnx,synch-pipedelay-1 = < 0x02 >; |
| 280 | xlnx,synch-pipedelay-2 = < 0x02 >; |
| 281 | xlnx,synch-pipedelay-3 = < 0x02 >; |
| 282 | xlnx,tavdv-ps-mem-0 = < 0x1fbd0 >; |
| 283 | xlnx,tavdv-ps-mem-1 = < 0x3a98 >; |
| 284 | xlnx,tavdv-ps-mem-2 = < 0x3a98 >; |
| 285 | xlnx,tavdv-ps-mem-3 = < 0x3a98 >; |
| 286 | xlnx,tcedv-ps-mem-0 = < 0x1fbd0 >; |
| 287 | xlnx,tcedv-ps-mem-1 = < 0x3a98 >; |
| 288 | xlnx,tcedv-ps-mem-2 = < 0x3a98 >; |
| 289 | xlnx,tcedv-ps-mem-3 = < 0x3a98 >; |
| 290 | xlnx,thzce-ps-mem-0 = < 0x88b8 >; |
| 291 | xlnx,thzce-ps-mem-1 = < 0x1b58 >; |
| 292 | xlnx,thzce-ps-mem-2 = < 0x1b58 >; |
| 293 | xlnx,thzce-ps-mem-3 = < 0x1b58 >; |
| 294 | xlnx,thzoe-ps-mem-0 = < 0x1b58 >; |
| 295 | xlnx,thzoe-ps-mem-1 = < 0x1b58 >; |
| 296 | xlnx,thzoe-ps-mem-2 = < 0x1b58 >; |
| 297 | xlnx,thzoe-ps-mem-3 = < 0x1b58 >; |
| 298 | xlnx,tlzwe-ps-mem-0 = < 0x88b8 >; |
| 299 | xlnx,tlzwe-ps-mem-1 = < 0x00 >; |
| 300 | xlnx,tlzwe-ps-mem-2 = < 0x00 >; |
| 301 | xlnx,tlzwe-ps-mem-3 = < 0x00 >; |
| 302 | xlnx,tpacc-ps-flash-0 = < 0x61a8 >; |
| 303 | xlnx,tpacc-ps-flash-1 = < 0x61a8 >; |
| 304 | xlnx,tpacc-ps-flash-2 = < 0x61a8 >; |
| 305 | xlnx,tpacc-ps-flash-3 = < 0x61a8 >; |
| 306 | xlnx,twc-ps-mem-0 = < 0x32c8 >; |
| 307 | xlnx,twc-ps-mem-1 = < 0x3a98 >; |
| 308 | xlnx,twc-ps-mem-2 = < 0x3a98 >; |
| 309 | xlnx,twc-ps-mem-3 = < 0x3a98 >; |
| 310 | xlnx,twp-ps-mem-0 = < 0x11170 >; |
| 311 | xlnx,twp-ps-mem-1 = < 0x2ee0 >; |
| 312 | xlnx,twp-ps-mem-2 = < 0x2ee0 >; |
| 313 | xlnx,twp-ps-mem-3 = < 0x2ee0 >; |
| 314 | xlnx,twph-ps-mem-0 = < 0x2ee0 >; |
| 315 | xlnx,twph-ps-mem-1 = < 0x2ee0 >; |
| 316 | xlnx,twph-ps-mem-2 = < 0x2ee0 >; |
| 317 | xlnx,twph-ps-mem-3 = < 0x2ee0 >; |
| 318 | |
| 319 | partition@0 { |
| 320 | label = "fpga"; |
| 321 | reg = < 0x00 0x100000 >; |
| 322 | }; |
| 323 | |
| 324 | partition@100000 { |
| 325 | label = "boot"; |
| 326 | reg = < 0x100000 0x40000 >; |
| 327 | }; |
| 328 | |
| 329 | partition@140000 { |
| 330 | label = "bootenv"; |
| 331 | reg = < 0x140000 0x20000 >; |
| 332 | }; |
| 333 | |
| 334 | partition@160000 { |
| 335 | label = "config"; |
| 336 | reg = < 0x160000 0x20000 >; |
| 337 | }; |
| 338 | |
| 339 | partition@180000 { |
| 340 | label = "image"; |
| 341 | reg = < 0x180000 0xa00000 >; |
| 342 | }; |
| 343 | |
| 344 | partition@b80000 { |
| 345 | label = "spare"; |
| 346 | reg = < 0xb80000 0x00 >; |
| 347 | }; |
| 348 | }; |
| 349 | }; |
| 350 | }; |