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Huacai Chenedf79e62010-06-29 10:49:29 +08001/*
2 * VT82C686B south bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
Paolo Bonzini6b620ca2012-01-13 17:44:23 +01008 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
Huacai Chenedf79e62010-06-29 10:49:29 +080011 */
12
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010013#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010014#include "hw/i386/pc.h"
15#include "hw/isa/vt82c686.h"
16#include "hw/i2c/i2c.h"
17#include "hw/i2c/smbus.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010018#include "hw/pci/pci.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010019#include "hw/isa/isa.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010020#include "hw/sysbus.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010021#include "hw/mips/mips.h"
22#include "hw/isa/apm.h"
23#include "hw/acpi/acpi.h"
24#include "hw/i2c/pm_smbus.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010025#include "sysemu/sysemu.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010026#include "qemu/timer.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010027#include "exec/address-spaces.h"
Huacai Chenedf79e62010-06-29 10:49:29 +080028
Huacai Chenedf79e62010-06-29 10:49:29 +080029//#define DEBUG_VT82C686B
30
31#ifdef DEBUG_VT82C686B
32#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
33#else
34#define DPRINTF(fmt, ...)
35#endif
36
37typedef struct SuperIOConfig
38{
39 uint8_t config[0xff];
40 uint8_t index;
41 uint8_t data;
42} SuperIOConfig;
43
44typedef struct VT82C686BState {
45 PCIDevice dev;
Jan Kiszkabcc37e22013-06-22 08:06:59 +020046 MemoryRegion superio;
Huacai Chenedf79e62010-06-29 10:49:29 +080047 SuperIOConfig superio_conf;
48} VT82C686BState;
49
Jan Kiszkabcc37e22013-06-22 08:06:59 +020050static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
51 unsigned size)
Huacai Chenedf79e62010-06-29 10:49:29 +080052{
53 int can_write;
54 SuperIOConfig *superio_conf = opaque;
55
Stefan Weilb2bedb22011-09-12 22:33:01 +020056 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
Huacai Chenedf79e62010-06-29 10:49:29 +080057 if (addr == 0x3f0) {
58 superio_conf->index = data & 0xff;
59 } else {
60 /* 0x3f1 */
61 switch (superio_conf->index) {
62 case 0x00 ... 0xdf:
63 case 0xe4:
64 case 0xe5:
65 case 0xe9 ... 0xed:
66 case 0xf3:
67 case 0xf5:
68 case 0xf7:
69 case 0xf9 ... 0xfb:
70 case 0xfd ... 0xff:
71 can_write = 0;
72 break;
73 default:
74 can_write = 1;
75
76 if (can_write) {
77 switch (superio_conf->index) {
78 case 0xe7:
79 if ((data & 0xff) != 0xfe) {
Stefan Weilb2bedb22011-09-12 22:33:01 +020080 DPRINTF("chage uart 1 base. unsupported yet\n");
Huacai Chenedf79e62010-06-29 10:49:29 +080081 }
82 break;
83 case 0xe8:
84 if ((data & 0xff) != 0xbe) {
Stefan Weilb2bedb22011-09-12 22:33:01 +020085 DPRINTF("chage uart 2 base. unsupported yet\n");
Huacai Chenedf79e62010-06-29 10:49:29 +080086 }
87 break;
88
89 default:
90 superio_conf->config[superio_conf->index] = data & 0xff;
91 }
92 }
93 }
94 superio_conf->config[superio_conf->index] = data & 0xff;
95 }
96}
97
Jan Kiszkabcc37e22013-06-22 08:06:59 +020098static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
Huacai Chenedf79e62010-06-29 10:49:29 +080099{
100 SuperIOConfig *superio_conf = opaque;
101
Stefan Weilb2bedb22011-09-12 22:33:01 +0200102 DPRINTF("superio_ioport_readb address 0x%x\n", addr);
Huacai Chenedf79e62010-06-29 10:49:29 +0800103 return (superio_conf->config[superio_conf->index]);
104}
105
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200106static const MemoryRegionOps superio_ops = {
107 .read = superio_ioport_readb,
108 .write = superio_ioport_writeb,
109 .endianness = DEVICE_NATIVE_ENDIAN,
110 .impl = {
111 .min_access_size = 1,
112 .max_access_size = 1,
113 },
114};
115
Huacai Chenedf79e62010-06-29 10:49:29 +0800116static void vt82c686b_reset(void * opaque)
117{
118 PCIDevice *d = opaque;
119 uint8_t *pci_conf = d->config;
120 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
121
122 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
123 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
124 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
125 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
126
127 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
128 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
129 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
130 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
131 pci_conf[0x59] = 0x04;
132 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
133 pci_conf[0x5f] = 0x04;
134 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
135
136 vt82c->superio_conf.config[0xe0] = 0x3c;
137 vt82c->superio_conf.config[0xe2] = 0x03;
138 vt82c->superio_conf.config[0xe3] = 0xfc;
139 vt82c->superio_conf.config[0xe6] = 0xde;
140 vt82c->superio_conf.config[0xe7] = 0xfe;
141 vt82c->superio_conf.config[0xe8] = 0xbe;
142}
143
144/* write config pci function0 registers. PCI-ISA bridge */
145static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
146 uint32_t val, int len)
147{
148 VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
149
Stefan Weilb2bedb22011-09-12 22:33:01 +0200150 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
Huacai Chenedf79e62010-06-29 10:49:29 +0800151 address, val, len);
152
153 pci_default_write_config(d, address, val, len);
154 if (address == 0x85) { /* enable or disable super IO configure */
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200155 memory_region_set_enabled(&vt686->superio, val & 0x2);
Huacai Chenedf79e62010-06-29 10:49:29 +0800156 }
157}
158
159#define ACPI_DBG_IO_ADDR 0xb044
160
161typedef struct VT686PMState {
162 PCIDevice dev;
Gerd Hoffmanna2902822012-11-23 08:29:27 +0100163 MemoryRegion io;
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100164 ACPIREGS ar;
Huacai Chenedf79e62010-06-29 10:49:29 +0800165 APMState apm;
Huacai Chenedf79e62010-06-29 10:49:29 +0800166 PMSMBus smb;
167 uint32_t smb_io_base;
168} VT686PMState;
169
170typedef struct VT686AC97State {
171 PCIDevice dev;
172} VT686AC97State;
173
174typedef struct VT686MC97State {
175 PCIDevice dev;
176} VT686MC97State;
177
Huacai Chenedf79e62010-06-29 10:49:29 +0800178static void pm_update_sci(VT686PMState *s)
179{
180 int sci_level, pmsts;
Huacai Chenedf79e62010-06-29 10:49:29 +0800181
Gerd Hoffmann2886be12012-02-23 13:45:17 +0100182 pmsts = acpi_pm1_evt_get_sts(&s->ar);
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100183 sci_level = (((pmsts & s->ar.pm1.evt.en) &
Isaku Yamahata04dc3082011-03-25 19:54:39 +0900184 (ACPI_BITMASK_RT_CLOCK_ENABLE |
185 ACPI_BITMASK_POWER_BUTTON_ENABLE |
186 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
187 ACPI_BITMASK_TIMER_ENABLE)) != 0);
Huacai Chenedf79e62010-06-29 10:49:29 +0800188 qemu_set_irq(s->dev.irq[0], sci_level);
189 /* schedule a timer interruption if needed */
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100190 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
Isaku Yamahataa54d41a2011-03-25 19:54:38 +0900191 !(pmsts & ACPI_BITMASK_TIMER_STATUS));
Huacai Chenedf79e62010-06-29 10:49:29 +0800192}
193
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100194static void pm_tmr_timer(ACPIREGS *ar)
Huacai Chenedf79e62010-06-29 10:49:29 +0800195{
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100196 VT686PMState *s = container_of(ar, VT686PMState, ar);
Huacai Chenedf79e62010-06-29 10:49:29 +0800197 pm_update_sci(s);
198}
199
Huacai Chenedf79e62010-06-29 10:49:29 +0800200static void pm_io_space_update(VT686PMState *s)
201{
202 uint32_t pm_io_base;
203
Gerd Hoffmanna2902822012-11-23 08:29:27 +0100204 pm_io_base = pci_get_long(s->dev.config + 0x40);
205 pm_io_base &= 0xffc0;
Huacai Chenedf79e62010-06-29 10:49:29 +0800206
Gerd Hoffmanna2902822012-11-23 08:29:27 +0100207 memory_region_transaction_begin();
208 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
209 memory_region_set_address(&s->io, pm_io_base);
210 memory_region_transaction_commit();
Huacai Chenedf79e62010-06-29 10:49:29 +0800211}
212
213static void pm_write_config(PCIDevice *d,
214 uint32_t address, uint32_t val, int len)
215{
Stefan Weilb2bedb22011-09-12 22:33:01 +0200216 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
Huacai Chenedf79e62010-06-29 10:49:29 +0800217 address, val, len);
218 pci_default_write_config(d, address, val, len);
219}
220
221static int vmstate_acpi_post_load(void *opaque, int version_id)
222{
223 VT686PMState *s = opaque;
224
225 pm_io_space_update(s);
226 return 0;
227}
228
229static const VMStateDescription vmstate_acpi = {
230 .name = "vt82c686b_pm",
231 .version_id = 1,
232 .minimum_version_id = 1,
233 .minimum_version_id_old = 1,
234 .post_load = vmstate_acpi_post_load,
235 .fields = (VMStateField []) {
236 VMSTATE_PCI_DEVICE(dev, VT686PMState),
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100237 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
238 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
239 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
Huacai Chenedf79e62010-06-29 10:49:29 +0800240 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
Gerd Hoffmann355bf2e2012-02-23 13:45:16 +0100241 VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
242 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
Huacai Chenedf79e62010-06-29 10:49:29 +0800243 VMSTATE_END_OF_LIST()
244 }
245};
246
247/*
248 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
249 * just register a PCI device now, functionalities will be implemented later.
250 */
251
252static int vt82c686b_ac97_initfn(PCIDevice *dev)
253{
254 VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
255 uint8_t *pci_conf = s->dev.config;
256
Huacai Chenedf79e62010-06-29 10:49:29 +0800257 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
258 PCI_COMMAND_PARITY);
259 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
260 PCI_STATUS_DEVSEL_MEDIUM);
261 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
262
263 return 0;
264}
265
266void vt82c686b_ac97_init(PCIBus *bus, int devfn)
267{
268 PCIDevice *dev;
269
270 dev = pci_create(bus, devfn, "VT82C686B_AC97");
271 qdev_init_nofail(&dev->qdev);
272}
273
Anthony Liguori40021f02011-12-04 12:22:06 -0600274static void via_ac97_class_init(ObjectClass *klass, void *data)
275{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600276 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
278
279 k->init = vt82c686b_ac97_initfn;
280 k->vendor_id = PCI_VENDOR_ID_VIA;
281 k->device_id = PCI_DEVICE_ID_VIA_AC97;
282 k->revision = 0x50;
283 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600284 dc->desc = "AC97";
Anthony Liguori40021f02011-12-04 12:22:06 -0600285}
286
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100287static const TypeInfo via_ac97_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600288 .name = "VT82C686B_AC97",
289 .parent = TYPE_PCI_DEVICE,
290 .instance_size = sizeof(VT686AC97State),
291 .class_init = via_ac97_class_init,
Huacai Chenedf79e62010-06-29 10:49:29 +0800292};
293
Huacai Chenedf79e62010-06-29 10:49:29 +0800294static int vt82c686b_mc97_initfn(PCIDevice *dev)
295{
296 VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
297 uint8_t *pci_conf = s->dev.config;
298
Huacai Chenedf79e62010-06-29 10:49:29 +0800299 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
300 PCI_COMMAND_VGA_PALETTE);
301 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
302 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
303
304 return 0;
305}
306
307void vt82c686b_mc97_init(PCIBus *bus, int devfn)
308{
309 PCIDevice *dev;
310
311 dev = pci_create(bus, devfn, "VT82C686B_MC97");
312 qdev_init_nofail(&dev->qdev);
313}
314
Anthony Liguori40021f02011-12-04 12:22:06 -0600315static void via_mc97_class_init(ObjectClass *klass, void *data)
316{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600317 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600318 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
319
320 k->init = vt82c686b_mc97_initfn;
321 k->vendor_id = PCI_VENDOR_ID_VIA;
322 k->device_id = PCI_DEVICE_ID_VIA_MC97;
323 k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
324 k->revision = 0x30;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600325 dc->desc = "MC97";
Anthony Liguori40021f02011-12-04 12:22:06 -0600326}
327
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100328static const TypeInfo via_mc97_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600329 .name = "VT82C686B_MC97",
330 .parent = TYPE_PCI_DEVICE,
331 .instance_size = sizeof(VT686MC97State),
332 .class_init = via_mc97_class_init,
Huacai Chenedf79e62010-06-29 10:49:29 +0800333};
334
Huacai Chenedf79e62010-06-29 10:49:29 +0800335/* vt82c686 pm init */
336static int vt82c686b_pm_initfn(PCIDevice *dev)
337{
338 VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
339 uint8_t *pci_conf;
340
341 pci_conf = s->dev.config;
Huacai Chenedf79e62010-06-29 10:49:29 +0800342 pci_set_word(pci_conf + PCI_COMMAND, 0);
343 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
344 PCI_STATUS_DEVSEL_MEDIUM);
345
346 /* 0x48-0x4B is Power Management I/O Base */
347 pci_set_long(pci_conf + 0x48, 0x00000001);
348
349 /* SMB ports:0xeee0~0xeeef */
350 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
351 pci_conf[0x90] = s->smb_io_base | 1;
352 pci_conf[0x91] = s->smb_io_base >> 8;
353 pci_conf[0xd2] = 0x90;
Gerd Hoffmann798512e2012-11-23 14:57:01 +0100354 pm_smbus_init(&s->dev.qdev, &s->smb);
355 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
Huacai Chenedf79e62010-06-29 10:49:29 +0800356
Julien Grall42d8a3c2012-09-19 12:50:03 +0100357 apm_init(dev, &s->apm, NULL, s);
Huacai Chenedf79e62010-06-29 10:49:29 +0800358
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400359 memory_region_init(&s->io, NULL, "vt82c686-pm", 64);
Gerd Hoffmanna2902822012-11-23 08:29:27 +0100360 memory_region_set_enabled(&s->io, false);
361 memory_region_add_subregion(get_system_io(), 0, &s->io);
Huacai Chenedf79e62010-06-29 10:49:29 +0800362
Gerd Hoffmann77d58b12012-11-22 12:12:30 +0100363 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
Gerd Hoffmannb5a7c022012-11-22 13:25:10 +0100364 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
Bruce Rogers560e6392013-04-02 12:41:40 -0600365 acpi_pm1_cnt_init(&s->ar, &s->io, 2);
Huacai Chenedf79e62010-06-29 10:49:29 +0800366
367 return 0;
368}
369
370i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
371 qemu_irq sci_irq)
372{
373 PCIDevice *dev;
374 VT686PMState *s;
375
376 dev = pci_create(bus, devfn, "VT82C686B_PM");
377 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
378
379 s = DO_UPCAST(VT686PMState, dev, dev);
380
381 qdev_init_nofail(&dev->qdev);
382
383 return s->smb.smbus;
384}
385
Anthony Liguori40021f02011-12-04 12:22:06 -0600386static Property via_pm_properties[] = {
387 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
388 DEFINE_PROP_END_OF_LIST(),
389};
390
391static void via_pm_class_init(ObjectClass *klass, void *data)
392{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600393 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600394 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
395
396 k->init = vt82c686b_pm_initfn;
397 k->config_write = pm_write_config;
398 k->vendor_id = PCI_VENDOR_ID_VIA;
399 k->device_id = PCI_DEVICE_ID_VIA_ACPI;
400 k->class_id = PCI_CLASS_BRIDGE_OTHER;
401 k->revision = 0x40;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600402 dc->desc = "PM";
403 dc->vmsd = &vmstate_acpi;
404 dc->props = via_pm_properties;
Anthony Liguori40021f02011-12-04 12:22:06 -0600405}
406
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100407static const TypeInfo via_pm_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600408 .name = "VT82C686B_PM",
409 .parent = TYPE_PCI_DEVICE,
410 .instance_size = sizeof(VT686PMState),
411 .class_init = via_pm_class_init,
Huacai Chenedf79e62010-06-29 10:49:29 +0800412};
413
Huacai Chenedf79e62010-06-29 10:49:29 +0800414static const VMStateDescription vmstate_via = {
415 .name = "vt82c686b",
416 .version_id = 1,
417 .minimum_version_id = 1,
418 .minimum_version_id_old = 1,
419 .fields = (VMStateField []) {
420 VMSTATE_PCI_DEVICE(dev, VT82C686BState),
421 VMSTATE_END_OF_LIST()
422 }
423};
424
425/* init the PCI-to-ISA bridge */
426static int vt82c686b_initfn(PCIDevice *d)
427{
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200428 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
Huacai Chenedf79e62010-06-29 10:49:29 +0800429 uint8_t *pci_conf;
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200430 ISABus *isa_bus;
Huacai Chenedf79e62010-06-29 10:49:29 +0800431 uint8_t *wmask;
432 int i;
433
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200434 isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d));
Huacai Chenedf79e62010-06-29 10:49:29 +0800435
436 pci_conf = d->config;
Huacai Chenedf79e62010-06-29 10:49:29 +0800437 pci_config_set_prog_interface(pci_conf, 0x0);
Huacai Chenedf79e62010-06-29 10:49:29 +0800438
439 wmask = d->wmask;
440 for (i = 0x00; i < 0xff; i++) {
441 if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
442 wmask[i] = 0x00;
443 }
444 }
445
Paolo Bonzini2c9b15c2013-06-06 05:41:28 -0400446 memory_region_init_io(&vt82c->superio, NULL, &superio_ops,
447 &vt82c->superio_conf, "superio", 2);
Jan Kiszkabcc37e22013-06-22 08:06:59 +0200448 memory_region_set_enabled(&vt82c->superio, false);
449 /* The floppy also uses 0x3f0 and 0x3f1.
450 * But we do not emulate a floppy, so just set it here. */
451 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
452 &vt82c->superio);
453
Huacai Chenedf79e62010-06-29 10:49:29 +0800454 qemu_register_reset(vt82c686b_reset, d);
455
456 return 0;
457}
458
Hervé Poussineauc9940ed2011-12-15 22:09:57 +0100459ISABus *vt82c686b_init(PCIBus *bus, int devfn)
Huacai Chenedf79e62010-06-29 10:49:29 +0800460{
461 PCIDevice *d;
462
Isaku Yamahataaa5fb7b2010-07-12 20:53:57 +0900463 d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
Huacai Chenedf79e62010-06-29 10:49:29 +0800464
Andreas Färber2ae0e482013-06-07 14:11:07 +0200465 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
Huacai Chenedf79e62010-06-29 10:49:29 +0800466}
467
Anthony Liguori40021f02011-12-04 12:22:06 -0600468static void via_class_init(ObjectClass *klass, void *data)
469{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600470 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -0600471 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
472
473 k->init = vt82c686b_initfn;
474 k->config_write = vt82c686b_write_config;
475 k->vendor_id = PCI_VENDOR_ID_VIA;
476 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
477 k->class_id = PCI_CLASS_BRIDGE_ISA;
478 k->revision = 0x40;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600479 dc->desc = "ISA bridge";
480 dc->no_user = 1;
481 dc->vmsd = &vmstate_via;
Anthony Liguori40021f02011-12-04 12:22:06 -0600482}
483
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100484static const TypeInfo via_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600485 .name = "VT82C686B",
486 .parent = TYPE_PCI_DEVICE,
487 .instance_size = sizeof(VT82C686BState),
488 .class_init = via_class_init,
Huacai Chenedf79e62010-06-29 10:49:29 +0800489};
490
Andreas Färber83f7d432012-02-09 15:20:55 +0100491static void vt82c686b_register_types(void)
Huacai Chenedf79e62010-06-29 10:49:29 +0800492{
Andreas Färber83f7d432012-02-09 15:20:55 +0100493 type_register_static(&via_ac97_info);
494 type_register_static(&via_mc97_info);
495 type_register_static(&via_pm_info);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600496 type_register_static(&via_info);
Huacai Chenedf79e62010-06-29 10:49:29 +0800497}
Andreas Färber83f7d432012-02-09 15:20:55 +0100498
499type_init(vt82c686b_register_types)