Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU model of the LatticeMico32 timer block. |
| 3 | * |
| 4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | * |
| 19 | * |
| 20 | * Specification available at: |
| 21 | * http://www.latticesemi.com/documents/mico32timer.pdf |
| 22 | */ |
| 23 | |
Peter Maydell | ea99dde | 2016-01-26 18:16:57 +0000 | [diff] [blame] | 24 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 25 | #include "hw/hw.h" |
| 26 | #include "hw/sysbus.h" |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 27 | #include "trace.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 28 | #include "qemu/timer.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 29 | #include "hw/ptimer.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 30 | #include "qemu/error-report.h" |
Alex Bligh | 6a1751b | 2013-08-21 16:02:47 +0100 | [diff] [blame] | 31 | #include "qemu/main-loop.h" |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 32 | |
| 33 | #define DEFAULT_FREQUENCY (50*1000000) |
| 34 | |
| 35 | enum { |
| 36 | R_SR = 0, |
| 37 | R_CR, |
| 38 | R_PERIOD, |
| 39 | R_SNAPSHOT, |
| 40 | R_MAX |
| 41 | }; |
| 42 | |
| 43 | enum { |
| 44 | SR_TO = (1 << 0), |
| 45 | SR_RUN = (1 << 1), |
| 46 | }; |
| 47 | |
| 48 | enum { |
| 49 | CR_ITO = (1 << 0), |
| 50 | CR_CONT = (1 << 1), |
| 51 | CR_START = (1 << 2), |
| 52 | CR_STOP = (1 << 3), |
| 53 | }; |
| 54 | |
Andreas Färber | fe54d85 | 2013-07-27 14:54:54 +0200 | [diff] [blame] | 55 | #define TYPE_LM32_TIMER "lm32-timer" |
| 56 | #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER) |
| 57 | |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 58 | struct LM32TimerState { |
Andreas Färber | fe54d85 | 2013-07-27 14:54:54 +0200 | [diff] [blame] | 59 | SysBusDevice parent_obj; |
| 60 | |
Avi Kivity | d09510b | 2011-11-20 11:44:25 +0200 | [diff] [blame] | 61 | MemoryRegion iomem; |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 62 | |
| 63 | QEMUBH *bh; |
| 64 | ptimer_state *ptimer; |
| 65 | |
| 66 | qemu_irq irq; |
| 67 | uint32_t freq_hz; |
| 68 | |
| 69 | uint32_t regs[R_MAX]; |
| 70 | }; |
| 71 | typedef struct LM32TimerState LM32TimerState; |
| 72 | |
| 73 | static void timer_update_irq(LM32TimerState *s) |
| 74 | { |
| 75 | int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); |
| 76 | |
| 77 | trace_lm32_timer_irq_state(state); |
| 78 | qemu_set_irq(s->irq, state); |
| 79 | } |
| 80 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 81 | static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size) |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 82 | { |
| 83 | LM32TimerState *s = opaque; |
| 84 | uint32_t r = 0; |
| 85 | |
| 86 | addr >>= 2; |
| 87 | switch (addr) { |
| 88 | case R_SR: |
| 89 | case R_CR: |
| 90 | case R_PERIOD: |
| 91 | r = s->regs[addr]; |
| 92 | break; |
| 93 | case R_SNAPSHOT: |
| 94 | r = (uint32_t)ptimer_get_count(s->ptimer); |
| 95 | break; |
| 96 | default: |
Markus Armbruster | dd3d677 | 2011-06-22 14:03:56 +0200 | [diff] [blame] | 97 | error_report("lm32_timer: read access to unknown register 0x" |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 98 | TARGET_FMT_plx, addr << 2); |
| 99 | break; |
| 100 | } |
| 101 | |
| 102 | trace_lm32_timer_memory_read(addr << 2, r); |
| 103 | return r; |
| 104 | } |
| 105 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 106 | static void timer_write(void *opaque, hwaddr addr, |
Avi Kivity | d09510b | 2011-11-20 11:44:25 +0200 | [diff] [blame] | 107 | uint64_t value, unsigned size) |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 108 | { |
| 109 | LM32TimerState *s = opaque; |
| 110 | |
| 111 | trace_lm32_timer_memory_write(addr, value); |
| 112 | |
| 113 | addr >>= 2; |
| 114 | switch (addr) { |
| 115 | case R_SR: |
| 116 | s->regs[R_SR] &= ~SR_TO; |
| 117 | break; |
| 118 | case R_CR: |
| 119 | s->regs[R_CR] = value; |
| 120 | if (s->regs[R_CR] & CR_START) { |
| 121 | ptimer_run(s->ptimer, 1); |
| 122 | } |
| 123 | if (s->regs[R_CR] & CR_STOP) { |
| 124 | ptimer_stop(s->ptimer); |
| 125 | } |
| 126 | break; |
| 127 | case R_PERIOD: |
| 128 | s->regs[R_PERIOD] = value; |
| 129 | ptimer_set_count(s->ptimer, value); |
| 130 | break; |
| 131 | case R_SNAPSHOT: |
| 132 | error_report("lm32_timer: write access to read only register 0x" |
| 133 | TARGET_FMT_plx, addr << 2); |
| 134 | break; |
| 135 | default: |
Markus Armbruster | dd3d677 | 2011-06-22 14:03:56 +0200 | [diff] [blame] | 136 | error_report("lm32_timer: write access to unknown register 0x" |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 137 | TARGET_FMT_plx, addr << 2); |
| 138 | break; |
| 139 | } |
| 140 | timer_update_irq(s); |
| 141 | } |
| 142 | |
Avi Kivity | d09510b | 2011-11-20 11:44:25 +0200 | [diff] [blame] | 143 | static const MemoryRegionOps timer_ops = { |
| 144 | .read = timer_read, |
| 145 | .write = timer_write, |
| 146 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 147 | .valid = { |
| 148 | .min_access_size = 4, |
| 149 | .max_access_size = 4, |
| 150 | }, |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | static void timer_hit(void *opaque) |
| 154 | { |
| 155 | LM32TimerState *s = opaque; |
| 156 | |
| 157 | trace_lm32_timer_hit(); |
| 158 | |
| 159 | s->regs[R_SR] |= SR_TO; |
| 160 | |
| 161 | if (s->regs[R_CR] & CR_CONT) { |
| 162 | ptimer_set_count(s->ptimer, s->regs[R_PERIOD]); |
| 163 | ptimer_run(s->ptimer, 1); |
| 164 | } |
| 165 | timer_update_irq(s); |
| 166 | } |
| 167 | |
| 168 | static void timer_reset(DeviceState *d) |
| 169 | { |
Andreas Färber | fe54d85 | 2013-07-27 14:54:54 +0200 | [diff] [blame] | 170 | LM32TimerState *s = LM32_TIMER(d); |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 171 | int i; |
| 172 | |
| 173 | for (i = 0; i < R_MAX; i++) { |
| 174 | s->regs[i] = 0; |
| 175 | } |
| 176 | ptimer_stop(s->ptimer); |
| 177 | } |
| 178 | |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 179 | static void lm32_timer_init(Object *obj) |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 180 | { |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 181 | LM32TimerState *s = LM32_TIMER(obj); |
| 182 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 183 | |
| 184 | sysbus_init_irq(dev, &s->irq); |
| 185 | |
| 186 | s->bh = qemu_bh_new(timer_hit, s); |
Dmitry Osipenko | e7ea81c | 2016-09-22 18:13:06 +0100 | [diff] [blame] | 187 | s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT); |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 188 | |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 189 | memory_region_init_io(&s->iomem, obj, &timer_ops, s, |
Paolo Bonzini | 853dca1 | 2013-06-06 21:25:08 -0400 | [diff] [blame] | 190 | "timer", R_MAX * 4); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 191 | sysbus_init_mmio(dev, &s->iomem); |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 192 | } |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 193 | |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 194 | static void lm32_timer_realize(DeviceState *dev, Error **errp) |
| 195 | { |
| 196 | LM32TimerState *s = LM32_TIMER(dev); |
| 197 | |
| 198 | ptimer_set_freq(s->ptimer, s->freq_hz); |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | static const VMStateDescription vmstate_lm32_timer = { |
| 202 | .name = "lm32-timer", |
| 203 | .version_id = 1, |
| 204 | .minimum_version_id = 1, |
Juan Quintela | 35d0845 | 2014-04-16 16:01:33 +0200 | [diff] [blame] | 205 | .fields = (VMStateField[]) { |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 206 | VMSTATE_PTIMER(ptimer, LM32TimerState), |
| 207 | VMSTATE_UINT32(freq_hz, LM32TimerState), |
| 208 | VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX), |
| 209 | VMSTATE_END_OF_LIST() |
| 210 | } |
| 211 | }; |
| 212 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 213 | static Property lm32_timer_properties[] = { |
| 214 | DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY), |
| 215 | DEFINE_PROP_END_OF_LIST(), |
| 216 | }; |
| 217 | |
| 218 | static void lm32_timer_class_init(ObjectClass *klass, void *data) |
| 219 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 220 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 221 | |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 222 | dc->realize = lm32_timer_realize; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 223 | dc->reset = timer_reset; |
| 224 | dc->vmsd = &vmstate_lm32_timer; |
| 225 | dc->props = lm32_timer_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 226 | } |
| 227 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 228 | static const TypeInfo lm32_timer_info = { |
Andreas Färber | fe54d85 | 2013-07-27 14:54:54 +0200 | [diff] [blame] | 229 | .name = TYPE_LM32_TIMER, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 230 | .parent = TYPE_SYS_BUS_DEVICE, |
| 231 | .instance_size = sizeof(LM32TimerState), |
xiaoqiang zhao | a18eac5 | 2016-02-22 11:15:27 +0800 | [diff] [blame] | 232 | .instance_init = lm32_timer_init, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 233 | .class_init = lm32_timer_class_init, |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 234 | }; |
| 235 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 236 | static void lm32_timer_register_types(void) |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 237 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 238 | type_register_static(&lm32_timer_info); |
Michael Walle | ea7924d | 2011-02-17 23:45:10 +0100 | [diff] [blame] | 239 | } |
| 240 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 241 | type_init(lm32_timer_register_types) |