Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 1 | # AArch64 SVE instruction descriptions |
| 2 | # |
| 3 | # Copyright (c) 2017 Linaro, Ltd |
| 4 | # |
| 5 | # This library is free software; you can redistribute it and/or |
| 6 | # modify it under the terms of the GNU Lesser General Public |
| 7 | # License as published by the Free Software Foundation; either |
Chetan Pant | 50f57e0 | 2020-10-23 12:29:13 +0000 | [diff] [blame] | 8 | # version 2.1 of the License, or (at your option) any later version. |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 9 | # |
| 10 | # This library is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | # Lesser General Public License for more details. |
| 14 | # |
| 15 | # You should have received a copy of the GNU Lesser General Public |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 17 | |
| 18 | # |
| 19 | # This file is processed by scripts/decodetree.py |
| 20 | # |
| 21 | |
| 22 | ########################################################################### |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 23 | # Named fields. These are primarily for disjoint fields. |
| 24 | |
Richard Henderson | f25a236 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 25 | %imm4_16_p1 16:4 !function=plus1 |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 26 | %imm6_22_5 22:1 5:5 |
Richard Henderson | 30562ab | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 27 | %imm7_22_16 22:2 16:5 |
Richard Henderson | b94f8f6 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 28 | %imm8_16_10 16:5 10:3 |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 29 | %imm9_16_10 16:s6 10:3 |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 30 | %size_23 23:2 |
Richard Henderson | 6845986 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 31 | %dtype_23_13 23:2 13:2 |
Richard Henderson | ca40a6e | 2018-06-29 15:11:08 +0100 | [diff] [blame] | 32 | %index3_22_19 22:1 19:2 |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 33 | |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 34 | # A combination of tsz:imm3 -- extract esize. |
| 35 | %tszimm_esz 22:2 5:5 !function=tszimm_esz |
| 36 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) |
| 37 | %tszimm_shr 22:2 5:5 !function=tszimm_shr |
| 38 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize |
| 39 | %tszimm_shl 22:2 5:5 !function=tszimm_shl |
| 40 | |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 41 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
| 42 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz |
| 43 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr |
| 44 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl |
| 45 | |
Richard Henderson | f25a236 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 46 | # Signed 8-bit immediate, optionally shifted left by 8. |
| 47 | %sh8_i8s 5:9 !function=expand_imm_sh8s |
Richard Henderson | 6e6a157 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 48 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
| 49 | %sh8_i8u 5:9 !function=expand_imm_sh8u |
Richard Henderson | f25a236 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 50 | |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 51 | # Unsigned load of msz into esz=2, represented as a dtype. |
| 52 | %msz_dtype 23:2 !function=msz_dtype |
| 53 | |
Richard Henderson | f97cfd5 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 54 | # Either a copy of rd (at bit 0), or a different source |
| 55 | # as propagated via the MOVPRFX instruction. |
| 56 | %reg_movprfx 0:5 |
| 57 | |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 58 | ########################################################################### |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 59 | # Named attribute sets. These are used to make nice(er) names |
| 60 | # when creating helpers common to those for the individual |
| 61 | # instruction patterns. |
| 62 | |
Richard Henderson | 028e2a7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 63 | &rr_esz rd rn esz |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 64 | &rri rd rn imm |
Richard Henderson | e1fa116 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 65 | &rr_dbm rd rn dbm |
Richard Henderson | 4b242d9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 66 | &rrri rd rn rm imm |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 67 | &rri_esz rd rn imm esz |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 68 | &rrr_esz rd rn rm esz |
Richard Henderson | 047cec9 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 69 | &rpr_esz rd pg rn esz |
Richard Henderson | 35da316 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 70 | &rpr_s rd pg rn s |
Richard Henderson | 516e246 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 71 | &rprr_s rd pg rn rm s |
Richard Henderson | f97cfd5 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 72 | &rprr_esz rd pg rn rm esz |
Richard Henderson | 96a36e4 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 73 | &rprrr_esz rd pg rn rm ra esz |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 74 | &rpri_esz rd pg rn imm esz |
Richard Henderson | 24e82e6 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 75 | &ptrue rd esz pat s |
| 76 | &incdec_cnt rd pat esz imm d u |
| 77 | &incdec2_cnt rd rn pat esz imm d u |
Richard Henderson | 9ee3a61 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 78 | &incdec_pred rd pg esz d u |
| 79 | &incdec2_pred rd rn pg esz d u |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 80 | &rprr_load rd pg rn rm dtype nreg |
| 81 | &rpri_load rd pg rn imm dtype nreg |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 82 | &rprr_store rd pg rn rm msz esz nreg |
| 83 | &rpri_store rd pg rn imm msz esz nreg |
Richard Henderson | 673e9fa | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 84 | &rprr_gather_load rd pg rn rm esz msz u ff xs scale |
| 85 | &rpri_gather_load rd pg rn imm esz msz u ff |
Richard Henderson | f6dbf62 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 86 | &rprr_scatter_store rd pg rn rm esz msz xs scale |
Richard Henderson | 408ecde | 2018-06-29 15:11:07 +0100 | [diff] [blame] | 87 | &rpri_scatter_store rd pg rn imm esz msz |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 88 | |
| 89 | ########################################################################### |
| 90 | # Named instruction formats. These are generally used to |
| 91 | # reduce the amount of duplication between instruction patterns. |
| 92 | |
Richard Henderson | 028e2a7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 93 | # Two operand with unused vector element size |
| 94 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 |
| 95 | |
| 96 | # Two operand |
| 97 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz |
Richard Henderson | 0762cd4 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 98 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
Richard Henderson | 028e2a7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 99 | |
Richard Henderson | 35da316 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 100 | # Two operand with governing predicate, flags setting |
| 101 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s |
Richard Henderson | 407e6ce | 2019-01-07 15:23:45 +0000 | [diff] [blame] | 102 | @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 |
Richard Henderson | 35da316 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 103 | |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 104 | # Three operand with unused vector element size |
| 105 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 |
| 106 | |
Richard Henderson | 516e246 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 107 | # Three predicate operand, with governing predicate, flag setting |
| 108 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s |
| 109 | |
Richard Henderson | fea98f9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 110 | # Three operand, vector element size |
| 111 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz |
Richard Henderson | d731d8cb | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 112 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
Richard Henderson | 30562ab | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 113 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
| 114 | &rrr_esz rn=%reg_movprfx |
Richard Henderson | 6e6a157 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 115 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
| 116 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u |
| 117 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ |
| 118 | &rri_esz rn=%reg_movprfx |
| 119 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ |
| 120 | &rri_esz rn=%reg_movprfx |
Richard Henderson | fea98f9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 121 | |
Richard Henderson | 4b242d9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 122 | # Three operand with "memory" size, aka immediate left shift |
| 123 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri |
| 124 | |
Richard Henderson | f97cfd5 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 125 | # Two register operand, with governing predicate, vector element size |
| 126 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ |
| 127 | &rprr_esz rn=%reg_movprfx |
| 128 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ |
| 129 | &rprr_esz rm=%reg_movprfx |
Richard Henderson | d3fe4a2 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 130 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
Richard Henderson | 757f9cf | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 131 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
Richard Henderson | f97cfd5 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 132 | |
Richard Henderson | 96a36e4 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 133 | # Three register operand, with governing predicate, vector element size |
| 134 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ |
| 135 | &rprrr_esz ra=%reg_movprfx |
| 136 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ |
| 137 | &rprrr_esz rn=%reg_movprfx |
Richard Henderson | 6ceabaa | 2018-06-29 15:11:04 +0100 | [diff] [blame] | 138 | @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ |
| 139 | &rprrr_esz rn=%reg_movprfx |
Richard Henderson | 96a36e4 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 140 | |
Richard Henderson | 047cec9 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 141 | # One register operand, with governing predicate, vector element size |
| 142 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz |
Richard Henderson | 9ee3a61 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 143 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
Richard Henderson | 4d2e2a0 | 2018-06-29 15:11:09 +0100 | [diff] [blame] | 144 | @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz |
Richard Henderson | 047cec9 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 145 | |
Richard Henderson | 8092c6a | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 146 | # One register operand, with governing predicate, no vector element size |
| 147 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 |
| 148 | |
Richard Henderson | 96f922c | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 149 | # Two register operands with a 6-bit signed immediate. |
| 150 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri |
| 151 | |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 152 | # Two register operand, one immediate operand, with predicate, |
Richard Henderson | 830d1a5 | 2020-08-28 10:02:49 +0100 | [diff] [blame] | 153 | # element size encoded as TSZHL. |
| 154 | @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ |
| 155 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl |
| 156 | @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ |
| 157 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 158 | |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 159 | # Similarly without predicate. |
Richard Henderson | 830d1a5 | 2020-08-28 10:02:49 +0100 | [diff] [blame] | 160 | @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ |
| 161 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl |
| 162 | @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ |
| 163 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 164 | |
Richard Henderson | f25a236 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 165 | # Two register operand, one immediate operand, with 4-bit predicate. |
| 166 | # User must fill in imm. |
| 167 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ |
| 168 | &rpri_esz rn=%reg_movprfx |
| 169 | |
Richard Henderson | cc48aff | 2018-06-29 15:11:08 +0100 | [diff] [blame] | 170 | # Two register operand, one one-bit floating-point operand. |
| 171 | @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ |
| 172 | &rpri_esz rn=%reg_movprfx |
| 173 | |
Richard Henderson | e1fa116 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 174 | # Two register operand, one encoded bitmask. |
| 175 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ |
| 176 | &rr_dbm rn=%reg_movprfx |
| 177 | |
Richard Henderson | 38cadeb | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 178 | # Predicate output, vector and immediate input, |
| 179 | # controlling predicate, element size. |
| 180 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz |
| 181 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz |
| 182 | |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 183 | # Basic Load/Store with 9-bit immediate offset |
| 184 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ |
| 185 | &rri imm=%imm9_16_10 |
| 186 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ |
| 187 | &rri imm=%imm9_16_10 |
| 188 | |
Richard Henderson | 24e82e6 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 189 | # One register, pattern, and uint4+1. |
| 190 | # User must fill in U and D. |
| 191 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ |
| 192 | &incdec_cnt imm=%imm4_16_p1 |
| 193 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ |
| 194 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx |
| 195 | |
Richard Henderson | 9ee3a61 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 196 | # One register, predicate. |
| 197 | # User must fill in U and D. |
| 198 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred |
| 199 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ |
| 200 | &incdec2_pred rn=%reg_movprfx |
| 201 | |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 202 | # Loads; user must fill in NREG. |
| 203 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load |
| 204 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load |
| 205 | |
| 206 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ |
| 207 | &rprr_load dtype=%msz_dtype |
| 208 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ |
| 209 | &rpri_load dtype=%msz_dtype |
| 210 | |
Richard Henderson | 673e9fa | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 211 | # Gather Loads. |
| 212 | @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ |
| 213 | &rprr_gather_load xs=2 |
| 214 | @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ |
| 215 | &rprr_gather_load |
| 216 | @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ |
| 217 | &rprr_gather_load |
| 218 | @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ |
| 219 | &rprr_gather_load |
| 220 | @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ |
| 221 | &rprr_gather_load xs=2 |
| 222 | @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ |
| 223 | &rprr_gather_load xs=2 |
| 224 | @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ |
| 225 | &rpri_gather_load |
| 226 | |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 227 | # Stores; user must fill in ESZ, MSZ, NREG as needed. |
| 228 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store |
| 229 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store |
| 230 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ |
| 231 | &rprr_store nreg=0 |
Richard Henderson | f6dbf62 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 232 | @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ |
| 233 | &rprr_scatter_store |
Richard Henderson | 408ecde | 2018-06-29 15:11:07 +0100 | [diff] [blame] | 234 | @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ |
| 235 | &rpri_scatter_store |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 236 | |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 237 | ########################################################################### |
| 238 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. |
| 239 | |
Richard Henderson | f97cfd5 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 240 | ### SVE Integer Arithmetic - Binary Predicated Group |
| 241 | |
| 242 | # SVE bitwise logical vector operations (predicated) |
| 243 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm |
| 244 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm |
| 245 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm |
| 246 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm |
| 247 | |
| 248 | # SVE integer add/subtract vectors (predicated) |
| 249 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm |
| 250 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm |
| 251 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR |
| 252 | |
| 253 | # SVE integer min/max/difference (predicated) |
| 254 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm |
| 255 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm |
| 256 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm |
| 257 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm |
| 258 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm |
| 259 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm |
| 260 | |
| 261 | # SVE integer multiply/divide (predicated) |
| 262 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm |
| 263 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm |
| 264 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm |
| 265 | # Note that divide requires size >= 2; below 2 is unallocated. |
| 266 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm |
| 267 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm |
| 268 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR |
| 269 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR |
| 270 | |
Richard Henderson | 047cec9 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 271 | ### SVE Integer Reduction Group |
| 272 | |
| 273 | # SVE bitwise logical reduction (predicated) |
| 274 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn |
| 275 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn |
| 276 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn |
| 277 | |
Richard Henderson | a210358 | 2018-06-29 15:11:11 +0100 | [diff] [blame] | 278 | # SVE constructive prefix (predicated) |
| 279 | MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn |
| 280 | MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn |
| 281 | |
Richard Henderson | 047cec9 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 282 | # SVE integer add reduction (predicated) |
| 283 | # Note that saddv requires size != 3. |
| 284 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn |
| 285 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn |
| 286 | |
| 287 | # SVE integer min/max reduction (predicated) |
| 288 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn |
| 289 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn |
| 290 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn |
| 291 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn |
| 292 | |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 293 | ### SVE Shift by Immediate - Predicated Group |
| 294 | |
| 295 | # SVE bitwise shift by immediate (predicated) |
Richard Henderson | 830d1a5 | 2020-08-28 10:02:49 +0100 | [diff] [blame] | 296 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr |
| 297 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr |
| 298 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl |
| 299 | ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr |
Richard Henderson | ccd841c | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 300 | |
Richard Henderson | 27721db | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 301 | # SVE bitwise shift by vector (predicated) |
| 302 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm |
| 303 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm |
| 304 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm |
| 305 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR |
| 306 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR |
| 307 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR |
| 308 | |
Richard Henderson | fe7f8df | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 309 | # SVE bitwise shift by wide elements (predicated) |
| 310 | # Note these require size != 3. |
| 311 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm |
| 312 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm |
| 313 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm |
| 314 | |
Richard Henderson | afac6d0 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 315 | ### SVE Integer Arithmetic - Unary Predicated Group |
| 316 | |
| 317 | # SVE unary bit operations (predicated) |
| 318 | # Note esz != 0 for FABS and FNEG. |
| 319 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn |
| 320 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn |
| 321 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn |
| 322 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn |
| 323 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn |
| 324 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn |
| 325 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn |
| 326 | |
| 327 | # SVE integer unary operations (predicated) |
| 328 | # Note esz > original size for extensions. |
| 329 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn |
| 330 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn |
| 331 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn |
| 332 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn |
| 333 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn |
| 334 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn |
| 335 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn |
| 336 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn |
| 337 | |
Richard Henderson | abfdefd | 2018-06-29 15:11:07 +0100 | [diff] [blame] | 338 | ### SVE Floating Point Compare - Vectors Group |
| 339 | |
| 340 | # SVE floating-point compare vectors |
| 341 | FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm |
| 342 | FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm |
| 343 | FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm |
| 344 | FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm |
| 345 | FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm |
| 346 | FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm |
| 347 | FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm |
| 348 | |
Richard Henderson | 96a36e4 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 349 | ### SVE Integer Multiply-Add Group |
| 350 | |
| 351 | # SVE integer multiply-add writing addend (predicated) |
| 352 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm |
| 353 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm |
| 354 | |
| 355 | # SVE integer multiply-add writing multiplicand (predicated) |
| 356 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD |
| 357 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB |
| 358 | |
Richard Henderson | fea98f9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 359 | ### SVE Integer Arithmetic - Unpredicated Group |
| 360 | |
| 361 | # SVE integer add/subtract vectors (unpredicated) |
| 362 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm |
| 363 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm |
| 364 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm |
| 365 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm |
| 366 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm |
| 367 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm |
| 368 | |
Richard Henderson | 38388f7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 369 | ### SVE Logical - Unpredicated Group |
| 370 | |
| 371 | # SVE bitwise logical operations (unpredicated) |
| 372 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| 373 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| 374 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| 375 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 376 | |
Richard Henderson | 9a56c9c | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 377 | ### SVE Index Generation Group |
| 378 | |
| 379 | # SVE index generation (immediate start, immediate increment) |
| 380 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 |
| 381 | |
| 382 | # SVE index generation (immediate start, register increment) |
| 383 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 |
| 384 | |
| 385 | # SVE index generation (register start, immediate increment) |
| 386 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 |
| 387 | |
| 388 | # SVE index generation (register start, register increment) |
| 389 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm |
| 390 | |
Richard Henderson | 96f922c | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 391 | ### SVE Stack Allocation Group |
| 392 | |
| 393 | # SVE stack frame adjustment |
| 394 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 |
| 395 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 |
| 396 | |
| 397 | # SVE stack frame size |
| 398 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 |
| 399 | |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 400 | ### SVE Bitwise Shift - Unpredicated Group |
| 401 | |
| 402 | # SVE bitwise shift by immediate (unpredicated) |
Richard Henderson | 830d1a5 | 2020-08-28 10:02:49 +0100 | [diff] [blame] | 403 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr |
| 404 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr |
| 405 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl |
Richard Henderson | d9d78dc | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 406 | |
| 407 | # SVE bitwise shift by wide elements (unpredicated) |
| 408 | # Note esz != 3 |
| 409 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm |
| 410 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm |
| 411 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm |
| 412 | |
Richard Henderson | 4b242d9 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 413 | ### SVE Compute Vector Address Group |
| 414 | |
| 415 | # SVE vector address generation |
| 416 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm |
| 417 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm |
| 418 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm |
| 419 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm |
| 420 | |
Richard Henderson | 0762cd4 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 421 | ### SVE Integer Misc - Unpredicated Group |
| 422 | |
Richard Henderson | a210358 | 2018-06-29 15:11:11 +0100 | [diff] [blame] | 423 | # SVE constructive prefix (unpredicated) |
| 424 | MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 |
| 425 | |
Richard Henderson | 0762cd4 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 426 | # SVE floating-point exponential accelerator |
| 427 | # Note esz != 0 |
| 428 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn |
| 429 | |
Richard Henderson | a1f233f | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 430 | # SVE floating-point trig select coefficient |
| 431 | # Note esz != 0 |
| 432 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm |
| 433 | |
Richard Henderson | 24e82e6 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 434 | ### SVE Element Count Group |
| 435 | |
| 436 | # SVE element count |
| 437 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 |
| 438 | |
| 439 | # SVE inc/dec register by element count |
| 440 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 |
| 441 | |
| 442 | # SVE saturating inc/dec register by element count |
| 443 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt |
| 444 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt |
| 445 | |
| 446 | # SVE inc/dec vector by element count |
| 447 | # Note this requires esz != 0. |
| 448 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 |
| 449 | |
| 450 | # SVE saturating inc/dec vector by element count |
| 451 | # Note these require esz != 0. |
| 452 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt |
Richard Henderson | 516e246 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 453 | |
Richard Henderson | e1fa116 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 454 | ### SVE Bitwise Immediate Group |
| 455 | |
| 456 | # SVE bitwise logical with immediate (unpredicated) |
| 457 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm |
| 458 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm |
| 459 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm |
| 460 | |
| 461 | # SVE broadcast bitmask immediate |
| 462 | DUPM 00000101 11 0000 dbm:13 rd:5 |
| 463 | |
Richard Henderson | f25a236 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 464 | ### SVE Integer Wide Immediate - Predicated Group |
| 465 | |
| 466 | # SVE copy floating-point immediate (predicated) |
| 467 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 |
| 468 | |
| 469 | # SVE copy integer immediate (predicated) |
| 470 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s |
| 471 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s |
| 472 | |
Richard Henderson | b94f8f6 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 473 | ### SVE Permute - Extract Group |
| 474 | |
| 475 | # SVE extract vector (immediate offset) |
| 476 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ |
| 477 | &rrri rn=%reg_movprfx imm=%imm8_16_10 |
| 478 | |
Richard Henderson | 30562ab | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 479 | ### SVE Permute - Unpredicated Group |
| 480 | |
| 481 | # SVE broadcast general register |
| 482 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn |
| 483 | |
| 484 | # SVE broadcast indexed element |
| 485 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ |
| 486 | &rri imm=%imm7_22_16 |
| 487 | |
| 488 | # SVE insert SIMD&FP scalar register |
| 489 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm |
| 490 | |
| 491 | # SVE insert general register |
| 492 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm |
| 493 | |
| 494 | # SVE reverse vector elements |
| 495 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn |
| 496 | |
| 497 | # SVE vector table lookup |
| 498 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm |
| 499 | |
| 500 | # SVE unpack vector elements |
| 501 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 |
| 502 | |
Richard Henderson | d731d8cb | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 503 | ### SVE Permute - Predicates Group |
| 504 | |
| 505 | # SVE permute predicate elements |
| 506 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm |
| 507 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm |
| 508 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm |
| 509 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm |
| 510 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm |
| 511 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm |
| 512 | |
| 513 | # SVE reverse predicate elements |
| 514 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn |
| 515 | |
| 516 | # SVE unpack predicate elements |
| 517 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 |
| 518 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 |
| 519 | |
Richard Henderson | 234b48e | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 520 | ### SVE Permute - Interleaving Group |
| 521 | |
| 522 | # SVE permute vector elements |
| 523 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm |
| 524 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm |
| 525 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm |
| 526 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm |
| 527 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm |
| 528 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm |
| 529 | |
Richard Henderson | 3ca879a | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 530 | ### SVE Permute - Predicated Group |
| 531 | |
| 532 | # SVE compress active elements |
| 533 | # Note esz >= 2 |
| 534 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn |
| 535 | |
Richard Henderson | ef23cb7 | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 536 | # SVE conditionally broadcast element to vector |
| 537 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm |
| 538 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm |
| 539 | |
| 540 | # SVE conditionally copy element to SIMD&FP scalar |
| 541 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn |
| 542 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn |
| 543 | |
| 544 | # SVE conditionally copy element to general register |
| 545 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn |
| 546 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn |
| 547 | |
| 548 | # SVE copy element to SIMD&FP scalar register |
| 549 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn |
| 550 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn |
| 551 | |
| 552 | # SVE copy element to general register |
| 553 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn |
| 554 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn |
| 555 | |
Richard Henderson | 792a557 | 2018-06-15 14:57:14 +0100 | [diff] [blame] | 556 | # SVE copy element from SIMD&FP scalar register |
| 557 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn |
| 558 | |
| 559 | # SVE copy element from general register to vector (predicated) |
| 560 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn |
| 561 | |
Richard Henderson | dae8fb9 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 562 | # SVE reverse within elements |
| 563 | # Note esz >= operation size |
| 564 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn |
| 565 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn |
| 566 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn |
| 567 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn |
| 568 | |
Richard Henderson | b48ff24 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 569 | # SVE vector splice (predicated) |
| 570 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm |
| 571 | |
Richard Henderson | d3fe4a2 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 572 | ### SVE Select Vectors Group |
| 573 | |
| 574 | # SVE select vector elements (predicated) |
| 575 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm |
| 576 | |
Richard Henderson | 757f9cf | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 577 | ### SVE Integer Compare - Vectors Group |
| 578 | |
| 579 | # SVE integer compare_vectors |
| 580 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm |
| 581 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm |
| 582 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm |
| 583 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm |
| 584 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm |
| 585 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm |
| 586 | |
| 587 | # SVE integer compare with wide elements |
| 588 | # Note these require esz != 3. |
| 589 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm |
| 590 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm |
| 591 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm |
| 592 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm |
| 593 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm |
| 594 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm |
| 595 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm |
| 596 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm |
| 597 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm |
| 598 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm |
| 599 | |
Richard Henderson | 38cadeb | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 600 | ### SVE Integer Compare - Unsigned Immediate Group |
| 601 | |
| 602 | # SVE integer compare with unsigned immediate |
| 603 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 |
| 604 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 |
| 605 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 |
| 606 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 |
| 607 | |
| 608 | ### SVE Integer Compare - Signed Immediate Group |
| 609 | |
| 610 | # SVE integer compare with signed immediate |
| 611 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 |
| 612 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 |
| 613 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 |
| 614 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 |
| 615 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 |
| 616 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 |
| 617 | |
Richard Henderson | e1fa116 | 2018-05-18 17:48:09 +0100 | [diff] [blame] | 618 | ### SVE Predicate Logical Operations Group |
| 619 | |
Richard Henderson | 516e246 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 620 | # SVE predicate logical operations |
| 621 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s |
| 622 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s |
| 623 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s |
| 624 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s |
| 625 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s |
| 626 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s |
| 627 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s |
| 628 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s |
| 629 | |
Richard Henderson | 9e18d7a | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 630 | ### SVE Predicate Misc Group |
| 631 | |
| 632 | # SVE predicate test |
| 633 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 |
| 634 | |
Richard Henderson | 028e2a7 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 635 | # SVE predicate initialize |
| 636 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 |
| 637 | |
| 638 | # SVE initialize FFR |
| 639 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 |
| 640 | |
| 641 | # SVE zero predicate register |
| 642 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 |
| 643 | |
| 644 | # SVE predicate read from FFR (predicated) |
| 645 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 |
| 646 | |
| 647 | # SVE predicate read from FFR (unpredicated) |
| 648 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 |
| 649 | |
| 650 | # SVE FFR write from predicate (WRFFR) |
| 651 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 |
| 652 | |
| 653 | # SVE predicate first active |
| 654 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 |
| 655 | |
| 656 | # SVE predicate next active |
| 657 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn |
| 658 | |
Richard Henderson | 35da316 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 659 | ### SVE Partition Break Group |
| 660 | |
| 661 | # SVE propagate break from previous partition |
| 662 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s |
| 663 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s |
| 664 | |
| 665 | # SVE partition break condition |
| 666 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s |
| 667 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s |
Richard Henderson | 407e6ce | 2019-01-07 15:23:45 +0000 | [diff] [blame] | 668 | BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 |
| 669 | BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 |
Richard Henderson | 35da316 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 670 | |
| 671 | # SVE propagate break to next partition |
| 672 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s |
| 673 | |
Richard Henderson | 9ee3a61 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 674 | ### SVE Predicate Count Group |
| 675 | |
| 676 | # SVE predicate count |
| 677 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn |
| 678 | |
| 679 | # SVE inc/dec register by predicate count |
| 680 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 |
| 681 | |
| 682 | # SVE inc/dec vector by predicate count |
| 683 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 |
| 684 | |
| 685 | # SVE saturating inc/dec register by predicate count |
| 686 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred |
| 687 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred |
| 688 | |
| 689 | # SVE saturating inc/dec vector by predicate count |
| 690 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred |
| 691 | |
Richard Henderson | caf1cef | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 692 | ### SVE Integer Compare - Scalars Group |
| 693 | |
| 694 | # SVE conditionally terminate scalars |
| 695 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 |
| 696 | |
| 697 | # SVE integer compare scalar count and limit |
| 698 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 |
| 699 | |
Richard Henderson | ed49196 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 700 | ### SVE Integer Wide Immediate - Unpredicated Group |
| 701 | |
| 702 | # SVE broadcast floating-point immediate (unpredicated) |
| 703 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 |
| 704 | |
| 705 | # SVE broadcast integer immediate (unpredicated) |
| 706 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s |
| 707 | |
Richard Henderson | 6e6a157 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 708 | # SVE integer add/subtract immediate (unpredicated) |
| 709 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u |
| 710 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u |
| 711 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u |
| 712 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u |
| 713 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u |
| 714 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u |
| 715 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u |
| 716 | |
| 717 | # SVE integer min/max immediate (unpredicated) |
| 718 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s |
| 719 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u |
| 720 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s |
| 721 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u |
| 722 | |
| 723 | # SVE integer multiply immediate (unpredicated) |
| 724 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s |
| 725 | |
Richard Henderson | d730eca | 2018-06-29 15:11:13 +0100 | [diff] [blame] | 726 | # SVE integer dot product (unpredicated) |
| 727 | DOT_zzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 ra=%reg_movprfx |
| 728 | |
Richard Henderson | 16fcfdc | 2018-06-29 15:11:15 +0100 | [diff] [blame] | 729 | # SVE integer dot product (indexed) |
| 730 | DOT_zzx 01000100 101 index:2 rm:3 00000 u:1 rn:5 rd:5 \ |
| 731 | sz=0 ra=%reg_movprfx |
| 732 | DOT_zzx 01000100 111 index:1 rm:4 00000 u:1 rn:5 rd:5 \ |
| 733 | sz=1 ra=%reg_movprfx |
| 734 | |
Richard Henderson | 76a9d9c | 2018-06-29 15:11:11 +0100 | [diff] [blame] | 735 | # SVE floating-point complex add (predicated) |
| 736 | FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ |
| 737 | rn=%reg_movprfx |
| 738 | |
Richard Henderson | 05f48ba | 2018-06-29 15:11:12 +0100 | [diff] [blame] | 739 | # SVE floating-point complex multiply-add (predicated) |
| 740 | FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ |
| 741 | ra=%reg_movprfx |
| 742 | |
Richard Henderson | 18fc240 | 2018-06-29 15:11:12 +0100 | [diff] [blame] | 743 | # SVE floating-point complex multiply-add (indexed) |
| 744 | FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ |
| 745 | ra=%reg_movprfx esz=1 |
| 746 | FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ |
| 747 | ra=%reg_movprfx esz=2 |
| 748 | |
Richard Henderson | ca40a6e | 2018-06-29 15:11:08 +0100 | [diff] [blame] | 749 | ### SVE FP Multiply-Add Indexed Group |
| 750 | |
| 751 | # SVE floating-point multiply-add (indexed) |
| 752 | FMLA_zzxz 01100100 0.1 .. rm:3 00000 sub:1 rn:5 rd:5 \ |
| 753 | ra=%reg_movprfx index=%index3_22_19 esz=1 |
| 754 | FMLA_zzxz 01100100 101 index:2 rm:3 00000 sub:1 rn:5 rd:5 \ |
| 755 | ra=%reg_movprfx esz=2 |
| 756 | FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \ |
| 757 | ra=%reg_movprfx esz=3 |
| 758 | |
| 759 | ### SVE FP Multiply Indexed Group |
| 760 | |
| 761 | # SVE floating-point multiply (indexed) |
| 762 | FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \ |
| 763 | index=%index3_22_19 esz=1 |
| 764 | FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2 |
| 765 | FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3 |
| 766 | |
Richard Henderson | 23fbe79 | 2018-06-29 15:11:08 +0100 | [diff] [blame] | 767 | ### SVE FP Fast Reduction Group |
| 768 | |
| 769 | FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn |
| 770 | FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn |
| 771 | FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn |
| 772 | FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn |
| 773 | FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn |
| 774 | |
Richard Henderson | 3887c03 | 2018-06-29 15:11:09 +0100 | [diff] [blame] | 775 | ## SVE Floating Point Unary Operations - Unpredicated Group |
| 776 | |
| 777 | FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn |
| 778 | FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn |
| 779 | |
Richard Henderson | 4d2e2a0 | 2018-06-29 15:11:09 +0100 | [diff] [blame] | 780 | ### SVE FP Compare with Zero Group |
| 781 | |
| 782 | FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn |
| 783 | FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn |
| 784 | FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn |
| 785 | FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn |
| 786 | FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn |
| 787 | FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn |
| 788 | |
Richard Henderson | 7f9ddf6 | 2018-06-29 15:11:04 +0100 | [diff] [blame] | 789 | ### SVE FP Accumulating Reduction Group |
| 790 | |
| 791 | # SVE floating-point serial reduction (predicated) |
| 792 | FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm |
| 793 | |
Richard Henderson | 29b8046 | 2018-06-15 14:57:15 +0100 | [diff] [blame] | 794 | ### SVE Floating Point Arithmetic - Unpredicated Group |
| 795 | |
| 796 | # SVE floating-point arithmetic (unpredicated) |
| 797 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm |
| 798 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm |
| 799 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm |
| 800 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm |
| 801 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm |
| 802 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm |
| 803 | |
Richard Henderson | ec3b87c | 2018-06-29 15:11:04 +0100 | [diff] [blame] | 804 | ### SVE FP Arithmetic Predicated Group |
| 805 | |
| 806 | # SVE floating-point arithmetic (predicated) |
| 807 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm |
| 808 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm |
| 809 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm |
| 810 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR |
| 811 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm |
| 812 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm |
| 813 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm |
| 814 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm |
| 815 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm |
| 816 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm |
| 817 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm |
| 818 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR |
| 819 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm |
| 820 | |
Richard Henderson | cc48aff | 2018-06-29 15:11:08 +0100 | [diff] [blame] | 821 | # SVE floating-point arithmetic with immediate (predicated) |
| 822 | FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 |
| 823 | FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 |
| 824 | FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 |
| 825 | FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 |
| 826 | FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 |
| 827 | FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 |
| 828 | FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 |
| 829 | FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 |
| 830 | |
Richard Henderson | 67fcd9a | 2018-06-29 15:11:09 +0100 | [diff] [blame] | 831 | # SVE floating-point trig multiply-add coefficient |
| 832 | FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx |
| 833 | |
Richard Henderson | 6ceabaa | 2018-06-29 15:11:04 +0100 | [diff] [blame] | 834 | ### SVE FP Multiply-Add Group |
| 835 | |
| 836 | # SVE floating-point multiply-accumulate writing addend |
| 837 | FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm |
| 838 | FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm |
| 839 | FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm |
| 840 | FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm |
| 841 | |
| 842 | # SVE floating-point multiply-accumulate writing multiplicand |
| 843 | # Alter the operand extraction order and reuse the helpers from above. |
| 844 | # FMAD, FMSB, FNMAD, FNMS |
| 845 | FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra |
| 846 | FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra |
| 847 | FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra |
| 848 | FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra |
| 849 | |
Richard Henderson | 8092c6a | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 850 | ### SVE FP Unary Operations Predicated Group |
| 851 | |
Richard Henderson | 46d33d1 | 2018-06-29 15:11:10 +0100 | [diff] [blame] | 852 | # SVE floating-point convert precision |
| 853 | FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 |
| 854 | FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 |
| 855 | FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 |
| 856 | FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 |
| 857 | FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 |
| 858 | FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 |
| 859 | |
Richard Henderson | df4de1a | 2018-06-29 15:11:10 +0100 | [diff] [blame] | 860 | # SVE floating-point convert to integer |
| 861 | FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 862 | FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 863 | FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 864 | FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 865 | FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 866 | FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 867 | FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 868 | FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 869 | FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 870 | FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 871 | FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 872 | FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 873 | FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 874 | FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 875 | |
Richard Henderson | cda3c75 | 2018-06-29 15:11:10 +0100 | [diff] [blame] | 876 | # SVE floating-point round to integral value |
| 877 | FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn |
| 878 | FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn |
| 879 | FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn |
| 880 | FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn |
| 881 | FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn |
| 882 | FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn |
| 883 | FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn |
| 884 | |
Richard Henderson | ec5b375 | 2018-06-29 15:11:11 +0100 | [diff] [blame] | 885 | # SVE floating-point unary operations |
| 886 | FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn |
| 887 | FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn |
| 888 | |
Richard Henderson | 8092c6a | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 889 | # SVE integer convert to floating-point |
| 890 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 891 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 892 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 893 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 894 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 895 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 896 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 |
| 897 | |
| 898 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 899 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 900 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 901 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 902 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 903 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 904 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 |
| 905 | |
Richard Henderson | d182229 | 2018-05-18 17:48:08 +0100 | [diff] [blame] | 906 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| 907 | |
| 908 | # SVE load predicate register |
| 909 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 |
| 910 | |
| 911 | # SVE load vector register |
| 912 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 913 | |
Richard Henderson | 6845986 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 914 | # SVE load and broadcast element |
| 915 | LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ |
| 916 | &rpri_load dtype=%dtype_23_13 nreg=0 |
| 917 | |
Richard Henderson | 673e9fa | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 918 | # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) |
| 919 | # SVE 32-bit gather load (scalar plus 32-bit scaled offsets) |
| 920 | LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ |
| 921 | @rprr_g_load_xs_u esz=2 msz=0 scale=0 |
| 922 | LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ |
| 923 | @rprr_g_load_xs_u_sc esz=2 msz=1 |
| 924 | LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ |
| 925 | @rprr_g_load_xs_sc esz=2 msz=2 u=1 |
| 926 | |
| 927 | # SVE 32-bit gather load (vector plus immediate) |
| 928 | LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ |
| 929 | @rpri_g_load esz=2 |
| 930 | |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 931 | ### SVE Memory Contiguous Load Group |
| 932 | |
| 933 | # SVE contiguous load (scalar plus scalar) |
| 934 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 |
| 935 | |
Richard Henderson | e2654d7 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 936 | # SVE contiguous first-fault load (scalar plus scalar) |
| 937 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 |
| 938 | |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 939 | # SVE contiguous load (scalar plus immediate) |
| 940 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 |
| 941 | |
Richard Henderson | e2654d7 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 942 | # SVE contiguous non-fault load (scalar plus immediate) |
| 943 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 |
| 944 | |
Richard Henderson | c4e7c49 | 2018-06-29 15:11:02 +0100 | [diff] [blame] | 945 | # SVE contiguous non-temporal load (scalar plus scalar) |
| 946 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D |
| 947 | # SVE load multiple structures (scalar plus scalar) |
| 948 | # LD2B, LD2H, LD2W, LD2D; etc. |
| 949 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz |
| 950 | |
| 951 | # SVE contiguous non-temporal load (scalar plus immediate) |
| 952 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D |
| 953 | # SVE load multiple structures (scalar plus immediate) |
| 954 | # LD2B, LD2H, LD2W, LD2D; etc. |
| 955 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 956 | |
Richard Henderson | 05abe30 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 957 | # SVE load and broadcast quadword (scalar plus scalar) |
| 958 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ |
| 959 | @rprr_load_msz nreg=0 |
| 960 | |
| 961 | # SVE load and broadcast quadword (scalar plus immediate) |
| 962 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD |
| 963 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ |
| 964 | @rpri_load_msz nreg=0 |
| 965 | |
Richard Henderson | dec6cf6 | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 966 | # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) |
| 967 | PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- |
| 968 | |
| 969 | # SVE 32-bit gather prefetch (vector plus immediate) |
| 970 | PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- |
| 971 | |
| 972 | # SVE contiguous prefetch (scalar plus immediate) |
| 973 | PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- |
| 974 | |
| 975 | # SVE contiguous prefetch (scalar plus scalar) |
| 976 | PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- |
| 977 | |
| 978 | ### SVE Memory 64-bit Gather Group |
| 979 | |
Richard Henderson | 673e9fa | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 980 | # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) |
| 981 | # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) |
| 982 | LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ |
| 983 | @rprr_g_load_xs_u esz=3 msz=0 scale=0 |
| 984 | LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ |
| 985 | @rprr_g_load_xs_u_sc esz=3 msz=1 |
| 986 | LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ |
| 987 | @rprr_g_load_xs_u_sc esz=3 msz=2 |
| 988 | LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ |
| 989 | @rprr_g_load_xs_sc esz=3 msz=3 u=1 |
| 990 | |
| 991 | # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) |
| 992 | # SVE 64-bit gather load (scalar plus 64-bit scaled offsets) |
| 993 | LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ |
| 994 | @rprr_g_load_u esz=3 msz=0 scale=0 |
| 995 | LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ |
| 996 | @rprr_g_load_u_sc esz=3 msz=1 |
| 997 | LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ |
| 998 | @rprr_g_load_u_sc esz=3 msz=2 |
| 999 | LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ |
| 1000 | @rprr_g_load_sc esz=3 msz=3 u=1 |
| 1001 | |
| 1002 | # SVE 64-bit gather load (vector plus immediate) |
| 1003 | LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ |
| 1004 | @rpri_g_load esz=3 |
| 1005 | |
Richard Henderson | dec6cf6 | 2018-06-29 15:11:06 +0100 | [diff] [blame] | 1006 | # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) |
| 1007 | PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- |
| 1008 | |
| 1009 | # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) |
| 1010 | PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- |
| 1011 | |
| 1012 | # SVE 64-bit gather prefetch (vector plus immediate) |
| 1013 | PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- |
| 1014 | |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 1015 | ### SVE Memory Store Group |
| 1016 | |
Richard Henderson | 5047c20 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 1017 | # SVE store predicate register |
| 1018 | STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 |
| 1019 | |
| 1020 | # SVE store vector register |
| 1021 | STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 |
| 1022 | |
Richard Henderson | 1a039c7 | 2018-06-29 15:11:03 +0100 | [diff] [blame] | 1023 | # SVE contiguous store (scalar plus immediate) |
| 1024 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz |
| 1025 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ |
| 1026 | @rpri_store_msz nreg=0 |
| 1027 | |
| 1028 | # SVE contiguous store (scalar plus scalar) |
| 1029 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz |
| 1030 | # Enumerate msz lest we conflict with STR_zri. |
| 1031 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ |
| 1032 | @rprr_store_esz_n0 msz=0 |
| 1033 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ |
| 1034 | @rprr_store_esz_n0 msz=1 |
| 1035 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ |
| 1036 | @rprr_store_esz_n0 msz=2 |
| 1037 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ |
| 1038 | @rprr_store msz=3 esz=3 nreg=0 |
| 1039 | |
| 1040 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) |
| 1041 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) |
| 1042 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ |
| 1043 | @rpri_store_msz esz=%size_23 |
| 1044 | |
| 1045 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) |
| 1046 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) |
| 1047 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ |
| 1048 | @rprr_store esz=%size_23 |
Richard Henderson | f6dbf62 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 1049 | |
| 1050 | # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) |
| 1051 | # Require msz > 0 && msz <= esz. |
| 1052 | ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ |
| 1053 | @rprr_scatter_store xs=0 esz=2 scale=1 |
| 1054 | ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ |
| 1055 | @rprr_scatter_store xs=1 esz=2 scale=1 |
| 1056 | |
| 1057 | # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) |
| 1058 | # Require msz <= esz. |
| 1059 | ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ |
| 1060 | @rprr_scatter_store xs=0 esz=2 scale=0 |
| 1061 | ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ |
| 1062 | @rprr_scatter_store xs=1 esz=2 scale=0 |
| 1063 | |
| 1064 | # SVE 64-bit scatter store (scalar plus 64-bit scaled offset) |
| 1065 | # Require msz > 0 |
| 1066 | ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ |
| 1067 | @rprr_scatter_store xs=2 esz=3 scale=1 |
| 1068 | |
| 1069 | # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) |
| 1070 | ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ |
| 1071 | @rprr_scatter_store xs=2 esz=3 scale=0 |
| 1072 | |
Richard Henderson | 408ecde | 2018-06-29 15:11:07 +0100 | [diff] [blame] | 1073 | # SVE 64-bit scatter store (vector plus immediate) |
| 1074 | ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ |
| 1075 | @rpri_scatter_store esz=3 |
| 1076 | |
| 1077 | # SVE 32-bit scatter store (vector plus immediate) |
| 1078 | ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ |
| 1079 | @rpri_scatter_store esz=2 |
| 1080 | |
Richard Henderson | f6dbf62 | 2018-06-29 15:11:05 +0100 | [diff] [blame] | 1081 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) |
| 1082 | # Require msz > 0 |
| 1083 | ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ |
| 1084 | @rprr_scatter_store xs=0 esz=3 scale=1 |
| 1085 | ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ |
| 1086 | @rprr_scatter_store xs=1 esz=3 scale=1 |
| 1087 | |
| 1088 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) |
| 1089 | ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ |
| 1090 | @rprr_scatter_store xs=0 esz=3 scale=0 |
| 1091 | ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ |
| 1092 | @rprr_scatter_store xs=1 esz=3 scale=0 |