blob: 5c906033588dfa79dd0895ab1e1c26682ee31e52 [file] [log] [blame]
Richard Henderson38388f72018-05-18 17:48:08 +01001# AArch64 SVE instruction descriptions
2#
3# Copyright (c) 2017 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
Chetan Pant50f57e02020-10-23 12:29:13 +00008# version 2.1 of the License, or (at your option) any later version.
Richard Henderson38388f72018-05-18 17:48:08 +01009#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
21
22###########################################################################
Richard Hendersond1822292018-05-18 17:48:08 +010023# Named fields. These are primarily for disjoint fields.
24
Richard Hendersonf25a2362018-05-18 17:48:09 +010025%imm4_16_p1 16:4 !function=plus1
Richard Hendersonccd841c2018-05-18 17:48:08 +010026%imm6_22_5 22:1 5:5
Richard Henderson30562ab2018-06-15 14:57:14 +010027%imm7_22_16 22:2 16:5
Richard Hendersonb94f8f62018-05-18 17:48:09 +010028%imm8_16_10 16:5 10:3
Richard Hendersond1822292018-05-18 17:48:08 +010029%imm9_16_10 16:s6 10:3
Richard Henderson1a039c72018-06-29 15:11:03 +010030%size_23 23:2
Richard Henderson68459862018-06-29 15:11:05 +010031%dtype_23_13 23:2 13:2
Richard Hendersonca40a6e2018-06-29 15:11:08 +010032%index3_22_19 22:1 19:2
Richard Hendersond1822292018-05-18 17:48:08 +010033
Richard Hendersonccd841c2018-05-18 17:48:08 +010034# A combination of tsz:imm3 -- extract esize.
35%tszimm_esz 22:2 5:5 !function=tszimm_esz
36# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
37%tszimm_shr 22:2 5:5 !function=tszimm_shr
38# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
39%tszimm_shl 22:2 5:5 !function=tszimm_shl
40
Richard Hendersond9d78dc2018-05-18 17:48:09 +010041# Similarly for the tszh/tszl pair at 22/16 for zzi
42%tszimm16_esz 22:2 16:5 !function=tszimm_esz
43%tszimm16_shr 22:2 16:5 !function=tszimm_shr
44%tszimm16_shl 22:2 16:5 !function=tszimm_shl
45
Richard Hendersonf25a2362018-05-18 17:48:09 +010046# Signed 8-bit immediate, optionally shifted left by 8.
47%sh8_i8s 5:9 !function=expand_imm_sh8s
Richard Henderson6e6a1572018-06-15 14:57:15 +010048# Unsigned 8-bit immediate, optionally shifted left by 8.
49%sh8_i8u 5:9 !function=expand_imm_sh8u
Richard Hendersonf25a2362018-05-18 17:48:09 +010050
Richard Hendersonc4e7c492018-06-29 15:11:02 +010051# Unsigned load of msz into esz=2, represented as a dtype.
52%msz_dtype 23:2 !function=msz_dtype
53
Richard Hendersonf97cfd52018-05-18 17:48:08 +010054# Either a copy of rd (at bit 0), or a different source
55# as propagated via the MOVPRFX instruction.
56%reg_movprfx 0:5
57
Richard Hendersond1822292018-05-18 17:48:08 +010058###########################################################################
Richard Henderson38388f72018-05-18 17:48:08 +010059# Named attribute sets. These are used to make nice(er) names
60# when creating helpers common to those for the individual
61# instruction patterns.
62
Richard Henderson028e2a72018-05-18 17:48:08 +010063&rr_esz rd rn esz
Richard Hendersond1822292018-05-18 17:48:08 +010064&rri rd rn imm
Richard Hendersone1fa1162018-05-18 17:48:09 +010065&rr_dbm rd rn dbm
Richard Henderson4b242d92018-05-18 17:48:09 +010066&rrri rd rn rm imm
Richard Hendersond9d78dc2018-05-18 17:48:09 +010067&rri_esz rd rn imm esz
Richard Henderson38388f72018-05-18 17:48:08 +010068&rrr_esz rd rn rm esz
Richard Henderson047cec92018-05-18 17:48:08 +010069&rpr_esz rd pg rn esz
Richard Henderson35da3162018-06-15 14:57:15 +010070&rpr_s rd pg rn s
Richard Henderson516e2462018-05-18 17:48:08 +010071&rprr_s rd pg rn rm s
Richard Hendersonf97cfd52018-05-18 17:48:08 +010072&rprr_esz rd pg rn rm esz
Richard Henderson96a36e42018-05-18 17:48:08 +010073&rprrr_esz rd pg rn rm ra esz
Richard Hendersonccd841c2018-05-18 17:48:08 +010074&rpri_esz rd pg rn imm esz
Richard Henderson24e82e62018-05-18 17:48:09 +010075&ptrue rd esz pat s
76&incdec_cnt rd pat esz imm d u
77&incdec2_cnt rd rn pat esz imm d u
Richard Henderson9ee3a612018-06-15 14:57:15 +010078&incdec_pred rd pg esz d u
79&incdec2_pred rd rn pg esz d u
Richard Hendersonc4e7c492018-06-29 15:11:02 +010080&rprr_load rd pg rn rm dtype nreg
81&rpri_load rd pg rn imm dtype nreg
Richard Henderson1a039c72018-06-29 15:11:03 +010082&rprr_store rd pg rn rm msz esz nreg
83&rpri_store rd pg rn imm msz esz nreg
Richard Henderson673e9fa2018-06-29 15:11:06 +010084&rprr_gather_load rd pg rn rm esz msz u ff xs scale
85&rpri_gather_load rd pg rn imm esz msz u ff
Richard Hendersonf6dbf622018-06-29 15:11:05 +010086&rprr_scatter_store rd pg rn rm esz msz xs scale
Richard Henderson408ecde2018-06-29 15:11:07 +010087&rpri_scatter_store rd pg rn imm esz msz
Richard Henderson38388f72018-05-18 17:48:08 +010088
89###########################################################################
90# Named instruction formats. These are generally used to
91# reduce the amount of duplication between instruction patterns.
92
Richard Henderson028e2a72018-05-18 17:48:08 +010093# Two operand with unused vector element size
94@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
95
96# Two operand
97@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
Richard Henderson0762cd42018-05-18 17:48:09 +010098@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
Richard Henderson028e2a72018-05-18 17:48:08 +010099
Richard Henderson35da3162018-06-15 14:57:15 +0100100# Two operand with governing predicate, flags setting
101@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
Richard Henderson407e6ce2019-01-07 15:23:45 +0000102@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0
Richard Henderson35da3162018-06-15 14:57:15 +0100103
Richard Henderson38388f72018-05-18 17:48:08 +0100104# Three operand with unused vector element size
105@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
106
Richard Henderson516e2462018-05-18 17:48:08 +0100107# Three predicate operand, with governing predicate, flag setting
108@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
109
Richard Hendersonfea98f92018-05-18 17:48:09 +0100110# Three operand, vector element size
111@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
Richard Hendersond731d8cb2018-06-15 14:57:14 +0100112@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
Richard Henderson30562ab2018-06-15 14:57:14 +0100113@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
114 &rrr_esz rn=%reg_movprfx
Richard Henderson6e6a1572018-06-15 14:57:15 +0100115@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
116 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
117@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
118 &rri_esz rn=%reg_movprfx
119@rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
120 &rri_esz rn=%reg_movprfx
Richard Hendersonfea98f92018-05-18 17:48:09 +0100121
Richard Henderson4b242d92018-05-18 17:48:09 +0100122# Three operand with "memory" size, aka immediate left shift
123@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
124
Richard Hendersonf97cfd52018-05-18 17:48:08 +0100125# Two register operand, with governing predicate, vector element size
126@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
127 &rprr_esz rn=%reg_movprfx
128@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
129 &rprr_esz rm=%reg_movprfx
Richard Hendersond3fe4a22018-06-15 14:57:15 +0100130@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
Richard Henderson757f9cf2018-06-15 14:57:15 +0100131@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
Richard Hendersonf97cfd52018-05-18 17:48:08 +0100132
Richard Henderson96a36e42018-05-18 17:48:08 +0100133# Three register operand, with governing predicate, vector element size
134@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
135 &rprrr_esz ra=%reg_movprfx
136@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
137 &rprrr_esz rn=%reg_movprfx
Richard Henderson6ceabaa2018-06-29 15:11:04 +0100138@rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
139 &rprrr_esz rn=%reg_movprfx
Richard Henderson96a36e42018-05-18 17:48:08 +0100140
Richard Henderson047cec92018-05-18 17:48:08 +0100141# One register operand, with governing predicate, vector element size
142@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
Richard Henderson9ee3a612018-06-15 14:57:15 +0100143@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
Richard Henderson4d2e2a02018-06-29 15:11:09 +0100144@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
Richard Henderson047cec92018-05-18 17:48:08 +0100145
Richard Henderson8092c6a2018-06-29 15:11:03 +0100146# One register operand, with governing predicate, no vector element size
147@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
148
Richard Henderson96f922c2018-05-18 17:48:09 +0100149# Two register operands with a 6-bit signed immediate.
150@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
151
Richard Hendersonccd841c2018-05-18 17:48:08 +0100152# Two register operand, one immediate operand, with predicate,
Richard Henderson830d1a52020-08-28 10:02:49 +0100153# element size encoded as TSZHL.
154@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
155 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
156@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
157 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
Richard Hendersonccd841c2018-05-18 17:48:08 +0100158
Richard Hendersond9d78dc2018-05-18 17:48:09 +0100159# Similarly without predicate.
Richard Henderson830d1a52020-08-28 10:02:49 +0100160@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
161 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
162@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
163 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
Richard Hendersond9d78dc2018-05-18 17:48:09 +0100164
Richard Hendersonf25a2362018-05-18 17:48:09 +0100165# Two register operand, one immediate operand, with 4-bit predicate.
166# User must fill in imm.
167@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
168 &rpri_esz rn=%reg_movprfx
169
Richard Hendersoncc48aff2018-06-29 15:11:08 +0100170# Two register operand, one one-bit floating-point operand.
171@rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
172 &rpri_esz rn=%reg_movprfx
173
Richard Hendersone1fa1162018-05-18 17:48:09 +0100174# Two register operand, one encoded bitmask.
175@rdn_dbm ........ .. .... dbm:13 rd:5 \
176 &rr_dbm rn=%reg_movprfx
177
Richard Henderson38cadeb2018-06-15 14:57:15 +0100178# Predicate output, vector and immediate input,
179# controlling predicate, element size.
180@pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
181@pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
182
Richard Hendersond1822292018-05-18 17:48:08 +0100183# Basic Load/Store with 9-bit immediate offset
184@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
185 &rri imm=%imm9_16_10
186@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
187 &rri imm=%imm9_16_10
188
Richard Henderson24e82e62018-05-18 17:48:09 +0100189# One register, pattern, and uint4+1.
190# User must fill in U and D.
191@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
192 &incdec_cnt imm=%imm4_16_p1
193@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
194 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
195
Richard Henderson9ee3a612018-06-15 14:57:15 +0100196# One register, predicate.
197# User must fill in U and D.
198@incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
199@incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
200 &incdec2_pred rn=%reg_movprfx
201
Richard Hendersonc4e7c492018-06-29 15:11:02 +0100202# Loads; user must fill in NREG.
203@rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
204@rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
205
206@rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
207 &rprr_load dtype=%msz_dtype
208@rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
209 &rpri_load dtype=%msz_dtype
210
Richard Henderson673e9fa2018-06-29 15:11:06 +0100211# Gather Loads.
212@rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
213 &rprr_gather_load xs=2
214@rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
215 &rprr_gather_load
216@rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
217 &rprr_gather_load
218@rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
219 &rprr_gather_load
220@rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
221 &rprr_gather_load xs=2
222@rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
223 &rprr_gather_load xs=2
224@rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
225 &rpri_gather_load
226
Richard Henderson1a039c72018-06-29 15:11:03 +0100227# Stores; user must fill in ESZ, MSZ, NREG as needed.
228@rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
229@rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
230@rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
231 &rprr_store nreg=0
Richard Hendersonf6dbf622018-06-29 15:11:05 +0100232@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
233 &rprr_scatter_store
Richard Henderson408ecde2018-06-29 15:11:07 +0100234@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
235 &rpri_scatter_store
Richard Henderson1a039c72018-06-29 15:11:03 +0100236
Richard Henderson38388f72018-05-18 17:48:08 +0100237###########################################################################
238# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
239
Richard Hendersonf97cfd52018-05-18 17:48:08 +0100240### SVE Integer Arithmetic - Binary Predicated Group
241
242# SVE bitwise logical vector operations (predicated)
243ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
244EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
245AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
246BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
247
248# SVE integer add/subtract vectors (predicated)
249ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
250SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
251SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
252
253# SVE integer min/max/difference (predicated)
254SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
255UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
256SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
257UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
258SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
259UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
260
261# SVE integer multiply/divide (predicated)
262MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
263SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
264UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
265# Note that divide requires size >= 2; below 2 is unallocated.
266SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
267UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
268SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
269UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
270
Richard Henderson047cec92018-05-18 17:48:08 +0100271### SVE Integer Reduction Group
272
273# SVE bitwise logical reduction (predicated)
274ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
275EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
276ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
277
Richard Hendersona2103582018-06-29 15:11:11 +0100278# SVE constructive prefix (predicated)
279MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
280MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
281
Richard Henderson047cec92018-05-18 17:48:08 +0100282# SVE integer add reduction (predicated)
283# Note that saddv requires size != 3.
284UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
285SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
286
287# SVE integer min/max reduction (predicated)
288SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
289UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
290SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
291UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
292
Richard Hendersonccd841c2018-05-18 17:48:08 +0100293### SVE Shift by Immediate - Predicated Group
294
295# SVE bitwise shift by immediate (predicated)
Richard Henderson830d1a52020-08-28 10:02:49 +0100296ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
297LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
298LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
299ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
Richard Hendersonccd841c2018-05-18 17:48:08 +0100300
Richard Henderson27721db2018-05-18 17:48:08 +0100301# SVE bitwise shift by vector (predicated)
302ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
303LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
304LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
305ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
306LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
307LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
308
Richard Hendersonfe7f8df2018-05-18 17:48:08 +0100309# SVE bitwise shift by wide elements (predicated)
310# Note these require size != 3.
311ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
312LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
313LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
314
Richard Hendersonafac6d02018-05-18 17:48:08 +0100315### SVE Integer Arithmetic - Unary Predicated Group
316
317# SVE unary bit operations (predicated)
318# Note esz != 0 for FABS and FNEG.
319CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
320CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
321CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
322CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
323NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
324FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
325FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
326
327# SVE integer unary operations (predicated)
328# Note esz > original size for extensions.
329ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
330NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
331SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
332UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
333SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
334UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
335SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
336UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
337
Richard Hendersonabfdefd2018-06-29 15:11:07 +0100338### SVE Floating Point Compare - Vectors Group
339
340# SVE floating-point compare vectors
341FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
342FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
343FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
344FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
345FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
346FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
347FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
348
Richard Henderson96a36e42018-05-18 17:48:08 +0100349### SVE Integer Multiply-Add Group
350
351# SVE integer multiply-add writing addend (predicated)
352MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
353MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
354
355# SVE integer multiply-add writing multiplicand (predicated)
356MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
357MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
358
Richard Hendersonfea98f92018-05-18 17:48:09 +0100359### SVE Integer Arithmetic - Unpredicated Group
360
361# SVE integer add/subtract vectors (unpredicated)
362ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
363SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
364SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
365UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
366SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
367UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
368
Richard Henderson38388f72018-05-18 17:48:08 +0100369### SVE Logical - Unpredicated Group
370
371# SVE bitwise logical operations (unpredicated)
372AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
373ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
374EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
375BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
Richard Hendersond1822292018-05-18 17:48:08 +0100376
Richard Henderson9a56c9c2018-05-18 17:48:09 +0100377### SVE Index Generation Group
378
379# SVE index generation (immediate start, immediate increment)
380INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
381
382# SVE index generation (immediate start, register increment)
383INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
384
385# SVE index generation (register start, immediate increment)
386INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
387
388# SVE index generation (register start, register increment)
389INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
390
Richard Henderson96f922c2018-05-18 17:48:09 +0100391### SVE Stack Allocation Group
392
393# SVE stack frame adjustment
394ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
395ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
396
397# SVE stack frame size
398RDVL 00000100 101 11111 01010 imm:s6 rd:5
399
Richard Hendersond9d78dc2018-05-18 17:48:09 +0100400### SVE Bitwise Shift - Unpredicated Group
401
402# SVE bitwise shift by immediate (unpredicated)
Richard Henderson830d1a52020-08-28 10:02:49 +0100403ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
404LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
405LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
Richard Hendersond9d78dc2018-05-18 17:48:09 +0100406
407# SVE bitwise shift by wide elements (unpredicated)
408# Note esz != 3
409ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
410LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
411LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
412
Richard Henderson4b242d92018-05-18 17:48:09 +0100413### SVE Compute Vector Address Group
414
415# SVE vector address generation
416ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
417ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
418ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
419ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
420
Richard Henderson0762cd42018-05-18 17:48:09 +0100421### SVE Integer Misc - Unpredicated Group
422
Richard Hendersona2103582018-06-29 15:11:11 +0100423# SVE constructive prefix (unpredicated)
424MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
425
Richard Henderson0762cd42018-05-18 17:48:09 +0100426# SVE floating-point exponential accelerator
427# Note esz != 0
428FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
429
Richard Hendersona1f233f2018-05-18 17:48:09 +0100430# SVE floating-point trig select coefficient
431# Note esz != 0
432FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
433
Richard Henderson24e82e62018-05-18 17:48:09 +0100434### SVE Element Count Group
435
436# SVE element count
437CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
438
439# SVE inc/dec register by element count
440INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
441
442# SVE saturating inc/dec register by element count
443SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
444SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
445
446# SVE inc/dec vector by element count
447# Note this requires esz != 0.
448INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
449
450# SVE saturating inc/dec vector by element count
451# Note these require esz != 0.
452SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
Richard Henderson516e2462018-05-18 17:48:08 +0100453
Richard Hendersone1fa1162018-05-18 17:48:09 +0100454### SVE Bitwise Immediate Group
455
456# SVE bitwise logical with immediate (unpredicated)
457ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
458EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
459AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
460
461# SVE broadcast bitmask immediate
462DUPM 00000101 11 0000 dbm:13 rd:5
463
Richard Hendersonf25a2362018-05-18 17:48:09 +0100464### SVE Integer Wide Immediate - Predicated Group
465
466# SVE copy floating-point immediate (predicated)
467FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
468
469# SVE copy integer immediate (predicated)
470CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
471CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
472
Richard Hendersonb94f8f62018-05-18 17:48:09 +0100473### SVE Permute - Extract Group
474
475# SVE extract vector (immediate offset)
476EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
477 &rrri rn=%reg_movprfx imm=%imm8_16_10
478
Richard Henderson30562ab2018-06-15 14:57:14 +0100479### SVE Permute - Unpredicated Group
480
481# SVE broadcast general register
482DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
483
484# SVE broadcast indexed element
485DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
486 &rri imm=%imm7_22_16
487
488# SVE insert SIMD&FP scalar register
489INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
490
491# SVE insert general register
492INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
493
494# SVE reverse vector elements
495REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
496
497# SVE vector table lookup
498TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
499
500# SVE unpack vector elements
501UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
502
Richard Hendersond731d8cb2018-06-15 14:57:14 +0100503### SVE Permute - Predicates Group
504
505# SVE permute predicate elements
506ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
507ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
508UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
509UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
510TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
511TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
512
513# SVE reverse predicate elements
514REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
515
516# SVE unpack predicate elements
517PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
518PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
519
Richard Henderson234b48e2018-06-15 14:57:14 +0100520### SVE Permute - Interleaving Group
521
522# SVE permute vector elements
523ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
524ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
525UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
526UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
527TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
528TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
529
Richard Henderson3ca879a2018-06-15 14:57:14 +0100530### SVE Permute - Predicated Group
531
532# SVE compress active elements
533# Note esz >= 2
534COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
535
Richard Hendersonef23cb72018-06-15 14:57:14 +0100536# SVE conditionally broadcast element to vector
537CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
538CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
539
540# SVE conditionally copy element to SIMD&FP scalar
541CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
542CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
543
544# SVE conditionally copy element to general register
545CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
546CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
547
548# SVE copy element to SIMD&FP scalar register
549LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
550LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
551
552# SVE copy element to general register
553LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
554LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
555
Richard Henderson792a5572018-06-15 14:57:14 +0100556# SVE copy element from SIMD&FP scalar register
557CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
558
559# SVE copy element from general register to vector (predicated)
560CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
561
Richard Hendersondae8fb92018-06-15 14:57:15 +0100562# SVE reverse within elements
563# Note esz >= operation size
564REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
565REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
566REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
567RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
568
Richard Hendersonb48ff242018-06-15 14:57:15 +0100569# SVE vector splice (predicated)
570SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
571
Richard Hendersond3fe4a22018-06-15 14:57:15 +0100572### SVE Select Vectors Group
573
574# SVE select vector elements (predicated)
575SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
576
Richard Henderson757f9cf2018-06-15 14:57:15 +0100577### SVE Integer Compare - Vectors Group
578
579# SVE integer compare_vectors
580CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
581CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
582CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
583CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
584CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
585CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
586
587# SVE integer compare with wide elements
588# Note these require esz != 3.
589CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
590CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
591CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
592CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
593CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
594CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
595CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
596CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
597CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
598CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
599
Richard Henderson38cadeb2018-06-15 14:57:15 +0100600### SVE Integer Compare - Unsigned Immediate Group
601
602# SVE integer compare with unsigned immediate
603CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
604CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
605CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
606CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
607
608### SVE Integer Compare - Signed Immediate Group
609
610# SVE integer compare with signed immediate
611CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
612CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
613CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
614CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
615CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
616CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
617
Richard Hendersone1fa1162018-05-18 17:48:09 +0100618### SVE Predicate Logical Operations Group
619
Richard Henderson516e2462018-05-18 17:48:08 +0100620# SVE predicate logical operations
621AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
622BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
623EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
624SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
625ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
626ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
627NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
628NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
629
Richard Henderson9e18d7a2018-05-18 17:48:08 +0100630### SVE Predicate Misc Group
631
632# SVE predicate test
633PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
634
Richard Henderson028e2a72018-05-18 17:48:08 +0100635# SVE predicate initialize
636PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
637
638# SVE initialize FFR
639SETFFR 00100101 0010 1100 1001 0000 0000 0000
640
641# SVE zero predicate register
642PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
643
644# SVE predicate read from FFR (predicated)
645RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
646
647# SVE predicate read from FFR (unpredicated)
648RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
649
650# SVE FFR write from predicate (WRFFR)
651WRFFR 00100101 0010 1000 1001 000 rn:4 00000
652
653# SVE predicate first active
654PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
655
656# SVE predicate next active
657PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
658
Richard Henderson35da3162018-06-15 14:57:15 +0100659### SVE Partition Break Group
660
661# SVE propagate break from previous partition
662BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
663BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
664
665# SVE partition break condition
666BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
667BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
Richard Henderson407e6ce2019-01-07 15:23:45 +0000668BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
669BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
Richard Henderson35da3162018-06-15 14:57:15 +0100670
671# SVE propagate break to next partition
672BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
673
Richard Henderson9ee3a612018-06-15 14:57:15 +0100674### SVE Predicate Count Group
675
676# SVE predicate count
677CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
678
679# SVE inc/dec register by predicate count
680INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
681
682# SVE inc/dec vector by predicate count
683INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
684
685# SVE saturating inc/dec register by predicate count
686SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
687SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
688
689# SVE saturating inc/dec vector by predicate count
690SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
691
Richard Hendersoncaf1cef2018-06-15 14:57:15 +0100692### SVE Integer Compare - Scalars Group
693
694# SVE conditionally terminate scalars
695CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
696
697# SVE integer compare scalar count and limit
698WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
699
Richard Hendersoned491962018-06-15 14:57:15 +0100700### SVE Integer Wide Immediate - Unpredicated Group
701
702# SVE broadcast floating-point immediate (unpredicated)
703FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
704
705# SVE broadcast integer immediate (unpredicated)
706DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
707
Richard Henderson6e6a1572018-06-15 14:57:15 +0100708# SVE integer add/subtract immediate (unpredicated)
709ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
710SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
711SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
712SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
713UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
714SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
715UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
716
717# SVE integer min/max immediate (unpredicated)
718SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
719UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
720SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
721UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
722
723# SVE integer multiply immediate (unpredicated)
724MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
725
Richard Hendersond730eca2018-06-29 15:11:13 +0100726# SVE integer dot product (unpredicated)
727DOT_zzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 ra=%reg_movprfx
728
Richard Henderson16fcfdc2018-06-29 15:11:15 +0100729# SVE integer dot product (indexed)
730DOT_zzx 01000100 101 index:2 rm:3 00000 u:1 rn:5 rd:5 \
731 sz=0 ra=%reg_movprfx
732DOT_zzx 01000100 111 index:1 rm:4 00000 u:1 rn:5 rd:5 \
733 sz=1 ra=%reg_movprfx
734
Richard Henderson76a9d9c2018-06-29 15:11:11 +0100735# SVE floating-point complex add (predicated)
736FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \
737 rn=%reg_movprfx
738
Richard Henderson05f48ba2018-06-29 15:11:12 +0100739# SVE floating-point complex multiply-add (predicated)
740FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \
741 ra=%reg_movprfx
742
Richard Henderson18fc2402018-06-29 15:11:12 +0100743# SVE floating-point complex multiply-add (indexed)
744FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \
745 ra=%reg_movprfx esz=1
746FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \
747 ra=%reg_movprfx esz=2
748
Richard Hendersonca40a6e2018-06-29 15:11:08 +0100749### SVE FP Multiply-Add Indexed Group
750
751# SVE floating-point multiply-add (indexed)
752FMLA_zzxz 01100100 0.1 .. rm:3 00000 sub:1 rn:5 rd:5 \
753 ra=%reg_movprfx index=%index3_22_19 esz=1
754FMLA_zzxz 01100100 101 index:2 rm:3 00000 sub:1 rn:5 rd:5 \
755 ra=%reg_movprfx esz=2
756FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \
757 ra=%reg_movprfx esz=3
758
759### SVE FP Multiply Indexed Group
760
761# SVE floating-point multiply (indexed)
762FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
763 index=%index3_22_19 esz=1
764FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2
765FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3
766
Richard Henderson23fbe792018-06-29 15:11:08 +0100767### SVE FP Fast Reduction Group
768
769FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
770FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
771FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
772FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
773FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
774
Richard Henderson3887c032018-06-29 15:11:09 +0100775## SVE Floating Point Unary Operations - Unpredicated Group
776
777FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
778FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
779
Richard Henderson4d2e2a02018-06-29 15:11:09 +0100780### SVE FP Compare with Zero Group
781
782FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
783FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
784FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
785FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
786FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
787FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
788
Richard Henderson7f9ddf62018-06-29 15:11:04 +0100789### SVE FP Accumulating Reduction Group
790
791# SVE floating-point serial reduction (predicated)
792FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
793
Richard Henderson29b80462018-06-15 14:57:15 +0100794### SVE Floating Point Arithmetic - Unpredicated Group
795
796# SVE floating-point arithmetic (unpredicated)
797FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
798FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
799FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
800FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
801FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
802FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
803
Richard Hendersonec3b87c2018-06-29 15:11:04 +0100804### SVE FP Arithmetic Predicated Group
805
806# SVE floating-point arithmetic (predicated)
807FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
808FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
809FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
810FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
811FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
812FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
813FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
814FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
815FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
816FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
817FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
818FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
819FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
820
Richard Hendersoncc48aff2018-06-29 15:11:08 +0100821# SVE floating-point arithmetic with immediate (predicated)
822FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
823FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
824FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
825FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
826FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
827FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
828FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
829FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
830
Richard Henderson67fcd9a2018-06-29 15:11:09 +0100831# SVE floating-point trig multiply-add coefficient
832FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
833
Richard Henderson6ceabaa2018-06-29 15:11:04 +0100834### SVE FP Multiply-Add Group
835
836# SVE floating-point multiply-accumulate writing addend
837FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
838FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
839FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
840FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
841
842# SVE floating-point multiply-accumulate writing multiplicand
843# Alter the operand extraction order and reuse the helpers from above.
844# FMAD, FMSB, FNMAD, FNMS
845FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
846FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
847FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
848FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
849
Richard Henderson8092c6a2018-06-29 15:11:03 +0100850### SVE FP Unary Operations Predicated Group
851
Richard Henderson46d33d12018-06-29 15:11:10 +0100852# SVE floating-point convert precision
853FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
854FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
855FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
856FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
857FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
858FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
859
Richard Hendersondf4de1a2018-06-29 15:11:10 +0100860# SVE floating-point convert to integer
861FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
862FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
863FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
864FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
865FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
866FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
867FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
868FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
869FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
870FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
871FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
872FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
873FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
874FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
875
Richard Hendersoncda3c752018-06-29 15:11:10 +0100876# SVE floating-point round to integral value
877FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
878FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
879FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
880FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
881FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
882FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
883FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
884
Richard Hendersonec5b3752018-06-29 15:11:11 +0100885# SVE floating-point unary operations
886FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
887FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
888
Richard Henderson8092c6a2018-06-29 15:11:03 +0100889# SVE integer convert to floating-point
890SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
891SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
892SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
893SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
894SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
895SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
896SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
897
898UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
899UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
900UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
901UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
902UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
903UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
904UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
905
Richard Hendersond1822292018-05-18 17:48:08 +0100906### SVE Memory - 32-bit Gather and Unsized Contiguous Group
907
908# SVE load predicate register
909LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
910
911# SVE load vector register
912LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
Richard Hendersonc4e7c492018-06-29 15:11:02 +0100913
Richard Henderson68459862018-06-29 15:11:05 +0100914# SVE load and broadcast element
915LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
916 &rpri_load dtype=%dtype_23_13 nreg=0
917
Richard Henderson673e9fa2018-06-29 15:11:06 +0100918# SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
919# SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
920LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
921 @rprr_g_load_xs_u esz=2 msz=0 scale=0
922LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
923 @rprr_g_load_xs_u_sc esz=2 msz=1
924LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
925 @rprr_g_load_xs_sc esz=2 msz=2 u=1
926
927# SVE 32-bit gather load (vector plus immediate)
928LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
929 @rpri_g_load esz=2
930
Richard Hendersonc4e7c492018-06-29 15:11:02 +0100931### SVE Memory Contiguous Load Group
932
933# SVE contiguous load (scalar plus scalar)
934LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
935
Richard Hendersone2654d72018-06-29 15:11:02 +0100936# SVE contiguous first-fault load (scalar plus scalar)
937LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
938
Richard Hendersonc4e7c492018-06-29 15:11:02 +0100939# SVE contiguous load (scalar plus immediate)
940LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
941
Richard Hendersone2654d72018-06-29 15:11:02 +0100942# SVE contiguous non-fault load (scalar plus immediate)
943LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
944
Richard Hendersonc4e7c492018-06-29 15:11:02 +0100945# SVE contiguous non-temporal load (scalar plus scalar)
946# LDNT1B, LDNT1H, LDNT1W, LDNT1D
947# SVE load multiple structures (scalar plus scalar)
948# LD2B, LD2H, LD2W, LD2D; etc.
949LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
950
951# SVE contiguous non-temporal load (scalar plus immediate)
952# LDNT1B, LDNT1H, LDNT1W, LDNT1D
953# SVE load multiple structures (scalar plus immediate)
954# LD2B, LD2H, LD2W, LD2D; etc.
955LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
Richard Henderson1a039c72018-06-29 15:11:03 +0100956
Richard Henderson05abe302018-06-29 15:11:03 +0100957# SVE load and broadcast quadword (scalar plus scalar)
958LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
959 @rprr_load_msz nreg=0
960
961# SVE load and broadcast quadword (scalar plus immediate)
962# LD1RQB, LD1RQH, LD1RQS, LD1RQD
963LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
964 @rpri_load_msz nreg=0
965
Richard Hendersondec6cf62018-06-29 15:11:06 +0100966# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
967PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
968
969# SVE 32-bit gather prefetch (vector plus immediate)
970PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
971
972# SVE contiguous prefetch (scalar plus immediate)
973PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
974
975# SVE contiguous prefetch (scalar plus scalar)
976PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
977
978### SVE Memory 64-bit Gather Group
979
Richard Henderson673e9fa2018-06-29 15:11:06 +0100980# SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
981# SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
982LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
983 @rprr_g_load_xs_u esz=3 msz=0 scale=0
984LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
985 @rprr_g_load_xs_u_sc esz=3 msz=1
986LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
987 @rprr_g_load_xs_u_sc esz=3 msz=2
988LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
989 @rprr_g_load_xs_sc esz=3 msz=3 u=1
990
991# SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
992# SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
993LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
994 @rprr_g_load_u esz=3 msz=0 scale=0
995LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
996 @rprr_g_load_u_sc esz=3 msz=1
997LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
998 @rprr_g_load_u_sc esz=3 msz=2
999LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
1000 @rprr_g_load_sc esz=3 msz=3 u=1
1001
1002# SVE 64-bit gather load (vector plus immediate)
1003LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
1004 @rpri_g_load esz=3
1005
Richard Hendersondec6cf62018-06-29 15:11:06 +01001006# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
1007PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
1008
1009# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
1010PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
1011
1012# SVE 64-bit gather prefetch (vector plus immediate)
1013PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
1014
Richard Henderson1a039c72018-06-29 15:11:03 +01001015### SVE Memory Store Group
1016
Richard Henderson5047c202018-06-29 15:11:05 +01001017# SVE store predicate register
1018STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
1019
1020# SVE store vector register
1021STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
1022
Richard Henderson1a039c72018-06-29 15:11:03 +01001023# SVE contiguous store (scalar plus immediate)
1024# ST1B, ST1H, ST1W, ST1D; require msz <= esz
1025ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
1026 @rpri_store_msz nreg=0
1027
1028# SVE contiguous store (scalar plus scalar)
1029# ST1B, ST1H, ST1W, ST1D; require msz <= esz
1030# Enumerate msz lest we conflict with STR_zri.
1031ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
1032 @rprr_store_esz_n0 msz=0
1033ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
1034 @rprr_store_esz_n0 msz=1
1035ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
1036 @rprr_store_esz_n0 msz=2
1037ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
1038 @rprr_store msz=3 esz=3 nreg=0
1039
1040# SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
1041# SVE store multiple structures (scalar plus immediate) (nreg != 0)
1042ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
1043 @rpri_store_msz esz=%size_23
1044
1045# SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
1046# SVE store multiple structures (scalar plus scalar) (nreg != 0)
1047ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
1048 @rprr_store esz=%size_23
Richard Hendersonf6dbf622018-06-29 15:11:05 +01001049
1050# SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
1051# Require msz > 0 && msz <= esz.
1052ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
1053 @rprr_scatter_store xs=0 esz=2 scale=1
1054ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
1055 @rprr_scatter_store xs=1 esz=2 scale=1
1056
1057# SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
1058# Require msz <= esz.
1059ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
1060 @rprr_scatter_store xs=0 esz=2 scale=0
1061ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
1062 @rprr_scatter_store xs=1 esz=2 scale=0
1063
1064# SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
1065# Require msz > 0
1066ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
1067 @rprr_scatter_store xs=2 esz=3 scale=1
1068
1069# SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
1070ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
1071 @rprr_scatter_store xs=2 esz=3 scale=0
1072
Richard Henderson408ecde2018-06-29 15:11:07 +01001073# SVE 64-bit scatter store (vector plus immediate)
1074ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
1075 @rpri_scatter_store esz=3
1076
1077# SVE 32-bit scatter store (vector plus immediate)
1078ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
1079 @rpri_scatter_store esz=2
1080
Richard Hendersonf6dbf622018-06-29 15:11:05 +01001081# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
1082# Require msz > 0
1083ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
1084 @rprr_scatter_store xs=0 esz=3 scale=1
1085ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
1086 @rprr_scatter_store xs=1 esz=3 scale=1
1087
1088# SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
1089ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
1090 @rprr_scatter_store xs=0 esz=3 scale=0
1091ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
1092 @rprr_scatter_store xs=1 esz=3 scale=0