| Yodel Eldar | 5a28fa5 | 2025-07-10 11:45:27 +0100 | [diff] [blame] | 1 | <?xml version="1.0"?> |
| 2 | <!-- Copyright (C) 2025 Free Software Foundation, Inc. |
| 3 | |
| 4 | Copying and distribution of this file, with or without modification, |
| 5 | are permitted in any medium without royalty provided the copyright |
| 6 | notice and this notice are preserved. --> |
| 7 | |
| 8 | <!DOCTYPE feature SYSTEM "gdb-target.dtd"> |
| 9 | <feature name="org.gnu.gdb.alpha.core"> |
| 10 | <!-- IEEE rounding mode values --> |
| 11 | <enum id="dyn_rm_enum" size="8"> |
| 12 | <!-- Chopped rounding mode --> |
| 13 | <evalue name="chop" value="0"/> |
| 14 | <!-- Minus infinity --> |
| 15 | <evalue name="-inf" value="1"/> |
| 16 | <!-- Normal rounding --> |
| 17 | <evalue name="norm" value="2"/> |
| 18 | <!-- Plus infinity --> |
| 19 | <evalue name="+inf" value="3"/> |
| 20 | </enum> |
| 21 | |
| 22 | <!-- Floating-Point Control Register Flags --> |
| 23 | <flags id="fpcr_flags" size="8"> |
| 24 | <!-- Denormal Operand Exception Disable --> |
| 25 | <field name="DNOD" start="47" end="47"/> |
| 26 | <!-- Denormal Operands to Zero --> |
| 27 | <field name="DNZ" start="48" end="48"/> |
| 28 | <!-- Invalid Operation Disable --> |
| 29 | <field name="INVD" start="49" end="49"/> |
| 30 | <!-- Division by Zero Disable --> |
| 31 | <field name="DZED" start="50" end="50"/> |
| 32 | <!-- Overflow Disable --> |
| 33 | <field name="OVFD" start="51" end="51"/> |
| 34 | <!-- Invalid Operation --> |
| 35 | <field name="INV" start="52" end="52"/> |
| 36 | <!-- Division by Zero --> |
| 37 | <field name="DZE" start="53" end="53"/> |
| 38 | <!-- Overflow --> |
| 39 | <field name="OVF" start="54" end="54"/> |
| 40 | <!-- Underflow --> |
| 41 | <field name="UNF" start="55" end="55"/> |
| 42 | <!-- Inexact Result --> |
| 43 | <field name="INE" start="56" end="56"/> |
| 44 | <!-- Integer Overflow --> |
| 45 | <field name="IOV" start="57" end="57"/> |
| 46 | <!-- Dynamic Rounding Mode --> |
| 47 | <field name="DYN_RM" start="58" end="59" type="dyn_rm_enum"/> |
| 48 | <!-- Underflow to Zero --> |
| 49 | <field name="UNDZ" start="60" end="60"/> |
| 50 | <!-- Underflow Disable --> |
| 51 | <field name="UNFD" start="61" end="61"/> |
| 52 | <!-- Inexact Disable --> |
| 53 | <field name="INED" start="62" end="62"/> |
| 54 | <!-- Summary Bit --> |
| 55 | <field name="SUM" start="63" end="63"/> |
| 56 | </flags> |
| 57 | |
| 58 | <!-- Integer Registers --> |
| 59 | <reg name="v0" bitsize="64" type="int64"/> |
| 60 | <reg name="t0" bitsize="64" type="int64"/> |
| 61 | <reg name="t1" bitsize="64" type="int64"/> |
| 62 | <reg name="t2" bitsize="64" type="int64"/> |
| 63 | <reg name="t3" bitsize="64" type="int64"/> |
| 64 | <reg name="t4" bitsize="64" type="int64"/> |
| 65 | <reg name="t5" bitsize="64" type="int64"/> |
| 66 | <reg name="t6" bitsize="64" type="int64"/> |
| 67 | <reg name="t7" bitsize="64" type="int64"/> |
| 68 | <reg name="s0" bitsize="64" type="int64"/> |
| 69 | <reg name="s1" bitsize="64" type="int64"/> |
| 70 | <reg name="s2" bitsize="64" type="int64"/> |
| 71 | <reg name="s3" bitsize="64" type="int64"/> |
| 72 | <reg name="s4" bitsize="64" type="int64"/> |
| 73 | <reg name="s5" bitsize="64" type="int64"/> |
| 74 | <reg name="fp" bitsize="64" type="int64"/> |
| 75 | <reg name="a0" bitsize="64" type="int64"/> |
| 76 | <reg name="a1" bitsize="64" type="int64"/> |
| 77 | <reg name="a2" bitsize="64" type="int64"/> |
| 78 | <reg name="a3" bitsize="64" type="int64"/> |
| 79 | <reg name="a4" bitsize="64" type="int64"/> |
| 80 | <reg name="a5" bitsize="64" type="int64"/> |
| 81 | <reg name="t8" bitsize="64" type="int64"/> |
| 82 | <reg name="t9" bitsize="64" type="int64"/> |
| 83 | <reg name="t10" bitsize="64" type="int64"/> |
| 84 | <reg name="t11" bitsize="64" type="int64"/> |
| 85 | <reg name="ra" bitsize="64" type="int64"/> |
| 86 | <reg name="t12" bitsize="64" type="int64"/> |
| 87 | <reg name="at" bitsize="64" type="int64"/> |
| 88 | <reg name="gp" bitsize="64" type="data_ptr"/> |
| 89 | <reg name="sp" bitsize="64" type="data_ptr"/> |
| 90 | <reg name="zero" bitsize="64" type="int64" save-restore="no"/> |
| 91 | |
| 92 | <!-- Floating-Point Registers --> |
| 93 | <reg name="f0" bitsize="64" type="float" group="float"/> |
| 94 | <reg name="f1" bitsize="64" type="float" group="float"/> |
| 95 | <reg name="f2" bitsize="64" type="float" group="float"/> |
| 96 | <reg name="f3" bitsize="64" type="float" group="float"/> |
| 97 | <reg name="f4" bitsize="64" type="float" group="float"/> |
| 98 | <reg name="f5" bitsize="64" type="float" group="float"/> |
| 99 | <reg name="f6" bitsize="64" type="float" group="float"/> |
| 100 | <reg name="f7" bitsize="64" type="float" group="float"/> |
| 101 | <reg name="f8" bitsize="64" type="float" group="float"/> |
| 102 | <reg name="f9" bitsize="64" type="float" group="float"/> |
| 103 | <reg name="f10" bitsize="64" type="float" group="float"/> |
| 104 | <reg name="f11" bitsize="64" type="float" group="float"/> |
| 105 | <reg name="f12" bitsize="64" type="float" group="float"/> |
| 106 | <reg name="f13" bitsize="64" type="float" group="float"/> |
| 107 | <reg name="f14" bitsize="64" type="float" group="float"/> |
| 108 | <reg name="f15" bitsize="64" type="float" group="float"/> |
| 109 | <reg name="f16" bitsize="64" type="float" group="float"/> |
| 110 | <reg name="f17" bitsize="64" type="float" group="float"/> |
| 111 | <reg name="f18" bitsize="64" type="float" group="float"/> |
| 112 | <reg name="f19" bitsize="64" type="float" group="float"/> |
| 113 | <reg name="f20" bitsize="64" type="float" group="float"/> |
| 114 | <reg name="f21" bitsize="64" type="float" group="float"/> |
| 115 | <reg name="f22" bitsize="64" type="float" group="float"/> |
| 116 | <reg name="f23" bitsize="64" type="float" group="float"/> |
| 117 | <reg name="f24" bitsize="64" type="float" group="float"/> |
| 118 | <reg name="f25" bitsize="64" type="float" group="float"/> |
| 119 | <reg name="f26" bitsize="64" type="float" group="float"/> |
| 120 | <reg name="f27" bitsize="64" type="float" group="float"/> |
| 121 | <reg name="f28" bitsize="64" type="float" group="float"/> |
| 122 | <reg name="f29" bitsize="64" type="float" group="float"/> |
| 123 | <reg name="f30" bitsize="64" type="float" group="float"/> |
| 124 | |
| 125 | <!-- Floating-Point Control Register --> |
| 126 | <reg name="fpcr" bitsize="64" type="fpcr_flags" group="float"/> |
| 127 | |
| 128 | <!-- Program Counter --> |
| 129 | <reg name="pc" bitsize="64" type="code_ptr"/> |
| 130 | |
| 131 | <!-- Reserved Index for Former Virtual Register --> |
| 132 | <reg name="" bitsize="64" type="int64" save-restore="no"/> |
| 133 | |
| 134 | <!-- PALcode Memory Slot --> |
| 135 | <reg name="unique" bitsize="64" type="int64" group="system"/> |
| 136 | </feature> |