blob: 0e32830a877754a49578e648e9d0c3e20503f227 [file] [log] [blame]
bellard420557e2004-09-30 22:13:50 +00001/*
bellard6f7e9ae2005-03-13 09:43:36 +00002 * QEMU TCX Frame buffer
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard6f7e9ae2005-03-13 09:43:36 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard420557e2004-09-30 22:13:50 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Blue Swirlf40070c2009-07-12 19:21:36 +000024
pbrook87ecb682007-11-17 17:14:51 +000025#include "console.h"
blueswir194470842007-06-10 16:06:20 +000026#include "pixel_ops.h"
Blue Swirlf40070c2009-07-12 19:21:36 +000027#include "sysbus.h"
Gerd Hoffmannee6847d2009-07-15 13:43:31 +020028#include "qdev-addr.h"
bellard420557e2004-09-30 22:13:50 +000029
bellard420557e2004-09-30 22:13:50 +000030#define MAXX 1024
31#define MAXY 768
bellard6f7e9ae2005-03-13 09:43:36 +000032#define TCX_DAC_NREGS 16
blueswir18508b892007-05-06 17:39:55 +000033#define TCX_THC_NREGS_8 0x081c
34#define TCX_THC_NREGS_24 0x1000
35#define TCX_TEC_NREGS 0x1000
bellard420557e2004-09-30 22:13:50 +000036
bellard420557e2004-09-30 22:13:50 +000037typedef struct TCXState {
Blue Swirlf40070c2009-07-12 19:21:36 +000038 SysBusDevice busdev;
Anthony Liguoric227f092009-10-01 16:12:16 -050039 target_phys_addr_t addr;
bellard420557e2004-09-30 22:13:50 +000040 DisplayState *ds;
bellard8d5f07f2004-10-04 21:23:09 +000041 uint8_t *vram;
blueswir1eee0b832007-04-21 19:45:49 +000042 uint32_t *vram24, *cplane;
Anthony Liguoric227f092009-10-01 16:12:16 -050043 ram_addr_t vram_offset, vram24_offset, cplane_offset;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +020044 uint32_t vram_size;
blueswir1eee0b832007-04-21 19:45:49 +000045 uint16_t width, height, depth;
bellarde80cfcf2004-12-19 23:18:01 +000046 uint8_t r[256], g[256], b[256];
bellard21206a12006-09-09 11:31:34 +000047 uint32_t palette[256];
bellard6f7e9ae2005-03-13 09:43:36 +000048 uint8_t dac_index, dac_state;
bellard420557e2004-09-30 22:13:50 +000049} TCXState;
50
pbrook95219892006-04-09 01:06:34 +000051static void tcx_screen_dump(void *opaque, const char *filename);
blueswir1eee0b832007-04-21 19:45:49 +000052static void tcx24_screen_dump(void *opaque, const char *filename);
Blue Swirld3ffcaf2009-07-16 13:45:57 +000053
54static void tcx_set_dirty(TCXState *s)
55{
56 unsigned int i;
57
58 for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) {
59 cpu_physical_memory_set_dirty(s->vram_offset + i);
60 }
61}
62
63static void tcx24_set_dirty(TCXState *s)
64{
65 unsigned int i;
66
67 for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) {
68 cpu_physical_memory_set_dirty(s->vram24_offset + i);
69 cpu_physical_memory_set_dirty(s->cplane_offset + i);
70 }
71}
pbrook95219892006-04-09 01:06:34 +000072
bellard21206a12006-09-09 11:31:34 +000073static void update_palette_entries(TCXState *s, int start, int end)
74{
75 int i;
76 for(i = start; i < end; i++) {
aliguori0e1f5a02008-11-24 19:29:13 +000077 switch(ds_get_bits_per_pixel(s->ds)) {
bellard21206a12006-09-09 11:31:34 +000078 default:
79 case 8:
80 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
81 break;
82 case 15:
aliguori8927bcf2009-01-15 22:07:16 +000083 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000084 break;
85 case 16:
aliguori8927bcf2009-01-15 22:07:16 +000086 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000087 break;
88 case 32:
aliguori7b5d76d2009-03-13 15:02:13 +000089 if (is_surface_bgr(s->ds->surface))
90 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
91 else
92 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
bellard21206a12006-09-09 11:31:34 +000093 break;
94 }
95 }
Blue Swirld3ffcaf2009-07-16 13:45:57 +000096 if (s->depth == 24) {
97 tcx24_set_dirty(s);
98 } else {
99 tcx_set_dirty(s);
100 }
bellard21206a12006-09-09 11:31:34 +0000101}
102
ths5fafdf22007-09-16 21:08:06 +0000103static void tcx_draw_line32(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000104 const uint8_t *s, int width)
bellard420557e2004-09-30 22:13:50 +0000105{
bellarde80cfcf2004-12-19 23:18:01 +0000106 int x;
107 uint8_t val;
ths8bdc2152006-12-21 17:24:45 +0000108 uint32_t *p = (uint32_t *)d;
bellarde80cfcf2004-12-19 23:18:01 +0000109
110 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000111 val = *s++;
ths8bdc2152006-12-21 17:24:45 +0000112 *p++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000113 }
bellard420557e2004-09-30 22:13:50 +0000114}
115
ths5fafdf22007-09-16 21:08:06 +0000116static void tcx_draw_line16(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000117 const uint8_t *s, int width)
bellarde80cfcf2004-12-19 23:18:01 +0000118{
119 int x;
120 uint8_t val;
ths8bdc2152006-12-21 17:24:45 +0000121 uint16_t *p = (uint16_t *)d;
bellard8d5f07f2004-10-04 21:23:09 +0000122
bellarde80cfcf2004-12-19 23:18:01 +0000123 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000124 val = *s++;
ths8bdc2152006-12-21 17:24:45 +0000125 *p++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000126 }
127}
128
ths5fafdf22007-09-16 21:08:06 +0000129static void tcx_draw_line8(TCXState *s1, uint8_t *d,
blueswir1f930d072007-10-06 11:28:21 +0000130 const uint8_t *s, int width)
bellarde80cfcf2004-12-19 23:18:01 +0000131{
132 int x;
133 uint8_t val;
134
135 for(x = 0; x < width; x++) {
blueswir1f930d072007-10-06 11:28:21 +0000136 val = *s++;
bellard21206a12006-09-09 11:31:34 +0000137 *d++ = s1->palette[val];
bellarde80cfcf2004-12-19 23:18:01 +0000138 }
139}
140
blueswir1688ea2e2008-07-24 11:26:38 +0000141/*
142 XXX Could be much more optimal:
143 * detect if line/page/whole screen is in 24 bit mode
144 * if destination is also BGR, use memcpy
145 */
blueswir1eee0b832007-04-21 19:45:49 +0000146static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
147 const uint8_t *s, int width,
148 const uint32_t *cplane,
149 const uint32_t *s24)
150{
aliguori7b5d76d2009-03-13 15:02:13 +0000151 int x, bgr, r, g, b;
blueswir1688ea2e2008-07-24 11:26:38 +0000152 uint8_t val, *p8;
blueswir1eee0b832007-04-21 19:45:49 +0000153 uint32_t *p = (uint32_t *)d;
154 uint32_t dval;
155
aliguori7b5d76d2009-03-13 15:02:13 +0000156 bgr = is_surface_bgr(s1->ds->surface);
blueswir1eee0b832007-04-21 19:45:49 +0000157 for(x = 0; x < width; x++, s++, s24++) {
blueswir1688ea2e2008-07-24 11:26:38 +0000158 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
159 // 24-bit direct, BGR order
160 p8 = (uint8_t *)s24;
161 p8++;
162 b = *p8++;
163 g = *p8++;
Blue Swirlf7e683b2010-01-13 18:58:51 +0000164 r = *p8;
aliguori7b5d76d2009-03-13 15:02:13 +0000165 if (bgr)
166 dval = rgb_to_pixel32bgr(r, g, b);
167 else
168 dval = rgb_to_pixel32(r, g, b);
blueswir1eee0b832007-04-21 19:45:49 +0000169 } else {
170 val = *s;
171 dval = s1->palette[val];
172 }
173 *p++ = dval;
174 }
175}
176
Anthony Liguoric227f092009-10-01 16:12:16 -0500177static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
178 ram_addr_t cpage)
blueswir1eee0b832007-04-21 19:45:49 +0000179{
180 int ret;
181 unsigned int off;
182
183 ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
184 for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
185 ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
186 ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
187 }
188 return ret;
189}
190
Anthony Liguoric227f092009-10-01 16:12:16 -0500191static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
192 ram_addr_t page_max, ram_addr_t page24,
193 ram_addr_t cpage)
blueswir1eee0b832007-04-21 19:45:49 +0000194{
195 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
196 VGA_DIRTY_FLAG);
197 page_min -= ts->vram_offset;
198 page_max -= ts->vram_offset;
199 cpu_physical_memory_reset_dirty(page24 + page_min * 4,
200 page24 + page_max * 4 + TARGET_PAGE_SIZE,
201 VGA_DIRTY_FLAG);
202 cpu_physical_memory_reset_dirty(cpage + page_min * 4,
203 cpage + page_max * 4 + TARGET_PAGE_SIZE,
204 VGA_DIRTY_FLAG);
205}
206
bellarde80cfcf2004-12-19 23:18:01 +0000207/* Fixed line length 1024 allows us to do nice tricks not possible on
208 VGA... */
pbrook95219892006-04-09 01:06:34 +0000209static void tcx_update_display(void *opaque)
bellarde80cfcf2004-12-19 23:18:01 +0000210{
211 TCXState *ts = opaque;
Anthony Liguoric227f092009-10-01 16:12:16 -0500212 ram_addr_t page, page_min, page_max;
bellard550be122006-08-02 22:19:33 +0000213 int y, y_start, dd, ds;
bellarde80cfcf2004-12-19 23:18:01 +0000214 uint8_t *d, *s;
blueswir1b3ceef22007-06-25 19:56:13 +0000215 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
bellarde80cfcf2004-12-19 23:18:01 +0000216
aliguori0e1f5a02008-11-24 19:29:13 +0000217 if (ds_get_bits_per_pixel(ts->ds) == 0)
blueswir1f930d072007-10-06 11:28:21 +0000218 return;
bellard6f7e9ae2005-03-13 09:43:36 +0000219 page = ts->vram_offset;
bellarde80cfcf2004-12-19 23:18:01 +0000220 y_start = -1;
Blue Swirlc0c440f2009-04-27 18:10:37 +0000221 page_min = -1;
bellard550be122006-08-02 22:19:33 +0000222 page_max = 0;
aliguori0e1f5a02008-11-24 19:29:13 +0000223 d = ds_get_data(ts->ds);
bellard6f7e9ae2005-03-13 09:43:36 +0000224 s = ts->vram;
aliguori0e1f5a02008-11-24 19:29:13 +0000225 dd = ds_get_linesize(ts->ds);
bellarde80cfcf2004-12-19 23:18:01 +0000226 ds = 1024;
227
aliguori0e1f5a02008-11-24 19:29:13 +0000228 switch (ds_get_bits_per_pixel(ts->ds)) {
bellarde80cfcf2004-12-19 23:18:01 +0000229 case 32:
blueswir1f930d072007-10-06 11:28:21 +0000230 f = tcx_draw_line32;
231 break;
bellard21206a12006-09-09 11:31:34 +0000232 case 15:
233 case 16:
blueswir1f930d072007-10-06 11:28:21 +0000234 f = tcx_draw_line16;
235 break;
bellarde80cfcf2004-12-19 23:18:01 +0000236 default:
237 case 8:
blueswir1f930d072007-10-06 11:28:21 +0000238 f = tcx_draw_line8;
239 break;
bellarde80cfcf2004-12-19 23:18:01 +0000240 case 0:
blueswir1f930d072007-10-06 11:28:21 +0000241 return;
bellarde80cfcf2004-12-19 23:18:01 +0000242 }
ths3b46e622007-09-17 08:09:54 +0000243
bellard6f7e9ae2005-03-13 09:43:36 +0000244 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
blueswir1f930d072007-10-06 11:28:21 +0000245 if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
246 if (y_start < 0)
bellarde80cfcf2004-12-19 23:18:01 +0000247 y_start = y;
248 if (page < page_min)
249 page_min = page;
250 if (page > page_max)
251 page_max = page;
blueswir1f930d072007-10-06 11:28:21 +0000252 f(ts, d, s, ts->width);
253 d += dd;
254 s += ds;
255 f(ts, d, s, ts->width);
256 d += dd;
257 s += ds;
258 f(ts, d, s, ts->width);
259 d += dd;
260 s += ds;
261 f(ts, d, s, ts->width);
262 d += dd;
263 s += ds;
264 } else {
bellarde80cfcf2004-12-19 23:18:01 +0000265 if (y_start >= 0) {
266 /* flush to display */
ths5fafdf22007-09-16 21:08:06 +0000267 dpy_update(ts->ds, 0, y_start,
bellard6f7e9ae2005-03-13 09:43:36 +0000268 ts->width, y - y_start);
bellarde80cfcf2004-12-19 23:18:01 +0000269 y_start = -1;
270 }
blueswir1f930d072007-10-06 11:28:21 +0000271 d += dd * 4;
272 s += ds * 4;
273 }
bellarde80cfcf2004-12-19 23:18:01 +0000274 }
275 if (y_start >= 0) {
blueswir1f930d072007-10-06 11:28:21 +0000276 /* flush to display */
277 dpy_update(ts->ds, 0, y_start,
278 ts->width, y - y_start);
bellarde80cfcf2004-12-19 23:18:01 +0000279 }
280 /* reset modified pages */
Blue Swirlc0c440f2009-04-27 18:10:37 +0000281 if (page_max >= page_min) {
bellard0a962c02005-02-10 22:00:27 +0000282 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
283 VGA_DIRTY_FLAG);
bellarde80cfcf2004-12-19 23:18:01 +0000284 }
285}
286
blueswir1eee0b832007-04-21 19:45:49 +0000287static void tcx24_update_display(void *opaque)
288{
289 TCXState *ts = opaque;
Anthony Liguoric227f092009-10-01 16:12:16 -0500290 ram_addr_t page, page_min, page_max, cpage, page24;
blueswir1eee0b832007-04-21 19:45:49 +0000291 int y, y_start, dd, ds;
292 uint8_t *d, *s;
293 uint32_t *cptr, *s24;
294
aliguori0e1f5a02008-11-24 19:29:13 +0000295 if (ds_get_bits_per_pixel(ts->ds) != 32)
blueswir1eee0b832007-04-21 19:45:49 +0000296 return;
297 page = ts->vram_offset;
298 page24 = ts->vram24_offset;
299 cpage = ts->cplane_offset;
300 y_start = -1;
Blue Swirlc0c440f2009-04-27 18:10:37 +0000301 page_min = -1;
blueswir1eee0b832007-04-21 19:45:49 +0000302 page_max = 0;
aliguori0e1f5a02008-11-24 19:29:13 +0000303 d = ds_get_data(ts->ds);
blueswir1eee0b832007-04-21 19:45:49 +0000304 s = ts->vram;
305 s24 = ts->vram24;
306 cptr = ts->cplane;
aliguori0e1f5a02008-11-24 19:29:13 +0000307 dd = ds_get_linesize(ts->ds);
blueswir1eee0b832007-04-21 19:45:49 +0000308 ds = 1024;
309
310 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
311 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
blueswir122548762008-05-10 10:12:00 +0000312 if (check_dirty(page, page24, cpage)) {
blueswir1eee0b832007-04-21 19:45:49 +0000313 if (y_start < 0)
314 y_start = y;
315 if (page < page_min)
316 page_min = page;
317 if (page > page_max)
318 page_max = page;
319 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
320 d += dd;
321 s += ds;
322 cptr += ds;
323 s24 += ds;
324 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
325 d += dd;
326 s += ds;
327 cptr += ds;
328 s24 += ds;
329 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
330 d += dd;
331 s += ds;
332 cptr += ds;
333 s24 += ds;
334 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
335 d += dd;
336 s += ds;
337 cptr += ds;
338 s24 += ds;
339 } else {
340 if (y_start >= 0) {
341 /* flush to display */
342 dpy_update(ts->ds, 0, y_start,
343 ts->width, y - y_start);
344 y_start = -1;
345 }
346 d += dd * 4;
347 s += ds * 4;
348 cptr += ds * 4;
349 s24 += ds * 4;
350 }
351 }
352 if (y_start >= 0) {
353 /* flush to display */
354 dpy_update(ts->ds, 0, y_start,
355 ts->width, y - y_start);
356 }
357 /* reset modified pages */
Blue Swirlc0c440f2009-04-27 18:10:37 +0000358 if (page_max >= page_min) {
blueswir1eee0b832007-04-21 19:45:49 +0000359 reset_dirty(ts, page_min, page_max, page24, cpage);
360 }
361}
362
pbrook95219892006-04-09 01:06:34 +0000363static void tcx_invalidate_display(void *opaque)
bellard420557e2004-09-30 22:13:50 +0000364{
365 TCXState *s = opaque;
bellard420557e2004-09-30 22:13:50 +0000366
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000367 tcx_set_dirty(s);
368 qemu_console_resize(s->ds, s->width, s->height);
bellarde80cfcf2004-12-19 23:18:01 +0000369}
370
blueswir1eee0b832007-04-21 19:45:49 +0000371static void tcx24_invalidate_display(void *opaque)
372{
373 TCXState *s = opaque;
blueswir1eee0b832007-04-21 19:45:49 +0000374
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000375 tcx_set_dirty(s);
376 tcx24_set_dirty(s);
377 qemu_console_resize(s->ds, s->width, s->height);
blueswir1eee0b832007-04-21 19:45:49 +0000378}
379
Juan Quintelae59fb372009-09-29 22:48:21 +0200380static int vmstate_tcx_post_load(void *opaque, int version_id)
bellarde80cfcf2004-12-19 23:18:01 +0000381{
382 TCXState *s = opaque;
ths3b46e622007-09-17 08:09:54 +0000383
bellard21206a12006-09-09 11:31:34 +0000384 update_palette_entries(s, 0, 256);
Blue Swirld3ffcaf2009-07-16 13:45:57 +0000385 if (s->depth == 24) {
386 tcx24_set_dirty(s);
387 } else {
388 tcx_set_dirty(s);
389 }
blueswir15425a212007-04-13 19:24:07 +0000390
bellard420557e2004-09-30 22:13:50 +0000391 return 0;
392}
393
Blue Swirlc0c41a42009-08-28 20:43:01 +0000394static const VMStateDescription vmstate_tcx = {
395 .name ="tcx",
396 .version_id = 4,
397 .minimum_version_id = 4,
398 .minimum_version_id_old = 4,
Juan Quintela752ff2f2009-09-10 03:04:30 +0200399 .post_load = vmstate_tcx_post_load,
Blue Swirlc0c41a42009-08-28 20:43:01 +0000400 .fields = (VMStateField []) {
401 VMSTATE_UINT16(height, TCXState),
402 VMSTATE_UINT16(width, TCXState),
403 VMSTATE_UINT16(depth, TCXState),
404 VMSTATE_BUFFER(r, TCXState),
405 VMSTATE_BUFFER(g, TCXState),
406 VMSTATE_BUFFER(b, TCXState),
407 VMSTATE_UINT8(dac_index, TCXState),
408 VMSTATE_UINT8(dac_state, TCXState),
409 VMSTATE_END_OF_LIST()
410 }
411};
412
Michael S. Tsirkin7f23f812009-09-16 13:40:27 +0300413static void tcx_reset(DeviceState *d)
bellard420557e2004-09-30 22:13:50 +0000414{
Michael S. Tsirkin7f23f812009-09-16 13:40:27 +0300415 TCXState *s = container_of(d, TCXState, busdev.qdev);
bellard420557e2004-09-30 22:13:50 +0000416
bellarde80cfcf2004-12-19 23:18:01 +0000417 /* Initialize palette */
418 memset(s->r, 0, 256);
419 memset(s->g, 0, 256);
420 memset(s->b, 0, 256);
421 s->r[255] = s->g[255] = s->b[255] = 255;
bellard21206a12006-09-09 11:31:34 +0000422 update_palette_entries(s, 0, 256);
bellarde80cfcf2004-12-19 23:18:01 +0000423 memset(s->vram, 0, MAXX*MAXY);
blueswir1eee0b832007-04-21 19:45:49 +0000424 cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
425 MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
bellard6f7e9ae2005-03-13 09:43:36 +0000426 s->dac_index = 0;
427 s->dac_state = 0;
bellard420557e2004-09-30 22:13:50 +0000428}
429
Anthony Liguoric227f092009-10-01 16:12:16 -0500430static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
bellard6f7e9ae2005-03-13 09:43:36 +0000431{
432 return 0;
433}
434
Anthony Liguoric227f092009-10-01 16:12:16 -0500435static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
bellard6f7e9ae2005-03-13 09:43:36 +0000436{
437 TCXState *s = opaque;
bellard6f7e9ae2005-03-13 09:43:36 +0000438
blueswir1e64d7d52008-12-02 17:47:02 +0000439 switch (addr) {
bellard6f7e9ae2005-03-13 09:43:36 +0000440 case 0:
blueswir1f930d072007-10-06 11:28:21 +0000441 s->dac_index = val >> 24;
442 s->dac_state = 0;
443 break;
blueswir1e64d7d52008-12-02 17:47:02 +0000444 case 4:
blueswir1f930d072007-10-06 11:28:21 +0000445 switch (s->dac_state) {
446 case 0:
447 s->r[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000448 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir1f930d072007-10-06 11:28:21 +0000449 s->dac_state++;
450 break;
451 case 1:
452 s->g[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000453 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir1f930d072007-10-06 11:28:21 +0000454 s->dac_state++;
455 break;
456 case 2:
457 s->b[s->dac_index] = val >> 24;
bellard21206a12006-09-09 11:31:34 +0000458 update_palette_entries(s, s->dac_index, s->dac_index + 1);
blueswir15c8cdbf2007-04-17 19:42:21 +0000459 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
blueswir1f930d072007-10-06 11:28:21 +0000460 default:
461 s->dac_state = 0;
462 break;
463 }
464 break;
bellard6f7e9ae2005-03-13 09:43:36 +0000465 default:
blueswir1f930d072007-10-06 11:28:21 +0000466 break;
bellard6f7e9ae2005-03-13 09:43:36 +0000467 }
468 return;
469}
470
Blue Swirld60efc62009-08-25 18:29:31 +0000471static CPUReadMemoryFunc * const tcx_dac_read[3] = {
blueswir17c560452008-01-01 17:06:38 +0000472 NULL,
473 NULL,
bellard6f7e9ae2005-03-13 09:43:36 +0000474 tcx_dac_readl,
475};
476
Blue Swirld60efc62009-08-25 18:29:31 +0000477static CPUWriteMemoryFunc * const tcx_dac_write[3] = {
blueswir17c560452008-01-01 17:06:38 +0000478 NULL,
479 NULL,
bellard6f7e9ae2005-03-13 09:43:36 +0000480 tcx_dac_writel,
481};
482
Anthony Liguoric227f092009-10-01 16:12:16 -0500483static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
blueswir18508b892007-05-06 17:39:55 +0000484{
485 return 0;
486}
487
Anthony Liguoric227f092009-10-01 16:12:16 -0500488static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
blueswir18508b892007-05-06 17:39:55 +0000489 uint32_t val)
490{
491}
492
Blue Swirld60efc62009-08-25 18:29:31 +0000493static CPUReadMemoryFunc * const tcx_dummy_read[3] = {
blueswir17c560452008-01-01 17:06:38 +0000494 NULL,
495 NULL,
blueswir18508b892007-05-06 17:39:55 +0000496 tcx_dummy_readl,
497};
498
Blue Swirld60efc62009-08-25 18:29:31 +0000499static CPUWriteMemoryFunc * const tcx_dummy_write[3] = {
blueswir17c560452008-01-01 17:06:38 +0000500 NULL,
501 NULL,
blueswir18508b892007-05-06 17:39:55 +0000502 tcx_dummy_writel,
503};
504
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200505static int tcx_init1(SysBusDevice *dev)
Blue Swirlf40070c2009-07-12 19:21:36 +0000506{
507 TCXState *s = FROM_SYSBUS(TCXState, dev);
blueswir18508b892007-05-06 17:39:55 +0000508 int io_memory, dummy_memory;
Anthony Liguoric227f092009-10-01 16:12:16 -0500509 ram_addr_t vram_offset;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200510 int size;
pbrookdc828ca2009-04-09 22:21:07 +0000511 uint8_t *vram_base;
512
Alex Williamson1724f042010-06-25 11:09:35 -0600513 vram_offset = qemu_ram_alloc(NULL, "tcx.vram", s->vram_size * (1 + 4 + 4));
pbrookdc828ca2009-04-09 22:21:07 +0000514 vram_base = qemu_get_ram_ptr(vram_offset);
bellarde80cfcf2004-12-19 23:18:01 +0000515 s->vram_offset = vram_offset;
516
Blue Swirlf40070c2009-07-12 19:21:36 +0000517 /* 8-bit plane */
blueswir1eee0b832007-04-21 19:45:49 +0000518 s->vram = vram_base;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200519 size = s->vram_size;
Blue Swirlf40070c2009-07-12 19:21:36 +0000520 sysbus_init_mmio(dev, size, s->vram_offset);
blueswir1eee0b832007-04-21 19:45:49 +0000521 vram_offset += size;
522 vram_base += size;
523
Blue Swirlf40070c2009-07-12 19:21:36 +0000524 /* DAC */
Alexander Graf2507c122010-12-08 12:05:37 +0100525 io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s,
526 DEVICE_NATIVE_ENDIAN);
Blue Swirlf40070c2009-07-12 19:21:36 +0000527 sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory);
bellarde80cfcf2004-12-19 23:18:01 +0000528
Blue Swirlf40070c2009-07-12 19:21:36 +0000529 /* TEC (dummy) */
Avi Kivity1eed09c2009-06-14 11:38:51 +0300530 dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write,
Alexander Graf2507c122010-12-08 12:05:37 +0100531 s, DEVICE_NATIVE_ENDIAN);
Blue Swirlf40070c2009-07-12 19:21:36 +0000532 sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory);
533 /* THC: NetBSD writes here even with 8-bit display: dummy */
534 sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory);
535
536 if (s->depth == 24) {
537 /* 24-bit plane */
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200538 size = s->vram_size * 4;
blueswir1eee0b832007-04-21 19:45:49 +0000539 s->vram24 = (uint32_t *)vram_base;
540 s->vram24_offset = vram_offset;
Blue Swirlf40070c2009-07-12 19:21:36 +0000541 sysbus_init_mmio(dev, size, vram_offset);
blueswir1eee0b832007-04-21 19:45:49 +0000542 vram_offset += size;
543 vram_base += size;
544
Blue Swirlf40070c2009-07-12 19:21:36 +0000545 /* Control plane */
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200546 size = s->vram_size * 4;
blueswir1eee0b832007-04-21 19:45:49 +0000547 s->cplane = (uint32_t *)vram_base;
548 s->cplane_offset = vram_offset;
Blue Swirlf40070c2009-07-12 19:21:36 +0000549 sysbus_init_mmio(dev, size, vram_offset);
550
aliguori3023f332009-01-16 19:04:14 +0000551 s->ds = graphic_console_init(tcx24_update_display,
552 tcx24_invalidate_display,
553 tcx24_screen_dump, NULL, s);
blueswir1eee0b832007-04-21 19:45:49 +0000554 } else {
Blue Swirlf40070c2009-07-12 19:21:36 +0000555 /* THC 8 bit (dummy) */
556 sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory);
557
aliguori3023f332009-01-16 19:04:14 +0000558 s->ds = graphic_console_init(tcx_update_display,
559 tcx_invalidate_display,
560 tcx_screen_dump, NULL, s);
blueswir1eee0b832007-04-21 19:45:49 +0000561 }
562
Blue Swirlf40070c2009-07-12 19:21:36 +0000563 qemu_console_resize(s->ds, s->width, s->height);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200564 return 0;
bellard420557e2004-09-30 22:13:50 +0000565}
566
pbrook95219892006-04-09 01:06:34 +0000567static void tcx_screen_dump(void *opaque, const char *filename)
bellard8d5f07f2004-10-04 21:23:09 +0000568{
bellarde80cfcf2004-12-19 23:18:01 +0000569 TCXState *s = opaque;
bellard8d5f07f2004-10-04 21:23:09 +0000570 FILE *f;
bellarde80cfcf2004-12-19 23:18:01 +0000571 uint8_t *d, *d1, v;
bellard8d5f07f2004-10-04 21:23:09 +0000572 int y, x;
573
574 f = fopen(filename, "wb");
575 if (!f)
bellarde80cfcf2004-12-19 23:18:01 +0000576 return;
bellard6f7e9ae2005-03-13 09:43:36 +0000577 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
578 d1 = s->vram;
579 for(y = 0; y < s->height; y++) {
bellard8d5f07f2004-10-04 21:23:09 +0000580 d = d1;
bellard6f7e9ae2005-03-13 09:43:36 +0000581 for(x = 0; x < s->width; x++) {
bellard8d5f07f2004-10-04 21:23:09 +0000582 v = *d;
bellarde80cfcf2004-12-19 23:18:01 +0000583 fputc(s->r[v], f);
584 fputc(s->g[v], f);
585 fputc(s->b[v], f);
bellard8d5f07f2004-10-04 21:23:09 +0000586 d++;
587 }
bellarde80cfcf2004-12-19 23:18:01 +0000588 d1 += MAXX;
bellard8d5f07f2004-10-04 21:23:09 +0000589 }
590 fclose(f);
591 return;
592}
593
blueswir1eee0b832007-04-21 19:45:49 +0000594static void tcx24_screen_dump(void *opaque, const char *filename)
595{
596 TCXState *s = opaque;
597 FILE *f;
598 uint8_t *d, *d1, v;
599 uint32_t *s24, *cptr, dval;
600 int y, x;
bellard8d5f07f2004-10-04 21:23:09 +0000601
blueswir1eee0b832007-04-21 19:45:49 +0000602 f = fopen(filename, "wb");
603 if (!f)
604 return;
605 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
606 d1 = s->vram;
607 s24 = s->vram24;
608 cptr = s->cplane;
609 for(y = 0; y < s->height; y++) {
610 d = d1;
611 for(x = 0; x < s->width; x++, d++, s24++) {
612 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
613 dval = *s24 & 0x00ffffff;
614 fputc((dval >> 16) & 0xff, f);
615 fputc((dval >> 8) & 0xff, f);
616 fputc(dval & 0xff, f);
617 } else {
618 v = *d;
619 fputc(s->r[v], f);
620 fputc(s->g[v], f);
621 fputc(s->b[v], f);
622 }
623 }
624 d1 += MAXX;
625 }
626 fclose(f);
627 return;
628}
Blue Swirlf40070c2009-07-12 19:21:36 +0000629
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200630static SysBusDeviceInfo tcx_info = {
631 .init = tcx_init1,
632 .qdev.name = "SUNW,tcx",
633 .qdev.size = sizeof(TCXState),
Gerd Hoffmann20bb8272009-09-01 09:56:15 +0200634 .qdev.reset = tcx_reset,
635 .qdev.vmsd = &vmstate_tcx,
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200636 .qdev.props = (Property[]) {
Gerd Hoffmann53dad492009-08-03 17:35:43 +0200637 DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
638 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
639 DEFINE_PROP_UINT16("width", TCXState, width, -1),
640 DEFINE_PROP_UINT16("height", TCXState, height, -1),
641 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
642 DEFINE_PROP_END_OF_LIST(),
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200643 }
644};
645
Blue Swirlf40070c2009-07-12 19:21:36 +0000646static void tcx_register_devices(void)
647{
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200648 sysbus_register_withprop(&tcx_info);
Blue Swirlf40070c2009-07-12 19:21:36 +0000649}
650
651device_init(tcx_register_devices)