bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 1 | /* |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 2 | * QEMU TCX Frame buffer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 24 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 25 | #include "console.h" |
blueswir1 | 9447084 | 2007-06-10 16:06:20 +0000 | [diff] [blame] | 26 | #include "pixel_ops.h" |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 27 | #include "sysbus.h" |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 28 | #include "qdev-addr.h" |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 29 | |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 30 | #define MAXX 1024 |
| 31 | #define MAXY 768 |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 32 | #define TCX_DAC_NREGS 16 |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 33 | #define TCX_THC_NREGS_8 0x081c |
| 34 | #define TCX_THC_NREGS_24 0x1000 |
| 35 | #define TCX_TEC_NREGS 0x1000 |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 36 | |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 37 | typedef struct TCXState { |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 38 | SysBusDevice busdev; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 39 | target_phys_addr_t addr; |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 40 | DisplayState *ds; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 41 | uint8_t *vram; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 42 | uint32_t *vram24, *cplane; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 43 | ram_addr_t vram_offset, vram24_offset, cplane_offset; |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 44 | uint32_t vram_size; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 45 | uint16_t width, height, depth; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 46 | uint8_t r[256], g[256], b[256]; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 47 | uint32_t palette[256]; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 48 | uint8_t dac_index, dac_state; |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 49 | } TCXState; |
| 50 | |
pbrook | 9521989 | 2006-04-09 01:06:34 +0000 | [diff] [blame] | 51 | static void tcx_screen_dump(void *opaque, const char *filename); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 52 | static void tcx24_screen_dump(void *opaque, const char *filename); |
Blue Swirl | d3ffcaf | 2009-07-16 13:45:57 +0000 | [diff] [blame] | 53 | |
| 54 | static void tcx_set_dirty(TCXState *s) |
| 55 | { |
| 56 | unsigned int i; |
| 57 | |
| 58 | for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) { |
| 59 | cpu_physical_memory_set_dirty(s->vram_offset + i); |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | static void tcx24_set_dirty(TCXState *s) |
| 64 | { |
| 65 | unsigned int i; |
| 66 | |
| 67 | for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) { |
| 68 | cpu_physical_memory_set_dirty(s->vram24_offset + i); |
| 69 | cpu_physical_memory_set_dirty(s->cplane_offset + i); |
| 70 | } |
| 71 | } |
pbrook | 9521989 | 2006-04-09 01:06:34 +0000 | [diff] [blame] | 72 | |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 73 | static void update_palette_entries(TCXState *s, int start, int end) |
| 74 | { |
| 75 | int i; |
| 76 | for(i = start; i < end; i++) { |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 77 | switch(ds_get_bits_per_pixel(s->ds)) { |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 78 | default: |
| 79 | case 8: |
| 80 | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
| 81 | break; |
| 82 | case 15: |
aliguori | 8927bcf | 2009-01-15 22:07:16 +0000 | [diff] [blame] | 83 | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 84 | break; |
| 85 | case 16: |
aliguori | 8927bcf | 2009-01-15 22:07:16 +0000 | [diff] [blame] | 86 | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 87 | break; |
| 88 | case 32: |
aliguori | 7b5d76d | 2009-03-13 15:02:13 +0000 | [diff] [blame] | 89 | if (is_surface_bgr(s->ds->surface)) |
| 90 | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
| 91 | else |
| 92 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 93 | break; |
| 94 | } |
| 95 | } |
Blue Swirl | d3ffcaf | 2009-07-16 13:45:57 +0000 | [diff] [blame] | 96 | if (s->depth == 24) { |
| 97 | tcx24_set_dirty(s); |
| 98 | } else { |
| 99 | tcx_set_dirty(s); |
| 100 | } |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 101 | } |
| 102 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 103 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 104 | const uint8_t *s, int width) |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 105 | { |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 106 | int x; |
| 107 | uint8_t val; |
ths | 8bdc215 | 2006-12-21 17:24:45 +0000 | [diff] [blame] | 108 | uint32_t *p = (uint32_t *)d; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 109 | |
| 110 | for(x = 0; x < width; x++) { |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 111 | val = *s++; |
ths | 8bdc215 | 2006-12-21 17:24:45 +0000 | [diff] [blame] | 112 | *p++ = s1->palette[val]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 113 | } |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 114 | } |
| 115 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 116 | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 117 | const uint8_t *s, int width) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 118 | { |
| 119 | int x; |
| 120 | uint8_t val; |
ths | 8bdc215 | 2006-12-21 17:24:45 +0000 | [diff] [blame] | 121 | uint16_t *p = (uint16_t *)d; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 122 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 123 | for(x = 0; x < width; x++) { |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 124 | val = *s++; |
ths | 8bdc215 | 2006-12-21 17:24:45 +0000 | [diff] [blame] | 125 | *p++ = s1->palette[val]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 126 | } |
| 127 | } |
| 128 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 129 | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 130 | const uint8_t *s, int width) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 131 | { |
| 132 | int x; |
| 133 | uint8_t val; |
| 134 | |
| 135 | for(x = 0; x < width; x++) { |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 136 | val = *s++; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 137 | *d++ = s1->palette[val]; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 138 | } |
| 139 | } |
| 140 | |
blueswir1 | 688ea2e | 2008-07-24 11:26:38 +0000 | [diff] [blame] | 141 | /* |
| 142 | XXX Could be much more optimal: |
| 143 | * detect if line/page/whole screen is in 24 bit mode |
| 144 | * if destination is also BGR, use memcpy |
| 145 | */ |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 146 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
| 147 | const uint8_t *s, int width, |
| 148 | const uint32_t *cplane, |
| 149 | const uint32_t *s24) |
| 150 | { |
aliguori | 7b5d76d | 2009-03-13 15:02:13 +0000 | [diff] [blame] | 151 | int x, bgr, r, g, b; |
blueswir1 | 688ea2e | 2008-07-24 11:26:38 +0000 | [diff] [blame] | 152 | uint8_t val, *p8; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 153 | uint32_t *p = (uint32_t *)d; |
| 154 | uint32_t dval; |
| 155 | |
aliguori | 7b5d76d | 2009-03-13 15:02:13 +0000 | [diff] [blame] | 156 | bgr = is_surface_bgr(s1->ds->surface); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 157 | for(x = 0; x < width; x++, s++, s24++) { |
blueswir1 | 688ea2e | 2008-07-24 11:26:38 +0000 | [diff] [blame] | 158 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
| 159 | // 24-bit direct, BGR order |
| 160 | p8 = (uint8_t *)s24; |
| 161 | p8++; |
| 162 | b = *p8++; |
| 163 | g = *p8++; |
Blue Swirl | f7e683b | 2010-01-13 18:58:51 +0000 | [diff] [blame] | 164 | r = *p8; |
aliguori | 7b5d76d | 2009-03-13 15:02:13 +0000 | [diff] [blame] | 165 | if (bgr) |
| 166 | dval = rgb_to_pixel32bgr(r, g, b); |
| 167 | else |
| 168 | dval = rgb_to_pixel32(r, g, b); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 169 | } else { |
| 170 | val = *s; |
| 171 | dval = s1->palette[val]; |
| 172 | } |
| 173 | *p++ = dval; |
| 174 | } |
| 175 | } |
| 176 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 177 | static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
| 178 | ram_addr_t cpage) |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 179 | { |
| 180 | int ret; |
| 181 | unsigned int off; |
| 182 | |
| 183 | ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
| 184 | for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
| 185 | ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
| 186 | ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
| 187 | } |
| 188 | return ret; |
| 189 | } |
| 190 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 191 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
| 192 | ram_addr_t page_max, ram_addr_t page24, |
| 193 | ram_addr_t cpage) |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 194 | { |
| 195 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
| 196 | VGA_DIRTY_FLAG); |
| 197 | page_min -= ts->vram_offset; |
| 198 | page_max -= ts->vram_offset; |
| 199 | cpu_physical_memory_reset_dirty(page24 + page_min * 4, |
| 200 | page24 + page_max * 4 + TARGET_PAGE_SIZE, |
| 201 | VGA_DIRTY_FLAG); |
| 202 | cpu_physical_memory_reset_dirty(cpage + page_min * 4, |
| 203 | cpage + page_max * 4 + TARGET_PAGE_SIZE, |
| 204 | VGA_DIRTY_FLAG); |
| 205 | } |
| 206 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 207 | /* Fixed line length 1024 allows us to do nice tricks not possible on |
| 208 | VGA... */ |
pbrook | 9521989 | 2006-04-09 01:06:34 +0000 | [diff] [blame] | 209 | static void tcx_update_display(void *opaque) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 210 | { |
| 211 | TCXState *ts = opaque; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 212 | ram_addr_t page, page_min, page_max; |
bellard | 550be12 | 2006-08-02 22:19:33 +0000 | [diff] [blame] | 213 | int y, y_start, dd, ds; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 214 | uint8_t *d, *s; |
blueswir1 | b3ceef2 | 2007-06-25 19:56:13 +0000 | [diff] [blame] | 215 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 216 | |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 217 | if (ds_get_bits_per_pixel(ts->ds) == 0) |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 218 | return; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 219 | page = ts->vram_offset; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 220 | y_start = -1; |
Blue Swirl | c0c440f | 2009-04-27 18:10:37 +0000 | [diff] [blame] | 221 | page_min = -1; |
bellard | 550be12 | 2006-08-02 22:19:33 +0000 | [diff] [blame] | 222 | page_max = 0; |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 223 | d = ds_get_data(ts->ds); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 224 | s = ts->vram; |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 225 | dd = ds_get_linesize(ts->ds); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 226 | ds = 1024; |
| 227 | |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 228 | switch (ds_get_bits_per_pixel(ts->ds)) { |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 229 | case 32: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 230 | f = tcx_draw_line32; |
| 231 | break; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 232 | case 15: |
| 233 | case 16: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 234 | f = tcx_draw_line16; |
| 235 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 236 | default: |
| 237 | case 8: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 238 | f = tcx_draw_line8; |
| 239 | break; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 240 | case 0: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 241 | return; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 242 | } |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 243 | |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 244 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 245 | if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { |
| 246 | if (y_start < 0) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 247 | y_start = y; |
| 248 | if (page < page_min) |
| 249 | page_min = page; |
| 250 | if (page > page_max) |
| 251 | page_max = page; |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 252 | f(ts, d, s, ts->width); |
| 253 | d += dd; |
| 254 | s += ds; |
| 255 | f(ts, d, s, ts->width); |
| 256 | d += dd; |
| 257 | s += ds; |
| 258 | f(ts, d, s, ts->width); |
| 259 | d += dd; |
| 260 | s += ds; |
| 261 | f(ts, d, s, ts->width); |
| 262 | d += dd; |
| 263 | s += ds; |
| 264 | } else { |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 265 | if (y_start >= 0) { |
| 266 | /* flush to display */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 267 | dpy_update(ts->ds, 0, y_start, |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 268 | ts->width, y - y_start); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 269 | y_start = -1; |
| 270 | } |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 271 | d += dd * 4; |
| 272 | s += ds * 4; |
| 273 | } |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 274 | } |
| 275 | if (y_start >= 0) { |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 276 | /* flush to display */ |
| 277 | dpy_update(ts->ds, 0, y_start, |
| 278 | ts->width, y - y_start); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 279 | } |
| 280 | /* reset modified pages */ |
Blue Swirl | c0c440f | 2009-04-27 18:10:37 +0000 | [diff] [blame] | 281 | if (page_max >= page_min) { |
bellard | 0a962c0 | 2005-02-10 22:00:27 +0000 | [diff] [blame] | 282 | cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
| 283 | VGA_DIRTY_FLAG); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 284 | } |
| 285 | } |
| 286 | |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 287 | static void tcx24_update_display(void *opaque) |
| 288 | { |
| 289 | TCXState *ts = opaque; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 290 | ram_addr_t page, page_min, page_max, cpage, page24; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 291 | int y, y_start, dd, ds; |
| 292 | uint8_t *d, *s; |
| 293 | uint32_t *cptr, *s24; |
| 294 | |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 295 | if (ds_get_bits_per_pixel(ts->ds) != 32) |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 296 | return; |
| 297 | page = ts->vram_offset; |
| 298 | page24 = ts->vram24_offset; |
| 299 | cpage = ts->cplane_offset; |
| 300 | y_start = -1; |
Blue Swirl | c0c440f | 2009-04-27 18:10:37 +0000 | [diff] [blame] | 301 | page_min = -1; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 302 | page_max = 0; |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 303 | d = ds_get_data(ts->ds); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 304 | s = ts->vram; |
| 305 | s24 = ts->vram24; |
| 306 | cptr = ts->cplane; |
aliguori | 0e1f5a0 | 2008-11-24 19:29:13 +0000 | [diff] [blame] | 307 | dd = ds_get_linesize(ts->ds); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 308 | ds = 1024; |
| 309 | |
| 310 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
| 311 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
blueswir1 | 2254876 | 2008-05-10 10:12:00 +0000 | [diff] [blame] | 312 | if (check_dirty(page, page24, cpage)) { |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 313 | if (y_start < 0) |
| 314 | y_start = y; |
| 315 | if (page < page_min) |
| 316 | page_min = page; |
| 317 | if (page > page_max) |
| 318 | page_max = page; |
| 319 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
| 320 | d += dd; |
| 321 | s += ds; |
| 322 | cptr += ds; |
| 323 | s24 += ds; |
| 324 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
| 325 | d += dd; |
| 326 | s += ds; |
| 327 | cptr += ds; |
| 328 | s24 += ds; |
| 329 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
| 330 | d += dd; |
| 331 | s += ds; |
| 332 | cptr += ds; |
| 333 | s24 += ds; |
| 334 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
| 335 | d += dd; |
| 336 | s += ds; |
| 337 | cptr += ds; |
| 338 | s24 += ds; |
| 339 | } else { |
| 340 | if (y_start >= 0) { |
| 341 | /* flush to display */ |
| 342 | dpy_update(ts->ds, 0, y_start, |
| 343 | ts->width, y - y_start); |
| 344 | y_start = -1; |
| 345 | } |
| 346 | d += dd * 4; |
| 347 | s += ds * 4; |
| 348 | cptr += ds * 4; |
| 349 | s24 += ds * 4; |
| 350 | } |
| 351 | } |
| 352 | if (y_start >= 0) { |
| 353 | /* flush to display */ |
| 354 | dpy_update(ts->ds, 0, y_start, |
| 355 | ts->width, y - y_start); |
| 356 | } |
| 357 | /* reset modified pages */ |
Blue Swirl | c0c440f | 2009-04-27 18:10:37 +0000 | [diff] [blame] | 358 | if (page_max >= page_min) { |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 359 | reset_dirty(ts, page_min, page_max, page24, cpage); |
| 360 | } |
| 361 | } |
| 362 | |
pbrook | 9521989 | 2006-04-09 01:06:34 +0000 | [diff] [blame] | 363 | static void tcx_invalidate_display(void *opaque) |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 364 | { |
| 365 | TCXState *s = opaque; |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 366 | |
Blue Swirl | d3ffcaf | 2009-07-16 13:45:57 +0000 | [diff] [blame] | 367 | tcx_set_dirty(s); |
| 368 | qemu_console_resize(s->ds, s->width, s->height); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 369 | } |
| 370 | |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 371 | static void tcx24_invalidate_display(void *opaque) |
| 372 | { |
| 373 | TCXState *s = opaque; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 374 | |
Blue Swirl | d3ffcaf | 2009-07-16 13:45:57 +0000 | [diff] [blame] | 375 | tcx_set_dirty(s); |
| 376 | tcx24_set_dirty(s); |
| 377 | qemu_console_resize(s->ds, s->width, s->height); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 378 | } |
| 379 | |
Juan Quintela | e59fb37 | 2009-09-29 22:48:21 +0200 | [diff] [blame] | 380 | static int vmstate_tcx_post_load(void *opaque, int version_id) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 381 | { |
| 382 | TCXState *s = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 383 | |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 384 | update_palette_entries(s, 0, 256); |
Blue Swirl | d3ffcaf | 2009-07-16 13:45:57 +0000 | [diff] [blame] | 385 | if (s->depth == 24) { |
| 386 | tcx24_set_dirty(s); |
| 387 | } else { |
| 388 | tcx_set_dirty(s); |
| 389 | } |
blueswir1 | 5425a21 | 2007-04-13 19:24:07 +0000 | [diff] [blame] | 390 | |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 391 | return 0; |
| 392 | } |
| 393 | |
Blue Swirl | c0c41a4 | 2009-08-28 20:43:01 +0000 | [diff] [blame] | 394 | static const VMStateDescription vmstate_tcx = { |
| 395 | .name ="tcx", |
| 396 | .version_id = 4, |
| 397 | .minimum_version_id = 4, |
| 398 | .minimum_version_id_old = 4, |
Juan Quintela | 752ff2f | 2009-09-10 03:04:30 +0200 | [diff] [blame] | 399 | .post_load = vmstate_tcx_post_load, |
Blue Swirl | c0c41a4 | 2009-08-28 20:43:01 +0000 | [diff] [blame] | 400 | .fields = (VMStateField []) { |
| 401 | VMSTATE_UINT16(height, TCXState), |
| 402 | VMSTATE_UINT16(width, TCXState), |
| 403 | VMSTATE_UINT16(depth, TCXState), |
| 404 | VMSTATE_BUFFER(r, TCXState), |
| 405 | VMSTATE_BUFFER(g, TCXState), |
| 406 | VMSTATE_BUFFER(b, TCXState), |
| 407 | VMSTATE_UINT8(dac_index, TCXState), |
| 408 | VMSTATE_UINT8(dac_state, TCXState), |
| 409 | VMSTATE_END_OF_LIST() |
| 410 | } |
| 411 | }; |
| 412 | |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 413 | static void tcx_reset(DeviceState *d) |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 414 | { |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 415 | TCXState *s = container_of(d, TCXState, busdev.qdev); |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 416 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 417 | /* Initialize palette */ |
| 418 | memset(s->r, 0, 256); |
| 419 | memset(s->g, 0, 256); |
| 420 | memset(s->b, 0, 256); |
| 421 | s->r[255] = s->g[255] = s->b[255] = 255; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 422 | update_palette_entries(s, 0, 256); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 423 | memset(s->vram, 0, MAXX*MAXY); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 424 | cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
| 425 | MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 426 | s->dac_index = 0; |
| 427 | s->dac_state = 0; |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 430 | static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 431 | { |
| 432 | return 0; |
| 433 | } |
| 434 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 435 | static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 436 | { |
| 437 | TCXState *s = opaque; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 438 | |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 439 | switch (addr) { |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 440 | case 0: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 441 | s->dac_index = val >> 24; |
| 442 | s->dac_state = 0; |
| 443 | break; |
blueswir1 | e64d7d5 | 2008-12-02 17:47:02 +0000 | [diff] [blame] | 444 | case 4: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 445 | switch (s->dac_state) { |
| 446 | case 0: |
| 447 | s->r[s->dac_index] = val >> 24; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 448 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 449 | s->dac_state++; |
| 450 | break; |
| 451 | case 1: |
| 452 | s->g[s->dac_index] = val >> 24; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 453 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 454 | s->dac_state++; |
| 455 | break; |
| 456 | case 2: |
| 457 | s->b[s->dac_index] = val >> 24; |
bellard | 21206a1 | 2006-09-09 11:31:34 +0000 | [diff] [blame] | 458 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
blueswir1 | 5c8cdbf | 2007-04-17 19:42:21 +0000 | [diff] [blame] | 459 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 460 | default: |
| 461 | s->dac_state = 0; |
| 462 | break; |
| 463 | } |
| 464 | break; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 465 | default: |
blueswir1 | f930d07 | 2007-10-06 11:28:21 +0000 | [diff] [blame] | 466 | break; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 467 | } |
| 468 | return; |
| 469 | } |
| 470 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 471 | static CPUReadMemoryFunc * const tcx_dac_read[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 472 | NULL, |
| 473 | NULL, |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 474 | tcx_dac_readl, |
| 475 | }; |
| 476 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 477 | static CPUWriteMemoryFunc * const tcx_dac_write[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 478 | NULL, |
| 479 | NULL, |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 480 | tcx_dac_writel, |
| 481 | }; |
| 482 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 483 | static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 484 | { |
| 485 | return 0; |
| 486 | } |
| 487 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 488 | static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 489 | uint32_t val) |
| 490 | { |
| 491 | } |
| 492 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 493 | static CPUReadMemoryFunc * const tcx_dummy_read[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 494 | NULL, |
| 495 | NULL, |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 496 | tcx_dummy_readl, |
| 497 | }; |
| 498 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 499 | static CPUWriteMemoryFunc * const tcx_dummy_write[3] = { |
blueswir1 | 7c56045 | 2008-01-01 17:06:38 +0000 | [diff] [blame] | 500 | NULL, |
| 501 | NULL, |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 502 | tcx_dummy_writel, |
| 503 | }; |
| 504 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 505 | static int tcx_init1(SysBusDevice *dev) |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 506 | { |
| 507 | TCXState *s = FROM_SYSBUS(TCXState, dev); |
blueswir1 | 8508b89 | 2007-05-06 17:39:55 +0000 | [diff] [blame] | 508 | int io_memory, dummy_memory; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 509 | ram_addr_t vram_offset; |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 510 | int size; |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 511 | uint8_t *vram_base; |
| 512 | |
Alex Williamson | 1724f04 | 2010-06-25 11:09:35 -0600 | [diff] [blame] | 513 | vram_offset = qemu_ram_alloc(NULL, "tcx.vram", s->vram_size * (1 + 4 + 4)); |
pbrook | dc828ca | 2009-04-09 22:21:07 +0000 | [diff] [blame] | 514 | vram_base = qemu_get_ram_ptr(vram_offset); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 515 | s->vram_offset = vram_offset; |
| 516 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 517 | /* 8-bit plane */ |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 518 | s->vram = vram_base; |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 519 | size = s->vram_size; |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 520 | sysbus_init_mmio(dev, size, s->vram_offset); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 521 | vram_offset += size; |
| 522 | vram_base += size; |
| 523 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 524 | /* DAC */ |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 525 | io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s, |
| 526 | DEVICE_NATIVE_ENDIAN); |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 527 | sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory); |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 528 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 529 | /* TEC (dummy) */ |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 530 | dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write, |
Alexander Graf | 2507c12 | 2010-12-08 12:05:37 +0100 | [diff] [blame] | 531 | s, DEVICE_NATIVE_ENDIAN); |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 532 | sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory); |
| 533 | /* THC: NetBSD writes here even with 8-bit display: dummy */ |
| 534 | sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory); |
| 535 | |
| 536 | if (s->depth == 24) { |
| 537 | /* 24-bit plane */ |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 538 | size = s->vram_size * 4; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 539 | s->vram24 = (uint32_t *)vram_base; |
| 540 | s->vram24_offset = vram_offset; |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 541 | sysbus_init_mmio(dev, size, vram_offset); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 542 | vram_offset += size; |
| 543 | vram_base += size; |
| 544 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 545 | /* Control plane */ |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 546 | size = s->vram_size * 4; |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 547 | s->cplane = (uint32_t *)vram_base; |
| 548 | s->cplane_offset = vram_offset; |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 549 | sysbus_init_mmio(dev, size, vram_offset); |
| 550 | |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 551 | s->ds = graphic_console_init(tcx24_update_display, |
| 552 | tcx24_invalidate_display, |
| 553 | tcx24_screen_dump, NULL, s); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 554 | } else { |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 555 | /* THC 8 bit (dummy) */ |
| 556 | sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory); |
| 557 | |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 558 | s->ds = graphic_console_init(tcx_update_display, |
| 559 | tcx_invalidate_display, |
| 560 | tcx_screen_dump, NULL, s); |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 561 | } |
| 562 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 563 | qemu_console_resize(s->ds, s->width, s->height); |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 564 | return 0; |
bellard | 420557e | 2004-09-30 22:13:50 +0000 | [diff] [blame] | 565 | } |
| 566 | |
pbrook | 9521989 | 2006-04-09 01:06:34 +0000 | [diff] [blame] | 567 | static void tcx_screen_dump(void *opaque, const char *filename) |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 568 | { |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 569 | TCXState *s = opaque; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 570 | FILE *f; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 571 | uint8_t *d, *d1, v; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 572 | int y, x; |
| 573 | |
| 574 | f = fopen(filename, "wb"); |
| 575 | if (!f) |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 576 | return; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 577 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
| 578 | d1 = s->vram; |
| 579 | for(y = 0; y < s->height; y++) { |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 580 | d = d1; |
bellard | 6f7e9ae | 2005-03-13 09:43:36 +0000 | [diff] [blame] | 581 | for(x = 0; x < s->width; x++) { |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 582 | v = *d; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 583 | fputc(s->r[v], f); |
| 584 | fputc(s->g[v], f); |
| 585 | fputc(s->b[v], f); |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 586 | d++; |
| 587 | } |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 588 | d1 += MAXX; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 589 | } |
| 590 | fclose(f); |
| 591 | return; |
| 592 | } |
| 593 | |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 594 | static void tcx24_screen_dump(void *opaque, const char *filename) |
| 595 | { |
| 596 | TCXState *s = opaque; |
| 597 | FILE *f; |
| 598 | uint8_t *d, *d1, v; |
| 599 | uint32_t *s24, *cptr, dval; |
| 600 | int y, x; |
bellard | 8d5f07f | 2004-10-04 21:23:09 +0000 | [diff] [blame] | 601 | |
blueswir1 | eee0b83 | 2007-04-21 19:45:49 +0000 | [diff] [blame] | 602 | f = fopen(filename, "wb"); |
| 603 | if (!f) |
| 604 | return; |
| 605 | fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
| 606 | d1 = s->vram; |
| 607 | s24 = s->vram24; |
| 608 | cptr = s->cplane; |
| 609 | for(y = 0; y < s->height; y++) { |
| 610 | d = d1; |
| 611 | for(x = 0; x < s->width; x++, d++, s24++) { |
| 612 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
| 613 | dval = *s24 & 0x00ffffff; |
| 614 | fputc((dval >> 16) & 0xff, f); |
| 615 | fputc((dval >> 8) & 0xff, f); |
| 616 | fputc(dval & 0xff, f); |
| 617 | } else { |
| 618 | v = *d; |
| 619 | fputc(s->r[v], f); |
| 620 | fputc(s->g[v], f); |
| 621 | fputc(s->b[v], f); |
| 622 | } |
| 623 | } |
| 624 | d1 += MAXX; |
| 625 | } |
| 626 | fclose(f); |
| 627 | return; |
| 628 | } |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 629 | |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 630 | static SysBusDeviceInfo tcx_info = { |
| 631 | .init = tcx_init1, |
| 632 | .qdev.name = "SUNW,tcx", |
| 633 | .qdev.size = sizeof(TCXState), |
Gerd Hoffmann | 20bb827 | 2009-09-01 09:56:15 +0200 | [diff] [blame] | 634 | .qdev.reset = tcx_reset, |
| 635 | .qdev.vmsd = &vmstate_tcx, |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 636 | .qdev.props = (Property[]) { |
Gerd Hoffmann | 53dad49 | 2009-08-03 17:35:43 +0200 | [diff] [blame] | 637 | DEFINE_PROP_TADDR("addr", TCXState, addr, -1), |
| 638 | DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), |
| 639 | DEFINE_PROP_UINT16("width", TCXState, width, -1), |
| 640 | DEFINE_PROP_UINT16("height", TCXState, height, -1), |
| 641 | DEFINE_PROP_UINT16("depth", TCXState, depth, -1), |
| 642 | DEFINE_PROP_END_OF_LIST(), |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 643 | } |
| 644 | }; |
| 645 | |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 646 | static void tcx_register_devices(void) |
| 647 | { |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 648 | sysbus_register_withprop(&tcx_info); |
Blue Swirl | f40070c | 2009-07-12 19:21:36 +0000 | [diff] [blame] | 649 | } |
| 650 | |
| 651 | device_init(tcx_register_devices) |