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Fabien Chouteauddd10552011-09-13 04:00:32 +00001/*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Peter Maydell0d755902016-01-26 18:16:58 +000024#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010025#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010026#include "hw/ppc/ppc.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010027#include "qemu/timer.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010028#include "sysemu/sysemu.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010029#include "hw/timer/m48t59.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010030#include "qemu/log.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010031#include "hw/loader.h"
Bharat Bhushan31f2cb82013-02-24 18:16:21 +000032#include "kvm_ppc.h"
Fabien Chouteauddd10552011-09-13 04:00:32 +000033
34
35/* Timer Control Register */
36
37#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
Peter Maydella1f7f972014-03-17 16:00:37 +000038#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
Fabien Chouteauddd10552011-09-13 04:00:32 +000039#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
Peter Maydella1f7f972014-03-17 16:00:37 +000040#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
41#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
42#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
Fabien Chouteauddd10552011-09-13 04:00:32 +000043#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
Peter Maydella1f7f972014-03-17 16:00:37 +000044#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
45#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
46#define TCR_ARE (1U << 22) /* Auto-Reload Enable */
Fabien Chouteauddd10552011-09-13 04:00:32 +000047
48/* Timer Control Register (e500 specific fields) */
49
50#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
51#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
52#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
53#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
54
55/* Timer Status Register */
56
Peter Maydella1f7f972014-03-17 16:00:37 +000057#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
58#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
Fabien Chouteauddd10552011-09-13 04:00:32 +000059#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
Peter Maydella1f7f972014-03-17 16:00:37 +000060#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
61#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
62#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
Fabien Chouteauddd10552011-09-13 04:00:32 +000063
64typedef struct booke_timer_t booke_timer_t;
65struct booke_timer_t {
66
67 uint64_t fit_next;
Stefan Weil1246b252013-12-01 08:49:47 +010068 QEMUTimer *fit_timer;
Fabien Chouteauddd10552011-09-13 04:00:32 +000069
70 uint64_t wdt_next;
Stefan Weil1246b252013-12-01 08:49:47 +010071 QEMUTimer *wdt_timer;
Fabien Chouteauddd10552011-09-13 04:00:32 +000072
73 uint32_t flags;
74};
75
Andreas Färber70585812012-12-01 03:55:58 +010076static void booke_update_irq(PowerPCCPU *cpu)
Fabien Chouteauddd10552011-09-13 04:00:32 +000077{
Andreas Färber70585812012-12-01 03:55:58 +010078 CPUPPCState *env = &cpu->env;
79
80 ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
Fabien Chouteauddd10552011-09-13 04:00:32 +000081 (env->spr[SPR_BOOKE_TSR] & TSR_DIS
82 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));
83
Andreas Färber70585812012-12-01 03:55:58 +010084 ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
Fabien Chouteauddd10552011-09-13 04:00:32 +000085 (env->spr[SPR_BOOKE_TSR] & TSR_WIS
86 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));
87
Andreas Färber70585812012-12-01 03:55:58 +010088 ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
Fabien Chouteauddd10552011-09-13 04:00:32 +000089 (env->spr[SPR_BOOKE_TSR] & TSR_FIS
90 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
91}
92
93/* Return the location of the bit of time base at which the FIT will raise an
94 interrupt */
Andreas Färbere2684c02012-03-14 01:38:23 +010095static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
Fabien Chouteauddd10552011-09-13 04:00:32 +000096{
97 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
98
99 if (tb_env->flags & PPC_TIMER_E500) {
100 /* e500 Fixed-interval timer period extension */
101 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
102 >> TCR_E500_FPEXT_SHIFT;
103 fp = 63 - (fp | fpext << 2);
104 } else {
105 fp = env->fit_period[fp];
106 }
107
108 return fp;
109}
110
111/* Return the location of the bit of time base at which the WDT will raise an
112 interrupt */
Andreas Färbere2684c02012-03-14 01:38:23 +0100113static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
Fabien Chouteauddd10552011-09-13 04:00:32 +0000114{
115 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
116
117 if (tb_env->flags & PPC_TIMER_E500) {
118 /* e500 Watchdog timer period extension */
119 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
120 >> TCR_E500_WPEXT_SHIFT;
121 wp = 63 - (wp | wpext << 2);
122 } else {
123 wp = env->wdt_period[wp];
124 }
125
126 return wp;
127}
128
Andreas Färbere2684c02012-03-14 01:38:23 +0100129static void booke_update_fixed_timer(CPUPPCState *env,
Fabien Chouteauddd10552011-09-13 04:00:32 +0000130 uint8_t target_bit,
131 uint64_t *next,
Alexander Graf455df3f2013-11-25 22:46:54 +0100132 QEMUTimer *timer,
133 int tsr_bit)
Fabien Chouteauddd10552011-09-13 04:00:32 +0000134{
135 ppc_tb_t *tb_env = env->tb_env;
Bharat Bhushanab8131a2013-06-12 18:00:50 +0530136 uint64_t delta_tick, ticks = 0;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000137 uint64_t tb;
Bharat Bhushanab8131a2013-06-12 18:00:50 +0530138 uint64_t period;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000139 uint64_t now;
140
Alexander Graf455df3f2013-11-25 22:46:54 +0100141 if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
142 /*
143 * Don't arm the timer again when the guest has the current
144 * interrupt still pending. Wait for it to ack it.
145 */
146 return;
147 }
148
Alex Blighbc72ad62013-08-21 16:03:08 +0100149 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000150 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
Bharat Bhushanab8131a2013-06-12 18:00:50 +0530151 period = 1ULL << target_bit;
152 delta_tick = period - (tb & (period - 1));
Fabien Chouteauddd10552011-09-13 04:00:32 +0000153
Bharat Bhushanab8131a2013-06-12 18:00:50 +0530154 /* the timer triggers only when the selected bit toggles from 0 to 1 */
155 if (tb & period) {
156 ticks = period;
157 }
Fabien Chouteauddd10552011-09-13 04:00:32 +0000158
Bharat Bhushanab8131a2013-06-12 18:00:50 +0530159 if (ticks + delta_tick < ticks) {
160 /* Overflow, so assume the biggest number we can express. */
161 ticks = UINT64_MAX;
162 } else {
163 ticks += delta_tick;
164 }
165
166 *next = now + muldiv64(ticks, get_ticks_per_sec(), tb_env->tb_freq);
167 if ((*next < now) || (*next > INT64_MAX)) {
168 /* Overflow, so assume the biggest number the qemu timer supports. */
169 *next = INT64_MAX;
170 }
Fabien Chouteauddd10552011-09-13 04:00:32 +0000171
172 /* XXX: If expire time is now. We can't run the callback because we don't
173 * have access to it. So we just set the timer one nanosecond later.
174 */
175
176 if (*next == now) {
177 (*next)++;
Alexander Graf84dc96e2013-11-25 22:46:55 +0100178 } else {
179 /*
180 * There's no point to fake any granularity that's more fine grained
181 * than milliseconds. Anything beyond that just overloads the system.
182 */
183 *next = MAX(*next, now + SCALE_MS);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000184 }
185
Alexander Graf455df3f2013-11-25 22:46:54 +0100186 /* Fire the next timer */
Alex Blighbc72ad62013-08-21 16:03:08 +0100187 timer_mod(timer, *next);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000188}
189
190static void booke_decr_cb(void *opaque)
191{
Andreas Färberee0c98e2012-12-01 04:35:15 +0100192 PowerPCCPU *cpu = opaque;
193 CPUPPCState *env = &cpu->env;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000194
Fabien Chouteauddd10552011-09-13 04:00:32 +0000195 env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
Andreas Färber70585812012-12-01 03:55:58 +0100196 booke_update_irq(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000197
198 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
199 /* Auto Reload */
200 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
201 }
202}
203
204static void booke_fit_cb(void *opaque)
205{
Andreas Färberee0c98e2012-12-01 04:35:15 +0100206 PowerPCCPU *cpu = opaque;
207 CPUPPCState *env = &cpu->env;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000208 ppc_tb_t *tb_env;
209 booke_timer_t *booke_timer;
210
Fabien Chouteauddd10552011-09-13 04:00:32 +0000211 tb_env = env->tb_env;
212 booke_timer = tb_env->opaque;
213 env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
214
Andreas Färber70585812012-12-01 03:55:58 +0100215 booke_update_irq(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000216
217 booke_update_fixed_timer(env,
218 booke_get_fit_target(env, tb_env),
219 &booke_timer->fit_next,
Alexander Graf455df3f2013-11-25 22:46:54 +0100220 booke_timer->fit_timer,
221 TSR_FIS);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000222}
223
224static void booke_wdt_cb(void *opaque)
225{
Andreas Färberee0c98e2012-12-01 04:35:15 +0100226 PowerPCCPU *cpu = opaque;
227 CPUPPCState *env = &cpu->env;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000228 ppc_tb_t *tb_env;
229 booke_timer_t *booke_timer;
230
Fabien Chouteauddd10552011-09-13 04:00:32 +0000231 tb_env = env->tb_env;
232 booke_timer = tb_env->opaque;
233
234 /* TODO: There's lots of complicated stuff to do here */
235
Andreas Färber70585812012-12-01 03:55:58 +0100236 booke_update_irq(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000237
238 booke_update_fixed_timer(env,
239 booke_get_wdt_target(env, tb_env),
240 &booke_timer->wdt_next,
Alexander Graf455df3f2013-11-25 22:46:54 +0100241 booke_timer->wdt_timer,
242 TSR_WIS);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000243}
244
Andreas Färbere2684c02012-03-14 01:38:23 +0100245void store_booke_tsr(CPUPPCState *env, target_ulong val)
Fabien Chouteauddd10552011-09-13 04:00:32 +0000246{
Andreas Färber70585812012-12-01 03:55:58 +0100247 PowerPCCPU *cpu = ppc_env_get_cpu(env);
Alexander Graf455df3f2013-11-25 22:46:54 +0100248 ppc_tb_t *tb_env = env->tb_env;
249 booke_timer_t *booke_timer = tb_env->opaque;
Andreas Färber70585812012-12-01 03:55:58 +0100250
Fabien Chouteauddd10552011-09-13 04:00:32 +0000251 env->spr[SPR_BOOKE_TSR] &= ~val;
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000252 kvmppc_clear_tsr_bits(cpu, val);
Alexander Graf455df3f2013-11-25 22:46:54 +0100253
254 if (val & TSR_FIS) {
255 booke_update_fixed_timer(env,
256 booke_get_fit_target(env, tb_env),
257 &booke_timer->fit_next,
258 booke_timer->fit_timer,
259 TSR_FIS);
260 }
261
262 if (val & TSR_WIS) {
263 booke_update_fixed_timer(env,
264 booke_get_wdt_target(env, tb_env),
265 &booke_timer->wdt_next,
266 booke_timer->wdt_timer,
267 TSR_WIS);
268 }
269
Andreas Färber70585812012-12-01 03:55:58 +0100270 booke_update_irq(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000271}
272
Andreas Färbere2684c02012-03-14 01:38:23 +0100273void store_booke_tcr(CPUPPCState *env, target_ulong val)
Fabien Chouteauddd10552011-09-13 04:00:32 +0000274{
Andreas Färber70585812012-12-01 03:55:58 +0100275 PowerPCCPU *cpu = ppc_env_get_cpu(env);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000276 ppc_tb_t *tb_env = env->tb_env;
277 booke_timer_t *booke_timer = tb_env->opaque;
278
279 tb_env = env->tb_env;
280 env->spr[SPR_BOOKE_TCR] = val;
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000281 kvmppc_set_tcr(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000282
Andreas Färber70585812012-12-01 03:55:58 +0100283 booke_update_irq(cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000284
285 booke_update_fixed_timer(env,
286 booke_get_fit_target(env, tb_env),
287 &booke_timer->fit_next,
Alexander Graf455df3f2013-11-25 22:46:54 +0100288 booke_timer->fit_timer,
289 TSR_FIS);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000290
291 booke_update_fixed_timer(env,
292 booke_get_wdt_target(env, tb_env),
293 &booke_timer->wdt_next,
Alexander Graf455df3f2013-11-25 22:46:54 +0100294 booke_timer->wdt_timer,
295 TSR_WIS);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000296}
297
Bharat Bhushan88a78d92012-12-27 19:16:51 +0000298static void ppc_booke_timer_reset_handle(void *opaque)
299{
300 PowerPCCPU *cpu = opaque;
301 CPUPPCState *env = &cpu->env;
302
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000303 store_booke_tcr(env, 0);
304 store_booke_tsr(env, -1);
305}
Bharat Bhushan88a78d92012-12-27 19:16:51 +0000306
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000307/*
308 * This function will be called whenever the CPU state changes.
309 * CPU states are defined "typedef enum RunState".
310 * Regarding timer, When CPU state changes to running after debug halt
311 * or similar cases which takes time then in between final watchdog
312 * expiry happenes. This will cause exit to QEMU and configured watchdog
313 * action will be taken. To avoid this we always clear the watchdog state when
314 * state changes to running.
315 */
316static void cpu_state_change_handler(void *opaque, int running, RunState state)
317{
318 PowerPCCPU *cpu = opaque;
319 CPUPPCState *env = &cpu->env;
320
321 if (!running) {
322 return;
323 }
324
325 /*
326 * Clear watchdog interrupt condition by clearing TSR.
327 */
328 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
Bharat Bhushan88a78d92012-12-27 19:16:51 +0000329}
330
Andreas Färbera34a92b2012-12-01 04:43:18 +0100331void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
Fabien Chouteauddd10552011-09-13 04:00:32 +0000332{
333 ppc_tb_t *tb_env;
334 booke_timer_t *booke_timer;
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000335 int ret = 0;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000336
337 tb_env = g_malloc0(sizeof(ppc_tb_t));
338 booke_timer = g_malloc0(sizeof(booke_timer_t));
339
Andreas Färbera34a92b2012-12-01 04:43:18 +0100340 cpu->env.tb_env = tb_env;
Fabien Chouteauddd10552011-09-13 04:00:32 +0000341 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
342
343 tb_env->tb_freq = freq;
344 tb_env->decr_freq = freq;
345 tb_env->opaque = booke_timer;
Alex Blighbc72ad62013-08-21 16:03:08 +0100346 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000347
348 booke_timer->fit_timer =
Alex Blighbc72ad62013-08-21 16:03:08 +0100349 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000350 booke_timer->wdt_timer =
Alex Blighbc72ad62013-08-21 16:03:08 +0100351 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
Bharat Bhushan88a78d92012-12-27 19:16:51 +0000352
Bharat Bhushan31f2cb82013-02-24 18:16:21 +0000353 ret = kvmppc_booke_watchdog_enable(cpu);
354
355 if (ret) {
356 /* TODO: Start the QEMU emulated watchdog if not running on KVM.
357 * Also start the QEMU emulated watchdog if KVM does not support
358 * emulated watchdog or somehow it is not enabled (supported but
359 * not enabled is though some bug and requires debugging :)).
360 */
361 }
362
363 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
364
Bharat Bhushan88a78d92012-12-27 19:16:51 +0000365 qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
Fabien Chouteauddd10552011-09-13 04:00:32 +0000366}