Aurelien Jarno | 7b9cbad | 2010-03-14 23:30:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU MIPS timer support |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 5 | * of this software and associated documentation files (the "Software"), to deal |
| 6 | * in the Software without restriction, including without limitation the rights |
| 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 8 | * copies of the Software, and to permit persons to whom the Software is |
| 9 | * furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 20 | * THE SOFTWARE. |
| 21 | */ |
| 22 | |
Peter Maydell | c684822 | 2016-01-18 17:35:00 +0000 | [diff] [blame] | 23 | #include "qemu/osdep.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 24 | #include "hw/hw.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 25 | #include "hw/mips/cpudevs.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 26 | #include "qemu/timer.h" |
Sanjay Lal | 353a243 | 2014-06-17 23:10:27 +0100 | [diff] [blame] | 27 | #include "sysemu/kvm.h" |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 28 | |
Laurent Vivier | 683dca6 | 2015-08-25 16:16:21 +0200 | [diff] [blame] | 29 | #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ |
aurel32 | ea86e4e | 2008-04-11 04:55:31 +0000 | [diff] [blame] | 30 | |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 31 | /* XXX: do not use a global */ |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 32 | uint32_t cpu_mips_get_random (CPUMIPSState *env) |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 33 | { |
Serge Vakulenko | ceb0ee1 | 2015-07-05 23:14:50 -0700 | [diff] [blame] | 34 | static uint32_t seed = 1; |
aurel32 | 59d9413 | 2009-01-08 18:48:12 +0000 | [diff] [blame] | 35 | static uint32_t prev_idx = 0; |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 36 | uint32_t idx; |
Leon Alrae | 3adafef | 2015-09-10 10:15:28 +0100 | [diff] [blame] | 37 | uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; |
| 38 | |
| 39 | if (nb_rand_tlb == 1) { |
| 40 | return env->tlb->nb_tlb - 1; |
| 41 | } |
| 42 | |
aurel32 | 59d9413 | 2009-01-08 18:48:12 +0000 | [diff] [blame] | 43 | /* Don't return same value twice, so get another value */ |
| 44 | do { |
Serge Vakulenko | ceb0ee1 | 2015-07-05 23:14:50 -0700 | [diff] [blame] | 45 | /* Use a simple algorithm of Linear Congruential Generator |
| 46 | * from ISO/IEC 9899 standard. */ |
| 47 | seed = 1103515245 * seed + 12345; |
Leon Alrae | 3adafef | 2015-09-10 10:15:28 +0100 | [diff] [blame] | 48 | idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; |
aurel32 | 59d9413 | 2009-01-08 18:48:12 +0000 | [diff] [blame] | 49 | } while (idx == prev_idx); |
| 50 | prev_idx = idx; |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 51 | return idx; |
| 52 | } |
| 53 | |
| 54 | /* MIPS R4K timer */ |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 55 | static void cpu_mips_timer_update(CPUMIPSState *env) |
aurel32 | ea86e4e | 2008-04-11 04:55:31 +0000 | [diff] [blame] | 56 | { |
| 57 | uint64_t now, next; |
| 58 | uint32_t wait; |
| 59 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 60 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Laurent Vivier | 683dca6 | 2015-08-25 16:16:21 +0200 | [diff] [blame] | 61 | wait = env->CP0_Compare - env->CP0_Count - (uint32_t)(now / TIMER_PERIOD); |
| 62 | next = now + (uint64_t)wait * TIMER_PERIOD; |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 63 | timer_mod(env->timer, next); |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 64 | } |
| 65 | |
Edgar E. Iglesias | b1dfe64 | 2011-01-18 00:07:49 +0100 | [diff] [blame] | 66 | /* Expire the timer. */ |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 67 | static void cpu_mips_timer_expire(CPUMIPSState *env) |
Edgar E. Iglesias | b1dfe64 | 2011-01-18 00:07:49 +0100 | [diff] [blame] | 68 | { |
| 69 | cpu_mips_timer_update(env); |
| 70 | if (env->insn_flags & ISA_MIPS32R2) { |
| 71 | env->CP0_Cause |= 1 << CP0Ca_TI; |
| 72 | } |
| 73 | qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
| 74 | } |
| 75 | |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 76 | uint32_t cpu_mips_get_count (CPUMIPSState *env) |
Edgar E. Iglesias | b1dfe64 | 2011-01-18 00:07:49 +0100 | [diff] [blame] | 77 | { |
| 78 | if (env->CP0_Cause & (1 << CP0Ca_DC)) { |
| 79 | return env->CP0_Count; |
| 80 | } else { |
Edgar E. Iglesias | e027e1f | 2011-01-18 00:12:22 +0100 | [diff] [blame] | 81 | uint64_t now; |
| 82 | |
Alex Bligh | bc72ad6 | 2013-08-21 16:03:08 +0100 | [diff] [blame] | 83 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
Alex Bligh | e93379b | 2013-08-21 16:02:39 +0100 | [diff] [blame] | 84 | if (timer_pending(env->timer) |
| 85 | && timer_expired(env->timer, now)) { |
Edgar E. Iglesias | e027e1f | 2011-01-18 00:12:22 +0100 | [diff] [blame] | 86 | /* The timer has already expired. */ |
| 87 | cpu_mips_timer_expire(env); |
| 88 | } |
| 89 | |
Laurent Vivier | 683dca6 | 2015-08-25 16:16:21 +0200 | [diff] [blame] | 90 | return env->CP0_Count + (uint32_t)(now / TIMER_PERIOD); |
Edgar E. Iglesias | b1dfe64 | 2011-01-18 00:07:49 +0100 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 94 | void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 95 | { |
James Hogan | 4b69c7e | 2014-06-17 23:10:26 +0100 | [diff] [blame] | 96 | /* |
| 97 | * This gets called from cpu_state_reset(), potentially before timer init. |
| 98 | * So env->timer may be NULL, which is also the case with KVM enabled so |
| 99 | * treat timer as disabled in that case. |
| 100 | */ |
| 101 | if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) |
aurel32 | ea86e4e | 2008-04-11 04:55:31 +0000 | [diff] [blame] | 102 | env->CP0_Count = count; |
| 103 | else { |
| 104 | /* Store new count register */ |
Laurent Vivier | 683dca6 | 2015-08-25 16:16:21 +0200 | [diff] [blame] | 105 | env->CP0_Count = count - |
| 106 | (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD); |
aurel32 | ea86e4e | 2008-04-11 04:55:31 +0000 | [diff] [blame] | 107 | /* Update timer timer */ |
| 108 | cpu_mips_timer_update(env); |
| 109 | } |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 112 | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value) |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 113 | { |
ths | 3529b53 | 2007-04-05 23:17:40 +0000 | [diff] [blame] | 114 | env->CP0_Compare = value; |
aurel32 | ea86e4e | 2008-04-11 04:55:31 +0000 | [diff] [blame] | 115 | if (!(env->CP0_Cause & (1 << CP0Ca_DC))) |
| 116 | cpu_mips_timer_update(env); |
| 117 | if (env->insn_flags & ISA_MIPS32R2) |
ths | 39d51eb | 2007-03-18 12:43:40 +0000 | [diff] [blame] | 118 | env->CP0_Cause &= ~(1 << CP0Ca_TI); |
ths | 4253218 | 2007-09-25 16:53:15 +0000 | [diff] [blame] | 119 | qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); |
| 120 | } |
| 121 | |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 122 | void cpu_mips_start_count(CPUMIPSState *env) |
ths | 4253218 | 2007-09-25 16:53:15 +0000 | [diff] [blame] | 123 | { |
| 124 | cpu_mips_store_count(env, env->CP0_Count); |
| 125 | } |
| 126 | |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 127 | void cpu_mips_stop_count(CPUMIPSState *env) |
ths | 4253218 | 2007-09-25 16:53:15 +0000 | [diff] [blame] | 128 | { |
| 129 | /* Store the current value */ |
Laurent Vivier | 683dca6 | 2015-08-25 16:16:21 +0200 | [diff] [blame] | 130 | env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / |
| 131 | TIMER_PERIOD); |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | static void mips_timer_cb (void *opaque) |
| 135 | { |
Andreas Färber | 61c56c8 | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 136 | CPUMIPSState *env; |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 137 | |
| 138 | env = opaque; |
| 139 | #if 0 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 140 | qemu_log("%s\n", __func__); |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 141 | #endif |
ths | 4253218 | 2007-09-25 16:53:15 +0000 | [diff] [blame] | 142 | |
| 143 | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 144 | return; |
| 145 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 146 | /* ??? This callback should occur when the counter is exactly equal to |
| 147 | the comparator value. Offset the count by one to avoid immediately |
| 148 | retriggering the callback before any virtual time has passed. */ |
| 149 | env->CP0_Count++; |
Edgar E. Iglesias | b1dfe64 | 2011-01-18 00:07:49 +0100 | [diff] [blame] | 150 | cpu_mips_timer_expire(env); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 151 | env->CP0_Count--; |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 152 | } |
| 153 | |
Paolo Bonzini | 5a975d4 | 2016-03-15 14:32:19 +0100 | [diff] [blame] | 154 | void cpu_mips_clock_init (MIPSCPU *cpu) |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 155 | { |
Paolo Bonzini | 5a975d4 | 2016-03-15 14:32:19 +0100 | [diff] [blame] | 156 | CPUMIPSState *env = &cpu->env; |
| 157 | |
Sanjay Lal | 353a243 | 2014-06-17 23:10:27 +0100 | [diff] [blame] | 158 | /* |
| 159 | * If we're in KVM mode, don't create the periodic timer, that is handled in |
| 160 | * kernel. |
| 161 | */ |
| 162 | if (!kvm_enabled()) { |
| 163 | env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env); |
| 164 | } |
ths | e16fe40 | 2006-12-06 21:38:37 +0000 | [diff] [blame] | 165 | } |