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Aurelien Jarno7b9cbad2010-03-14 23:30:19 +01001/*
2 * QEMU MIPS timer support
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
Peter Maydellc6848222016-01-18 17:35:00 +000023#include "qemu/osdep.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010024#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010025#include "hw/mips/cpudevs.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010026#include "qemu/timer.h"
Sanjay Lal353a2432014-06-17 23:10:27 +010027#include "sysemu/kvm.h"
thse16fe402006-12-06 21:38:37 +000028
Laurent Vivier683dca62015-08-25 16:16:21 +020029#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
aurel32ea86e4e2008-04-11 04:55:31 +000030
thse16fe402006-12-06 21:38:37 +000031/* XXX: do not use a global */
Andreas Färber61c56c82012-03-14 01:38:23 +010032uint32_t cpu_mips_get_random (CPUMIPSState *env)
thse16fe402006-12-06 21:38:37 +000033{
Serge Vakulenkoceb0ee12015-07-05 23:14:50 -070034 static uint32_t seed = 1;
aurel3259d94132009-01-08 18:48:12 +000035 static uint32_t prev_idx = 0;
thse16fe402006-12-06 21:38:37 +000036 uint32_t idx;
Leon Alrae3adafef2015-09-10 10:15:28 +010037 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
38
39 if (nb_rand_tlb == 1) {
40 return env->tlb->nb_tlb - 1;
41 }
42
aurel3259d94132009-01-08 18:48:12 +000043 /* Don't return same value twice, so get another value */
44 do {
Serge Vakulenkoceb0ee12015-07-05 23:14:50 -070045 /* Use a simple algorithm of Linear Congruential Generator
46 * from ISO/IEC 9899 standard. */
47 seed = 1103515245 * seed + 12345;
Leon Alrae3adafef2015-09-10 10:15:28 +010048 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
aurel3259d94132009-01-08 18:48:12 +000049 } while (idx == prev_idx);
50 prev_idx = idx;
thse16fe402006-12-06 21:38:37 +000051 return idx;
52}
53
54/* MIPS R4K timer */
Andreas Färber61c56c82012-03-14 01:38:23 +010055static void cpu_mips_timer_update(CPUMIPSState *env)
aurel32ea86e4e2008-04-11 04:55:31 +000056{
57 uint64_t now, next;
58 uint32_t wait;
59
Alex Blighbc72ad62013-08-21 16:03:08 +010060 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Laurent Vivier683dca62015-08-25 16:16:21 +020061 wait = env->CP0_Compare - env->CP0_Count - (uint32_t)(now / TIMER_PERIOD);
62 next = now + (uint64_t)wait * TIMER_PERIOD;
Alex Blighbc72ad62013-08-21 16:03:08 +010063 timer_mod(env->timer, next);
thse16fe402006-12-06 21:38:37 +000064}
65
Edgar E. Iglesiasb1dfe642011-01-18 00:07:49 +010066/* Expire the timer. */
Andreas Färber61c56c82012-03-14 01:38:23 +010067static void cpu_mips_timer_expire(CPUMIPSState *env)
Edgar E. Iglesiasb1dfe642011-01-18 00:07:49 +010068{
69 cpu_mips_timer_update(env);
70 if (env->insn_flags & ISA_MIPS32R2) {
71 env->CP0_Cause |= 1 << CP0Ca_TI;
72 }
73 qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
74}
75
Andreas Färber61c56c82012-03-14 01:38:23 +010076uint32_t cpu_mips_get_count (CPUMIPSState *env)
Edgar E. Iglesiasb1dfe642011-01-18 00:07:49 +010077{
78 if (env->CP0_Cause & (1 << CP0Ca_DC)) {
79 return env->CP0_Count;
80 } else {
Edgar E. Iglesiase027e1f2011-01-18 00:12:22 +010081 uint64_t now;
82
Alex Blighbc72ad62013-08-21 16:03:08 +010083 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
Alex Blighe93379b2013-08-21 16:02:39 +010084 if (timer_pending(env->timer)
85 && timer_expired(env->timer, now)) {
Edgar E. Iglesiase027e1f2011-01-18 00:12:22 +010086 /* The timer has already expired. */
87 cpu_mips_timer_expire(env);
88 }
89
Laurent Vivier683dca62015-08-25 16:16:21 +020090 return env->CP0_Count + (uint32_t)(now / TIMER_PERIOD);
Edgar E. Iglesiasb1dfe642011-01-18 00:07:49 +010091 }
92}
93
Andreas Färber61c56c82012-03-14 01:38:23 +010094void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
thse16fe402006-12-06 21:38:37 +000095{
James Hogan4b69c7e2014-06-17 23:10:26 +010096 /*
97 * This gets called from cpu_state_reset(), potentially before timer init.
98 * So env->timer may be NULL, which is also the case with KVM enabled so
99 * treat timer as disabled in that case.
100 */
101 if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer)
aurel32ea86e4e2008-04-11 04:55:31 +0000102 env->CP0_Count = count;
103 else {
104 /* Store new count register */
Laurent Vivier683dca62015-08-25 16:16:21 +0200105 env->CP0_Count = count -
106 (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
aurel32ea86e4e2008-04-11 04:55:31 +0000107 /* Update timer timer */
108 cpu_mips_timer_update(env);
109 }
thse16fe402006-12-06 21:38:37 +0000110}
111
Andreas Färber61c56c82012-03-14 01:38:23 +0100112void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
thse16fe402006-12-06 21:38:37 +0000113{
ths3529b532007-04-05 23:17:40 +0000114 env->CP0_Compare = value;
aurel32ea86e4e2008-04-11 04:55:31 +0000115 if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
116 cpu_mips_timer_update(env);
117 if (env->insn_flags & ISA_MIPS32R2)
ths39d51eb2007-03-18 12:43:40 +0000118 env->CP0_Cause &= ~(1 << CP0Ca_TI);
ths42532182007-09-25 16:53:15 +0000119 qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
120}
121
Andreas Färber61c56c82012-03-14 01:38:23 +0100122void cpu_mips_start_count(CPUMIPSState *env)
ths42532182007-09-25 16:53:15 +0000123{
124 cpu_mips_store_count(env, env->CP0_Count);
125}
126
Andreas Färber61c56c82012-03-14 01:38:23 +0100127void cpu_mips_stop_count(CPUMIPSState *env)
ths42532182007-09-25 16:53:15 +0000128{
129 /* Store the current value */
Laurent Vivier683dca62015-08-25 16:16:21 +0200130 env->CP0_Count += (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
131 TIMER_PERIOD);
thse16fe402006-12-06 21:38:37 +0000132}
133
134static void mips_timer_cb (void *opaque)
135{
Andreas Färber61c56c82012-03-14 01:38:23 +0100136 CPUMIPSState *env;
thse16fe402006-12-06 21:38:37 +0000137
138 env = opaque;
139#if 0
aliguori93fcfe32009-01-15 22:34:14 +0000140 qemu_log("%s\n", __func__);
thse16fe402006-12-06 21:38:37 +0000141#endif
ths42532182007-09-25 16:53:15 +0000142
143 if (env->CP0_Cause & (1 << CP0Ca_DC))
144 return;
145
pbrook2e70f6e2008-06-29 01:03:05 +0000146 /* ??? This callback should occur when the counter is exactly equal to
147 the comparator value. Offset the count by one to avoid immediately
148 retriggering the callback before any virtual time has passed. */
149 env->CP0_Count++;
Edgar E. Iglesiasb1dfe642011-01-18 00:07:49 +0100150 cpu_mips_timer_expire(env);
pbrook2e70f6e2008-06-29 01:03:05 +0000151 env->CP0_Count--;
thse16fe402006-12-06 21:38:37 +0000152}
153
Paolo Bonzini5a975d42016-03-15 14:32:19 +0100154void cpu_mips_clock_init (MIPSCPU *cpu)
thse16fe402006-12-06 21:38:37 +0000155{
Paolo Bonzini5a975d42016-03-15 14:32:19 +0100156 CPUMIPSState *env = &cpu->env;
157
Sanjay Lal353a2432014-06-17 23:10:27 +0100158 /*
159 * If we're in KVM mode, don't create the periodic timer, that is handled in
160 * kernel.
161 */
162 if (!kvm_enabled()) {
163 env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
164 }
thse16fe402006-12-06 21:38:37 +0000165}