blob: 31c089dac0a7db66ac4d6270c293d1294bbc598a [file] [log] [blame]
bellard7d132992003-03-06 23:23:54 +00001/*
陳韋任e965fc32012-02-06 14:02:55 +08002 * emulator main execution loop
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard66321a12005-04-06 20:47:48 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
bellard7d132992003-03-06 23:23:54 +00005 *
bellard3ef693a2003-03-23 20:17:16 +00006 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
bellard7d132992003-03-06 23:23:54 +000010 *
bellard3ef693a2003-03-23 20:17:16 +000011 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
bellard7d132992003-03-06 23:23:54 +000015 *
bellard3ef693a2003-03-23 20:17:16 +000016 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard7d132992003-03-06 23:23:54 +000018 */
bellarde4533c72003-06-15 19:51:39 +000019#include "config.h"
Blue Swirlcea5f9a2011-05-15 16:03:25 +000020#include "cpu.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +020021#include "disas/disas.h"
bellard7cb69ca2008-05-10 10:55:51 +000022#include "tcg.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/atomic.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010024#include "sysemu/qtest.h"
bellard7d132992003-03-06 23:23:54 +000025
Andreas Färber3993c6b2012-05-03 06:43:49 +020026bool qemu_cpu_has_work(CPUState *cpu)
aliguori6a4955a2009-04-24 18:03:20 +000027{
Andreas Färber3993c6b2012-05-03 06:43:49 +020028 return cpu_has_work(cpu);
aliguori6a4955a2009-04-24 18:03:20 +000029}
30
Andreas Färber9349b4f2012-03-14 01:38:32 +010031void cpu_loop_exit(CPUArchState *env)
bellarde4533c72003-06-15 19:51:39 +000032{
Andreas Färberd77953b2013-01-16 19:29:31 +010033 CPUState *cpu = ENV_GET_CPU(env);
34
35 cpu->current_tb = NULL;
Peter Maydell6ab7e542013-02-20 15:21:09 +000036 siglongjmp(env->jmp_env, 1);
bellarde4533c72003-06-15 19:51:39 +000037}
thsbfed01f2007-06-03 17:44:37 +000038
bellardfbf9eeb2004-04-25 21:21:33 +000039/* exit the current TB from a signal handler. The host registers are
40 restored in a state compatible with the CPU emulator
41 */
Blue Swirl9eff14f2011-05-21 08:42:35 +000042#if defined(CONFIG_SOFTMMU)
Andreas Färber9349b4f2012-03-14 01:38:32 +010043void cpu_resume_from_signal(CPUArchState *env, void *puc)
bellardfbf9eeb2004-04-25 21:21:33 +000044{
Blue Swirl9eff14f2011-05-21 08:42:35 +000045 /* XXX: restore cpu registers saved in host registers */
46
47 env->exception_index = -1;
Peter Maydell6ab7e542013-02-20 15:21:09 +000048 siglongjmp(env->jmp_env, 1);
Blue Swirl9eff14f2011-05-21 08:42:35 +000049}
Blue Swirl9eff14f2011-05-21 08:42:35 +000050#endif
bellardfbf9eeb2004-04-25 21:21:33 +000051
Peter Maydell77211372013-02-22 18:10:02 +000052/* Execute a TB, and fix up the CPU state afterwards if necessary */
53static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
54{
55 CPUArchState *env = cpu->env_ptr;
56 tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr);
57 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
58 /* We didn't start executing this TB (eg because the instruction
59 * counter hit zero); we must restore the guest PC to the address
60 * of the start of the TB.
61 */
62 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
63 cpu_pc_from_tb(env, tb);
64 }
Peter Maydell378df4b2013-02-22 18:10:03 +000065 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
66 /* We were asked to stop executing TBs (probably a pending
67 * interrupt. We've now stopped, so clear the flag.
68 */
69 cpu->tcg_exit_req = 0;
70 }
Peter Maydell77211372013-02-22 18:10:02 +000071 return next_tb;
72}
73
pbrook2e70f6e2008-06-29 01:03:05 +000074/* Execute the code without caching the generated code. An interpreter
75 could be used if available. */
Andreas Färber9349b4f2012-03-14 01:38:32 +010076static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000077 TranslationBlock *orig_tb)
pbrook2e70f6e2008-06-29 01:03:05 +000078{
Andreas Färberd77953b2013-01-16 19:29:31 +010079 CPUState *cpu = ENV_GET_CPU(env);
pbrook2e70f6e2008-06-29 01:03:05 +000080 TranslationBlock *tb;
81
82 /* Should never happen.
83 We only end up here when an existing TB is too long. */
84 if (max_cycles > CF_COUNT_MASK)
85 max_cycles = CF_COUNT_MASK;
86
87 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
88 max_cycles);
Andreas Färberd77953b2013-01-16 19:29:31 +010089 cpu->current_tb = tb;
pbrook2e70f6e2008-06-29 01:03:05 +000090 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +000091 cpu_tb_exec(cpu, tb->tc_ptr);
Andreas Färberd77953b2013-01-16 19:29:31 +010092 cpu->current_tb = NULL;
pbrook2e70f6e2008-06-29 01:03:05 +000093 tb_phys_invalidate(tb, -1);
94 tb_free(tb);
95}
96
Andreas Färber9349b4f2012-03-14 01:38:32 +010097static TranslationBlock *tb_find_slow(CPUArchState *env,
Blue Swirlcea5f9a2011-05-15 16:03:25 +000098 target_ulong pc,
bellard8a40a182005-11-20 10:35:40 +000099 target_ulong cs_base,
j_mayerc0686882007-09-20 22:47:42 +0000100 uint64_t flags)
bellard8a40a182005-11-20 10:35:40 +0000101{
102 TranslationBlock *tb, **ptb1;
bellard8a40a182005-11-20 10:35:40 +0000103 unsigned int h;
Blue Swirl337fc752011-09-04 11:06:22 +0000104 tb_page_addr_t phys_pc, phys_page1;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000105 target_ulong virt_page2;
ths3b46e622007-09-17 08:09:54 +0000106
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700107 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
ths3b46e622007-09-17 08:09:54 +0000108
bellard8a40a182005-11-20 10:35:40 +0000109 /* find translated block using physical mappings */
Paul Brook41c1b1c2010-03-12 16:54:58 +0000110 phys_pc = get_page_addr_code(env, pc);
bellard8a40a182005-11-20 10:35:40 +0000111 phys_page1 = phys_pc & TARGET_PAGE_MASK;
bellard8a40a182005-11-20 10:35:40 +0000112 h = tb_phys_hash_func(phys_pc);
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700113 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
bellard8a40a182005-11-20 10:35:40 +0000114 for(;;) {
115 tb = *ptb1;
116 if (!tb)
117 goto not_found;
ths5fafdf22007-09-16 21:08:06 +0000118 if (tb->pc == pc &&
bellard8a40a182005-11-20 10:35:40 +0000119 tb->page_addr[0] == phys_page1 &&
ths5fafdf22007-09-16 21:08:06 +0000120 tb->cs_base == cs_base &&
bellard8a40a182005-11-20 10:35:40 +0000121 tb->flags == flags) {
122 /* check next page if needed */
123 if (tb->page_addr[1] != -1) {
Blue Swirl337fc752011-09-04 11:06:22 +0000124 tb_page_addr_t phys_page2;
125
ths5fafdf22007-09-16 21:08:06 +0000126 virt_page2 = (pc & TARGET_PAGE_MASK) +
bellard8a40a182005-11-20 10:35:40 +0000127 TARGET_PAGE_SIZE;
Paul Brook41c1b1c2010-03-12 16:54:58 +0000128 phys_page2 = get_page_addr_code(env, virt_page2);
bellard8a40a182005-11-20 10:35:40 +0000129 if (tb->page_addr[1] == phys_page2)
130 goto found;
131 } else {
132 goto found;
133 }
134 }
135 ptb1 = &tb->phys_hash_next;
136 }
137 not_found:
pbrook2e70f6e2008-06-29 01:03:05 +0000138 /* if no translated code available, then translate it now */
139 tb = tb_gen_code(env, pc, cs_base, flags, 0);
ths3b46e622007-09-17 08:09:54 +0000140
bellard8a40a182005-11-20 10:35:40 +0000141 found:
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300142 /* Move the last found TB to the head of the list */
143 if (likely(*ptb1)) {
144 *ptb1 = tb->phys_hash_next;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700145 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
146 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
Kirill Batuzov2c90fe22010-12-02 16:12:46 +0300147 }
bellard8a40a182005-11-20 10:35:40 +0000148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
bellard8a40a182005-11-20 10:35:40 +0000150 return tb;
151}
152
Andreas Färber9349b4f2012-03-14 01:38:32 +0100153static inline TranslationBlock *tb_find_fast(CPUArchState *env)
bellard8a40a182005-11-20 10:35:40 +0000154{
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
aliguori6b917542008-11-18 19:46:41 +0000157 int flags;
bellard8a40a182005-11-20 10:35:40 +0000158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
aliguori6b917542008-11-18 19:46:41 +0000162 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bellardbce61842008-02-01 22:18:51 +0000163 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
ths551bd272008-07-03 17:57:36 +0000164 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
165 tb->flags != flags)) {
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000166 tb = tb_find_slow(env, pc, cs_base, flags);
bellard8a40a182005-11-20 10:35:40 +0000167 }
168 return tb;
169}
170
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100171static CPUDebugExcpHandler *debug_excp_handler;
172
Igor Mammedov84e3b602012-06-21 18:29:38 +0200173void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100174{
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100175 debug_excp_handler = handler;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100176}
177
Andreas Färber9349b4f2012-03-14 01:38:32 +0100178static void cpu_handle_debug_exception(CPUArchState *env)
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100179{
180 CPUWatchpoint *wp;
181
182 if (!env->watchpoint_hit) {
183 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
184 wp->flags &= ~BP_WATCHPOINT_HIT;
185 }
186 }
187 if (debug_excp_handler) {
188 debug_excp_handler(env);
189 }
190}
191
bellard7d132992003-03-06 23:23:54 +0000192/* main execution loop */
193
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300194volatile sig_atomic_t exit_request;
195
Andreas Färber9349b4f2012-03-14 01:38:32 +0100196int cpu_exec(CPUArchState *env)
bellard7d132992003-03-06 23:23:54 +0000197{
Andreas Färberc356a1b2012-05-04 19:39:23 +0200198 CPUState *cpu = ENV_GET_CPU(env);
Andreas Färber97a8ea52013-02-02 10:57:51 +0100199#if !(defined(CONFIG_USER_ONLY) && \
200 (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
201 CPUClass *cc = CPU_GET_CLASS(cpu);
202#endif
bellard8a40a182005-11-20 10:35:40 +0000203 int ret, interrupt_request;
bellard8a40a182005-11-20 10:35:40 +0000204 TranslationBlock *tb;
bellardc27004e2005-01-03 23:35:10 +0000205 uint8_t *tc_ptr;
Stefan Weil69784ea2012-03-16 23:50:54 +0100206 tcg_target_ulong next_tb;
bellard8c6939c2003-06-09 15:28:00 +0000207
Andreas Färber259186a2013-01-17 18:51:17 +0100208 if (cpu->halted) {
Andreas Färber3993c6b2012-05-03 06:43:49 +0200209 if (!cpu_has_work(cpu)) {
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100210 return EXCP_HALTED;
211 }
212
Andreas Färber259186a2013-01-17 18:51:17 +0100213 cpu->halted = 0;
Paolo Bonzinieda48c32011-03-12 17:43:56 +0100214 }
bellard5a1e3cf2005-11-23 21:02:53 +0000215
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000216 cpu_single_env = env;
bellarde4533c72003-06-15 19:51:39 +0000217
Olivier Hainqueec9bd892013-04-09 18:06:54 +0200218 /* As long as cpu_single_env is null, up to the assignment just above,
219 * requests by other threads to exit the execution loop are expected to
220 * be issued using the exit_request global. We must make sure that our
221 * evaluation of the global value is performed past the cpu_single_env
222 * value transition point, which requires a memory barrier as well as
223 * an instruction scheduling constraint on modern architectures. */
224 smp_mb();
225
Jan Kiszkac629a4b2010-06-25 16:56:52 +0200226 if (unlikely(exit_request)) {
Andreas Färberfcd7d002012-12-17 08:02:44 +0100227 cpu->exit_request = 1;
Marcelo Tosatti1a28cac2010-05-04 09:45:20 -0300228 }
229
thsecb644f2007-06-03 18:45:53 +0000230#if defined(TARGET_I386)
Jan Kiszka6792a572011-02-07 12:19:18 +0100231 /* put eflags in CPU temporary format */
232 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
233 DF = 1 - (2 * ((env->eflags >> 10) & 1));
234 CC_OP = CC_OP_EFLAGS;
235 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
bellard93ac68b2003-09-30 20:57:29 +0000236#elif defined(TARGET_SPARC)
pbrooke6e59062006-10-22 00:18:54 +0000237#elif defined(TARGET_M68K)
238 env->cc_op = CC_OP_FLAGS;
239 env->cc_dest = env->sr & 0xf;
240 env->cc_x = (env->sr >> 4) & 1;
thsecb644f2007-06-03 18:45:53 +0000241#elif defined(TARGET_ALPHA)
242#elif defined(TARGET_ARM)
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800243#elif defined(TARGET_UNICORE32)
thsecb644f2007-06-03 18:45:53 +0000244#elif defined(TARGET_PPC)
Elie Richa4e85f822011-07-22 05:58:39 +0000245 env->reserve_addr = -1;
Michael Walle81ea0e12011-02-17 23:45:02 +0100246#elif defined(TARGET_LM32)
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200247#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000248#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400249#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800250#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000251#elif defined(TARGET_SH4)
thsf1ccf902007-10-08 13:16:14 +0000252#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100253#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400254#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000255 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000256#else
257#error unsupported target CPU
258#endif
bellard3fb2ded2003-06-24 13:22:59 +0000259 env->exception_index = -1;
bellard9d27abd2003-05-10 13:13:54 +0000260
bellard7d132992003-03-06 23:23:54 +0000261 /* prepare setjmp context for exception handling */
bellard3fb2ded2003-06-24 13:22:59 +0000262 for(;;) {
Peter Maydell6ab7e542013-02-20 15:21:09 +0000263 if (sigsetjmp(env->jmp_env, 0) == 0) {
bellard3fb2ded2003-06-24 13:22:59 +0000264 /* if an exception is pending, we execute it here */
265 if (env->exception_index >= 0) {
266 if (env->exception_index >= EXCP_INTERRUPT) {
267 /* exit request from the cpu execution loop */
268 ret = env->exception_index;
Jan Kiszka1009d2e2011-03-15 12:26:13 +0100269 if (ret == EXCP_DEBUG) {
270 cpu_handle_debug_exception(env);
271 }
bellard3fb2ded2003-06-24 13:22:59 +0000272 break;
aurel3272d239e2009-01-14 19:40:27 +0000273 } else {
274#if defined(CONFIG_USER_ONLY)
bellard3fb2ded2003-06-24 13:22:59 +0000275 /* if user mode only, we simulate a fake exception
ths9f083492006-12-07 18:28:42 +0000276 which will be handled outside the cpu execution
bellard3fb2ded2003-06-24 13:22:59 +0000277 loop */
bellard83479e72003-06-25 16:12:37 +0000278#if defined(TARGET_I386)
Andreas Färber97a8ea52013-02-02 10:57:51 +0100279 cc->do_interrupt(cpu);
bellard83479e72003-06-25 16:12:37 +0000280#endif
bellard3fb2ded2003-06-24 13:22:59 +0000281 ret = env->exception_index;
282 break;
aurel3272d239e2009-01-14 19:40:27 +0000283#else
Andreas Färber97a8ea52013-02-02 10:57:51 +0100284 cc->do_interrupt(cpu);
Paolo Bonzini301d2902010-01-15 09:41:01 +0100285 env->exception_index = -1;
aurel3272d239e2009-01-14 19:40:27 +0000286#endif
bellard3fb2ded2003-06-24 13:22:59 +0000287 }
ths5fafdf22007-09-16 21:08:06 +0000288 }
bellard9df217a2005-02-10 22:05:51 +0000289
blueswir1b5fc09a2008-05-04 06:38:18 +0000290 next_tb = 0; /* force lookup of first TB */
bellard3fb2ded2003-06-24 13:22:59 +0000291 for(;;) {
Andreas Färber259186a2013-01-17 18:51:17 +0100292 interrupt_request = cpu->interrupt_request;
malce1638bd2008-11-06 18:54:46 +0000293 if (unlikely(interrupt_request)) {
294 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
295 /* Mask out external interrupts for this step. */
Richard Henderson3125f762011-05-04 13:34:25 -0700296 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
malce1638bd2008-11-06 18:54:46 +0000297 }
pbrook6658ffb2007-03-16 23:58:11 +0000298 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
Andreas Färber259186a2013-01-17 18:51:17 +0100299 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
pbrook6658ffb2007-03-16 23:58:11 +0000300 env->exception_index = EXCP_DEBUG;
Blue Swirl1162c042011-05-14 12:52:35 +0000301 cpu_loop_exit(env);
pbrook6658ffb2007-03-16 23:58:11 +0000302 }
balroga90b7312007-05-01 01:28:01 +0000303#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200304 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800305 defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
balroga90b7312007-05-01 01:28:01 +0000306 if (interrupt_request & CPU_INTERRUPT_HALT) {
Andreas Färber259186a2013-01-17 18:51:17 +0100307 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
308 cpu->halted = 1;
balroga90b7312007-05-01 01:28:01 +0000309 env->exception_index = EXCP_HLT;
Blue Swirl1162c042011-05-14 12:52:35 +0000310 cpu_loop_exit(env);
balroga90b7312007-05-01 01:28:01 +0000311 }
312#endif
bellard68a79312003-06-30 13:12:32 +0000313#if defined(TARGET_I386)
Jan Kiszka5d62c432012-07-09 16:42:32 +0200314#if !defined(CONFIG_USER_ONLY)
315 if (interrupt_request & CPU_INTERRUPT_POLL) {
Andreas Färber259186a2013-01-17 18:51:17 +0100316 cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
Jan Kiszka5d62c432012-07-09 16:42:32 +0200317 apic_poll_irq(env->apic_state);
318 }
319#endif
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300320 if (interrupt_request & CPU_INTERRUPT_INIT) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000321 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
322 0);
Andreas Färber232fc232012-05-05 01:14:41 +0200323 do_cpu_init(x86_env_get_cpu(env));
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300324 env->exception_index = EXCP_HALTED;
Blue Swirl1162c042011-05-14 12:52:35 +0000325 cpu_loop_exit(env);
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300326 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
Andreas Färber232fc232012-05-05 01:14:41 +0200327 do_cpu_sipi(x86_env_get_cpu(env));
Gleb Natapovb09ea7d2009-06-17 23:26:59 +0300328 } else if (env->hflags2 & HF2_GIF_MASK) {
bellarddb620f42008-06-04 17:02:19 +0000329 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
330 !(env->hflags & HF_SMM_MASK)) {
Blue Swirl77b2bc22012-04-28 19:35:10 +0000331 cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
332 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100333 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
Blue Swirle694d4e2011-05-16 19:38:48 +0000334 do_smm_enter(env);
bellarddb620f42008-06-04 17:02:19 +0000335 next_tb = 0;
336 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
337 !(env->hflags2 & HF2_NMI_MASK)) {
Andreas Färber259186a2013-01-17 18:51:17 +0100338 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
bellarddb620f42008-06-04 17:02:19 +0000339 env->hflags2 |= HF2_NMI_MASK;
Blue Swirle694d4e2011-05-16 19:38:48 +0000340 do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
bellarddb620f42008-06-04 17:02:19 +0000341 next_tb = 0;
陳韋任e965fc32012-02-06 14:02:55 +0800342 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
Andreas Färber259186a2013-01-17 18:51:17 +0100343 cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
Blue Swirle694d4e2011-05-16 19:38:48 +0000344 do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
Huang Ying79c4f6b2009-06-23 10:05:14 +0800345 next_tb = 0;
bellarddb620f42008-06-04 17:02:19 +0000346 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
347 (((env->hflags2 & HF2_VINTR_MASK) &&
348 (env->hflags2 & HF2_HIF_MASK)) ||
349 (!(env->hflags2 & HF2_VINTR_MASK) &&
350 (env->eflags & IF_MASK &&
351 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
352 int intno;
Blue Swirl77b2bc22012-04-28 19:35:10 +0000353 cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
354 0);
Andreas Färber259186a2013-01-17 18:51:17 +0100355 cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
356 CPU_INTERRUPT_VIRQ);
bellarddb620f42008-06-04 17:02:19 +0000357 intno = cpu_get_pic_interrupt(env);
malc4f213872012-08-27 18:33:12 +0400358 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
359 do_interrupt_x86_hardirq(env, intno, 1);
360 /* ensure that no TB jump will be modified as
361 the program flow was changed */
362 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000363#if !defined(CONFIG_USER_ONLY)
bellarddb620f42008-06-04 17:02:19 +0000364 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
365 (env->eflags & IF_MASK) &&
366 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
367 int intno;
368 /* FIXME: this should respect TPR */
Blue Swirl77b2bc22012-04-28 19:35:10 +0000369 cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
370 0);
bellarddb620f42008-06-04 17:02:19 +0000371 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
aliguori93fcfe32009-01-15 22:34:14 +0000372 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
Blue Swirle694d4e2011-05-16 19:38:48 +0000373 do_interrupt_x86_hardirq(env, intno, 1);
Andreas Färber259186a2013-01-17 18:51:17 +0100374 cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
bellarddb620f42008-06-04 17:02:19 +0000375 next_tb = 0;
ths0573fbf2007-09-23 15:28:04 +0000376#endif
bellarddb620f42008-06-04 17:02:19 +0000377 }
bellard68a79312003-06-30 13:12:32 +0000378 }
bellardce097762004-01-04 23:53:18 +0000379#elif defined(TARGET_PPC)
bellard9fddaa02004-05-21 12:59:32 +0000380 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
Andreas Färberc356a1b2012-05-04 19:39:23 +0200381 cpu_reset(cpu);
bellard9fddaa02004-05-21 12:59:32 +0000382 }
j_mayer47103572007-03-30 09:38:04 +0000383 if (interrupt_request & CPU_INTERRUPT_HARD) {
j_mayere9df0142007-04-09 22:45:36 +0000384 ppc_hw_interrupt(env);
Andreas Färber259186a2013-01-17 18:51:17 +0100385 if (env->pending_interrupts == 0) {
386 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
387 }
blueswir1b5fc09a2008-05-04 06:38:18 +0000388 next_tb = 0;
bellardce097762004-01-04 23:53:18 +0000389 }
Michael Walle81ea0e12011-02-17 23:45:02 +0100390#elif defined(TARGET_LM32)
391 if ((interrupt_request & CPU_INTERRUPT_HARD)
392 && (env->ie & IE_IE)) {
393 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100394 cc->do_interrupt(cpu);
Michael Walle81ea0e12011-02-17 23:45:02 +0100395 next_tb = 0;
396 }
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200397#elif defined(TARGET_MICROBLAZE)
398 if ((interrupt_request & CPU_INTERRUPT_HARD)
399 && (env->sregs[SR_MSR] & MSR_IE)
400 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
401 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
402 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100403 cc->do_interrupt(cpu);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200404 next_tb = 0;
405 }
bellard6af0bf92005-07-02 14:58:51 +0000406#elif defined(TARGET_MIPS)
407 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100408 cpu_mips_hw_interrupts_pending(env)) {
bellard6af0bf92005-07-02 14:58:51 +0000409 /* Raise it */
410 env->exception_index = EXCP_EXT_INTERRUPT;
411 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100412 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000413 next_tb = 0;
bellard6af0bf92005-07-02 14:58:51 +0000414 }
Jia Liub6a71ef2012-07-20 15:50:41 +0800415#elif defined(TARGET_OPENRISC)
416 {
417 int idx = -1;
418 if ((interrupt_request & CPU_INTERRUPT_HARD)
419 && (env->sr & SR_IEE)) {
420 idx = EXCP_INT;
421 }
422 if ((interrupt_request & CPU_INTERRUPT_TIMER)
423 && (env->sr & SR_TEE)) {
424 idx = EXCP_TICK;
425 }
426 if (idx >= 0) {
427 env->exception_index = idx;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100428 cc->do_interrupt(cpu);
Jia Liub6a71ef2012-07-20 15:50:41 +0800429 next_tb = 0;
430 }
431 }
bellarde95c8d52004-09-30 22:22:08 +0000432#elif defined(TARGET_SPARC)
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300433 if (interrupt_request & CPU_INTERRUPT_HARD) {
434 if (cpu_interrupts_enabled(env) &&
435 env->interrupt_index > 0) {
436 int pil = env->interrupt_index & 0xf;
437 int type = env->interrupt_index & 0xf0;
bellard66321a12005-04-06 20:47:48 +0000438
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300439 if (((type == TT_EXTINT) &&
440 cpu_pil_allowed(env, pil)) ||
441 type != TT_EXTINT) {
442 env->exception_index = env->interrupt_index;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100443 cc->do_interrupt(cpu);
Igor V. Kovalenkod532b262010-01-07 23:28:31 +0300444 next_tb = 0;
445 }
446 }
陳韋任e965fc32012-02-06 14:02:55 +0800447 }
bellardb5ff1b32005-11-26 10:38:39 +0000448#elif defined(TARGET_ARM)
449 if (interrupt_request & CPU_INTERRUPT_FIQ
450 && !(env->uncached_cpsr & CPSR_F)) {
451 env->exception_index = EXCP_FIQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100452 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000453 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000454 }
pbrook9ee6e8b2007-11-11 00:04:49 +0000455 /* ARMv7-M interrupt return works by loading a magic value
456 into the PC. On real hardware the load causes the
457 return to occur. The qemu implementation performs the
458 jump normally, then does the exception return when the
459 CPU tries to execute code at the magic address.
460 This will cause the magic PC value to be pushed to
Stefan Weila1c72732011-04-28 17:20:38 +0200461 the stack if an interrupt occurred at the wrong time.
pbrook9ee6e8b2007-11-11 00:04:49 +0000462 We avoid this by disabling interrupts when
463 pc contains a magic address. */
bellardb5ff1b32005-11-26 10:38:39 +0000464 if (interrupt_request & CPU_INTERRUPT_HARD
pbrook9ee6e8b2007-11-11 00:04:49 +0000465 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
466 || !(env->uncached_cpsr & CPSR_I))) {
bellardb5ff1b32005-11-26 10:38:39 +0000467 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100468 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000469 next_tb = 0;
bellardb5ff1b32005-11-26 10:38:39 +0000470 }
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800471#elif defined(TARGET_UNICORE32)
472 if (interrupt_request & CPU_INTERRUPT_HARD
473 && !(env->uncached_asr & ASR_I)) {
Guan Xuetaod48813d2012-08-10 14:42:23 +0800474 env->exception_index = UC32_EXCP_INTR;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100475 cc->do_interrupt(cpu);
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800476 next_tb = 0;
477 }
bellardfdf9b3e2006-04-27 21:07:38 +0000478#elif defined(TARGET_SH4)
thse96e2042007-12-02 06:18:24 +0000479 if (interrupt_request & CPU_INTERRUPT_HARD) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100480 cc->do_interrupt(cpu);
blueswir1b5fc09a2008-05-04 06:38:18 +0000481 next_tb = 0;
thse96e2042007-12-02 06:18:24 +0000482 }
j_mayereddf68a2007-04-05 07:22:49 +0000483#elif defined(TARGET_ALPHA)
Richard Henderson6a80e082011-04-18 15:09:09 -0700484 {
485 int idx = -1;
486 /* ??? This hard-codes the OSF/1 interrupt levels. */
陳韋任e965fc32012-02-06 14:02:55 +0800487 switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
Richard Henderson6a80e082011-04-18 15:09:09 -0700488 case 0 ... 3:
489 if (interrupt_request & CPU_INTERRUPT_HARD) {
490 idx = EXCP_DEV_INTERRUPT;
491 }
492 /* FALLTHRU */
493 case 4:
494 if (interrupt_request & CPU_INTERRUPT_TIMER) {
495 idx = EXCP_CLK_INTERRUPT;
496 }
497 /* FALLTHRU */
498 case 5:
499 if (interrupt_request & CPU_INTERRUPT_SMP) {
500 idx = EXCP_SMP_INTERRUPT;
501 }
502 /* FALLTHRU */
503 case 6:
504 if (interrupt_request & CPU_INTERRUPT_MCHK) {
505 idx = EXCP_MCHK;
506 }
507 }
508 if (idx >= 0) {
509 env->exception_index = idx;
510 env->error_code = 0;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100511 cc->do_interrupt(cpu);
Richard Henderson6a80e082011-04-18 15:09:09 -0700512 next_tb = 0;
513 }
j_mayereddf68a2007-04-05 07:22:49 +0000514 }
thsf1ccf902007-10-08 13:16:14 +0000515#elif defined(TARGET_CRIS)
edgar_igl1b1a38b2008-06-09 23:18:06 +0000516 if (interrupt_request & CPU_INTERRUPT_HARD
Edgar E. Iglesiasfb9fb692010-02-15 11:17:33 +0100517 && (env->pregs[PR_CCS] & I_FLAG)
518 && !env->locked_irq) {
edgar_igl1b1a38b2008-06-09 23:18:06 +0000519 env->exception_index = EXCP_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100520 cc->do_interrupt(cpu);
edgar_igl1b1a38b2008-06-09 23:18:06 +0000521 next_tb = 0;
522 }
Lars Persson82193142012-06-14 16:23:55 +0200523 if (interrupt_request & CPU_INTERRUPT_NMI) {
524 unsigned int m_flag_archval;
525 if (env->pregs[PR_VR] < 32) {
526 m_flag_archval = M_FLAG_V10;
527 } else {
528 m_flag_archval = M_FLAG_V32;
529 }
530 if ((env->pregs[PR_CCS] & m_flag_archval)) {
531 env->exception_index = EXCP_NMI;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100532 cc->do_interrupt(cpu);
Lars Persson82193142012-06-14 16:23:55 +0200533 next_tb = 0;
534 }
thsf1ccf902007-10-08 13:16:14 +0000535 }
pbrook06338792007-05-23 19:58:11 +0000536#elif defined(TARGET_M68K)
537 if (interrupt_request & CPU_INTERRUPT_HARD
538 && ((env->sr & SR_I) >> SR_I_SHIFT)
539 < env->pending_level) {
540 /* Real hardware gets the interrupt vector via an
541 IACK cycle at this point. Current emulated
542 hardware doesn't rely on this, so we
543 provide/save the vector when the interrupt is
544 first signalled. */
545 env->exception_index = env->pending_vector;
Blue Swirl3c688822011-05-21 07:55:24 +0000546 do_interrupt_m68k_hardirq(env);
blueswir1b5fc09a2008-05-04 06:38:18 +0000547 next_tb = 0;
pbrook06338792007-05-23 19:58:11 +0000548 }
Alexander Graf3110e292011-04-15 17:32:48 +0200549#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
550 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
551 (env->psw.mask & PSW_MASK_EXT)) {
Andreas Färber97a8ea52013-02-02 10:57:51 +0100552 cc->do_interrupt(cpu);
Alexander Graf3110e292011-04-15 17:32:48 +0200553 next_tb = 0;
554 }
Max Filippov40643d72011-09-06 03:55:41 +0400555#elif defined(TARGET_XTENSA)
556 if (interrupt_request & CPU_INTERRUPT_HARD) {
557 env->exception_index = EXC_IRQ;
Andreas Färber97a8ea52013-02-02 10:57:51 +0100558 cc->do_interrupt(cpu);
Max Filippov40643d72011-09-06 03:55:41 +0400559 next_tb = 0;
560 }
bellard68a79312003-06-30 13:12:32 +0000561#endif
Stefan Weilff2712b2011-04-28 17:20:35 +0200562 /* Don't use the cached interrupt_request value,
bellard9d050952006-05-22 22:03:52 +0000563 do_interrupt may have updated the EXITTB flag. */
Andreas Färber259186a2013-01-17 18:51:17 +0100564 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
565 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bellardbf3e8bf2004-02-16 21:58:54 +0000566 /* ensure that no TB jump will be modified as
567 the program flow was changed */
blueswir1b5fc09a2008-05-04 06:38:18 +0000568 next_tb = 0;
bellardbf3e8bf2004-02-16 21:58:54 +0000569 }
aurel32be214e62009-03-06 21:48:00 +0000570 }
Andreas Färberfcd7d002012-12-17 08:02:44 +0100571 if (unlikely(cpu->exit_request)) {
572 cpu->exit_request = 0;
aurel32be214e62009-03-06 21:48:00 +0000573 env->exception_index = EXCP_INTERRUPT;
Blue Swirl1162c042011-05-14 12:52:35 +0000574 cpu_loop_exit(env);
bellard3fb2ded2003-06-24 13:22:59 +0000575 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100576#if defined(DEBUG_DISAS)
aliguori8fec2b82009-01-15 22:36:53 +0000577 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
bellard3fb2ded2003-06-24 13:22:59 +0000578 /* restore flags in standard format */
thsecb644f2007-06-03 18:45:53 +0000579#if defined(TARGET_I386)
Peter Maydell6fd2a022012-10-05 15:04:43 +0100580 log_cpu_state(env, CPU_DUMP_CCOP);
pbrooke6e59062006-10-22 00:18:54 +0000581#elif defined(TARGET_M68K)
582 cpu_m68k_flush_flags(env, env->cc_op);
583 env->cc_op = CC_OP_FLAGS;
584 env->sr = (env->sr & 0xffe0)
585 | env->cc_dest | (env->cc_x << 4);
aliguori93fcfe32009-01-15 22:34:14 +0000586 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000587#else
Richard Hendersona73b1fd2010-04-28 16:07:57 -0700588 log_cpu_state(env, 0);
bellarde4533c72003-06-15 19:51:39 +0000589#endif
bellard3fb2ded2003-06-24 13:22:59 +0000590 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100591#endif /* DEBUG_DISAS */
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700592 spin_lock(&tcg_ctx.tb_ctx.tb_lock);
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000593 tb = tb_find_fast(env);
pbrookd5975362008-06-07 20:50:51 +0000594 /* Note: we do it here to avoid a gcc bug on Mac OS X when
595 doing it in tb_find_slow */
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700596 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
pbrookd5975362008-06-07 20:50:51 +0000597 /* as some TB could have been invalidated because
598 of memory exceptions while generating the code, we
599 must recompute the hash index here */
600 next_tb = 0;
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700601 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
pbrookd5975362008-06-07 20:50:51 +0000602 }
Peter Maydellc30d1ae2013-04-11 21:21:46 +0100603 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
604 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
605 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
606 }
bellard8a40a182005-11-20 10:35:40 +0000607 /* see if we can patch the calling TB. When the TB
608 spans two pages, we cannot safely do a direct
609 jump. */
Paolo Bonzini040f2fb2010-01-15 08:56:36 +0100610 if (next_tb != 0 && tb->page_addr[1] == -1) {
Peter Maydell09800112013-02-22 18:10:00 +0000611 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
612 next_tb & TB_EXIT_MASK, tb);
bellard3fb2ded2003-06-24 13:22:59 +0000613 }
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700614 spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
malc55e8b852008-11-04 14:18:13 +0000615
616 /* cpu_interrupt might be called while translating the
617 TB, but before it is linked into a potentially
618 infinite loop and becomes env->current_tb. Avoid
619 starting execution if there is a pending interrupt. */
Andreas Färberd77953b2013-01-16 19:29:31 +0100620 cpu->current_tb = tb;
Jan Kiszkab0052d12010-06-25 16:56:50 +0200621 barrier();
Andreas Färberfcd7d002012-12-17 08:02:44 +0100622 if (likely(!cpu->exit_request)) {
pbrook2e70f6e2008-06-29 01:03:05 +0000623 tc_ptr = tb->tc_ptr;
陳韋任e965fc32012-02-06 14:02:55 +0800624 /* execute the generated code */
Peter Maydell77211372013-02-22 18:10:02 +0000625 next_tb = cpu_tb_exec(cpu, tc_ptr);
Peter Maydell378df4b2013-02-22 18:10:03 +0000626 switch (next_tb & TB_EXIT_MASK) {
627 case TB_EXIT_REQUESTED:
628 /* Something asked us to stop executing
629 * chained TBs; just continue round the main
630 * loop. Whatever requested the exit will also
631 * have set something else (eg exit_request or
632 * interrupt_request) which we will handle
633 * next time around the loop.
634 */
635 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
636 next_tb = 0;
637 break;
638 case TB_EXIT_ICOUNT_EXPIRED:
639 {
thsbf20dc02008-06-30 17:22:19 +0000640 /* Instruction counter expired. */
pbrook2e70f6e2008-06-29 01:03:05 +0000641 int insns_left;
Peter Maydell09800112013-02-22 18:10:00 +0000642 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
pbrook2e70f6e2008-06-29 01:03:05 +0000643 insns_left = env->icount_decr.u32;
644 if (env->icount_extra && insns_left >= 0) {
645 /* Refill decrementer and continue execution. */
646 env->icount_extra += insns_left;
647 if (env->icount_extra > 0xffff) {
648 insns_left = 0xffff;
649 } else {
650 insns_left = env->icount_extra;
651 }
652 env->icount_extra -= insns_left;
653 env->icount_decr.u16.low = insns_left;
654 } else {
655 if (insns_left > 0) {
656 /* Execute remaining instructions. */
Blue Swirlcea5f9a2011-05-15 16:03:25 +0000657 cpu_exec_nocache(env, insns_left, tb);
pbrook2e70f6e2008-06-29 01:03:05 +0000658 }
659 env->exception_index = EXCP_INTERRUPT;
660 next_tb = 0;
Blue Swirl1162c042011-05-14 12:52:35 +0000661 cpu_loop_exit(env);
pbrook2e70f6e2008-06-29 01:03:05 +0000662 }
Peter Maydell378df4b2013-02-22 18:10:03 +0000663 break;
664 }
665 default:
666 break;
pbrook2e70f6e2008-06-29 01:03:05 +0000667 }
668 }
Andreas Färberd77953b2013-01-16 19:29:31 +0100669 cpu->current_tb = NULL;
bellard4cbf74b2003-08-10 21:48:43 +0000670 /* reset soft MMU for next block (it can currently
671 only be set by a memory fault) */
ths50a518e2007-06-03 18:52:15 +0000672 } /* for(;;) */
Jan Kiszka0d101932011-07-02 09:50:51 +0200673 } else {
674 /* Reload env after longjmp - the compiler may have smashed all
675 * local variables as longjmp is marked 'noreturn'. */
676 env = cpu_single_env;
bellard7d132992003-03-06 23:23:54 +0000677 }
bellard3fb2ded2003-06-24 13:22:59 +0000678 } /* for(;;) */
679
bellard7d132992003-03-06 23:23:54 +0000680
bellarde4533c72003-06-15 19:51:39 +0000681#if defined(TARGET_I386)
bellard9de5e442003-03-23 16:49:39 +0000682 /* restore flags in standard format */
Blue Swirle694d4e2011-05-16 19:38:48 +0000683 env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
684 | (DF & DF_MASK);
bellarde4533c72003-06-15 19:51:39 +0000685#elif defined(TARGET_ARM)
bellardb7bcbe92005-02-22 19:27:29 +0000686 /* XXX: Save/restore host fpu exception state?. */
Guan Xuetaod2fbca92011-04-12 16:27:03 +0800687#elif defined(TARGET_UNICORE32)
bellard93ac68b2003-09-30 20:57:29 +0000688#elif defined(TARGET_SPARC)
bellard67867302003-11-23 17:05:30 +0000689#elif defined(TARGET_PPC)
Michael Walle81ea0e12011-02-17 23:45:02 +0100690#elif defined(TARGET_LM32)
pbrooke6e59062006-10-22 00:18:54 +0000691#elif defined(TARGET_M68K)
692 cpu_m68k_flush_flags(env, env->cc_op);
693 env->cc_op = CC_OP_FLAGS;
694 env->sr = (env->sr & 0xffe0)
695 | env->cc_dest | (env->cc_x << 4);
Edgar E. Iglesiasb779e292009-05-20 21:31:33 +0200696#elif defined(TARGET_MICROBLAZE)
bellard6af0bf92005-07-02 14:58:51 +0000697#elif defined(TARGET_MIPS)
Anthony Greend15a9c22013-03-18 15:49:25 -0400698#elif defined(TARGET_MOXIE)
Jia Liue67db062012-07-20 15:50:39 +0800699#elif defined(TARGET_OPENRISC)
bellardfdf9b3e2006-04-27 21:07:38 +0000700#elif defined(TARGET_SH4)
j_mayereddf68a2007-04-05 07:22:49 +0000701#elif defined(TARGET_ALPHA)
thsf1ccf902007-10-08 13:16:14 +0000702#elif defined(TARGET_CRIS)
Alexander Graf10ec5112009-12-05 12:44:21 +0100703#elif defined(TARGET_S390X)
Max Filippov23288262011-09-06 03:55:25 +0400704#elif defined(TARGET_XTENSA)
bellardfdf9b3e2006-04-27 21:07:38 +0000705 /* XXXXX */
bellarde4533c72003-06-15 19:51:39 +0000706#else
707#error unsupported target CPU
708#endif
pbrook1057eaa2007-02-04 13:37:44 +0000709
bellard6a00d602005-11-21 23:25:50 +0000710 /* fail safe : never use cpu_single_env outside cpu_exec() */
ths5fafdf22007-09-16 21:08:06 +0000711 cpu_single_env = NULL;
bellard7d132992003-03-06 23:23:54 +0000712 return ret;
713}