bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 1 | /* |
陳韋任 | e965fc3 | 2012-02-06 14:02:55 +0800 | [diff] [blame] | 2 | * emulator main execution loop |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 5 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 10 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 15 | * |
bellard | 3ef693a | 2003-03-23 20:17:16 +0000 | [diff] [blame] | 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 18 | */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 19 | #include "config.h" |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 20 | #include "cpu.h" |
Paolo Bonzini | 76cad71 | 2012-10-24 11:12:21 +0200 | [diff] [blame] | 21 | #include "disas/disas.h" |
bellard | 7cb69ca | 2008-05-10 10:55:51 +0000 | [diff] [blame] | 22 | #include "tcg.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 23 | #include "qemu/atomic.h" |
Paolo Bonzini | 9c17d61 | 2012-12-17 18:20:04 +0100 | [diff] [blame] | 24 | #include "sysemu/qtest.h" |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 25 | |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 26 | bool qemu_cpu_has_work(CPUState *cpu) |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 27 | { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 28 | return cpu_has_work(cpu); |
aliguori | 6a4955a | 2009-04-24 18:03:20 +0000 | [diff] [blame] | 29 | } |
| 30 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 31 | void cpu_loop_exit(CPUArchState *env) |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 32 | { |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 33 | CPUState *cpu = ENV_GET_CPU(env); |
| 34 | |
| 35 | cpu->current_tb = NULL; |
Peter Maydell | 6ab7e54 | 2013-02-20 15:21:09 +0000 | [diff] [blame] | 36 | siglongjmp(env->jmp_env, 1); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 37 | } |
ths | bfed01f | 2007-06-03 17:44:37 +0000 | [diff] [blame] | 38 | |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 39 | /* exit the current TB from a signal handler. The host registers are |
| 40 | restored in a state compatible with the CPU emulator |
| 41 | */ |
Blue Swirl | 9eff14f | 2011-05-21 08:42:35 +0000 | [diff] [blame] | 42 | #if defined(CONFIG_SOFTMMU) |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 43 | void cpu_resume_from_signal(CPUArchState *env, void *puc) |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 44 | { |
Blue Swirl | 9eff14f | 2011-05-21 08:42:35 +0000 | [diff] [blame] | 45 | /* XXX: restore cpu registers saved in host registers */ |
| 46 | |
| 47 | env->exception_index = -1; |
Peter Maydell | 6ab7e54 | 2013-02-20 15:21:09 +0000 | [diff] [blame] | 48 | siglongjmp(env->jmp_env, 1); |
Blue Swirl | 9eff14f | 2011-05-21 08:42:35 +0000 | [diff] [blame] | 49 | } |
Blue Swirl | 9eff14f | 2011-05-21 08:42:35 +0000 | [diff] [blame] | 50 | #endif |
bellard | fbf9eeb | 2004-04-25 21:21:33 +0000 | [diff] [blame] | 51 | |
Peter Maydell | 7721137 | 2013-02-22 18:10:02 +0000 | [diff] [blame] | 52 | /* Execute a TB, and fix up the CPU state afterwards if necessary */ |
| 53 | static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) |
| 54 | { |
| 55 | CPUArchState *env = cpu->env_ptr; |
| 56 | tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr); |
| 57 | if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) { |
| 58 | /* We didn't start executing this TB (eg because the instruction |
| 59 | * counter hit zero); we must restore the guest PC to the address |
| 60 | * of the start of the TB. |
| 61 | */ |
| 62 | TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); |
| 63 | cpu_pc_from_tb(env, tb); |
| 64 | } |
Peter Maydell | 378df4b | 2013-02-22 18:10:03 +0000 | [diff] [blame] | 65 | if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) { |
| 66 | /* We were asked to stop executing TBs (probably a pending |
| 67 | * interrupt. We've now stopped, so clear the flag. |
| 68 | */ |
| 69 | cpu->tcg_exit_req = 0; |
| 70 | } |
Peter Maydell | 7721137 | 2013-02-22 18:10:02 +0000 | [diff] [blame] | 71 | return next_tb; |
| 72 | } |
| 73 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 74 | /* Execute the code without caching the generated code. An interpreter |
| 75 | could be used if available. */ |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 76 | static void cpu_exec_nocache(CPUArchState *env, int max_cycles, |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 77 | TranslationBlock *orig_tb) |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 78 | { |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 79 | CPUState *cpu = ENV_GET_CPU(env); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 80 | TranslationBlock *tb; |
| 81 | |
| 82 | /* Should never happen. |
| 83 | We only end up here when an existing TB is too long. */ |
| 84 | if (max_cycles > CF_COUNT_MASK) |
| 85 | max_cycles = CF_COUNT_MASK; |
| 86 | |
| 87 | tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags, |
| 88 | max_cycles); |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 89 | cpu->current_tb = tb; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 90 | /* execute the generated code */ |
Peter Maydell | 7721137 | 2013-02-22 18:10:02 +0000 | [diff] [blame] | 91 | cpu_tb_exec(cpu, tb->tc_ptr); |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 92 | cpu->current_tb = NULL; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 93 | tb_phys_invalidate(tb, -1); |
| 94 | tb_free(tb); |
| 95 | } |
| 96 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 97 | static TranslationBlock *tb_find_slow(CPUArchState *env, |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 98 | target_ulong pc, |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 99 | target_ulong cs_base, |
j_mayer | c068688 | 2007-09-20 22:47:42 +0000 | [diff] [blame] | 100 | uint64_t flags) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 101 | { |
| 102 | TranslationBlock *tb, **ptb1; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 103 | unsigned int h; |
Blue Swirl | 337fc75 | 2011-09-04 11:06:22 +0000 | [diff] [blame] | 104 | tb_page_addr_t phys_pc, phys_page1; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 105 | target_ulong virt_page2; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 106 | |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 107 | tcg_ctx.tb_ctx.tb_invalidated_flag = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 108 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 109 | /* find translated block using physical mappings */ |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 110 | phys_pc = get_page_addr_code(env, pc); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 111 | phys_page1 = phys_pc & TARGET_PAGE_MASK; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 112 | h = tb_phys_hash_func(phys_pc); |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 113 | ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h]; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 114 | for(;;) { |
| 115 | tb = *ptb1; |
| 116 | if (!tb) |
| 117 | goto not_found; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 118 | if (tb->pc == pc && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 119 | tb->page_addr[0] == phys_page1 && |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 120 | tb->cs_base == cs_base && |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 121 | tb->flags == flags) { |
| 122 | /* check next page if needed */ |
| 123 | if (tb->page_addr[1] != -1) { |
Blue Swirl | 337fc75 | 2011-09-04 11:06:22 +0000 | [diff] [blame] | 124 | tb_page_addr_t phys_page2; |
| 125 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 126 | virt_page2 = (pc & TARGET_PAGE_MASK) + |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 127 | TARGET_PAGE_SIZE; |
Paul Brook | 41c1b1c | 2010-03-12 16:54:58 +0000 | [diff] [blame] | 128 | phys_page2 = get_page_addr_code(env, virt_page2); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 129 | if (tb->page_addr[1] == phys_page2) |
| 130 | goto found; |
| 131 | } else { |
| 132 | goto found; |
| 133 | } |
| 134 | } |
| 135 | ptb1 = &tb->phys_hash_next; |
| 136 | } |
| 137 | not_found: |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 138 | /* if no translated code available, then translate it now */ |
| 139 | tb = tb_gen_code(env, pc, cs_base, flags, 0); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 140 | |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 141 | found: |
Kirill Batuzov | 2c90fe2 | 2010-12-02 16:12:46 +0300 | [diff] [blame] | 142 | /* Move the last found TB to the head of the list */ |
| 143 | if (likely(*ptb1)) { |
| 144 | *ptb1 = tb->phys_hash_next; |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 145 | tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h]; |
| 146 | tcg_ctx.tb_ctx.tb_phys_hash[h] = tb; |
Kirill Batuzov | 2c90fe2 | 2010-12-02 16:12:46 +0300 | [diff] [blame] | 147 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 148 | /* we add the TB in the virtual pc hash table */ |
| 149 | env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 150 | return tb; |
| 151 | } |
| 152 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 153 | static inline TranslationBlock *tb_find_fast(CPUArchState *env) |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 154 | { |
| 155 | TranslationBlock *tb; |
| 156 | target_ulong cs_base, pc; |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 157 | int flags; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 158 | |
| 159 | /* we record a subset of the CPU state. It will |
| 160 | always be the same before a given translated block |
| 161 | is executed. */ |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 162 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); |
bellard | bce6184 | 2008-02-01 22:18:51 +0000 | [diff] [blame] | 163 | tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]; |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 164 | if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || |
| 165 | tb->flags != flags)) { |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 166 | tb = tb_find_slow(env, pc, cs_base, flags); |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 167 | } |
| 168 | return tb; |
| 169 | } |
| 170 | |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 171 | static CPUDebugExcpHandler *debug_excp_handler; |
| 172 | |
Igor Mammedov | 84e3b60 | 2012-06-21 18:29:38 +0200 | [diff] [blame] | 173 | void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 174 | { |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 175 | debug_excp_handler = handler; |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 176 | } |
| 177 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 178 | static void cpu_handle_debug_exception(CPUArchState *env) |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 179 | { |
| 180 | CPUWatchpoint *wp; |
| 181 | |
| 182 | if (!env->watchpoint_hit) { |
| 183 | QTAILQ_FOREACH(wp, &env->watchpoints, entry) { |
| 184 | wp->flags &= ~BP_WATCHPOINT_HIT; |
| 185 | } |
| 186 | } |
| 187 | if (debug_excp_handler) { |
| 188 | debug_excp_handler(env); |
| 189 | } |
| 190 | } |
| 191 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 192 | /* main execution loop */ |
| 193 | |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 194 | volatile sig_atomic_t exit_request; |
| 195 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 196 | int cpu_exec(CPUArchState *env) |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 197 | { |
Andreas Färber | c356a1b | 2012-05-04 19:39:23 +0200 | [diff] [blame] | 198 | CPUState *cpu = ENV_GET_CPU(env); |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 199 | #if !(defined(CONFIG_USER_ONLY) && \ |
| 200 | (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X))) |
| 201 | CPUClass *cc = CPU_GET_CLASS(cpu); |
| 202 | #endif |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 203 | int ret, interrupt_request; |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 204 | TranslationBlock *tb; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 205 | uint8_t *tc_ptr; |
Stefan Weil | 69784ea | 2012-03-16 23:50:54 +0100 | [diff] [blame] | 206 | tcg_target_ulong next_tb; |
bellard | 8c6939c | 2003-06-09 15:28:00 +0000 | [diff] [blame] | 207 | |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 208 | if (cpu->halted) { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 209 | if (!cpu_has_work(cpu)) { |
Paolo Bonzini | eda48c3 | 2011-03-12 17:43:56 +0100 | [diff] [blame] | 210 | return EXCP_HALTED; |
| 211 | } |
| 212 | |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 213 | cpu->halted = 0; |
Paolo Bonzini | eda48c3 | 2011-03-12 17:43:56 +0100 | [diff] [blame] | 214 | } |
bellard | 5a1e3cf | 2005-11-23 21:02:53 +0000 | [diff] [blame] | 215 | |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 216 | cpu_single_env = env; |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 217 | |
Olivier Hainque | ec9bd89 | 2013-04-09 18:06:54 +0200 | [diff] [blame] | 218 | /* As long as cpu_single_env is null, up to the assignment just above, |
| 219 | * requests by other threads to exit the execution loop are expected to |
| 220 | * be issued using the exit_request global. We must make sure that our |
| 221 | * evaluation of the global value is performed past the cpu_single_env |
| 222 | * value transition point, which requires a memory barrier as well as |
| 223 | * an instruction scheduling constraint on modern architectures. */ |
| 224 | smp_mb(); |
| 225 | |
Jan Kiszka | c629a4b | 2010-06-25 16:56:52 +0200 | [diff] [blame] | 226 | if (unlikely(exit_request)) { |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 227 | cpu->exit_request = 1; |
Marcelo Tosatti | 1a28cac | 2010-05-04 09:45:20 -0300 | [diff] [blame] | 228 | } |
| 229 | |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 230 | #if defined(TARGET_I386) |
Jan Kiszka | 6792a57 | 2011-02-07 12:19:18 +0100 | [diff] [blame] | 231 | /* put eflags in CPU temporary format */ |
| 232 | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 233 | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
| 234 | CC_OP = CC_OP_EFLAGS; |
| 235 | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 236 | #elif defined(TARGET_SPARC) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 237 | #elif defined(TARGET_M68K) |
| 238 | env->cc_op = CC_OP_FLAGS; |
| 239 | env->cc_dest = env->sr & 0xf; |
| 240 | env->cc_x = (env->sr >> 4) & 1; |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 241 | #elif defined(TARGET_ALPHA) |
| 242 | #elif defined(TARGET_ARM) |
Guan Xuetao | d2fbca9 | 2011-04-12 16:27:03 +0800 | [diff] [blame] | 243 | #elif defined(TARGET_UNICORE32) |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 244 | #elif defined(TARGET_PPC) |
Elie Richa | 4e85f82 | 2011-07-22 05:58:39 +0000 | [diff] [blame] | 245 | env->reserve_addr = -1; |
Michael Walle | 81ea0e1 | 2011-02-17 23:45:02 +0100 | [diff] [blame] | 246 | #elif defined(TARGET_LM32) |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 247 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 248 | #elif defined(TARGET_MIPS) |
Anthony Green | d15a9c2 | 2013-03-18 15:49:25 -0400 | [diff] [blame] | 249 | #elif defined(TARGET_MOXIE) |
Jia Liu | e67db06 | 2012-07-20 15:50:39 +0800 | [diff] [blame] | 250 | #elif defined(TARGET_OPENRISC) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 251 | #elif defined(TARGET_SH4) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 252 | #elif defined(TARGET_CRIS) |
Alexander Graf | 10ec511 | 2009-12-05 12:44:21 +0100 | [diff] [blame] | 253 | #elif defined(TARGET_S390X) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 254 | #elif defined(TARGET_XTENSA) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 255 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 256 | #else |
| 257 | #error unsupported target CPU |
| 258 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 259 | env->exception_index = -1; |
bellard | 9d27abd | 2003-05-10 13:13:54 +0000 | [diff] [blame] | 260 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 261 | /* prepare setjmp context for exception handling */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 262 | for(;;) { |
Peter Maydell | 6ab7e54 | 2013-02-20 15:21:09 +0000 | [diff] [blame] | 263 | if (sigsetjmp(env->jmp_env, 0) == 0) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 264 | /* if an exception is pending, we execute it here */ |
| 265 | if (env->exception_index >= 0) { |
| 266 | if (env->exception_index >= EXCP_INTERRUPT) { |
| 267 | /* exit request from the cpu execution loop */ |
| 268 | ret = env->exception_index; |
Jan Kiszka | 1009d2e | 2011-03-15 12:26:13 +0100 | [diff] [blame] | 269 | if (ret == EXCP_DEBUG) { |
| 270 | cpu_handle_debug_exception(env); |
| 271 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 272 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 273 | } else { |
| 274 | #if defined(CONFIG_USER_ONLY) |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 275 | /* if user mode only, we simulate a fake exception |
ths | 9f08349 | 2006-12-07 18:28:42 +0000 | [diff] [blame] | 276 | which will be handled outside the cpu execution |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 277 | loop */ |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 278 | #if defined(TARGET_I386) |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 279 | cc->do_interrupt(cpu); |
bellard | 83479e7 | 2003-06-25 16:12:37 +0000 | [diff] [blame] | 280 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 281 | ret = env->exception_index; |
| 282 | break; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 283 | #else |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 284 | cc->do_interrupt(cpu); |
Paolo Bonzini | 301d290 | 2010-01-15 09:41:01 +0100 | [diff] [blame] | 285 | env->exception_index = -1; |
aurel32 | 72d239e | 2009-01-14 19:40:27 +0000 | [diff] [blame] | 286 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 287 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 288 | } |
bellard | 9df217a | 2005-02-10 22:05:51 +0000 | [diff] [blame] | 289 | |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 290 | next_tb = 0; /* force lookup of first TB */ |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 291 | for(;;) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 292 | interrupt_request = cpu->interrupt_request; |
malc | e1638bd | 2008-11-06 18:54:46 +0000 | [diff] [blame] | 293 | if (unlikely(interrupt_request)) { |
| 294 | if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) { |
| 295 | /* Mask out external interrupts for this step. */ |
Richard Henderson | 3125f76 | 2011-05-04 13:34:25 -0700 | [diff] [blame] | 296 | interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK; |
malc | e1638bd | 2008-11-06 18:54:46 +0000 | [diff] [blame] | 297 | } |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 298 | if (interrupt_request & CPU_INTERRUPT_DEBUG) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 299 | cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG; |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 300 | env->exception_index = EXCP_DEBUG; |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 301 | cpu_loop_exit(env); |
pbrook | 6658ffb | 2007-03-16 23:58:11 +0000 | [diff] [blame] | 302 | } |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 303 | #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 304 | defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ |
Guan Xuetao | d2fbca9 | 2011-04-12 16:27:03 +0800 | [diff] [blame] | 305 | defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32) |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 306 | if (interrupt_request & CPU_INTERRUPT_HALT) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 307 | cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; |
| 308 | cpu->halted = 1; |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 309 | env->exception_index = EXCP_HLT; |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 310 | cpu_loop_exit(env); |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 311 | } |
| 312 | #endif |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 313 | #if defined(TARGET_I386) |
Jan Kiszka | 5d62c43 | 2012-07-09 16:42:32 +0200 | [diff] [blame] | 314 | #if !defined(CONFIG_USER_ONLY) |
| 315 | if (interrupt_request & CPU_INTERRUPT_POLL) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 316 | cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; |
Jan Kiszka | 5d62c43 | 2012-07-09 16:42:32 +0200 | [diff] [blame] | 317 | apic_poll_irq(env->apic_state); |
| 318 | } |
| 319 | #endif |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 320 | if (interrupt_request & CPU_INTERRUPT_INIT) { |
Blue Swirl | 77b2bc2 | 2012-04-28 19:35:10 +0000 | [diff] [blame] | 321 | cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, |
| 322 | 0); |
Andreas Färber | 232fc23 | 2012-05-05 01:14:41 +0200 | [diff] [blame] | 323 | do_cpu_init(x86_env_get_cpu(env)); |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 324 | env->exception_index = EXCP_HALTED; |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 325 | cpu_loop_exit(env); |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 326 | } else if (interrupt_request & CPU_INTERRUPT_SIPI) { |
Andreas Färber | 232fc23 | 2012-05-05 01:14:41 +0200 | [diff] [blame] | 327 | do_cpu_sipi(x86_env_get_cpu(env)); |
Gleb Natapov | b09ea7d | 2009-06-17 23:26:59 +0300 | [diff] [blame] | 328 | } else if (env->hflags2 & HF2_GIF_MASK) { |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 329 | if ((interrupt_request & CPU_INTERRUPT_SMI) && |
| 330 | !(env->hflags & HF_SMM_MASK)) { |
Blue Swirl | 77b2bc2 | 2012-04-28 19:35:10 +0000 | [diff] [blame] | 331 | cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, |
| 332 | 0); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 333 | cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 334 | do_smm_enter(env); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 335 | next_tb = 0; |
| 336 | } else if ((interrupt_request & CPU_INTERRUPT_NMI) && |
| 337 | !(env->hflags2 & HF2_NMI_MASK)) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 338 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 339 | env->hflags2 |= HF2_NMI_MASK; |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 340 | do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 341 | next_tb = 0; |
陳韋任 | e965fc3 | 2012-02-06 14:02:55 +0800 | [diff] [blame] | 342 | } else if (interrupt_request & CPU_INTERRUPT_MCE) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 343 | cpu->interrupt_request &= ~CPU_INTERRUPT_MCE; |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 344 | do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); |
Huang Ying | 79c4f6b | 2009-06-23 10:05:14 +0800 | [diff] [blame] | 345 | next_tb = 0; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 346 | } else if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 347 | (((env->hflags2 & HF2_VINTR_MASK) && |
| 348 | (env->hflags2 & HF2_HIF_MASK)) || |
| 349 | (!(env->hflags2 & HF2_VINTR_MASK) && |
| 350 | (env->eflags & IF_MASK && |
| 351 | !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { |
| 352 | int intno; |
Blue Swirl | 77b2bc2 | 2012-04-28 19:35:10 +0000 | [diff] [blame] | 353 | cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, |
| 354 | 0); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 355 | cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD | |
| 356 | CPU_INTERRUPT_VIRQ); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 357 | intno = cpu_get_pic_interrupt(env); |
malc | 4f21387 | 2012-08-27 18:33:12 +0400 | [diff] [blame] | 358 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); |
| 359 | do_interrupt_x86_hardirq(env, intno, 1); |
| 360 | /* ensure that no TB jump will be modified as |
| 361 | the program flow was changed */ |
| 362 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 363 | #if !defined(CONFIG_USER_ONLY) |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 364 | } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && |
| 365 | (env->eflags & IF_MASK) && |
| 366 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
| 367 | int intno; |
| 368 | /* FIXME: this should respect TPR */ |
Blue Swirl | 77b2bc2 | 2012-04-28 19:35:10 +0000 | [diff] [blame] | 369 | cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, |
| 370 | 0); |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 371 | intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 372 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 373 | do_interrupt_x86_hardirq(env, intno, 1); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 374 | cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 375 | next_tb = 0; |
ths | 0573fbf | 2007-09-23 15:28:04 +0000 | [diff] [blame] | 376 | #endif |
bellard | db620f4 | 2008-06-04 17:02:19 +0000 | [diff] [blame] | 377 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 378 | } |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 379 | #elif defined(TARGET_PPC) |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 380 | if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
Andreas Färber | c356a1b | 2012-05-04 19:39:23 +0200 | [diff] [blame] | 381 | cpu_reset(cpu); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 382 | } |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 383 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 384 | ppc_hw_interrupt(env); |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 385 | if (env->pending_interrupts == 0) { |
| 386 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
| 387 | } |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 388 | next_tb = 0; |
bellard | ce09776 | 2004-01-04 23:53:18 +0000 | [diff] [blame] | 389 | } |
Michael Walle | 81ea0e1 | 2011-02-17 23:45:02 +0100 | [diff] [blame] | 390 | #elif defined(TARGET_LM32) |
| 391 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
| 392 | && (env->ie & IE_IE)) { |
| 393 | env->exception_index = EXCP_IRQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 394 | cc->do_interrupt(cpu); |
Michael Walle | 81ea0e1 | 2011-02-17 23:45:02 +0100 | [diff] [blame] | 395 | next_tb = 0; |
| 396 | } |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 397 | #elif defined(TARGET_MICROBLAZE) |
| 398 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
| 399 | && (env->sregs[SR_MSR] & MSR_IE) |
| 400 | && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) |
| 401 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { |
| 402 | env->exception_index = EXCP_IRQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 403 | cc->do_interrupt(cpu); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 404 | next_tb = 0; |
| 405 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 406 | #elif defined(TARGET_MIPS) |
| 407 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
Aurelien Jarno | 4cdc1cd | 2010-12-25 22:56:32 +0100 | [diff] [blame] | 408 | cpu_mips_hw_interrupts_pending(env)) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 409 | /* Raise it */ |
| 410 | env->exception_index = EXCP_EXT_INTERRUPT; |
| 411 | env->error_code = 0; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 412 | cc->do_interrupt(cpu); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 413 | next_tb = 0; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 414 | } |
Jia Liu | b6a71ef | 2012-07-20 15:50:41 +0800 | [diff] [blame] | 415 | #elif defined(TARGET_OPENRISC) |
| 416 | { |
| 417 | int idx = -1; |
| 418 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
| 419 | && (env->sr & SR_IEE)) { |
| 420 | idx = EXCP_INT; |
| 421 | } |
| 422 | if ((interrupt_request & CPU_INTERRUPT_TIMER) |
| 423 | && (env->sr & SR_TEE)) { |
| 424 | idx = EXCP_TICK; |
| 425 | } |
| 426 | if (idx >= 0) { |
| 427 | env->exception_index = idx; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 428 | cc->do_interrupt(cpu); |
Jia Liu | b6a71ef | 2012-07-20 15:50:41 +0800 | [diff] [blame] | 429 | next_tb = 0; |
| 430 | } |
| 431 | } |
bellard | e95c8d5 | 2004-09-30 22:22:08 +0000 | [diff] [blame] | 432 | #elif defined(TARGET_SPARC) |
Igor V. Kovalenko | d532b26 | 2010-01-07 23:28:31 +0300 | [diff] [blame] | 433 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 434 | if (cpu_interrupts_enabled(env) && |
| 435 | env->interrupt_index > 0) { |
| 436 | int pil = env->interrupt_index & 0xf; |
| 437 | int type = env->interrupt_index & 0xf0; |
bellard | 66321a1 | 2005-04-06 20:47:48 +0000 | [diff] [blame] | 438 | |
Igor V. Kovalenko | d532b26 | 2010-01-07 23:28:31 +0300 | [diff] [blame] | 439 | if (((type == TT_EXTINT) && |
| 440 | cpu_pil_allowed(env, pil)) || |
| 441 | type != TT_EXTINT) { |
| 442 | env->exception_index = env->interrupt_index; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 443 | cc->do_interrupt(cpu); |
Igor V. Kovalenko | d532b26 | 2010-01-07 23:28:31 +0300 | [diff] [blame] | 444 | next_tb = 0; |
| 445 | } |
| 446 | } |
陳韋任 | e965fc3 | 2012-02-06 14:02:55 +0800 | [diff] [blame] | 447 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 448 | #elif defined(TARGET_ARM) |
| 449 | if (interrupt_request & CPU_INTERRUPT_FIQ |
| 450 | && !(env->uncached_cpsr & CPSR_F)) { |
| 451 | env->exception_index = EXCP_FIQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 452 | cc->do_interrupt(cpu); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 453 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 454 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 455 | /* ARMv7-M interrupt return works by loading a magic value |
| 456 | into the PC. On real hardware the load causes the |
| 457 | return to occur. The qemu implementation performs the |
| 458 | jump normally, then does the exception return when the |
| 459 | CPU tries to execute code at the magic address. |
| 460 | This will cause the magic PC value to be pushed to |
Stefan Weil | a1c7273 | 2011-04-28 17:20:38 +0200 | [diff] [blame] | 461 | the stack if an interrupt occurred at the wrong time. |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 462 | We avoid this by disabling interrupts when |
| 463 | pc contains a magic address. */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 464 | if (interrupt_request & CPU_INTERRUPT_HARD |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 465 | && ((IS_M(env) && env->regs[15] < 0xfffffff0) |
| 466 | || !(env->uncached_cpsr & CPSR_I))) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 467 | env->exception_index = EXCP_IRQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 468 | cc->do_interrupt(cpu); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 469 | next_tb = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 470 | } |
Guan Xuetao | d2fbca9 | 2011-04-12 16:27:03 +0800 | [diff] [blame] | 471 | #elif defined(TARGET_UNICORE32) |
| 472 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 473 | && !(env->uncached_asr & ASR_I)) { |
Guan Xuetao | d48813d | 2012-08-10 14:42:23 +0800 | [diff] [blame] | 474 | env->exception_index = UC32_EXCP_INTR; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 475 | cc->do_interrupt(cpu); |
Guan Xuetao | d2fbca9 | 2011-04-12 16:27:03 +0800 | [diff] [blame] | 476 | next_tb = 0; |
| 477 | } |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 478 | #elif defined(TARGET_SH4) |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 479 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 480 | cc->do_interrupt(cpu); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 481 | next_tb = 0; |
ths | e96e204 | 2007-12-02 06:18:24 +0000 | [diff] [blame] | 482 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 483 | #elif defined(TARGET_ALPHA) |
Richard Henderson | 6a80e08 | 2011-04-18 15:09:09 -0700 | [diff] [blame] | 484 | { |
| 485 | int idx = -1; |
| 486 | /* ??? This hard-codes the OSF/1 interrupt levels. */ |
陳韋任 | e965fc3 | 2012-02-06 14:02:55 +0800 | [diff] [blame] | 487 | switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { |
Richard Henderson | 6a80e08 | 2011-04-18 15:09:09 -0700 | [diff] [blame] | 488 | case 0 ... 3: |
| 489 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 490 | idx = EXCP_DEV_INTERRUPT; |
| 491 | } |
| 492 | /* FALLTHRU */ |
| 493 | case 4: |
| 494 | if (interrupt_request & CPU_INTERRUPT_TIMER) { |
| 495 | idx = EXCP_CLK_INTERRUPT; |
| 496 | } |
| 497 | /* FALLTHRU */ |
| 498 | case 5: |
| 499 | if (interrupt_request & CPU_INTERRUPT_SMP) { |
| 500 | idx = EXCP_SMP_INTERRUPT; |
| 501 | } |
| 502 | /* FALLTHRU */ |
| 503 | case 6: |
| 504 | if (interrupt_request & CPU_INTERRUPT_MCHK) { |
| 505 | idx = EXCP_MCHK; |
| 506 | } |
| 507 | } |
| 508 | if (idx >= 0) { |
| 509 | env->exception_index = idx; |
| 510 | env->error_code = 0; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 511 | cc->do_interrupt(cpu); |
Richard Henderson | 6a80e08 | 2011-04-18 15:09:09 -0700 | [diff] [blame] | 512 | next_tb = 0; |
| 513 | } |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 514 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 515 | #elif defined(TARGET_CRIS) |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 516 | if (interrupt_request & CPU_INTERRUPT_HARD |
Edgar E. Iglesias | fb9fb69 | 2010-02-15 11:17:33 +0100 | [diff] [blame] | 517 | && (env->pregs[PR_CCS] & I_FLAG) |
| 518 | && !env->locked_irq) { |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 519 | env->exception_index = EXCP_IRQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 520 | cc->do_interrupt(cpu); |
edgar_igl | 1b1a38b | 2008-06-09 23:18:06 +0000 | [diff] [blame] | 521 | next_tb = 0; |
| 522 | } |
Lars Persson | 8219314 | 2012-06-14 16:23:55 +0200 | [diff] [blame] | 523 | if (interrupt_request & CPU_INTERRUPT_NMI) { |
| 524 | unsigned int m_flag_archval; |
| 525 | if (env->pregs[PR_VR] < 32) { |
| 526 | m_flag_archval = M_FLAG_V10; |
| 527 | } else { |
| 528 | m_flag_archval = M_FLAG_V32; |
| 529 | } |
| 530 | if ((env->pregs[PR_CCS] & m_flag_archval)) { |
| 531 | env->exception_index = EXCP_NMI; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 532 | cc->do_interrupt(cpu); |
Lars Persson | 8219314 | 2012-06-14 16:23:55 +0200 | [diff] [blame] | 533 | next_tb = 0; |
| 534 | } |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 535 | } |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 536 | #elif defined(TARGET_M68K) |
| 537 | if (interrupt_request & CPU_INTERRUPT_HARD |
| 538 | && ((env->sr & SR_I) >> SR_I_SHIFT) |
| 539 | < env->pending_level) { |
| 540 | /* Real hardware gets the interrupt vector via an |
| 541 | IACK cycle at this point. Current emulated |
| 542 | hardware doesn't rely on this, so we |
| 543 | provide/save the vector when the interrupt is |
| 544 | first signalled. */ |
| 545 | env->exception_index = env->pending_vector; |
Blue Swirl | 3c68882 | 2011-05-21 07:55:24 +0000 | [diff] [blame] | 546 | do_interrupt_m68k_hardirq(env); |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 547 | next_tb = 0; |
pbrook | 0633879 | 2007-05-23 19:58:11 +0000 | [diff] [blame] | 548 | } |
Alexander Graf | 3110e29 | 2011-04-15 17:32:48 +0200 | [diff] [blame] | 549 | #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY) |
| 550 | if ((interrupt_request & CPU_INTERRUPT_HARD) && |
| 551 | (env->psw.mask & PSW_MASK_EXT)) { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 552 | cc->do_interrupt(cpu); |
Alexander Graf | 3110e29 | 2011-04-15 17:32:48 +0200 | [diff] [blame] | 553 | next_tb = 0; |
| 554 | } |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 555 | #elif defined(TARGET_XTENSA) |
| 556 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 557 | env->exception_index = EXC_IRQ; |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 558 | cc->do_interrupt(cpu); |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 559 | next_tb = 0; |
| 560 | } |
bellard | 68a7931 | 2003-06-30 13:12:32 +0000 | [diff] [blame] | 561 | #endif |
Stefan Weil | ff2712b | 2011-04-28 17:20:35 +0200 | [diff] [blame] | 562 | /* Don't use the cached interrupt_request value, |
bellard | 9d05095 | 2006-05-22 22:03:52 +0000 | [diff] [blame] | 563 | do_interrupt may have updated the EXITTB flag. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 564 | if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) { |
| 565 | cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 566 | /* ensure that no TB jump will be modified as |
| 567 | the program flow was changed */ |
blueswir1 | b5fc09a | 2008-05-04 06:38:18 +0000 | [diff] [blame] | 568 | next_tb = 0; |
bellard | bf3e8bf | 2004-02-16 21:58:54 +0000 | [diff] [blame] | 569 | } |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 570 | } |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 571 | if (unlikely(cpu->exit_request)) { |
| 572 | cpu->exit_request = 0; |
aurel32 | be214e6 | 2009-03-06 21:48:00 +0000 | [diff] [blame] | 573 | env->exception_index = EXCP_INTERRUPT; |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 574 | cpu_loop_exit(env); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 575 | } |
Peter Maydell | c30d1ae | 2013-04-11 21:21:46 +0100 | [diff] [blame] | 576 | #if defined(DEBUG_DISAS) |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 577 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 578 | /* restore flags in standard format */ |
ths | ecb644f | 2007-06-03 18:45:53 +0000 | [diff] [blame] | 579 | #if defined(TARGET_I386) |
Peter Maydell | 6fd2a02 | 2012-10-05 15:04:43 +0100 | [diff] [blame] | 580 | log_cpu_state(env, CPU_DUMP_CCOP); |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 581 | #elif defined(TARGET_M68K) |
| 582 | cpu_m68k_flush_flags(env, env->cc_op); |
| 583 | env->cc_op = CC_OP_FLAGS; |
| 584 | env->sr = (env->sr & 0xffe0) |
| 585 | | env->cc_dest | (env->cc_x << 4); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 586 | log_cpu_state(env, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 587 | #else |
Richard Henderson | a73b1fd | 2010-04-28 16:07:57 -0700 | [diff] [blame] | 588 | log_cpu_state(env, 0); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 589 | #endif |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 590 | } |
Peter Maydell | c30d1ae | 2013-04-11 21:21:46 +0100 | [diff] [blame] | 591 | #endif /* DEBUG_DISAS */ |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 592 | spin_lock(&tcg_ctx.tb_ctx.tb_lock); |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 593 | tb = tb_find_fast(env); |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 594 | /* Note: we do it here to avoid a gcc bug on Mac OS X when |
| 595 | doing it in tb_find_slow */ |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 596 | if (tcg_ctx.tb_ctx.tb_invalidated_flag) { |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 597 | /* as some TB could have been invalidated because |
| 598 | of memory exceptions while generating the code, we |
| 599 | must recompute the hash index here */ |
| 600 | next_tb = 0; |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 601 | tcg_ctx.tb_ctx.tb_invalidated_flag = 0; |
pbrook | d597536 | 2008-06-07 20:50:51 +0000 | [diff] [blame] | 602 | } |
Peter Maydell | c30d1ae | 2013-04-11 21:21:46 +0100 | [diff] [blame] | 603 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
| 604 | qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n", |
| 605 | tb->tc_ptr, tb->pc, lookup_symbol(tb->pc)); |
| 606 | } |
bellard | 8a40a18 | 2005-11-20 10:35:40 +0000 | [diff] [blame] | 607 | /* see if we can patch the calling TB. When the TB |
| 608 | spans two pages, we cannot safely do a direct |
| 609 | jump. */ |
Paolo Bonzini | 040f2fb | 2010-01-15 08:56:36 +0100 | [diff] [blame] | 610 | if (next_tb != 0 && tb->page_addr[1] == -1) { |
Peter Maydell | 0980011 | 2013-02-22 18:10:00 +0000 | [diff] [blame] | 611 | tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK), |
| 612 | next_tb & TB_EXIT_MASK, tb); |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 613 | } |
Evgeny Voevodin | 5e5f07e | 2013-02-01 01:47:23 +0700 | [diff] [blame] | 614 | spin_unlock(&tcg_ctx.tb_ctx.tb_lock); |
malc | 55e8b85 | 2008-11-04 14:18:13 +0000 | [diff] [blame] | 615 | |
| 616 | /* cpu_interrupt might be called while translating the |
| 617 | TB, but before it is linked into a potentially |
| 618 | infinite loop and becomes env->current_tb. Avoid |
| 619 | starting execution if there is a pending interrupt. */ |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 620 | cpu->current_tb = tb; |
Jan Kiszka | b0052d1 | 2010-06-25 16:56:50 +0200 | [diff] [blame] | 621 | barrier(); |
Andreas Färber | fcd7d00 | 2012-12-17 08:02:44 +0100 | [diff] [blame] | 622 | if (likely(!cpu->exit_request)) { |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 623 | tc_ptr = tb->tc_ptr; |
陳韋任 | e965fc3 | 2012-02-06 14:02:55 +0800 | [diff] [blame] | 624 | /* execute the generated code */ |
Peter Maydell | 7721137 | 2013-02-22 18:10:02 +0000 | [diff] [blame] | 625 | next_tb = cpu_tb_exec(cpu, tc_ptr); |
Peter Maydell | 378df4b | 2013-02-22 18:10:03 +0000 | [diff] [blame] | 626 | switch (next_tb & TB_EXIT_MASK) { |
| 627 | case TB_EXIT_REQUESTED: |
| 628 | /* Something asked us to stop executing |
| 629 | * chained TBs; just continue round the main |
| 630 | * loop. Whatever requested the exit will also |
| 631 | * have set something else (eg exit_request or |
| 632 | * interrupt_request) which we will handle |
| 633 | * next time around the loop. |
| 634 | */ |
| 635 | tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); |
| 636 | next_tb = 0; |
| 637 | break; |
| 638 | case TB_EXIT_ICOUNT_EXPIRED: |
| 639 | { |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 640 | /* Instruction counter expired. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 641 | int insns_left; |
Peter Maydell | 0980011 | 2013-02-22 18:10:00 +0000 | [diff] [blame] | 642 | tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 643 | insns_left = env->icount_decr.u32; |
| 644 | if (env->icount_extra && insns_left >= 0) { |
| 645 | /* Refill decrementer and continue execution. */ |
| 646 | env->icount_extra += insns_left; |
| 647 | if (env->icount_extra > 0xffff) { |
| 648 | insns_left = 0xffff; |
| 649 | } else { |
| 650 | insns_left = env->icount_extra; |
| 651 | } |
| 652 | env->icount_extra -= insns_left; |
| 653 | env->icount_decr.u16.low = insns_left; |
| 654 | } else { |
| 655 | if (insns_left > 0) { |
| 656 | /* Execute remaining instructions. */ |
Blue Swirl | cea5f9a | 2011-05-15 16:03:25 +0000 | [diff] [blame] | 657 | cpu_exec_nocache(env, insns_left, tb); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 658 | } |
| 659 | env->exception_index = EXCP_INTERRUPT; |
| 660 | next_tb = 0; |
Blue Swirl | 1162c04 | 2011-05-14 12:52:35 +0000 | [diff] [blame] | 661 | cpu_loop_exit(env); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 662 | } |
Peter Maydell | 378df4b | 2013-02-22 18:10:03 +0000 | [diff] [blame] | 663 | break; |
| 664 | } |
| 665 | default: |
| 666 | break; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 667 | } |
| 668 | } |
Andreas Färber | d77953b | 2013-01-16 19:29:31 +0100 | [diff] [blame] | 669 | cpu->current_tb = NULL; |
bellard | 4cbf74b | 2003-08-10 21:48:43 +0000 | [diff] [blame] | 670 | /* reset soft MMU for next block (it can currently |
| 671 | only be set by a memory fault) */ |
ths | 50a518e | 2007-06-03 18:52:15 +0000 | [diff] [blame] | 672 | } /* for(;;) */ |
Jan Kiszka | 0d10193 | 2011-07-02 09:50:51 +0200 | [diff] [blame] | 673 | } else { |
| 674 | /* Reload env after longjmp - the compiler may have smashed all |
| 675 | * local variables as longjmp is marked 'noreturn'. */ |
| 676 | env = cpu_single_env; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 677 | } |
bellard | 3fb2ded | 2003-06-24 13:22:59 +0000 | [diff] [blame] | 678 | } /* for(;;) */ |
| 679 | |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 680 | |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 681 | #if defined(TARGET_I386) |
bellard | 9de5e44 | 2003-03-23 16:49:39 +0000 | [diff] [blame] | 682 | /* restore flags in standard format */ |
Blue Swirl | e694d4e | 2011-05-16 19:38:48 +0000 | [diff] [blame] | 683 | env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP) |
| 684 | | (DF & DF_MASK); |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 685 | #elif defined(TARGET_ARM) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 686 | /* XXX: Save/restore host fpu exception state?. */ |
Guan Xuetao | d2fbca9 | 2011-04-12 16:27:03 +0800 | [diff] [blame] | 687 | #elif defined(TARGET_UNICORE32) |
bellard | 93ac68b | 2003-09-30 20:57:29 +0000 | [diff] [blame] | 688 | #elif defined(TARGET_SPARC) |
bellard | 6786730 | 2003-11-23 17:05:30 +0000 | [diff] [blame] | 689 | #elif defined(TARGET_PPC) |
Michael Walle | 81ea0e1 | 2011-02-17 23:45:02 +0100 | [diff] [blame] | 690 | #elif defined(TARGET_LM32) |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 691 | #elif defined(TARGET_M68K) |
| 692 | cpu_m68k_flush_flags(env, env->cc_op); |
| 693 | env->cc_op = CC_OP_FLAGS; |
| 694 | env->sr = (env->sr & 0xffe0) |
| 695 | | env->cc_dest | (env->cc_x << 4); |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 696 | #elif defined(TARGET_MICROBLAZE) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 697 | #elif defined(TARGET_MIPS) |
Anthony Green | d15a9c2 | 2013-03-18 15:49:25 -0400 | [diff] [blame] | 698 | #elif defined(TARGET_MOXIE) |
Jia Liu | e67db06 | 2012-07-20 15:50:39 +0800 | [diff] [blame] | 699 | #elif defined(TARGET_OPENRISC) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 700 | #elif defined(TARGET_SH4) |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 701 | #elif defined(TARGET_ALPHA) |
ths | f1ccf90 | 2007-10-08 13:16:14 +0000 | [diff] [blame] | 702 | #elif defined(TARGET_CRIS) |
Alexander Graf | 10ec511 | 2009-12-05 12:44:21 +0100 | [diff] [blame] | 703 | #elif defined(TARGET_S390X) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 704 | #elif defined(TARGET_XTENSA) |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 705 | /* XXXXX */ |
bellard | e4533c7 | 2003-06-15 19:51:39 +0000 | [diff] [blame] | 706 | #else |
| 707 | #error unsupported target CPU |
| 708 | #endif |
pbrook | 1057eaa | 2007-02-04 13:37:44 +0000 | [diff] [blame] | 709 | |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 710 | /* fail safe : never use cpu_single_env outside cpu_exec() */ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 711 | cpu_single_env = NULL; |
bellard | 7d13299 | 2003-03-06 23:23:54 +0000 | [diff] [blame] | 712 | return ret; |
| 713 | } |