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Aurelien Jarnoafa05232009-10-17 14:17:47 +02001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
Paolo Bonzinicb9c3772012-12-06 12:15:58 +010026#ifndef TCG_TARGET_MIPS
Aurelien Jarnoafa05232009-10-17 14:17:47 +020027#define TCG_TARGET_MIPS 1
28
Richard Hendersonae0218e2014-04-25 19:22:44 +000029#define TCG_TARGET_INSN_UNIT_SIZE 4
Aurelien Jarnoafa05232009-10-17 14:17:47 +020030#define TCG_TARGET_NB_REGS 32
31
Richard Henderson771142c2011-11-09 08:03:33 +000032typedef enum {
Aurelien Jarnoafa05232009-10-17 14:17:47 +020033 TCG_REG_ZERO = 0,
34 TCG_REG_AT,
35 TCG_REG_V0,
36 TCG_REG_V1,
37 TCG_REG_A0,
38 TCG_REG_A1,
39 TCG_REG_A2,
40 TCG_REG_A3,
41 TCG_REG_T0,
42 TCG_REG_T1,
43 TCG_REG_T2,
44 TCG_REG_T3,
45 TCG_REG_T4,
46 TCG_REG_T5,
47 TCG_REG_T6,
48 TCG_REG_T7,
49 TCG_REG_S0,
50 TCG_REG_S1,
51 TCG_REG_S2,
52 TCG_REG_S3,
53 TCG_REG_S4,
54 TCG_REG_S5,
55 TCG_REG_S6,
56 TCG_REG_S7,
57 TCG_REG_T8,
58 TCG_REG_T9,
59 TCG_REG_K0,
60 TCG_REG_K1,
61 TCG_REG_GP,
62 TCG_REG_SP,
Richard Henderson41883902014-04-15 09:03:59 -070063 TCG_REG_S8,
Aurelien Jarnoafa05232009-10-17 14:17:47 +020064 TCG_REG_RA,
Richard Henderson41883902014-04-15 09:03:59 -070065
66 TCG_REG_CALL_STACK = TCG_REG_SP,
67 TCG_AREG0 = TCG_REG_S0,
Richard Henderson771142c2011-11-09 08:03:33 +000068} TCGReg;
Aurelien Jarnoafa05232009-10-17 14:17:47 +020069
Aurelien Jarnoafa05232009-10-17 14:17:47 +020070/* used for function call generation */
Aurelien Jarnoafa05232009-10-17 14:17:47 +020071#define TCG_TARGET_STACK_ALIGN 8
72#define TCG_TARGET_CALL_STACK_OFFSET 16
73#define TCG_TARGET_CALL_ALIGN_ARGS 1
74
Aurelien Jarno988902f2013-08-15 17:57:59 +020075/* MOVN/MOVZ instructions detection */
76#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
77 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
78 defined(_MIPS_ARCH_MIPS4)
79#define use_movnz_instructions 1
80#else
81extern bool use_movnz_instructions;
82#endif
83
84/* MIPS32 instruction set detection */
85#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
86#define use_mips32_instructions 1
87#else
88extern bool use_mips32_instructions;
89#endif
90
91/* MIPS32R2 instruction set detection */
92#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
93#define use_mips32r2_instructions 1
94#else
95extern bool use_mips32r2_instructions;
96#endif
97
Aurelien Jarnoafa05232009-10-17 14:17:47 +020098/* optional instructions */
Richard Henderson25c4d9c2011-08-17 14:11:46 -070099#define TCG_TARGET_HAS_div_i32 1
Richard Hendersonca675f42013-03-11 22:41:47 -0700100#define TCG_TARGET_HAS_rem_i32 1
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700101#define TCG_TARGET_HAS_not_i32 1
102#define TCG_TARGET_HAS_nor_i32 1
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700103#define TCG_TARGET_HAS_andc_i32 0
104#define TCG_TARGET_HAS_orc_i32 0
105#define TCG_TARGET_HAS_eqv_i32 0
106#define TCG_TARGET_HAS_nand_i32 0
Richard Hendersondf9ebea2014-03-26 10:59:14 -0700107#define TCG_TARGET_HAS_mulu2_i32 1
Aurelien Jarno174d4d22013-03-24 01:52:07 +0100108#define TCG_TARGET_HAS_muls2_i32 1
Richard Henderson3c9a8f12013-08-14 14:41:43 -0700109#define TCG_TARGET_HAS_muluh_i32 1
110#define TCG_TARGET_HAS_mulsh_i32 1
Aurelien Jarno7d7c4932012-09-21 18:20:26 +0200111
Aurelien Jarno988902f2013-08-15 17:57:59 +0200112/* optional instructions detected at runtime */
113#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
114#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
115#define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions
116#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
Aurelien Jarno3207bf22013-08-15 17:57:59 +0200117#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
118#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
Aurelien Jarno988902f2013-08-15 17:57:59 +0200119#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
Aurelien Jarnoc1cf85c2012-09-21 18:20:26 +0200120
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200121/* optional instructions automatically implemented */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700122#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
123#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
124#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200125
Brad03938c12011-05-25 23:06:00 -0400126#ifdef __OpenBSD__
127#include <machine/sysarch.h>
128#else
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200129#include <sys/cachectl.h>
Brad03938c12011-05-25 23:06:00 -0400130#endif
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200131
Richard Hendersonb93949e2013-08-20 14:22:50 -0700132static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
Aurelien Jarnoafa05232009-10-17 14:17:47 +0200133{
134 cacheflush ((void *)start, stop-start, ICACHE);
135}
Paolo Bonzinicb9c3772012-12-06 12:15:58 +0100136
137#endif