ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * CRIS emulation for qemu: main translation routines. |
| 3 | * |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008 AXIS Communications AB |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 5 | * Written by Edgar E. Iglesias. |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 21 | /* |
| 22 | * FIXME: |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 23 | * The condition code translation is in need of attention. |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 26 | #include "cpu.h" |
Paolo Bonzini | 76cad71 | 2012-10-24 11:12:21 +0200 | [diff] [blame] | 27 | #include "disas/disas.h" |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 28 | #include "tcg-op.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 29 | #include "exec/helper-proto.h" |
edgar_igl | 5281966 | 2009-01-26 22:21:30 +0000 | [diff] [blame] | 30 | #include "mmu.h" |
Paolo Bonzini | f08b617 | 2014-03-28 19:42:10 +0100 | [diff] [blame] | 31 | #include "exec/cpu_ldst.h" |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 32 | #include "crisv32-decode.h" |
| 33 | |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 34 | #include "exec/helper-gen.h" |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 35 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 36 | #define DISAS_CRIS 0 |
| 37 | #if DISAS_CRIS |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 38 | # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 39 | #else |
aliguori | d12d51d | 2009-01-15 21:48:06 +0000 | [diff] [blame] | 40 | # define LOG_DIS(...) do { } while (0) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 41 | #endif |
| 42 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 43 | #define D(x) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 44 | #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) |
| 45 | #define BUG_ON(x) ({if (x) BUG();}) |
| 46 | |
edgar_igl | 4f400ab | 2008-02-28 09:37:58 +0000 | [diff] [blame] | 47 | #define DISAS_SWI 5 |
| 48 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 49 | /* Used by the decoder. */ |
| 50 | #define EXTRACT_FIELD(src, start, end) \ |
| 51 | (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
| 52 | |
| 53 | #define CC_MASK_NZ 0xc |
| 54 | #define CC_MASK_NZV 0xe |
| 55 | #define CC_MASK_NZVC 0xf |
| 56 | #define CC_MASK_RNZV 0x10e |
| 57 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 58 | static TCGv_ptr cpu_env; |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 59 | static TCGv cpu_R[16]; |
| 60 | static TCGv cpu_PR[16]; |
| 61 | static TCGv cc_x; |
| 62 | static TCGv cc_src; |
| 63 | static TCGv cc_dest; |
| 64 | static TCGv cc_result; |
| 65 | static TCGv cc_op; |
| 66 | static TCGv cc_size; |
| 67 | static TCGv cc_mask; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 68 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 69 | static TCGv env_btaken; |
| 70 | static TCGv env_btarget; |
| 71 | static TCGv env_pc; |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 72 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 73 | #include "exec/gen-icount.h" |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 74 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 75 | /* This is the state at translation time. */ |
| 76 | typedef struct DisasContext { |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 77 | CRISCPU *cpu; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 78 | target_ulong pc, ppc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 79 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 80 | /* Decoder. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 81 | unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 82 | uint32_t ir; |
| 83 | uint32_t opcode; |
| 84 | unsigned int op1; |
| 85 | unsigned int op2; |
| 86 | unsigned int zsize, zzsize; |
| 87 | unsigned int mode; |
| 88 | unsigned int postinc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 89 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 90 | unsigned int size; |
| 91 | unsigned int src; |
| 92 | unsigned int dst; |
| 93 | unsigned int cond; |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 94 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 95 | int update_cc; |
| 96 | int cc_op; |
| 97 | int cc_size; |
| 98 | uint32_t cc_mask; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 99 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 100 | int cc_size_uptodate; /* -1 invalid or last written value. */ |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 101 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 102 | int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */ |
| 103 | int flags_uptodate; /* Wether or not $ccs is uptodate. */ |
| 104 | int flagx_known; /* Wether or not flags_x has the x flag known at |
| 105 | translation time. */ |
| 106 | int flags_x; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 107 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 108 | int clear_x; /* Clear x after this insn? */ |
| 109 | int clear_prefix; /* Clear prefix after this insn? */ |
| 110 | int clear_locked_irq; /* Clear the irq lockout. */ |
| 111 | int cpustate_changed; |
| 112 | unsigned int tb_flags; /* tb dependent flags. */ |
| 113 | int is_jmp; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 114 | |
Edgar E. Iglesias | 5cabc5c | 2011-01-10 23:24:36 +0100 | [diff] [blame] | 115 | #define JMP_NOJMP 0 |
| 116 | #define JMP_DIRECT 1 |
| 117 | #define JMP_DIRECT_CC 2 |
| 118 | #define JMP_INDIRECT 3 |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 119 | int jmp; /* 0=nojmp, 1=direct, 2=indirect. */ |
| 120 | uint32_t jmp_pc; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 121 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 122 | int delayed_branch; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 123 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 124 | struct TranslationBlock *tb; |
| 125 | int singlestep_enabled; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 126 | } DisasContext; |
| 127 | |
blueswir1 | 7ccfb2e | 2008-09-14 06:45:34 +0000 | [diff] [blame] | 128 | static void gen_BUG(DisasContext *dc, const char *file, int line) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 129 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 130 | printf("BUG: pc=%x %s %d\n", dc->pc, file, line); |
| 131 | qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 132 | cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 133 | } |
| 134 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 135 | static const char *regnames[] = |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 136 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 137 | "$r0", "$r1", "$r2", "$r3", |
| 138 | "$r4", "$r5", "$r6", "$r7", |
| 139 | "$r8", "$r9", "$r10", "$r11", |
| 140 | "$r12", "$r13", "$sp", "$acr", |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 141 | }; |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 142 | static const char *pregnames[] = |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 143 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 144 | "$bz", "$vr", "$pid", "$srs", |
| 145 | "$wz", "$exs", "$eda", "$mof", |
| 146 | "$dz", "$ebp", "$erp", "$srp", |
| 147 | "$nrp", "$ccs", "$usp", "$spc", |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 148 | }; |
| 149 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 150 | /* We need this table to handle preg-moves with implicit width. */ |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 151 | static int preg_sizes[] = { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 152 | 1, /* bz. */ |
| 153 | 1, /* vr. */ |
| 154 | 4, /* pid. */ |
| 155 | 1, /* srs. */ |
| 156 | 2, /* wz. */ |
| 157 | 4, 4, 4, |
| 158 | 4, 4, 4, 4, |
| 159 | 4, 4, 4, 4, |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 160 | }; |
| 161 | |
| 162 | #define t_gen_mov_TN_env(tn, member) \ |
Peter Maydell | 37654d9 | 2014-06-07 18:03:02 +0100 | [diff] [blame] | 163 | tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 164 | #define t_gen_mov_env_TN(member, tn) \ |
Peter Maydell | 37654d9 | 2014-06-07 18:03:02 +0100 | [diff] [blame] | 165 | tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 166 | |
| 167 | static inline void t_gen_mov_TN_preg(TCGv tn, int r) |
| 168 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 169 | if (r < 0 || r > 15) { |
| 170 | fprintf(stderr, "wrong register read $p%d\n", r); |
| 171 | } |
| 172 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { |
| 173 | tcg_gen_mov_tl(tn, tcg_const_tl(0)); |
| 174 | } else if (r == PR_VR) { |
| 175 | tcg_gen_mov_tl(tn, tcg_const_tl(32)); |
| 176 | } else { |
| 177 | tcg_gen_mov_tl(tn, cpu_PR[r]); |
| 178 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 179 | } |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 180 | static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 181 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 182 | if (r < 0 || r > 15) { |
| 183 | fprintf(stderr, "wrong register write $p%d\n", r); |
| 184 | } |
| 185 | if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { |
| 186 | return; |
| 187 | } else if (r == PR_SRS) { |
| 188 | tcg_gen_andi_tl(cpu_PR[r], tn, 3); |
| 189 | } else { |
| 190 | if (r == PR_PID) { |
| 191 | gen_helper_tlb_flush_pid(cpu_env, tn); |
| 192 | } |
| 193 | if (dc->tb_flags & S_FLAG && r == PR_SPC) { |
| 194 | gen_helper_spc_write(cpu_env, tn); |
| 195 | } else if (r == PR_CCS) { |
| 196 | dc->cpustate_changed = 1; |
| 197 | } |
| 198 | tcg_gen_mov_tl(cpu_PR[r], tn); |
| 199 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 200 | } |
| 201 | |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 202 | /* Sign extend at translation time. */ |
| 203 | static int sign_extend(unsigned int val, unsigned int width) |
| 204 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 205 | int sval; |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 206 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 207 | /* LSL. */ |
| 208 | val <<= 31 - width; |
| 209 | sval = val; |
| 210 | /* ASR. */ |
| 211 | sval >>= 31 - width; |
| 212 | return sval; |
Edgar E. Iglesias | 1884533 | 2010-06-16 13:46:15 +0200 | [diff] [blame] | 213 | } |
| 214 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 215 | static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 216 | unsigned int size, unsigned int sign) |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 217 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 218 | int r; |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 219 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 220 | switch (size) { |
| 221 | case 4: |
| 222 | { |
| 223 | r = cpu_ldl_code(env, addr); |
| 224 | break; |
| 225 | } |
| 226 | case 2: |
| 227 | { |
| 228 | if (sign) { |
| 229 | r = cpu_ldsw_code(env, addr); |
| 230 | } else { |
| 231 | r = cpu_lduw_code(env, addr); |
| 232 | } |
| 233 | break; |
| 234 | } |
| 235 | case 1: |
| 236 | { |
| 237 | if (sign) { |
| 238 | r = cpu_ldsb_code(env, addr); |
| 239 | } else { |
| 240 | r = cpu_ldub_code(env, addr); |
| 241 | } |
| 242 | break; |
| 243 | } |
| 244 | default: |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 245 | cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 246 | break; |
| 247 | } |
| 248 | return r; |
Edgar E. Iglesias | 7de141c | 2010-06-16 11:49:30 +0200 | [diff] [blame] | 249 | } |
| 250 | |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 251 | static void cris_lock_irq(DisasContext *dc) |
| 252 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 253 | dc->clear_locked_irq = 0; |
| 254 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(1)); |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 255 | } |
| 256 | |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 257 | static inline void t_gen_raise_exception(uint32_t index) |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 258 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 259 | TCGv_i32 tmp = tcg_const_i32(index); |
Aurelien Jarno | febc992 | 2012-08-30 16:56:39 +0200 | [diff] [blame] | 260 | gen_helper_raise_exception(cpu_env, tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 261 | tcg_temp_free_i32(tmp); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static void t_gen_lsl(TCGv d, TCGv a, TCGv b) |
| 265 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 266 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 267 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 268 | t0 = tcg_temp_new(); |
| 269 | t_31 = tcg_const_tl(31); |
| 270 | tcg_gen_shl_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 271 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 272 | tcg_gen_sub_tl(t0, t_31, b); |
| 273 | tcg_gen_sar_tl(t0, t0, t_31); |
| 274 | tcg_gen_and_tl(t0, t0, d); |
| 275 | tcg_gen_xor_tl(d, d, t0); |
| 276 | tcg_temp_free(t0); |
| 277 | tcg_temp_free(t_31); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | static void t_gen_lsr(TCGv d, TCGv a, TCGv b) |
| 281 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 282 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 283 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 284 | t0 = tcg_temp_new(); |
| 285 | t_31 = tcg_temp_new(); |
| 286 | tcg_gen_shr_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 287 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 288 | tcg_gen_movi_tl(t_31, 31); |
| 289 | tcg_gen_sub_tl(t0, t_31, b); |
| 290 | tcg_gen_sar_tl(t0, t0, t_31); |
| 291 | tcg_gen_and_tl(t0, t0, d); |
| 292 | tcg_gen_xor_tl(d, d, t0); |
| 293 | tcg_temp_free(t0); |
| 294 | tcg_temp_free(t_31); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | static void t_gen_asr(TCGv d, TCGv a, TCGv b) |
| 298 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 299 | TCGv t0, t_31; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 300 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 301 | t0 = tcg_temp_new(); |
| 302 | t_31 = tcg_temp_new(); |
| 303 | tcg_gen_sar_tl(d, a, b); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 304 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 305 | tcg_gen_movi_tl(t_31, 31); |
| 306 | tcg_gen_sub_tl(t0, t_31, b); |
| 307 | tcg_gen_sar_tl(t0, t0, t_31); |
| 308 | tcg_gen_or_tl(d, d, t0); |
| 309 | tcg_temp_free(t0); |
| 310 | tcg_temp_free(t_31); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 311 | } |
| 312 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 313 | static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 314 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 315 | int l1; |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 316 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 317 | l1 = gen_new_label(); |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 318 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 319 | /* |
| 320 | * d <<= 1 |
| 321 | * if (d >= s) |
| 322 | * d -= s; |
| 323 | */ |
| 324 | tcg_gen_shli_tl(d, a, 1); |
| 325 | tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1); |
| 326 | tcg_gen_sub_tl(d, d, b); |
| 327 | gen_set_label(l1); |
edgar_igl | aae6b32 | 2008-05-03 21:34:39 +0000 | [diff] [blame] | 328 | } |
| 329 | |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 330 | static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) |
| 331 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 332 | TCGv t; |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 333 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 334 | /* |
| 335 | * d <<= 1 |
| 336 | * if (n) |
| 337 | * d += s; |
| 338 | */ |
| 339 | t = tcg_temp_new(); |
| 340 | tcg_gen_shli_tl(d, a, 1); |
| 341 | tcg_gen_shli_tl(t, ccs, 31 - 3); |
| 342 | tcg_gen_sari_tl(t, t, 31); |
| 343 | tcg_gen_and_tl(t, t, b); |
| 344 | tcg_gen_add_tl(d, d, t); |
| 345 | tcg_temp_free(t); |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 346 | } |
| 347 | |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 348 | /* Extended arithmetics on CRIS. */ |
| 349 | static inline void t_gen_add_flag(TCGv d, int flag) |
| 350 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 351 | TCGv c; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 352 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 353 | c = tcg_temp_new(); |
| 354 | t_gen_mov_TN_preg(c, PR_CCS); |
| 355 | /* Propagate carry into d. */ |
| 356 | tcg_gen_andi_tl(c, c, 1 << flag); |
| 357 | if (flag) { |
| 358 | tcg_gen_shri_tl(c, c, flag); |
| 359 | } |
| 360 | tcg_gen_add_tl(d, d, c); |
| 361 | tcg_temp_free(c); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 362 | } |
| 363 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 364 | static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 365 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 366 | if (dc->flagx_known) { |
| 367 | if (dc->flags_x) { |
| 368 | TCGv c; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 369 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 370 | c = tcg_temp_new(); |
| 371 | t_gen_mov_TN_preg(c, PR_CCS); |
| 372 | /* C flag is already at bit 0. */ |
| 373 | tcg_gen_andi_tl(c, c, C_FLAG); |
| 374 | tcg_gen_add_tl(d, d, c); |
| 375 | tcg_temp_free(c); |
| 376 | } |
| 377 | } else { |
| 378 | TCGv x, c; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 379 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 380 | x = tcg_temp_new(); |
| 381 | c = tcg_temp_new(); |
| 382 | t_gen_mov_TN_preg(x, PR_CCS); |
| 383 | tcg_gen_mov_tl(c, x); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 384 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 385 | /* Propagate carry into d if X is set. Branch free. */ |
| 386 | tcg_gen_andi_tl(c, c, C_FLAG); |
| 387 | tcg_gen_andi_tl(x, x, X_FLAG); |
| 388 | tcg_gen_shri_tl(x, x, 4); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 389 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 390 | tcg_gen_and_tl(x, x, c); |
| 391 | tcg_gen_add_tl(d, d, x); |
| 392 | tcg_temp_free(x); |
| 393 | tcg_temp_free(c); |
| 394 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 395 | } |
| 396 | |
edgar_igl | a39f8f3 | 2008-05-12 07:57:23 +0000 | [diff] [blame] | 397 | static inline void t_gen_subx_carry(DisasContext *dc, TCGv d) |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 398 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 399 | if (dc->flagx_known) { |
| 400 | if (dc->flags_x) { |
| 401 | TCGv c; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 402 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 403 | c = tcg_temp_new(); |
| 404 | t_gen_mov_TN_preg(c, PR_CCS); |
| 405 | /* C flag is already at bit 0. */ |
| 406 | tcg_gen_andi_tl(c, c, C_FLAG); |
| 407 | tcg_gen_sub_tl(d, d, c); |
| 408 | tcg_temp_free(c); |
| 409 | } |
| 410 | } else { |
| 411 | TCGv x, c; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 412 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 413 | x = tcg_temp_new(); |
| 414 | c = tcg_temp_new(); |
| 415 | t_gen_mov_TN_preg(x, PR_CCS); |
| 416 | tcg_gen_mov_tl(c, x); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 417 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 418 | /* Propagate carry into d if X is set. Branch free. */ |
| 419 | tcg_gen_andi_tl(c, c, C_FLAG); |
| 420 | tcg_gen_andi_tl(x, x, X_FLAG); |
| 421 | tcg_gen_shri_tl(x, x, 4); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 422 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 423 | tcg_gen_and_tl(x, x, c); |
| 424 | tcg_gen_sub_tl(d, d, x); |
| 425 | tcg_temp_free(x); |
| 426 | tcg_temp_free(c); |
| 427 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | /* Swap the two bytes within each half word of the s operand. |
| 431 | T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */ |
| 432 | static inline void t_gen_swapb(TCGv d, TCGv s) |
| 433 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 434 | TCGv t, org_s; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 435 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 436 | t = tcg_temp_new(); |
| 437 | org_s = tcg_temp_new(); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 438 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 439 | /* d and s may refer to the same object. */ |
| 440 | tcg_gen_mov_tl(org_s, s); |
| 441 | tcg_gen_shli_tl(t, org_s, 8); |
| 442 | tcg_gen_andi_tl(d, t, 0xff00ff00); |
| 443 | tcg_gen_shri_tl(t, org_s, 8); |
| 444 | tcg_gen_andi_tl(t, t, 0x00ff00ff); |
| 445 | tcg_gen_or_tl(d, d, t); |
| 446 | tcg_temp_free(t); |
| 447 | tcg_temp_free(org_s); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | /* Swap the halfwords of the s operand. */ |
| 451 | static inline void t_gen_swapw(TCGv d, TCGv s) |
| 452 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 453 | TCGv t; |
| 454 | /* d and s refer the same object. */ |
| 455 | t = tcg_temp_new(); |
| 456 | tcg_gen_mov_tl(t, s); |
| 457 | tcg_gen_shli_tl(d, t, 16); |
| 458 | tcg_gen_shri_tl(t, t, 16); |
| 459 | tcg_gen_or_tl(d, d, t); |
| 460 | tcg_temp_free(t); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 461 | } |
| 462 | |
| 463 | /* Reverse the within each byte. |
| 464 | T0 = (((T0 << 7) & 0x80808080) | |
| 465 | ((T0 << 5) & 0x40404040) | |
| 466 | ((T0 << 3) & 0x20202020) | |
| 467 | ((T0 << 1) & 0x10101010) | |
| 468 | ((T0 >> 1) & 0x08080808) | |
| 469 | ((T0 >> 3) & 0x04040404) | |
| 470 | ((T0 >> 5) & 0x02020202) | |
| 471 | ((T0 >> 7) & 0x01010101)); |
| 472 | */ |
| 473 | static inline void t_gen_swapr(TCGv d, TCGv s) |
| 474 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 475 | struct { |
| 476 | int shift; /* LSL when positive, LSR when negative. */ |
| 477 | uint32_t mask; |
| 478 | } bitrev[] = { |
| 479 | {7, 0x80808080}, |
| 480 | {5, 0x40404040}, |
| 481 | {3, 0x20202020}, |
| 482 | {1, 0x10101010}, |
| 483 | {-1, 0x08080808}, |
| 484 | {-3, 0x04040404}, |
| 485 | {-5, 0x02020202}, |
| 486 | {-7, 0x01010101} |
| 487 | }; |
| 488 | int i; |
| 489 | TCGv t, org_s; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 490 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 491 | /* d and s refer the same object. */ |
| 492 | t = tcg_temp_new(); |
| 493 | org_s = tcg_temp_new(); |
| 494 | tcg_gen_mov_tl(org_s, s); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 495 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 496 | tcg_gen_shli_tl(t, org_s, bitrev[0].shift); |
| 497 | tcg_gen_andi_tl(d, t, bitrev[0].mask); |
| 498 | for (i = 1; i < ARRAY_SIZE(bitrev); i++) { |
| 499 | if (bitrev[i].shift >= 0) { |
| 500 | tcg_gen_shli_tl(t, org_s, bitrev[i].shift); |
| 501 | } else { |
| 502 | tcg_gen_shri_tl(t, org_s, -bitrev[i].shift); |
| 503 | } |
| 504 | tcg_gen_andi_tl(t, t, bitrev[i].mask); |
| 505 | tcg_gen_or_tl(d, d, t); |
| 506 | } |
| 507 | tcg_temp_free(t); |
| 508 | tcg_temp_free(org_s); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 509 | } |
| 510 | |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 511 | static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false) |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 512 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 513 | int l1; |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 514 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 515 | l1 = gen_new_label(); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 516 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 517 | /* Conditional jmp. */ |
| 518 | tcg_gen_mov_tl(env_pc, pc_false); |
| 519 | tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1); |
| 520 | tcg_gen_mov_tl(env_pc, pc_true); |
| 521 | gen_set_label(l1); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 522 | } |
| 523 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 524 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
| 525 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 526 | TranslationBlock *tb; |
| 527 | tb = dc->tb; |
| 528 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { |
| 529 | tcg_gen_goto_tb(n); |
| 530 | tcg_gen_movi_tl(env_pc, dest); |
Richard Henderson | 8cfd049 | 2013-08-20 15:53:10 -0700 | [diff] [blame] | 531 | tcg_gen_exit_tb((uintptr_t)tb + n); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 532 | } else { |
| 533 | tcg_gen_movi_tl(env_pc, dest); |
| 534 | tcg_gen_exit_tb(0); |
| 535 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 536 | } |
| 537 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 538 | static inline void cris_clear_x_flag(DisasContext *dc) |
| 539 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 540 | if (dc->flagx_known && dc->flags_x) { |
| 541 | dc->flags_uptodate = 0; |
| 542 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 543 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 544 | dc->flagx_known = 1; |
| 545 | dc->flags_x = 0; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 546 | } |
| 547 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 548 | static void cris_flush_cc_state(DisasContext *dc) |
| 549 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 550 | if (dc->cc_size_uptodate != dc->cc_size) { |
| 551 | tcg_gen_movi_tl(cc_size, dc->cc_size); |
| 552 | dc->cc_size_uptodate = dc->cc_size; |
| 553 | } |
| 554 | tcg_gen_movi_tl(cc_op, dc->cc_op); |
| 555 | tcg_gen_movi_tl(cc_mask, dc->cc_mask); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 556 | } |
| 557 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 558 | static void cris_evaluate_flags(DisasContext *dc) |
| 559 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 560 | if (dc->flags_uptodate) { |
| 561 | return; |
| 562 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 563 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 564 | cris_flush_cc_state(dc); |
edgar_igl | 6231868 | 2009-01-07 23:38:41 +0000 | [diff] [blame] | 565 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 566 | switch (dc->cc_op) { |
| 567 | case CC_OP_MCP: |
| 568 | gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, |
| 569 | cpu_PR[PR_CCS], cc_src, |
| 570 | cc_dest, cc_result); |
| 571 | break; |
| 572 | case CC_OP_MULS: |
| 573 | gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, |
| 574 | cpu_PR[PR_CCS], cc_result, |
| 575 | cpu_PR[PR_MOF]); |
| 576 | break; |
| 577 | case CC_OP_MULU: |
| 578 | gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, |
| 579 | cpu_PR[PR_CCS], cc_result, |
| 580 | cpu_PR[PR_MOF]); |
| 581 | break; |
| 582 | case CC_OP_MOVE: |
| 583 | case CC_OP_AND: |
| 584 | case CC_OP_OR: |
| 585 | case CC_OP_XOR: |
| 586 | case CC_OP_ASR: |
| 587 | case CC_OP_LSR: |
| 588 | case CC_OP_LSL: |
| 589 | switch (dc->cc_size) { |
| 590 | case 4: |
| 591 | gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], |
| 592 | cpu_env, cpu_PR[PR_CCS], cc_result); |
| 593 | break; |
| 594 | case 2: |
| 595 | gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], |
| 596 | cpu_env, cpu_PR[PR_CCS], cc_result); |
| 597 | break; |
| 598 | default: |
| 599 | gen_helper_evaluate_flags(cpu_env); |
| 600 | break; |
edgar_igl | 6231868 | 2009-01-07 23:38:41 +0000 | [diff] [blame] | 601 | } |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 602 | break; |
| 603 | case CC_OP_FLAGS: |
| 604 | /* live. */ |
| 605 | break; |
| 606 | case CC_OP_SUB: |
| 607 | case CC_OP_CMP: |
| 608 | if (dc->cc_size == 4) { |
| 609 | gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, |
| 610 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); |
| 611 | } else { |
| 612 | gen_helper_evaluate_flags(cpu_env); |
| 613 | } |
| 614 | |
| 615 | break; |
| 616 | default: |
| 617 | switch (dc->cc_size) { |
| 618 | case 4: |
| 619 | gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, |
| 620 | cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); |
| 621 | break; |
| 622 | default: |
| 623 | gen_helper_evaluate_flags(cpu_env); |
| 624 | break; |
| 625 | } |
| 626 | break; |
| 627 | } |
| 628 | |
| 629 | if (dc->flagx_known) { |
| 630 | if (dc->flags_x) { |
| 631 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG); |
| 632 | } else if (dc->cc_op == CC_OP_FLAGS) { |
| 633 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG); |
| 634 | } |
| 635 | } |
| 636 | dc->flags_uptodate = 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static void cris_cc_mask(DisasContext *dc, unsigned int mask) |
| 640 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 641 | uint32_t ovl; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 642 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 643 | if (!mask) { |
| 644 | dc->update_cc = 0; |
| 645 | return; |
| 646 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 647 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 648 | /* Check if we need to evaluate the condition codes due to |
| 649 | CC overlaying. */ |
| 650 | ovl = (dc->cc_mask ^ mask) & ~mask; |
| 651 | if (ovl) { |
| 652 | /* TODO: optimize this case. It trigs all the time. */ |
| 653 | cris_evaluate_flags(dc); |
| 654 | } |
| 655 | dc->cc_mask = mask; |
| 656 | dc->update_cc = 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 657 | } |
| 658 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 659 | static void cris_update_cc_op(DisasContext *dc, int op, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 660 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 661 | dc->cc_op = op; |
| 662 | dc->cc_size = size; |
| 663 | dc->flags_uptodate = 0; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 664 | } |
| 665 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 666 | static inline void cris_update_cc_x(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 667 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 668 | /* Save the x flag state at the time of the cc snapshot. */ |
| 669 | if (dc->flagx_known) { |
| 670 | if (dc->cc_x_uptodate == (2 | dc->flags_x)) { |
| 671 | return; |
| 672 | } |
| 673 | tcg_gen_movi_tl(cc_x, dc->flags_x); |
| 674 | dc->cc_x_uptodate = 2 | dc->flags_x; |
| 675 | } else { |
| 676 | tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG); |
| 677 | dc->cc_x_uptodate = 1; |
| 678 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 679 | } |
| 680 | |
| 681 | /* Update cc prior to executing ALU op. Needs source operands untouched. */ |
| 682 | static void cris_pre_alu_update_cc(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 683 | TCGv dst, TCGv src, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 684 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 685 | if (dc->update_cc) { |
| 686 | cris_update_cc_op(dc, op, size); |
| 687 | tcg_gen_mov_tl(cc_src, src); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 688 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 689 | if (op != CC_OP_MOVE |
| 690 | && op != CC_OP_AND |
| 691 | && op != CC_OP_OR |
| 692 | && op != CC_OP_XOR |
| 693 | && op != CC_OP_ASR |
| 694 | && op != CC_OP_LSR |
| 695 | && op != CC_OP_LSL) { |
| 696 | tcg_gen_mov_tl(cc_dest, dst); |
| 697 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 698 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 699 | cris_update_cc_x(dc); |
| 700 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 701 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 702 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 703 | /* Update cc after executing ALU op. needs the result. */ |
| 704 | static inline void cris_update_result(DisasContext *dc, TCGv res) |
| 705 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 706 | if (dc->update_cc) { |
| 707 | tcg_gen_mov_tl(cc_result, res); |
| 708 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 709 | } |
| 710 | |
| 711 | /* Returns one if the write back stage should execute. */ |
| 712 | static void cris_alu_op_exec(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 713 | TCGv dst, TCGv a, TCGv b, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 714 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 715 | /* Emit the ALU insns. */ |
| 716 | switch (op) { |
| 717 | case CC_OP_ADD: |
| 718 | tcg_gen_add_tl(dst, a, b); |
| 719 | /* Extended arithmetics. */ |
| 720 | t_gen_addx_carry(dc, dst); |
| 721 | break; |
| 722 | case CC_OP_ADDC: |
| 723 | tcg_gen_add_tl(dst, a, b); |
| 724 | t_gen_add_flag(dst, 0); /* C_FLAG. */ |
| 725 | break; |
| 726 | case CC_OP_MCP: |
| 727 | tcg_gen_add_tl(dst, a, b); |
| 728 | t_gen_add_flag(dst, 8); /* R_FLAG. */ |
| 729 | break; |
| 730 | case CC_OP_SUB: |
| 731 | tcg_gen_sub_tl(dst, a, b); |
| 732 | /* Extended arithmetics. */ |
| 733 | t_gen_subx_carry(dc, dst); |
| 734 | break; |
| 735 | case CC_OP_MOVE: |
| 736 | tcg_gen_mov_tl(dst, b); |
| 737 | break; |
| 738 | case CC_OP_OR: |
| 739 | tcg_gen_or_tl(dst, a, b); |
| 740 | break; |
| 741 | case CC_OP_AND: |
| 742 | tcg_gen_and_tl(dst, a, b); |
| 743 | break; |
| 744 | case CC_OP_XOR: |
| 745 | tcg_gen_xor_tl(dst, a, b); |
| 746 | break; |
| 747 | case CC_OP_LSL: |
| 748 | t_gen_lsl(dst, a, b); |
| 749 | break; |
| 750 | case CC_OP_LSR: |
| 751 | t_gen_lsr(dst, a, b); |
| 752 | break; |
| 753 | case CC_OP_ASR: |
| 754 | t_gen_asr(dst, a, b); |
| 755 | break; |
| 756 | case CC_OP_NEG: |
| 757 | tcg_gen_neg_tl(dst, b); |
| 758 | /* Extended arithmetics. */ |
| 759 | t_gen_subx_carry(dc, dst); |
| 760 | break; |
| 761 | case CC_OP_LZ: |
| 762 | gen_helper_lz(dst, b); |
| 763 | break; |
| 764 | case CC_OP_MULS: |
Richard Henderson | bf45f97 | 2013-02-19 23:52:11 -0800 | [diff] [blame] | 765 | tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 766 | break; |
| 767 | case CC_OP_MULU: |
Richard Henderson | bf45f97 | 2013-02-19 23:52:11 -0800 | [diff] [blame] | 768 | tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 769 | break; |
| 770 | case CC_OP_DSTEP: |
| 771 | t_gen_cris_dstep(dst, a, b); |
| 772 | break; |
| 773 | case CC_OP_MSTEP: |
| 774 | t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]); |
| 775 | break; |
| 776 | case CC_OP_BOUND: |
| 777 | { |
| 778 | int l1; |
| 779 | l1 = gen_new_label(); |
| 780 | tcg_gen_mov_tl(dst, a); |
| 781 | tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1); |
| 782 | tcg_gen_mov_tl(dst, b); |
| 783 | gen_set_label(l1); |
| 784 | } |
| 785 | break; |
| 786 | case CC_OP_CMP: |
| 787 | tcg_gen_sub_tl(dst, a, b); |
| 788 | /* Extended arithmetics. */ |
| 789 | t_gen_subx_carry(dc, dst); |
| 790 | break; |
| 791 | default: |
| 792 | qemu_log("illegal ALU op.\n"); |
| 793 | BUG(); |
| 794 | break; |
| 795 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 796 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 797 | if (size == 1) { |
| 798 | tcg_gen_andi_tl(dst, dst, 0xff); |
| 799 | } else if (size == 2) { |
| 800 | tcg_gen_andi_tl(dst, dst, 0xffff); |
| 801 | } |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | static void cris_alu(DisasContext *dc, int op, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 805 | TCGv d, TCGv op_a, TCGv op_b, int size) |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 806 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 807 | TCGv tmp; |
| 808 | int writeback; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 809 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 810 | writeback = 1; |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 811 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 812 | if (op == CC_OP_CMP) { |
| 813 | tmp = tcg_temp_new(); |
| 814 | writeback = 0; |
| 815 | } else if (size == 4) { |
| 816 | tmp = d; |
| 817 | writeback = 0; |
| 818 | } else { |
| 819 | tmp = tcg_temp_new(); |
| 820 | } |
edgar_igl | 4469629 | 2008-10-28 00:13:15 +0000 | [diff] [blame] | 821 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 822 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 823 | cris_pre_alu_update_cc(dc, op, op_a, op_b, size); |
| 824 | cris_alu_op_exec(dc, op, tmp, op_a, op_b, size); |
| 825 | cris_update_result(dc, tmp); |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 826 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 827 | /* Writeback. */ |
| 828 | if (writeback) { |
| 829 | if (size == 1) { |
| 830 | tcg_gen_andi_tl(d, d, ~0xff); |
| 831 | } else { |
| 832 | tcg_gen_andi_tl(d, d, ~0xffff); |
| 833 | } |
| 834 | tcg_gen_or_tl(d, d, tmp); |
| 835 | } |
| 836 | if (!TCGV_EQUAL(tmp, d)) { |
| 837 | tcg_temp_free(tmp); |
| 838 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 839 | } |
| 840 | |
| 841 | static int arith_cc(DisasContext *dc) |
| 842 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 843 | if (dc->update_cc) { |
| 844 | switch (dc->cc_op) { |
| 845 | case CC_OP_ADDC: return 1; |
| 846 | case CC_OP_ADD: return 1; |
| 847 | case CC_OP_SUB: return 1; |
| 848 | case CC_OP_DSTEP: return 1; |
| 849 | case CC_OP_LSL: return 1; |
| 850 | case CC_OP_LSR: return 1; |
| 851 | case CC_OP_ASR: return 1; |
| 852 | case CC_OP_CMP: return 1; |
| 853 | case CC_OP_NEG: return 1; |
| 854 | case CC_OP_OR: return 1; |
| 855 | case CC_OP_AND: return 1; |
| 856 | case CC_OP_XOR: return 1; |
| 857 | case CC_OP_MULU: return 1; |
| 858 | case CC_OP_MULS: return 1; |
| 859 | default: |
| 860 | return 0; |
| 861 | } |
| 862 | } |
| 863 | return 0; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 864 | } |
| 865 | |
edgar_igl | c5631f4 | 2008-10-27 13:52:44 +0000 | [diff] [blame] | 866 | static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 867 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 868 | int arith_opt, move_opt; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 869 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 870 | /* TODO: optimize more condition codes. */ |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 871 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 872 | /* |
| 873 | * If the flags are live, we've gotta look into the bits of CCS. |
| 874 | * Otherwise, if we just did an arithmetic operation we try to |
| 875 | * evaluate the condition code faster. |
| 876 | * |
| 877 | * When this function is done, T0 should be non-zero if the condition |
| 878 | * code is true. |
| 879 | */ |
| 880 | arith_opt = arith_cc(dc) && !dc->flags_uptodate; |
| 881 | move_opt = (dc->cc_op == CC_OP_MOVE); |
| 882 | switch (cond) { |
| 883 | case CC_EQ: |
| 884 | if ((arith_opt || move_opt) |
| 885 | && dc->cc_x_uptodate != (2 | X_FLAG)) { |
| 886 | tcg_gen_setcond_tl(TCG_COND_EQ, cc, |
| 887 | cc_result, tcg_const_tl(0)); |
| 888 | } else { |
| 889 | cris_evaluate_flags(dc); |
| 890 | tcg_gen_andi_tl(cc, |
| 891 | cpu_PR[PR_CCS], Z_FLAG); |
| 892 | } |
| 893 | break; |
| 894 | case CC_NE: |
| 895 | if ((arith_opt || move_opt) |
| 896 | && dc->cc_x_uptodate != (2 | X_FLAG)) { |
| 897 | tcg_gen_mov_tl(cc, cc_result); |
| 898 | } else { |
| 899 | cris_evaluate_flags(dc); |
| 900 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 901 | Z_FLAG); |
| 902 | tcg_gen_andi_tl(cc, cc, Z_FLAG); |
| 903 | } |
| 904 | break; |
| 905 | case CC_CS: |
| 906 | cris_evaluate_flags(dc); |
| 907 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG); |
| 908 | break; |
| 909 | case CC_CC: |
| 910 | cris_evaluate_flags(dc); |
| 911 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG); |
| 912 | tcg_gen_andi_tl(cc, cc, C_FLAG); |
| 913 | break; |
| 914 | case CC_VS: |
| 915 | cris_evaluate_flags(dc); |
| 916 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG); |
| 917 | break; |
| 918 | case CC_VC: |
| 919 | cris_evaluate_flags(dc); |
| 920 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 921 | V_FLAG); |
| 922 | tcg_gen_andi_tl(cc, cc, V_FLAG); |
| 923 | break; |
| 924 | case CC_PL: |
| 925 | if (arith_opt || move_opt) { |
| 926 | int bits = 31; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 927 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 928 | if (dc->cc_size == 1) { |
| 929 | bits = 7; |
| 930 | } else if (dc->cc_size == 2) { |
| 931 | bits = 15; |
| 932 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 933 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 934 | tcg_gen_shri_tl(cc, cc_result, bits); |
| 935 | tcg_gen_xori_tl(cc, cc, 1); |
| 936 | } else { |
| 937 | cris_evaluate_flags(dc); |
| 938 | tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], |
| 939 | N_FLAG); |
| 940 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 941 | } |
| 942 | break; |
| 943 | case CC_MI: |
| 944 | if (arith_opt || move_opt) { |
| 945 | int bits = 31; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 946 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 947 | if (dc->cc_size == 1) { |
| 948 | bits = 7; |
| 949 | } else if (dc->cc_size == 2) { |
| 950 | bits = 15; |
| 951 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 952 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 953 | tcg_gen_shri_tl(cc, cc_result, bits); |
| 954 | tcg_gen_andi_tl(cc, cc, 1); |
| 955 | } else { |
| 956 | cris_evaluate_flags(dc); |
| 957 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], |
| 958 | N_FLAG); |
| 959 | } |
| 960 | break; |
| 961 | case CC_LS: |
| 962 | cris_evaluate_flags(dc); |
| 963 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], |
| 964 | C_FLAG | Z_FLAG); |
| 965 | break; |
| 966 | case CC_HI: |
| 967 | cris_evaluate_flags(dc); |
| 968 | { |
| 969 | TCGv tmp; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 970 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 971 | tmp = tcg_temp_new(); |
| 972 | tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS], |
| 973 | C_FLAG | Z_FLAG); |
| 974 | /* Overlay the C flag on top of the Z. */ |
| 975 | tcg_gen_shli_tl(cc, tmp, 2); |
| 976 | tcg_gen_and_tl(cc, tmp, cc); |
| 977 | tcg_gen_andi_tl(cc, cc, Z_FLAG); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 978 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 979 | tcg_temp_free(tmp); |
| 980 | } |
| 981 | break; |
| 982 | case CC_GE: |
| 983 | cris_evaluate_flags(dc); |
| 984 | /* Overlay the V flag on top of the N. */ |
| 985 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); |
| 986 | tcg_gen_xor_tl(cc, |
| 987 | cpu_PR[PR_CCS], cc); |
| 988 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 989 | tcg_gen_xori_tl(cc, cc, N_FLAG); |
| 990 | break; |
| 991 | case CC_LT: |
| 992 | cris_evaluate_flags(dc); |
| 993 | /* Overlay the V flag on top of the N. */ |
| 994 | tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2); |
| 995 | tcg_gen_xor_tl(cc, |
| 996 | cpu_PR[PR_CCS], cc); |
| 997 | tcg_gen_andi_tl(cc, cc, N_FLAG); |
| 998 | break; |
| 999 | case CC_GT: |
| 1000 | cris_evaluate_flags(dc); |
| 1001 | { |
| 1002 | TCGv n, z; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1003 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1004 | n = tcg_temp_new(); |
| 1005 | z = tcg_temp_new(); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1006 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1007 | /* To avoid a shift we overlay everything on |
| 1008 | the V flag. */ |
| 1009 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); |
| 1010 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); |
| 1011 | /* invert Z. */ |
| 1012 | tcg_gen_xori_tl(z, z, 2); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1013 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1014 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 1015 | tcg_gen_xori_tl(n, n, 2); |
| 1016 | tcg_gen_and_tl(cc, z, n); |
| 1017 | tcg_gen_andi_tl(cc, cc, 2); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1018 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1019 | tcg_temp_free(n); |
| 1020 | tcg_temp_free(z); |
| 1021 | } |
| 1022 | break; |
| 1023 | case CC_LE: |
| 1024 | cris_evaluate_flags(dc); |
| 1025 | { |
| 1026 | TCGv n, z; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1027 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1028 | n = tcg_temp_new(); |
| 1029 | z = tcg_temp_new(); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1030 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1031 | /* To avoid a shift we overlay everything on |
| 1032 | the V flag. */ |
| 1033 | tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2); |
| 1034 | tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1035 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1036 | tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); |
| 1037 | tcg_gen_or_tl(cc, z, n); |
| 1038 | tcg_gen_andi_tl(cc, cc, 2); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1039 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1040 | tcg_temp_free(n); |
| 1041 | tcg_temp_free(z); |
| 1042 | } |
| 1043 | break; |
| 1044 | case CC_P: |
| 1045 | cris_evaluate_flags(dc); |
| 1046 | tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG); |
| 1047 | break; |
| 1048 | case CC_A: |
| 1049 | tcg_gen_movi_tl(cc, 1); |
| 1050 | break; |
| 1051 | default: |
| 1052 | BUG(); |
| 1053 | break; |
| 1054 | }; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1055 | } |
| 1056 | |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1057 | static void cris_store_direct_jmp(DisasContext *dc) |
| 1058 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1059 | /* Store the direct jmp state into the cpu-state. */ |
| 1060 | if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { |
| 1061 | if (dc->jmp == JMP_DIRECT) { |
| 1062 | tcg_gen_movi_tl(env_btaken, 1); |
| 1063 | } |
| 1064 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
| 1065 | dc->jmp = JMP_INDIRECT; |
| 1066 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1067 | } |
| 1068 | |
| 1069 | static void cris_prepare_cc_branch (DisasContext *dc, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1070 | int offset, int cond) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1071 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1072 | /* This helps us re-schedule the micro-code to insns in delay-slots |
| 1073 | before the actual jump. */ |
| 1074 | dc->delayed_branch = 2; |
| 1075 | dc->jmp = JMP_DIRECT_CC; |
| 1076 | dc->jmp_pc = dc->pc + offset; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1077 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1078 | gen_tst_cc(dc, env_btaken, cond); |
| 1079 | tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1080 | } |
| 1081 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1082 | |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1083 | /* jumps, when the dest is in a live reg for example. Direct should be set |
| 1084 | when the dest addr is constant to allow tb chaining. */ |
| 1085 | static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1086 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1087 | /* This helps us re-schedule the micro-code to insns in delay-slots |
| 1088 | before the actual jump. */ |
| 1089 | dc->delayed_branch = 2; |
| 1090 | dc->jmp = type; |
| 1091 | if (type == JMP_INDIRECT) { |
| 1092 | tcg_gen_movi_tl(env_btaken, 1); |
| 1093 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1094 | } |
| 1095 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1096 | static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) |
| 1097 | { |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 1098 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1099 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1100 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1101 | the cpu-state to be able to re-execute the jmp. */ |
| 1102 | if (dc->delayed_branch == 1) { |
| 1103 | cris_store_direct_jmp(dc); |
| 1104 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1105 | |
Richard Henderson | a1d22a3 | 2013-12-07 14:52:34 +1300 | [diff] [blame] | 1106 | tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1107 | } |
| 1108 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 1109 | static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1110 | unsigned int size, int sign) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1111 | { |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 1112 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1113 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1114 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1115 | the cpu-state to be able to re-execute the jmp. */ |
| 1116 | if (dc->delayed_branch == 1) { |
| 1117 | cris_store_direct_jmp(dc); |
| 1118 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1119 | |
Richard Henderson | a1d22a3 | 2013-12-07 14:52:34 +1300 | [diff] [blame] | 1120 | tcg_gen_qemu_ld_tl(dst, addr, mem_index, |
| 1121 | MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1122 | } |
| 1123 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 1124 | static void gen_store (DisasContext *dc, TCGv addr, TCGv val, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1125 | unsigned int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1126 | { |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 1127 | int mem_index = cpu_mmu_index(&dc->cpu->env); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1128 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1129 | /* If we get a fault on a delayslot we must keep the jmp state in |
| 1130 | the cpu-state to be able to re-execute the jmp. */ |
| 1131 | if (dc->delayed_branch == 1) { |
| 1132 | cris_store_direct_jmp(dc); |
| 1133 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1134 | |
| 1135 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1136 | /* Conditional writes. We only support the kind were X and P are known |
| 1137 | at translation time. */ |
| 1138 | if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) { |
| 1139 | dc->postinc = 0; |
| 1140 | cris_evaluate_flags(dc); |
| 1141 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG); |
| 1142 | return; |
| 1143 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1144 | |
Richard Henderson | a1d22a3 | 2013-12-07 14:52:34 +1300 | [diff] [blame] | 1145 | tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1146 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1147 | if (dc->flagx_known && dc->flags_x) { |
| 1148 | cris_evaluate_flags(dc); |
| 1149 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG); |
| 1150 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1151 | } |
| 1152 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1153 | static inline void t_gen_sext(TCGv d, TCGv s, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1154 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1155 | if (size == 1) { |
| 1156 | tcg_gen_ext8s_i32(d, s); |
| 1157 | } else if (size == 2) { |
| 1158 | tcg_gen_ext16s_i32(d, s); |
| 1159 | } else if (!TCGV_EQUAL(d, s)) { |
| 1160 | tcg_gen_mov_tl(d, s); |
| 1161 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1162 | } |
| 1163 | |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1164 | static inline void t_gen_zext(TCGv d, TCGv s, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1165 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1166 | if (size == 1) { |
| 1167 | tcg_gen_ext8u_i32(d, s); |
| 1168 | } else if (size == 2) { |
| 1169 | tcg_gen_ext16u_i32(d, s); |
| 1170 | } else if (!TCGV_EQUAL(d, s)) { |
| 1171 | tcg_gen_mov_tl(d, s); |
| 1172 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1173 | } |
| 1174 | |
| 1175 | #if DISAS_CRIS |
| 1176 | static char memsize_char(int size) |
| 1177 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1178 | switch (size) { |
| 1179 | case 1: return 'b'; break; |
| 1180 | case 2: return 'w'; break; |
| 1181 | case 4: return 'd'; break; |
| 1182 | default: |
| 1183 | return 'x'; |
| 1184 | break; |
| 1185 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1186 | } |
| 1187 | #endif |
| 1188 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1189 | static inline unsigned int memsize_z(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1190 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1191 | return dc->zsize + 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1192 | } |
| 1193 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1194 | static inline unsigned int memsize_zz(DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1195 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1196 | switch (dc->zzsize) { |
| 1197 | case 0: return 1; |
| 1198 | case 1: return 2; |
| 1199 | default: |
| 1200 | return 4; |
| 1201 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1202 | } |
| 1203 | |
edgar_igl | c7d0569 | 2008-05-03 06:54:52 +0000 | [diff] [blame] | 1204 | static inline void do_postinc (DisasContext *dc, int size) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1205 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1206 | if (dc->postinc) { |
| 1207 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size); |
| 1208 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1209 | } |
| 1210 | |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1211 | static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1212 | int size, int s_ext, TCGv dst) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1213 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1214 | if (s_ext) { |
| 1215 | t_gen_sext(dst, cpu_R[rs], size); |
| 1216 | } else { |
| 1217 | t_gen_zext(dst, cpu_R[rs], size); |
| 1218 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1219 | } |
| 1220 | |
| 1221 | /* Prepare T0 and T1 for a register alu operation. |
| 1222 | s_ext decides if the operand1 should be sign-extended or zero-extended when |
| 1223 | needed. */ |
| 1224 | static void dec_prep_alu_r(DisasContext *dc, int rs, int rd, |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1225 | int size, int s_ext, TCGv dst, TCGv src) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1226 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1227 | dec_prep_move_r(dc, rs, rd, size, s_ext, src); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1228 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1229 | if (s_ext) { |
| 1230 | t_gen_sext(dst, cpu_R[rd], size); |
| 1231 | } else { |
| 1232 | t_gen_zext(dst, cpu_R[rd], size); |
| 1233 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1234 | } |
| 1235 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1236 | static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc, |
| 1237 | int s_ext, int memsize, TCGv dst) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1238 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1239 | unsigned int rs; |
| 1240 | uint32_t imm; |
| 1241 | int is_imm; |
| 1242 | int insn_len = 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1243 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1244 | rs = dc->op1; |
| 1245 | is_imm = rs == 15 && dc->postinc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1246 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1247 | /* Load [$rs] onto T1. */ |
| 1248 | if (is_imm) { |
| 1249 | insn_len = 2 + memsize; |
| 1250 | if (memsize == 1) { |
| 1251 | insn_len++; |
| 1252 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1253 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1254 | imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext); |
| 1255 | tcg_gen_movi_tl(dst, imm); |
| 1256 | dc->postinc = 0; |
| 1257 | } else { |
| 1258 | cris_flush_cc_state(dc); |
| 1259 | gen_load(dc, dst, cpu_R[rs], memsize, 0); |
| 1260 | if (s_ext) { |
| 1261 | t_gen_sext(dst, dst, memsize); |
| 1262 | } else { |
| 1263 | t_gen_zext(dst, dst, memsize); |
| 1264 | } |
| 1265 | } |
| 1266 | return insn_len; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | /* Prepare T0 and T1 for a memory + alu operation. |
| 1270 | s_ext decides if the operand1 should be sign-extended or zero-extended when |
| 1271 | needed. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1272 | static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc, |
| 1273 | int s_ext, int memsize, TCGv dst, TCGv src) |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1274 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1275 | int insn_len; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1276 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1277 | insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src); |
| 1278 | tcg_gen_mov_tl(dst, cpu_R[dc->op2]); |
| 1279 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1280 | } |
| 1281 | |
| 1282 | #if DISAS_CRIS |
| 1283 | static const char *cc_name(int cc) |
| 1284 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1285 | static const char *cc_names[16] = { |
| 1286 | "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", |
| 1287 | "ls", "hi", "ge", "lt", "gt", "le", "a", "p" |
| 1288 | }; |
| 1289 | assert(cc < 16); |
| 1290 | return cc_names[cc]; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1291 | } |
| 1292 | #endif |
| 1293 | |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 1294 | /* Start of insn decoders. */ |
| 1295 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1296 | static int dec_bccq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1297 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1298 | int32_t offset; |
| 1299 | int sign; |
| 1300 | uint32_t cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1301 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1302 | offset = EXTRACT_FIELD(dc->ir, 1, 7); |
| 1303 | sign = EXTRACT_FIELD(dc->ir, 0, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1304 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1305 | offset *= 2; |
| 1306 | offset |= sign << 8; |
| 1307 | offset = sign_extend(offset, 8); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1308 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1309 | LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1310 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1311 | /* op2 holds the condition-code. */ |
| 1312 | cris_cc_mask(dc, 0); |
| 1313 | cris_prepare_cc_branch(dc, offset, cond); |
| 1314 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1315 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1316 | static int dec_addoq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1317 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1318 | int32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1319 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1320 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); |
| 1321 | imm = sign_extend(dc->op1, 7); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1322 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1323 | LOG_DIS("addoq %d, $r%u\n", imm, dc->op2); |
| 1324 | cris_cc_mask(dc, 0); |
| 1325 | /* Fetch register operand, */ |
| 1326 | tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1327 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1328 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1329 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1330 | static int dec_addq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1331 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1332 | LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1333 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1334 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1335 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1336 | cris_cc_mask(dc, CC_MASK_NZVC); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1337 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1338 | cris_alu(dc, CC_OP_ADD, |
| 1339 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); |
| 1340 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1341 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1342 | static int dec_moveq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1343 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1344 | uint32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1345 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1346 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1347 | imm = sign_extend(dc->op1, 5); |
| 1348 | LOG_DIS("moveq %d, $r%u\n", imm, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1349 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1350 | tcg_gen_movi_tl(cpu_R[dc->op2], imm); |
| 1351 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1352 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1353 | static int dec_subq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1354 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1355 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1356 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1357 | LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1358 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1359 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1360 | cris_alu(dc, CC_OP_SUB, |
| 1361 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); |
| 1362 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1363 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1364 | static int dec_cmpq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1365 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1366 | uint32_t imm; |
| 1367 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1368 | imm = sign_extend(dc->op1, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1369 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1370 | LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); |
| 1371 | cris_cc_mask(dc, CC_MASK_NZVC); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1372 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1373 | cris_alu(dc, CC_OP_CMP, |
| 1374 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); |
| 1375 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1376 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1377 | static int dec_andq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1378 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1379 | uint32_t imm; |
| 1380 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1381 | imm = sign_extend(dc->op1, 5); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1382 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1383 | LOG_DIS("andq %d, $r%d\n", imm, dc->op2); |
| 1384 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1385 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1386 | cris_alu(dc, CC_OP_AND, |
| 1387 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); |
| 1388 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1389 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1390 | static int dec_orq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1391 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1392 | uint32_t imm; |
| 1393 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1394 | imm = sign_extend(dc->op1, 5); |
| 1395 | LOG_DIS("orq %d, $r%d\n", imm, dc->op2); |
| 1396 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1397 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1398 | cris_alu(dc, CC_OP_OR, |
| 1399 | cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); |
| 1400 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1401 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1402 | static int dec_btstq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1403 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1404 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1405 | LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 1406 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1407 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1408 | cris_evaluate_flags(dc); |
Aurelien Jarno | febc992 | 2012-08-30 16:56:39 +0200 | [diff] [blame] | 1409 | gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1410 | tcg_const_tl(dc->op1), cpu_PR[PR_CCS]); |
| 1411 | cris_alu(dc, CC_OP_MOVE, |
| 1412 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1413 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1414 | dc->flags_uptodate = 1; |
| 1415 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1416 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1417 | static int dec_asrq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1418 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1419 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1420 | LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2); |
| 1421 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1422 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1423 | tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
| 1424 | cris_alu(dc, CC_OP_MOVE, |
| 1425 | cpu_R[dc->op2], |
| 1426 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1427 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1428 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1429 | static int dec_lslq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1430 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1431 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1432 | LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1433 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1434 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1435 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1436 | tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 1437 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1438 | cris_alu(dc, CC_OP_MOVE, |
| 1439 | cpu_R[dc->op2], |
| 1440 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1441 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1442 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1443 | static int dec_lsrq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1444 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1445 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1446 | LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1447 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1448 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1449 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1450 | tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
| 1451 | cris_alu(dc, CC_OP_MOVE, |
| 1452 | cpu_R[dc->op2], |
| 1453 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1454 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1455 | } |
| 1456 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1457 | static int dec_move_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1458 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1459 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1460 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1461 | LOG_DIS("move.%c $r%u, $r%u\n", |
| 1462 | memsize_char(size), dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1463 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1464 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1465 | if (size == 4) { |
| 1466 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]); |
| 1467 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1468 | cris_update_cc_op(dc, CC_OP_MOVE, 4); |
| 1469 | cris_update_cc_x(dc); |
| 1470 | cris_update_result(dc, cpu_R[dc->op2]); |
| 1471 | } else { |
| 1472 | TCGv t0; |
edgar_igl | 43d7ac4 | 2008-10-27 13:55:28 +0000 | [diff] [blame] | 1473 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1474 | t0 = tcg_temp_new(); |
| 1475 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
| 1476 | cris_alu(dc, CC_OP_MOVE, |
| 1477 | cpu_R[dc->op2], |
| 1478 | cpu_R[dc->op2], t0, size); |
| 1479 | tcg_temp_free(t0); |
| 1480 | } |
| 1481 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1482 | } |
| 1483 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1484 | static int dec_scc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1485 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1486 | int cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1487 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1488 | LOG_DIS("s%s $r%u\n", |
| 1489 | cc_name(cond), dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1490 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1491 | if (cond != CC_A) { |
| 1492 | int l1; |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 1493 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1494 | gen_tst_cc(dc, cpu_R[dc->op1], cond); |
| 1495 | l1 = gen_new_label(); |
| 1496 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1); |
| 1497 | tcg_gen_movi_tl(cpu_R[dc->op1], 1); |
| 1498 | gen_set_label(l1); |
| 1499 | } else { |
| 1500 | tcg_gen_movi_tl(cpu_R[dc->op1], 1); |
| 1501 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1502 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1503 | cris_cc_mask(dc, 0); |
| 1504 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1505 | } |
| 1506 | |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1507 | static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t) |
| 1508 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1509 | if (size == 4) { |
| 1510 | t[0] = cpu_R[dc->op2]; |
| 1511 | t[1] = cpu_R[dc->op1]; |
| 1512 | } else { |
| 1513 | t[0] = tcg_temp_new(); |
| 1514 | t[1] = tcg_temp_new(); |
| 1515 | } |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1516 | } |
| 1517 | |
| 1518 | static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t) |
| 1519 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1520 | if (size != 4) { |
| 1521 | tcg_temp_free(t[0]); |
| 1522 | tcg_temp_free(t[1]); |
| 1523 | } |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1524 | } |
| 1525 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1526 | static int dec_and_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1527 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1528 | TCGv t[2]; |
| 1529 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1530 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1531 | LOG_DIS("and.%c $r%u, $r%u\n", |
| 1532 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1533 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1534 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 1535 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1536 | cris_alu_alloc_temps(dc, size, t); |
| 1537 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1538 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); |
| 1539 | cris_alu_free_temps(dc, size, t); |
| 1540 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1541 | } |
| 1542 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1543 | static int dec_lz_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1544 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1545 | TCGv t0; |
| 1546 | LOG_DIS("lz $r%u, $r%u\n", |
| 1547 | dc->op1, dc->op2); |
| 1548 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1549 | t0 = tcg_temp_new(); |
| 1550 | dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); |
| 1551 | cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1552 | tcg_temp_free(t0); |
| 1553 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1554 | } |
| 1555 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1556 | static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1557 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1558 | TCGv t[2]; |
| 1559 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1560 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1561 | LOG_DIS("lsl.%c $r%u, $r%u\n", |
| 1562 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1563 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1564 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1565 | cris_alu_alloc_temps(dc, size, t); |
| 1566 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1567 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1568 | cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); |
| 1569 | cris_alu_alloc_temps(dc, size, t); |
| 1570 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1571 | } |
| 1572 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1573 | static int dec_lsr_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1574 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1575 | TCGv t[2]; |
| 1576 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1577 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1578 | LOG_DIS("lsr.%c $r%u, $r%u\n", |
| 1579 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1580 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1581 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1582 | cris_alu_alloc_temps(dc, size, t); |
| 1583 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1584 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1585 | cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); |
| 1586 | cris_alu_free_temps(dc, size, t); |
| 1587 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1588 | } |
| 1589 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1590 | static int dec_asr_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1591 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1592 | TCGv t[2]; |
| 1593 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1594 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1595 | LOG_DIS("asr.%c $r%u, $r%u\n", |
| 1596 | memsize_char(size), dc->op1, dc->op2); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1597 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1598 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1599 | cris_alu_alloc_temps(dc, size, t); |
| 1600 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); |
| 1601 | tcg_gen_andi_tl(t[1], t[1], 63); |
| 1602 | cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); |
| 1603 | cris_alu_free_temps(dc, size, t); |
| 1604 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1605 | } |
| 1606 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1607 | static int dec_muls_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1608 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1609 | TCGv t[2]; |
| 1610 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1611 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1612 | LOG_DIS("muls.%c $r%u, $r%u\n", |
| 1613 | memsize_char(size), dc->op1, dc->op2); |
| 1614 | cris_cc_mask(dc, CC_MASK_NZV); |
| 1615 | cris_alu_alloc_temps(dc, size, t); |
| 1616 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1617 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1618 | cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); |
| 1619 | cris_alu_free_temps(dc, size, t); |
| 1620 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1621 | } |
| 1622 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1623 | static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1624 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1625 | TCGv t[2]; |
| 1626 | int size = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1627 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1628 | LOG_DIS("mulu.%c $r%u, $r%u\n", |
| 1629 | memsize_char(size), dc->op1, dc->op2); |
| 1630 | cris_cc_mask(dc, CC_MASK_NZV); |
| 1631 | cris_alu_alloc_temps(dc, size, t); |
| 1632 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1633 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1634 | cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); |
| 1635 | cris_alu_alloc_temps(dc, size, t); |
| 1636 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1637 | } |
| 1638 | |
| 1639 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1640 | static int dec_dstep_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1641 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1642 | LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2); |
| 1643 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1644 | cris_alu(dc, CC_OP_DSTEP, |
| 1645 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); |
| 1646 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1647 | } |
| 1648 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1649 | static int dec_xor_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1650 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1651 | TCGv t[2]; |
| 1652 | int size = memsize_zz(dc); |
| 1653 | LOG_DIS("xor.%c $r%u, $r%u\n", |
| 1654 | memsize_char(size), dc->op1, dc->op2); |
| 1655 | BUG_ON(size != 4); /* xor is dword. */ |
| 1656 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1657 | cris_alu_alloc_temps(dc, size, t); |
| 1658 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1659 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1660 | cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); |
| 1661 | cris_alu_free_temps(dc, size, t); |
| 1662 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1663 | } |
| 1664 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1665 | static int dec_bound_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1666 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1667 | TCGv l0; |
| 1668 | int size = memsize_zz(dc); |
| 1669 | LOG_DIS("bound.%c $r%u, $r%u\n", |
| 1670 | memsize_char(size), dc->op1, dc->op2); |
| 1671 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1672 | l0 = tcg_temp_local_new(); |
| 1673 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); |
| 1674 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); |
| 1675 | tcg_temp_free(l0); |
| 1676 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1677 | } |
| 1678 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1679 | static int dec_cmp_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1680 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1681 | TCGv t[2]; |
| 1682 | int size = memsize_zz(dc); |
| 1683 | LOG_DIS("cmp.%c $r%u, $r%u\n", |
| 1684 | memsize_char(size), dc->op1, dc->op2); |
| 1685 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1686 | cris_alu_alloc_temps(dc, size, t); |
| 1687 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1688 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1689 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); |
| 1690 | cris_alu_free_temps(dc, size, t); |
| 1691 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1692 | } |
| 1693 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1694 | static int dec_abs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1695 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1696 | TCGv t0; |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 1697 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1698 | LOG_DIS("abs $r%u, $r%u\n", |
| 1699 | dc->op1, dc->op2); |
| 1700 | cris_cc_mask(dc, CC_MASK_NZ); |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 1701 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1702 | t0 = tcg_temp_new(); |
| 1703 | tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31); |
| 1704 | tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0); |
| 1705 | tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0); |
| 1706 | tcg_temp_free(t0); |
edgar_igl | 7dcfb08 | 2008-10-27 12:39:30 +0000 | [diff] [blame] | 1707 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1708 | cris_alu(dc, CC_OP_MOVE, |
| 1709 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1710 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1711 | } |
| 1712 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1713 | static int dec_add_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1714 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1715 | TCGv t[2]; |
| 1716 | int size = memsize_zz(dc); |
| 1717 | LOG_DIS("add.%c $r%u, $r%u\n", |
| 1718 | memsize_char(size), dc->op1, dc->op2); |
| 1719 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1720 | cris_alu_alloc_temps(dc, size, t); |
| 1721 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1722 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1723 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); |
| 1724 | cris_alu_free_temps(dc, size, t); |
| 1725 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1726 | } |
| 1727 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1728 | static int dec_addc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1729 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1730 | LOG_DIS("addc $r%u, $r%u\n", |
| 1731 | dc->op1, dc->op2); |
| 1732 | cris_evaluate_flags(dc); |
| 1733 | /* Set for this insn. */ |
| 1734 | dc->flagx_known = 1; |
| 1735 | dc->flags_x = X_FLAG; |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 1736 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1737 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1738 | cris_alu(dc, CC_OP_ADDC, |
| 1739 | cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); |
| 1740 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1741 | } |
| 1742 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1743 | static int dec_mcp_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1744 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1745 | LOG_DIS("mcp $p%u, $r%u\n", |
| 1746 | dc->op2, dc->op1); |
| 1747 | cris_evaluate_flags(dc); |
| 1748 | cris_cc_mask(dc, CC_MASK_RNZV); |
| 1749 | cris_alu(dc, CC_OP_MCP, |
| 1750 | cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4); |
| 1751 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1752 | } |
| 1753 | |
| 1754 | #if DISAS_CRIS |
| 1755 | static char * swapmode_name(int mode, char *modename) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1756 | int i = 0; |
| 1757 | if (mode & 8) { |
| 1758 | modename[i++] = 'n'; |
| 1759 | } |
| 1760 | if (mode & 4) { |
| 1761 | modename[i++] = 'w'; |
| 1762 | } |
| 1763 | if (mode & 2) { |
| 1764 | modename[i++] = 'b'; |
| 1765 | } |
| 1766 | if (mode & 1) { |
| 1767 | modename[i++] = 'r'; |
| 1768 | } |
| 1769 | modename[i++] = 0; |
| 1770 | return modename; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1771 | } |
| 1772 | #endif |
| 1773 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1774 | static int dec_swap_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1775 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1776 | TCGv t0; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1777 | #if DISAS_CRIS |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1778 | char modename[4]; |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 1779 | #endif |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1780 | LOG_DIS("swap%s $r%u\n", |
| 1781 | swapmode_name(dc->op2, modename), dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1782 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1783 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1784 | t0 = tcg_temp_new(); |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 1785 | tcg_gen_mov_tl(t0, cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1786 | if (dc->op2 & 8) { |
| 1787 | tcg_gen_not_tl(t0, t0); |
| 1788 | } |
| 1789 | if (dc->op2 & 4) { |
| 1790 | t_gen_swapw(t0, t0); |
| 1791 | } |
| 1792 | if (dc->op2 & 2) { |
| 1793 | t_gen_swapb(t0, t0); |
| 1794 | } |
| 1795 | if (dc->op2 & 1) { |
| 1796 | t_gen_swapr(t0, t0); |
| 1797 | } |
| 1798 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); |
| 1799 | tcg_temp_free(t0); |
| 1800 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1801 | } |
| 1802 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1803 | static int dec_or_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1804 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1805 | TCGv t[2]; |
| 1806 | int size = memsize_zz(dc); |
| 1807 | LOG_DIS("or.%c $r%u, $r%u\n", |
| 1808 | memsize_char(size), dc->op1, dc->op2); |
| 1809 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1810 | cris_alu_alloc_temps(dc, size, t); |
| 1811 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1812 | cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); |
| 1813 | cris_alu_free_temps(dc, size, t); |
| 1814 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1815 | } |
| 1816 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1817 | static int dec_addi_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1818 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1819 | TCGv t0; |
| 1820 | LOG_DIS("addi.%c $r%u, $r%u\n", |
| 1821 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); |
| 1822 | cris_cc_mask(dc, 0); |
| 1823 | t0 = tcg_temp_new(); |
| 1824 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); |
| 1825 | tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); |
| 1826 | tcg_temp_free(t0); |
| 1827 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1828 | } |
| 1829 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1830 | static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1831 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1832 | TCGv t0; |
| 1833 | LOG_DIS("addi.%c $r%u, $r%u, $acr\n", |
| 1834 | memsize_char(memsize_zz(dc)), dc->op2, dc->op1); |
| 1835 | cris_cc_mask(dc, 0); |
| 1836 | t0 = tcg_temp_new(); |
| 1837 | tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); |
| 1838 | tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); |
| 1839 | tcg_temp_free(t0); |
| 1840 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1841 | } |
| 1842 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1843 | static int dec_neg_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1844 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1845 | TCGv t[2]; |
| 1846 | int size = memsize_zz(dc); |
| 1847 | LOG_DIS("neg.%c $r%u, $r%u\n", |
| 1848 | memsize_char(size), dc->op1, dc->op2); |
| 1849 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1850 | cris_alu_alloc_temps(dc, size, t); |
| 1851 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 1852 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1853 | cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); |
| 1854 | cris_alu_free_temps(dc, size, t); |
| 1855 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1856 | } |
| 1857 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1858 | static int dec_btst_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1859 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1860 | LOG_DIS("btst $r%u, $r%u\n", |
| 1861 | dc->op1, dc->op2); |
| 1862 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1863 | cris_evaluate_flags(dc); |
Aurelien Jarno | febc992 | 2012-08-30 16:56:39 +0200 | [diff] [blame] | 1864 | gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1865 | cpu_R[dc->op1], cpu_PR[PR_CCS]); |
| 1866 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], |
| 1867 | cpu_R[dc->op2], cpu_R[dc->op2], 4); |
| 1868 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 1869 | dc->flags_uptodate = 1; |
| 1870 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1871 | } |
| 1872 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1873 | static int dec_sub_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1874 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1875 | TCGv t[2]; |
| 1876 | int size = memsize_zz(dc); |
| 1877 | LOG_DIS("sub.%c $r%u, $r%u\n", |
| 1878 | memsize_char(size), dc->op1, dc->op2); |
| 1879 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1880 | cris_alu_alloc_temps(dc, size, t); |
| 1881 | dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| 1882 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); |
| 1883 | cris_alu_free_temps(dc, size, t); |
| 1884 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1885 | } |
| 1886 | |
| 1887 | /* Zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1888 | static int dec_movu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1889 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1890 | TCGv t0; |
| 1891 | int size = memsize_z(dc); |
| 1892 | LOG_DIS("movu.%c $r%u, $r%u\n", |
| 1893 | memsize_char(size), |
| 1894 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1895 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1896 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1897 | t0 = tcg_temp_new(); |
| 1898 | dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); |
| 1899 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1900 | tcg_temp_free(t0); |
| 1901 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1902 | } |
| 1903 | |
| 1904 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1905 | static int dec_movs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1906 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1907 | TCGv t0; |
| 1908 | int size = memsize_z(dc); |
| 1909 | LOG_DIS("movs.%c $r%u, $r%u\n", |
| 1910 | memsize_char(size), |
| 1911 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1912 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1913 | cris_cc_mask(dc, CC_MASK_NZ); |
| 1914 | t0 = tcg_temp_new(); |
| 1915 | /* Size can only be qi or hi. */ |
| 1916 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1917 | cris_alu(dc, CC_OP_MOVE, |
| 1918 | cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); |
| 1919 | tcg_temp_free(t0); |
| 1920 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1921 | } |
| 1922 | |
| 1923 | /* zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1924 | static int dec_addu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1925 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1926 | TCGv t0; |
| 1927 | int size = memsize_z(dc); |
| 1928 | LOG_DIS("addu.%c $r%u, $r%u\n", |
| 1929 | memsize_char(size), |
| 1930 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1931 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1932 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1933 | t0 = tcg_temp_new(); |
| 1934 | /* Size can only be qi or hi. */ |
| 1935 | t_gen_zext(t0, cpu_R[dc->op1], size); |
| 1936 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1937 | tcg_temp_free(t0); |
| 1938 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1939 | } |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 1940 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1941 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1942 | static int dec_adds_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1943 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1944 | TCGv t0; |
| 1945 | int size = memsize_z(dc); |
| 1946 | LOG_DIS("adds.%c $r%u, $r%u\n", |
| 1947 | memsize_char(size), |
| 1948 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1949 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1950 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1951 | t0 = tcg_temp_new(); |
| 1952 | /* Size can only be qi or hi. */ |
| 1953 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1954 | cris_alu(dc, CC_OP_ADD, |
| 1955 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1956 | tcg_temp_free(t0); |
| 1957 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1958 | } |
| 1959 | |
| 1960 | /* Zero extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1961 | static int dec_subu_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1962 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1963 | TCGv t0; |
| 1964 | int size = memsize_z(dc); |
| 1965 | LOG_DIS("subu.%c $r%u, $r%u\n", |
| 1966 | memsize_char(size), |
| 1967 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1968 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1969 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1970 | t0 = tcg_temp_new(); |
| 1971 | /* Size can only be qi or hi. */ |
| 1972 | t_gen_zext(t0, cpu_R[dc->op1], size); |
| 1973 | cris_alu(dc, CC_OP_SUB, |
| 1974 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1975 | tcg_temp_free(t0); |
| 1976 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1977 | } |
| 1978 | |
| 1979 | /* Sign extension. From size to dword. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1980 | static int dec_subs_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1981 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1982 | TCGv t0; |
| 1983 | int size = memsize_z(dc); |
| 1984 | LOG_DIS("subs.%c $r%u, $r%u\n", |
| 1985 | memsize_char(size), |
| 1986 | dc->op1, dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1987 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 1988 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 1989 | t0 = tcg_temp_new(); |
| 1990 | /* Size can only be qi or hi. */ |
| 1991 | t_gen_sext(t0, cpu_R[dc->op1], size); |
| 1992 | cris_alu(dc, CC_OP_SUB, |
| 1993 | cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); |
| 1994 | tcg_temp_free(t0); |
| 1995 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1996 | } |
| 1997 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 1998 | static int dec_setclrf(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 1999 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2000 | uint32_t flags; |
| 2001 | int set = (~dc->opcode >> 2) & 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2002 | |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 2003 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2004 | flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4) |
| 2005 | | EXTRACT_FIELD(dc->ir, 0, 3); |
| 2006 | if (set && flags == 0) { |
| 2007 | LOG_DIS("nop\n"); |
| 2008 | return 2; |
| 2009 | } else if (!set && (flags & 0x20)) { |
| 2010 | LOG_DIS("di\n"); |
| 2011 | } else { |
| 2012 | LOG_DIS("%sf %x\n", set ? "set" : "clr", flags); |
| 2013 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2014 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2015 | /* User space is not allowed to touch these. Silently ignore. */ |
| 2016 | if (dc->tb_flags & U_FLAG) { |
| 2017 | flags &= ~(S_FLAG | I_FLAG | U_FLAG); |
| 2018 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2019 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2020 | if (flags & X_FLAG) { |
| 2021 | dc->flagx_known = 1; |
| 2022 | if (set) { |
| 2023 | dc->flags_x = X_FLAG; |
| 2024 | } else { |
| 2025 | dc->flags_x = 0; |
| 2026 | } |
| 2027 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2028 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2029 | /* Break the TB if any of the SPI flag changes. */ |
| 2030 | if (flags & (P_FLAG | S_FLAG)) { |
| 2031 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
| 2032 | dc->is_jmp = DISAS_UPDATE; |
| 2033 | dc->cpustate_changed = 1; |
| 2034 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 2035 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2036 | /* For the I flag, only act on posedge. */ |
| 2037 | if ((flags & I_FLAG)) { |
| 2038 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
| 2039 | dc->is_jmp = DISAS_UPDATE; |
| 2040 | dc->cpustate_changed = 1; |
| 2041 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2042 | |
| 2043 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2044 | /* Simply decode the flags. */ |
| 2045 | cris_evaluate_flags(dc); |
| 2046 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 2047 | cris_update_cc_x(dc); |
| 2048 | tcg_gen_movi_tl(cc_op, dc->cc_op); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2049 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2050 | if (set) { |
| 2051 | if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) { |
| 2052 | /* Enter user mode. */ |
| 2053 | t_gen_mov_env_TN(ksp, cpu_R[R_SP]); |
| 2054 | tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]); |
| 2055 | dc->cpustate_changed = 1; |
| 2056 | } |
| 2057 | tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags); |
| 2058 | } else { |
| 2059 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags); |
| 2060 | } |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 2061 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2062 | dc->flags_uptodate = 1; |
| 2063 | dc->clear_x = 0; |
| 2064 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2065 | } |
| 2066 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2067 | static int dec_move_rs(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2068 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2069 | LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); |
| 2070 | cris_cc_mask(dc, 0); |
Aurelien Jarno | febc992 | 2012-08-30 16:56:39 +0200 | [diff] [blame] | 2071 | gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2), |
| 2072 | tcg_const_tl(dc->op1)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2073 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2074 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2075 | static int dec_move_sr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2076 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2077 | LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); |
| 2078 | cris_cc_mask(dc, 0); |
Aurelien Jarno | febc992 | 2012-08-30 16:56:39 +0200 | [diff] [blame] | 2079 | gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1), |
| 2080 | tcg_const_tl(dc->op2)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2081 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2082 | } |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 2083 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2084 | static int dec_move_rp(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2085 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2086 | TCGv t[2]; |
| 2087 | LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2); |
| 2088 | cris_cc_mask(dc, 0); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2089 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2090 | t[0] = tcg_temp_new(); |
| 2091 | if (dc->op2 == PR_CCS) { |
| 2092 | cris_evaluate_flags(dc); |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 2093 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2094 | if (dc->tb_flags & U_FLAG) { |
| 2095 | t[1] = tcg_temp_new(); |
| 2096 | /* User space is not allowed to touch all flags. */ |
| 2097 | tcg_gen_andi_tl(t[0], t[0], 0x39f); |
| 2098 | tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); |
| 2099 | tcg_gen_or_tl(t[0], t[1], t[0]); |
| 2100 | tcg_temp_free(t[1]); |
| 2101 | } |
| 2102 | } else { |
Peter Maydell | 08397c4 | 2014-06-07 18:03:01 +0100 | [diff] [blame] | 2103 | tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2104 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2105 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2106 | t_gen_mov_preg_TN(dc, dc->op2, t[0]); |
| 2107 | if (dc->op2 == PR_CCS) { |
| 2108 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 2109 | dc->flags_uptodate = 1; |
| 2110 | } |
| 2111 | tcg_temp_free(t[0]); |
| 2112 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2113 | } |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2114 | static int dec_move_pr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2115 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2116 | TCGv t0; |
| 2117 | LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1); |
| 2118 | cris_cc_mask(dc, 0); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2119 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2120 | if (dc->op2 == PR_CCS) { |
| 2121 | cris_evaluate_flags(dc); |
| 2122 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2123 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2124 | if (dc->op2 == PR_DZ) { |
| 2125 | tcg_gen_movi_tl(cpu_R[dc->op1], 0); |
| 2126 | } else { |
| 2127 | t0 = tcg_temp_new(); |
| 2128 | t_gen_mov_TN_preg(t0, dc->op2); |
| 2129 | cris_alu(dc, CC_OP_MOVE, |
| 2130 | cpu_R[dc->op1], cpu_R[dc->op1], t0, |
| 2131 | preg_sizes[dc->op2]); |
| 2132 | tcg_temp_free(t0); |
| 2133 | } |
| 2134 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2135 | } |
| 2136 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2137 | static int dec_move_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2138 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2139 | int memsize = memsize_zz(dc); |
| 2140 | int insn_len; |
| 2141 | LOG_DIS("move.%c [$r%u%s, $r%u\n", |
| 2142 | memsize_char(memsize), |
| 2143 | dc->op1, dc->postinc ? "+]" : "]", |
| 2144 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2145 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2146 | if (memsize == 4) { |
| 2147 | insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]); |
| 2148 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2149 | cris_update_cc_op(dc, CC_OP_MOVE, 4); |
| 2150 | cris_update_cc_x(dc); |
| 2151 | cris_update_result(dc, cpu_R[dc->op2]); |
| 2152 | } else { |
| 2153 | TCGv t0; |
edgar_igl | fb48f71 | 2008-10-27 16:46:29 +0000 | [diff] [blame] | 2154 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2155 | t0 = tcg_temp_new(); |
| 2156 | insn_len = dec_prep_move_m(env, dc, 0, memsize, t0); |
| 2157 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2158 | cris_alu(dc, CC_OP_MOVE, |
| 2159 | cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); |
| 2160 | tcg_temp_free(t0); |
| 2161 | } |
| 2162 | do_postinc(dc, memsize); |
| 2163 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2164 | } |
| 2165 | |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 2166 | static inline void cris_alu_m_alloc_temps(TCGv *t) |
| 2167 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2168 | t[0] = tcg_temp_new(); |
| 2169 | t[1] = tcg_temp_new(); |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 2170 | } |
| 2171 | |
| 2172 | static inline void cris_alu_m_free_temps(TCGv *t) |
| 2173 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2174 | tcg_temp_free(t[0]); |
| 2175 | tcg_temp_free(t[1]); |
edgar_igl | 31c18d8 | 2008-10-27 20:24:59 +0000 | [diff] [blame] | 2176 | } |
| 2177 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2178 | static int dec_movs_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2179 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2180 | TCGv t[2]; |
| 2181 | int memsize = memsize_z(dc); |
| 2182 | int insn_len; |
| 2183 | LOG_DIS("movs.%c [$r%u%s, $r%u\n", |
| 2184 | memsize_char(memsize), |
| 2185 | dc->op1, dc->postinc ? "+]" : "]", |
| 2186 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2187 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2188 | cris_alu_m_alloc_temps(t); |
| 2189 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2190 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2191 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2192 | cris_alu(dc, CC_OP_MOVE, |
| 2193 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2194 | do_postinc(dc, memsize); |
| 2195 | cris_alu_m_free_temps(t); |
| 2196 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2197 | } |
| 2198 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2199 | static int dec_addu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2200 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2201 | TCGv t[2]; |
| 2202 | int memsize = memsize_z(dc); |
| 2203 | int insn_len; |
| 2204 | LOG_DIS("addu.%c [$r%u%s, $r%u\n", |
| 2205 | memsize_char(memsize), |
| 2206 | dc->op1, dc->postinc ? "+]" : "]", |
| 2207 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2208 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2209 | cris_alu_m_alloc_temps(t); |
| 2210 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2211 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2212 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2213 | cris_alu(dc, CC_OP_ADD, |
| 2214 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2215 | do_postinc(dc, memsize); |
| 2216 | cris_alu_m_free_temps(t); |
| 2217 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2218 | } |
| 2219 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2220 | static int dec_adds_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2221 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2222 | TCGv t[2]; |
| 2223 | int memsize = memsize_z(dc); |
| 2224 | int insn_len; |
| 2225 | LOG_DIS("adds.%c [$r%u%s, $r%u\n", |
| 2226 | memsize_char(memsize), |
| 2227 | dc->op1, dc->postinc ? "+]" : "]", |
| 2228 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2229 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2230 | cris_alu_m_alloc_temps(t); |
| 2231 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2232 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2233 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2234 | cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2235 | do_postinc(dc, memsize); |
| 2236 | cris_alu_m_free_temps(t); |
| 2237 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2238 | } |
| 2239 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2240 | static int dec_subu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2241 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2242 | TCGv t[2]; |
| 2243 | int memsize = memsize_z(dc); |
| 2244 | int insn_len; |
| 2245 | LOG_DIS("subu.%c [$r%u%s, $r%u\n", |
| 2246 | memsize_char(memsize), |
| 2247 | dc->op1, dc->postinc ? "+]" : "]", |
| 2248 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2249 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2250 | cris_alu_m_alloc_temps(t); |
| 2251 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2252 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2253 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2254 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2255 | do_postinc(dc, memsize); |
| 2256 | cris_alu_m_free_temps(t); |
| 2257 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2258 | } |
| 2259 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2260 | static int dec_subs_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2261 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2262 | TCGv t[2]; |
| 2263 | int memsize = memsize_z(dc); |
| 2264 | int insn_len; |
| 2265 | LOG_DIS("subs.%c [$r%u%s, $r%u\n", |
| 2266 | memsize_char(memsize), |
| 2267 | dc->op1, dc->postinc ? "+]" : "]", |
| 2268 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2269 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2270 | cris_alu_m_alloc_temps(t); |
| 2271 | /* sign extend. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2272 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2273 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2274 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2275 | do_postinc(dc, memsize); |
| 2276 | cris_alu_m_free_temps(t); |
| 2277 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2278 | } |
| 2279 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2280 | static int dec_movu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2281 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2282 | TCGv t[2]; |
| 2283 | int memsize = memsize_z(dc); |
| 2284 | int insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2285 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2286 | LOG_DIS("movu.%c [$r%u%s, $r%u\n", |
| 2287 | memsize_char(memsize), |
| 2288 | dc->op1, dc->postinc ? "+]" : "]", |
| 2289 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2290 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2291 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2292 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2293 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2294 | cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2295 | do_postinc(dc, memsize); |
| 2296 | cris_alu_m_free_temps(t); |
| 2297 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2298 | } |
| 2299 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2300 | static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2301 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2302 | TCGv t[2]; |
| 2303 | int memsize = memsize_z(dc); |
| 2304 | int insn_len; |
| 2305 | LOG_DIS("cmpu.%c [$r%u%s, $r%u\n", |
| 2306 | memsize_char(memsize), |
| 2307 | dc->op1, dc->postinc ? "+]" : "]", |
| 2308 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2309 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2310 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2311 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2312 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2313 | cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); |
| 2314 | do_postinc(dc, memsize); |
| 2315 | cris_alu_m_free_temps(t); |
| 2316 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2317 | } |
| 2318 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2319 | static int dec_cmps_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2320 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2321 | TCGv t[2]; |
| 2322 | int memsize = memsize_z(dc); |
| 2323 | int insn_len; |
| 2324 | LOG_DIS("cmps.%c [$r%u%s, $r%u\n", |
| 2325 | memsize_char(memsize), |
| 2326 | dc->op1, dc->postinc ? "+]" : "]", |
| 2327 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2328 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2329 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2330 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2331 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2332 | cris_alu(dc, CC_OP_CMP, |
| 2333 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], |
| 2334 | memsize_zz(dc)); |
| 2335 | do_postinc(dc, memsize); |
| 2336 | cris_alu_m_free_temps(t); |
| 2337 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2338 | } |
| 2339 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2340 | static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2341 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2342 | TCGv t[2]; |
| 2343 | int memsize = memsize_zz(dc); |
| 2344 | int insn_len; |
| 2345 | LOG_DIS("cmp.%c [$r%u%s, $r%u\n", |
| 2346 | memsize_char(memsize), |
| 2347 | dc->op1, dc->postinc ? "+]" : "]", |
| 2348 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2349 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2350 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2351 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2352 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2353 | cris_alu(dc, CC_OP_CMP, |
| 2354 | cpu_R[dc->op2], cpu_R[dc->op2], t[1], |
| 2355 | memsize_zz(dc)); |
| 2356 | do_postinc(dc, memsize); |
| 2357 | cris_alu_m_free_temps(t); |
| 2358 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2359 | } |
| 2360 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2361 | static int dec_test_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2362 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2363 | TCGv t[2]; |
| 2364 | int memsize = memsize_zz(dc); |
| 2365 | int insn_len; |
| 2366 | LOG_DIS("test.%c [$r%u%s] op2=%x\n", |
| 2367 | memsize_char(memsize), |
| 2368 | dc->op1, dc->postinc ? "+]" : "]", |
| 2369 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2370 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2371 | cris_evaluate_flags(dc); |
edgar_igl | dceaf39 | 2008-05-07 15:24:53 +0000 | [diff] [blame] | 2372 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2373 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2374 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2375 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2376 | tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2377 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2378 | cris_alu(dc, CC_OP_CMP, |
| 2379 | cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc)); |
| 2380 | do_postinc(dc, memsize); |
| 2381 | cris_alu_m_free_temps(t); |
| 2382 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2383 | } |
| 2384 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2385 | static int dec_and_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2386 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2387 | TCGv t[2]; |
| 2388 | int memsize = memsize_zz(dc); |
| 2389 | int insn_len; |
| 2390 | LOG_DIS("and.%c [$r%u%s, $r%u\n", |
| 2391 | memsize_char(memsize), |
| 2392 | dc->op1, dc->postinc ? "+]" : "]", |
| 2393 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2394 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2395 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2396 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2397 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2398 | cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2399 | do_postinc(dc, memsize); |
| 2400 | cris_alu_m_free_temps(t); |
| 2401 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2402 | } |
| 2403 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2404 | static int dec_add_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2405 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2406 | TCGv t[2]; |
| 2407 | int memsize = memsize_zz(dc); |
| 2408 | int insn_len; |
| 2409 | LOG_DIS("add.%c [$r%u%s, $r%u\n", |
| 2410 | memsize_char(memsize), |
| 2411 | dc->op1, dc->postinc ? "+]" : "]", |
| 2412 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2413 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2414 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2415 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2416 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2417 | cris_alu(dc, CC_OP_ADD, |
| 2418 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2419 | do_postinc(dc, memsize); |
| 2420 | cris_alu_m_free_temps(t); |
| 2421 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2422 | } |
| 2423 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2424 | static int dec_addo_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2425 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2426 | TCGv t[2]; |
| 2427 | int memsize = memsize_zz(dc); |
| 2428 | int insn_len; |
| 2429 | LOG_DIS("add.%c [$r%u%s, $r%u\n", |
| 2430 | memsize_char(memsize), |
| 2431 | dc->op1, dc->postinc ? "+]" : "]", |
| 2432 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2433 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2434 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2435 | insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2436 | cris_cc_mask(dc, 0); |
| 2437 | cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); |
| 2438 | do_postinc(dc, memsize); |
| 2439 | cris_alu_m_free_temps(t); |
| 2440 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2441 | } |
| 2442 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2443 | static int dec_bound_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2444 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2445 | TCGv l[2]; |
| 2446 | int memsize = memsize_zz(dc); |
| 2447 | int insn_len; |
| 2448 | LOG_DIS("bound.%c [$r%u%s, $r%u\n", |
| 2449 | memsize_char(memsize), |
| 2450 | dc->op1, dc->postinc ? "+]" : "]", |
| 2451 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2452 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2453 | l[0] = tcg_temp_local_new(); |
| 2454 | l[1] = tcg_temp_local_new(); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2455 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2456 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2457 | cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); |
| 2458 | do_postinc(dc, memsize); |
| 2459 | tcg_temp_free(l[0]); |
| 2460 | tcg_temp_free(l[1]); |
| 2461 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2462 | } |
| 2463 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2464 | static int dec_addc_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2465 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2466 | TCGv t[2]; |
| 2467 | int insn_len = 2; |
| 2468 | LOG_DIS("addc [$r%u%s, $r%u\n", |
| 2469 | dc->op1, dc->postinc ? "+]" : "]", |
| 2470 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2471 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2472 | cris_evaluate_flags(dc); |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 2473 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2474 | /* Set for this insn. */ |
| 2475 | dc->flagx_known = 1; |
| 2476 | dc->flags_x = X_FLAG; |
edgar_igl | a8cf66b | 2009-01-07 12:25:15 +0000 | [diff] [blame] | 2477 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2478 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2479 | insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2480 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2481 | cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); |
| 2482 | do_postinc(dc, 4); |
| 2483 | cris_alu_m_free_temps(t); |
| 2484 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2485 | } |
| 2486 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2487 | static int dec_sub_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2488 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2489 | TCGv t[2]; |
| 2490 | int memsize = memsize_zz(dc); |
| 2491 | int insn_len; |
| 2492 | LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n", |
| 2493 | memsize_char(memsize), |
| 2494 | dc->op1, dc->postinc ? "+]" : "]", |
| 2495 | dc->op2, dc->ir, dc->zzsize); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2496 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2497 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2498 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2499 | cris_cc_mask(dc, CC_MASK_NZVC); |
| 2500 | cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); |
| 2501 | do_postinc(dc, memsize); |
| 2502 | cris_alu_m_free_temps(t); |
| 2503 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2504 | } |
| 2505 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2506 | static int dec_or_m(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2507 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2508 | TCGv t[2]; |
| 2509 | int memsize = memsize_zz(dc); |
| 2510 | int insn_len; |
| 2511 | LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n", |
| 2512 | memsize_char(memsize), |
| 2513 | dc->op1, dc->postinc ? "+]" : "]", |
| 2514 | dc->op2, dc->pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2515 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2516 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2517 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2518 | cris_cc_mask(dc, CC_MASK_NZ); |
| 2519 | cris_alu(dc, CC_OP_OR, |
| 2520 | cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); |
| 2521 | do_postinc(dc, memsize); |
| 2522 | cris_alu_m_free_temps(t); |
| 2523 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2524 | } |
| 2525 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2526 | static int dec_move_mp(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2527 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2528 | TCGv t[2]; |
| 2529 | int memsize = memsize_zz(dc); |
| 2530 | int insn_len = 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2531 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2532 | LOG_DIS("move.%c [$r%u%s, $p%u\n", |
| 2533 | memsize_char(memsize), |
| 2534 | dc->op1, |
| 2535 | dc->postinc ? "+]" : "]", |
| 2536 | dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2537 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2538 | cris_alu_m_alloc_temps(t); |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2539 | insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2540 | cris_cc_mask(dc, 0); |
| 2541 | if (dc->op2 == PR_CCS) { |
| 2542 | cris_evaluate_flags(dc); |
| 2543 | if (dc->tb_flags & U_FLAG) { |
| 2544 | /* User space is not allowed to touch all flags. */ |
| 2545 | tcg_gen_andi_tl(t[1], t[1], 0x39f); |
| 2546 | tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f); |
| 2547 | tcg_gen_or_tl(t[1], t[0], t[1]); |
| 2548 | } |
| 2549 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2550 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2551 | t_gen_mov_preg_TN(dc, dc->op2, t[1]); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2552 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2553 | do_postinc(dc, memsize); |
| 2554 | cris_alu_m_free_temps(t); |
| 2555 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2556 | } |
| 2557 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2558 | static int dec_move_pm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2559 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2560 | TCGv t0; |
| 2561 | int memsize; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2562 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2563 | memsize = preg_sizes[dc->op2]; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2564 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2565 | LOG_DIS("move.%c $p%u, [$r%u%s\n", |
| 2566 | memsize_char(memsize), |
| 2567 | dc->op2, dc->op1, dc->postinc ? "+]" : "]"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2568 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2569 | /* prepare store. Address in T0, value in T1. */ |
| 2570 | if (dc->op2 == PR_CCS) { |
| 2571 | cris_evaluate_flags(dc); |
| 2572 | } |
| 2573 | t0 = tcg_temp_new(); |
| 2574 | t_gen_mov_TN_preg(t0, dc->op2); |
| 2575 | cris_flush_cc_state(dc); |
| 2576 | gen_store(dc, cpu_R[dc->op1], t0, memsize); |
| 2577 | tcg_temp_free(t0); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2578 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2579 | cris_cc_mask(dc, 0); |
| 2580 | if (dc->postinc) { |
| 2581 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); |
| 2582 | } |
| 2583 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2584 | } |
| 2585 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2586 | static int dec_movem_mr(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2587 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2588 | TCGv_i64 tmp[16]; |
| 2589 | TCGv tmp32; |
| 2590 | TCGv addr; |
| 2591 | int i; |
| 2592 | int nr = dc->op2 + 1; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2593 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2594 | LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1, |
| 2595 | dc->postinc ? "+]" : "]", dc->op2); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2596 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2597 | addr = tcg_temp_new(); |
| 2598 | /* There are probably better ways of doing this. */ |
| 2599 | cris_flush_cc_state(dc); |
| 2600 | for (i = 0; i < (nr >> 1); i++) { |
| 2601 | tmp[i] = tcg_temp_new_i64(); |
| 2602 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
| 2603 | gen_load64(dc, tmp[i], addr); |
| 2604 | } |
| 2605 | if (nr & 1) { |
| 2606 | tmp32 = tcg_temp_new_i32(); |
| 2607 | tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8); |
| 2608 | gen_load(dc, tmp32, addr, 4, 0); |
| 2609 | } else { |
| 2610 | TCGV_UNUSED(tmp32); |
| 2611 | } |
| 2612 | tcg_temp_free(addr); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2613 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2614 | for (i = 0; i < (nr >> 1); i++) { |
| 2615 | tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]); |
| 2616 | tcg_gen_shri_i64(tmp[i], tmp[i], 32); |
| 2617 | tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]); |
| 2618 | tcg_temp_free_i64(tmp[i]); |
| 2619 | } |
| 2620 | if (nr & 1) { |
| 2621 | tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); |
| 2622 | tcg_temp_free(tmp32); |
| 2623 | } |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2624 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2625 | /* writeback the updated pointer value. */ |
| 2626 | if (dc->postinc) { |
| 2627 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4); |
| 2628 | } |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2629 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2630 | /* gen_load might want to evaluate the previous insns flags. */ |
| 2631 | cris_cc_mask(dc, 0); |
| 2632 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2633 | } |
| 2634 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2635 | static int dec_movem_rm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2636 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2637 | TCGv tmp; |
| 2638 | TCGv addr; |
| 2639 | int i; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2640 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2641 | LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1, |
| 2642 | dc->postinc ? "+]" : "]"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2643 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2644 | cris_flush_cc_state(dc); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 2645 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2646 | tmp = tcg_temp_new(); |
| 2647 | addr = tcg_temp_new(); |
| 2648 | tcg_gen_movi_tl(tmp, 4); |
| 2649 | tcg_gen_mov_tl(addr, cpu_R[dc->op1]); |
| 2650 | for (i = 0; i <= dc->op2; i++) { |
| 2651 | /* Displace addr. */ |
| 2652 | /* Perform the store. */ |
| 2653 | gen_store(dc, addr, cpu_R[i], 4); |
| 2654 | tcg_gen_add_tl(addr, addr, tmp); |
| 2655 | } |
| 2656 | if (dc->postinc) { |
| 2657 | tcg_gen_mov_tl(cpu_R[dc->op1], addr); |
| 2658 | } |
| 2659 | cris_cc_mask(dc, 0); |
| 2660 | tcg_temp_free(tmp); |
| 2661 | tcg_temp_free(addr); |
| 2662 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2663 | } |
| 2664 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2665 | static int dec_move_rm(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2666 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2667 | int memsize; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2668 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2669 | memsize = memsize_zz(dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2670 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2671 | LOG_DIS("move.%c $r%u, [$r%u]\n", |
| 2672 | memsize_char(memsize), dc->op2, dc->op1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2673 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2674 | /* prepare store. */ |
| 2675 | cris_flush_cc_state(dc); |
| 2676 | gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize); |
edgar_igl | 17ac975 | 2008-05-06 08:30:15 +0000 | [diff] [blame] | 2677 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2678 | if (dc->postinc) { |
| 2679 | tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize); |
| 2680 | } |
| 2681 | cris_cc_mask(dc, 0); |
| 2682 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2683 | } |
| 2684 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2685 | static int dec_lapcq(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2686 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2687 | LOG_DIS("lapcq %x, $r%u\n", |
| 2688 | dc->pc + dc->op1*2, dc->op2); |
| 2689 | cris_cc_mask(dc, 0); |
| 2690 | tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2); |
| 2691 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2692 | } |
| 2693 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2694 | static int dec_lapc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2695 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2696 | unsigned int rd; |
| 2697 | int32_t imm; |
| 2698 | int32_t pc; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2699 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2700 | rd = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2701 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2702 | cris_cc_mask(dc, 0); |
| 2703 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
| 2704 | LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2705 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2706 | pc = dc->pc; |
| 2707 | pc += imm; |
| 2708 | tcg_gen_movi_tl(cpu_R[rd], pc); |
| 2709 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2710 | } |
| 2711 | |
| 2712 | /* Jump to special reg. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2713 | static int dec_jump_p(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2714 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2715 | LOG_DIS("jump $p%u\n", dc->op2); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2716 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2717 | if (dc->op2 == PR_CCS) { |
| 2718 | cris_evaluate_flags(dc); |
| 2719 | } |
| 2720 | t_gen_mov_TN_preg(env_btarget, dc->op2); |
| 2721 | /* rete will often have low bit set to indicate delayslot. */ |
| 2722 | tcg_gen_andi_tl(env_btarget, env_btarget, ~1); |
| 2723 | cris_cc_mask(dc, 0); |
| 2724 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2725 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2726 | } |
| 2727 | |
| 2728 | /* Jump and save. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2729 | static int dec_jas_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2730 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2731 | LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); |
| 2732 | cris_cc_mask(dc, 0); |
| 2733 | /* Store the return address in Pd. */ |
| 2734 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); |
| 2735 | if (dc->op2 > 15) { |
| 2736 | abort(); |
| 2737 | } |
| 2738 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4)); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 2739 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2740 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2741 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2742 | } |
| 2743 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2744 | static int dec_jas_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2745 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2746 | uint32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2747 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2748 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2749 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2750 | LOG_DIS("jas 0x%x\n", imm); |
| 2751 | cris_cc_mask(dc, 0); |
| 2752 | /* Store the return address in Pd. */ |
| 2753 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2754 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2755 | dc->jmp_pc = imm; |
| 2756 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2757 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2758 | } |
| 2759 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2760 | static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2761 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2762 | uint32_t imm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2763 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2764 | imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2765 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2766 | LOG_DIS("jasc 0x%x\n", imm); |
| 2767 | cris_cc_mask(dc, 0); |
| 2768 | /* Store the return address in Pd. */ |
| 2769 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4)); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2770 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2771 | dc->jmp_pc = imm; |
| 2772 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2773 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2774 | } |
| 2775 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2776 | static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2777 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2778 | LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); |
| 2779 | cris_cc_mask(dc, 0); |
| 2780 | /* Store the return address in Pd. */ |
| 2781 | tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); |
| 2782 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4)); |
| 2783 | cris_prepare_jmp(dc, JMP_INDIRECT); |
| 2784 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2785 | } |
| 2786 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2787 | static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2788 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2789 | int32_t offset; |
| 2790 | uint32_t cond = dc->op2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2791 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2792 | offset = cris_fetch(env, dc, dc->pc + 2, 2, 1); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2793 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2794 | LOG_DIS("b%s %d pc=%x dst=%x\n", |
| 2795 | cc_name(cond), offset, |
| 2796 | dc->pc, dc->pc + offset); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2797 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2798 | cris_cc_mask(dc, 0); |
| 2799 | /* op2 holds the condition-code. */ |
| 2800 | cris_prepare_cc_branch(dc, offset, cond); |
| 2801 | return 4; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2802 | } |
| 2803 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2804 | static int dec_bas_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2805 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2806 | int32_t simm; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2807 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2808 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2809 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2810 | LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
| 2811 | cris_cc_mask(dc, 0); |
| 2812 | /* Store the return address in Pd. */ |
| 2813 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2814 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2815 | dc->jmp_pc = dc->pc + simm; |
| 2816 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2817 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2818 | } |
| 2819 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2820 | static int dec_basc_im(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2821 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2822 | int32_t simm; |
| 2823 | simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2824 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2825 | LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); |
| 2826 | cris_cc_mask(dc, 0); |
| 2827 | /* Store the return address in Pd. */ |
| 2828 | t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12)); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 2829 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2830 | dc->jmp_pc = dc->pc + simm; |
| 2831 | cris_prepare_jmp(dc, JMP_DIRECT); |
| 2832 | return 6; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2833 | } |
| 2834 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2835 | static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2836 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2837 | cris_cc_mask(dc, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2838 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2839 | if (dc->op2 == 15) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 2840 | tcg_gen_st_i32(tcg_const_i32(1), cpu_env, |
| 2841 | -offsetof(CRISCPU, env) + offsetof(CPUState, halted)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2842 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
| 2843 | t_gen_raise_exception(EXCP_HLT); |
| 2844 | return 2; |
| 2845 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2846 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2847 | switch (dc->op2 & 7) { |
| 2848 | case 2: |
| 2849 | /* rfe. */ |
| 2850 | LOG_DIS("rfe\n"); |
| 2851 | cris_evaluate_flags(dc); |
| 2852 | gen_helper_rfe(cpu_env); |
| 2853 | dc->is_jmp = DISAS_UPDATE; |
| 2854 | break; |
| 2855 | case 5: |
| 2856 | /* rfn. */ |
| 2857 | LOG_DIS("rfn\n"); |
| 2858 | cris_evaluate_flags(dc); |
| 2859 | gen_helper_rfn(cpu_env); |
| 2860 | dc->is_jmp = DISAS_UPDATE; |
| 2861 | break; |
| 2862 | case 6: |
| 2863 | LOG_DIS("break %d\n", dc->op1); |
| 2864 | cris_evaluate_flags(dc); |
| 2865 | /* break. */ |
| 2866 | tcg_gen_movi_tl(env_pc, dc->pc + 2); |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 2867 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2868 | /* Breaks start at 16 in the exception vector. */ |
| 2869 | t_gen_mov_env_TN(trap_vector, |
| 2870 | tcg_const_tl(dc->op1 + 16)); |
| 2871 | t_gen_raise_exception(EXCP_BREAK); |
| 2872 | dc->is_jmp = DISAS_UPDATE; |
| 2873 | break; |
| 2874 | default: |
| 2875 | printf("op2=%x\n", dc->op2); |
| 2876 | BUG(); |
| 2877 | break; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2878 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2879 | } |
| 2880 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2881 | } |
| 2882 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2883 | static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc) |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2884 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2885 | return 2; |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2886 | } |
| 2887 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2888 | static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc) |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2889 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2890 | return 2; |
edgar_igl | 5d4a534 | 2008-02-25 09:58:22 +0000 | [diff] [blame] | 2891 | } |
| 2892 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 2893 | static int dec_null(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2894 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2895 | printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n", |
| 2896 | dc->pc, dc->opcode, dc->op1, dc->op2); |
| 2897 | fflush(NULL); |
| 2898 | BUG(); |
| 2899 | return 2; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2900 | } |
| 2901 | |
edgar_igl | 9b32fbf | 2008-10-07 22:54:52 +0000 | [diff] [blame] | 2902 | static struct decoder_info { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2903 | struct { |
| 2904 | uint32_t bits; |
| 2905 | uint32_t mask; |
| 2906 | }; |
| 2907 | int (*dec)(CPUCRISState *env, DisasContext *dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2908 | } decinfo[] = { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2909 | /* Order matters here. */ |
| 2910 | {DEC_MOVEQ, dec_moveq}, |
| 2911 | {DEC_BTSTQ, dec_btstq}, |
| 2912 | {DEC_CMPQ, dec_cmpq}, |
| 2913 | {DEC_ADDOQ, dec_addoq}, |
| 2914 | {DEC_ADDQ, dec_addq}, |
| 2915 | {DEC_SUBQ, dec_subq}, |
| 2916 | {DEC_ANDQ, dec_andq}, |
| 2917 | {DEC_ORQ, dec_orq}, |
| 2918 | {DEC_ASRQ, dec_asrq}, |
| 2919 | {DEC_LSLQ, dec_lslq}, |
| 2920 | {DEC_LSRQ, dec_lsrq}, |
| 2921 | {DEC_BCCQ, dec_bccq}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2922 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2923 | {DEC_BCC_IM, dec_bcc_im}, |
| 2924 | {DEC_JAS_IM, dec_jas_im}, |
| 2925 | {DEC_JAS_R, dec_jas_r}, |
| 2926 | {DEC_JASC_IM, dec_jasc_im}, |
| 2927 | {DEC_JASC_R, dec_jasc_r}, |
| 2928 | {DEC_BAS_IM, dec_bas_im}, |
| 2929 | {DEC_BASC_IM, dec_basc_im}, |
| 2930 | {DEC_JUMP_P, dec_jump_p}, |
| 2931 | {DEC_LAPC_IM, dec_lapc_im}, |
| 2932 | {DEC_LAPCQ, dec_lapcq}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2933 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2934 | {DEC_RFE_ETC, dec_rfe_etc}, |
| 2935 | {DEC_ADDC_MR, dec_addc_mr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2936 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2937 | {DEC_MOVE_MP, dec_move_mp}, |
| 2938 | {DEC_MOVE_PM, dec_move_pm}, |
| 2939 | {DEC_MOVEM_MR, dec_movem_mr}, |
| 2940 | {DEC_MOVEM_RM, dec_movem_rm}, |
| 2941 | {DEC_MOVE_PR, dec_move_pr}, |
| 2942 | {DEC_SCC_R, dec_scc_r}, |
| 2943 | {DEC_SETF, dec_setclrf}, |
| 2944 | {DEC_CLEARF, dec_setclrf}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2945 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2946 | {DEC_MOVE_SR, dec_move_sr}, |
| 2947 | {DEC_MOVE_RP, dec_move_rp}, |
| 2948 | {DEC_SWAP_R, dec_swap_r}, |
| 2949 | {DEC_ABS_R, dec_abs_r}, |
| 2950 | {DEC_LZ_R, dec_lz_r}, |
| 2951 | {DEC_MOVE_RS, dec_move_rs}, |
| 2952 | {DEC_BTST_R, dec_btst_r}, |
| 2953 | {DEC_ADDC_R, dec_addc_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2954 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2955 | {DEC_DSTEP_R, dec_dstep_r}, |
| 2956 | {DEC_XOR_R, dec_xor_r}, |
| 2957 | {DEC_MCP_R, dec_mcp_r}, |
| 2958 | {DEC_CMP_R, dec_cmp_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2959 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2960 | {DEC_ADDI_R, dec_addi_r}, |
| 2961 | {DEC_ADDI_ACR, dec_addi_acr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2962 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2963 | {DEC_ADD_R, dec_add_r}, |
| 2964 | {DEC_SUB_R, dec_sub_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2965 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2966 | {DEC_ADDU_R, dec_addu_r}, |
| 2967 | {DEC_ADDS_R, dec_adds_r}, |
| 2968 | {DEC_SUBU_R, dec_subu_r}, |
| 2969 | {DEC_SUBS_R, dec_subs_r}, |
| 2970 | {DEC_LSL_R, dec_lsl_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2971 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2972 | {DEC_AND_R, dec_and_r}, |
| 2973 | {DEC_OR_R, dec_or_r}, |
| 2974 | {DEC_BOUND_R, dec_bound_r}, |
| 2975 | {DEC_ASR_R, dec_asr_r}, |
| 2976 | {DEC_LSR_R, dec_lsr_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2977 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2978 | {DEC_MOVU_R, dec_movu_r}, |
| 2979 | {DEC_MOVS_R, dec_movs_r}, |
| 2980 | {DEC_NEG_R, dec_neg_r}, |
| 2981 | {DEC_MOVE_R, dec_move_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2982 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2983 | {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m}, |
| 2984 | {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2985 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2986 | {DEC_MULS_R, dec_muls_r}, |
| 2987 | {DEC_MULU_R, dec_mulu_r}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2988 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2989 | {DEC_ADDU_M, dec_addu_m}, |
| 2990 | {DEC_ADDS_M, dec_adds_m}, |
| 2991 | {DEC_SUBU_M, dec_subu_m}, |
| 2992 | {DEC_SUBS_M, dec_subs_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2993 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2994 | {DEC_CMPU_M, dec_cmpu_m}, |
| 2995 | {DEC_CMPS_M, dec_cmps_m}, |
| 2996 | {DEC_MOVU_M, dec_movu_m}, |
| 2997 | {DEC_MOVS_M, dec_movs_m}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 2998 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 2999 | {DEC_CMP_M, dec_cmp_m}, |
| 3000 | {DEC_ADDO_M, dec_addo_m}, |
| 3001 | {DEC_BOUND_M, dec_bound_m}, |
| 3002 | {DEC_ADD_M, dec_add_m}, |
| 3003 | {DEC_SUB_M, dec_sub_m}, |
| 3004 | {DEC_AND_M, dec_and_m}, |
| 3005 | {DEC_OR_M, dec_or_m}, |
| 3006 | {DEC_MOVE_RM, dec_move_rm}, |
| 3007 | {DEC_TEST_M, dec_test_m}, |
| 3008 | {DEC_MOVE_MR, dec_move_mr}, |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3009 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3010 | {{0, 0}, dec_null} |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3011 | }; |
| 3012 | |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 3013 | static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3014 | { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3015 | int insn_len = 2; |
| 3016 | int i; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3017 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3018 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
| 3019 | tcg_gen_debug_insn_start(dc->pc); |
Richard Henderson | fdefe51 | 2012-09-24 14:55:47 -0700 | [diff] [blame] | 3020 | } |
edgar_igl | 28de16d | 2008-09-22 20:51:28 +0000 | [diff] [blame] | 3021 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3022 | /* Load a halfword onto the instruction register. */ |
Aurelien Jarno | cf7e0c8 | 2012-09-07 16:13:27 +0200 | [diff] [blame] | 3023 | dc->ir = cris_fetch(env, dc, dc->pc, 2, 0); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3024 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3025 | /* Now decode it. */ |
| 3026 | dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11); |
| 3027 | dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3); |
| 3028 | dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15); |
| 3029 | dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4); |
| 3030 | dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5); |
| 3031 | dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3032 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3033 | /* Large switch for all insns. */ |
| 3034 | for (i = 0; i < ARRAY_SIZE(decinfo); i++) { |
| 3035 | if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { |
| 3036 | insn_len = decinfo[i].dec(env, dc); |
| 3037 | break; |
| 3038 | } |
| 3039 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3040 | |
edgar_igl | dd20fcd | 2008-10-08 08:28:16 +0000 | [diff] [blame] | 3041 | #if !defined(CONFIG_USER_ONLY) |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3042 | /* Single-stepping ? */ |
| 3043 | if (dc->tb_flags & S_FLAG) { |
| 3044 | int l1; |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 3045 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3046 | l1 = gen_new_label(); |
| 3047 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); |
| 3048 | /* We treat SPC as a break with an odd trap vector. */ |
| 3049 | cris_evaluate_flags(dc); |
| 3050 | t_gen_mov_env_TN(trap_vector, tcg_const_tl(3)); |
| 3051 | tcg_gen_movi_tl(env_pc, dc->pc + insn_len); |
| 3052 | tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); |
| 3053 | t_gen_raise_exception(EXCP_BREAK); |
| 3054 | gen_set_label(l1); |
| 3055 | } |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 3056 | #endif |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3057 | return insn_len; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3058 | } |
| 3059 | |
Andreas Färber | a1170bf | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 3060 | static void check_breakpoint(CPUCRISState *env, DisasContext *dc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3061 | { |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 3062 | CPUState *cs = CPU(cris_env_get_cpu(env)); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3063 | CPUBreakpoint *bp; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 3064 | |
Andreas Färber | f0c3c50 | 2013-08-26 21:22:53 +0200 | [diff] [blame] | 3065 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
| 3066 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3067 | if (bp->pc == dc->pc) { |
| 3068 | cris_evaluate_flags(dc); |
| 3069 | tcg_gen_movi_tl(env_pc, dc->pc); |
| 3070 | t_gen_raise_exception(EXCP_DEBUG); |
| 3071 | dc->is_jmp = DISAS_UPDATE; |
| 3072 | } |
| 3073 | } |
| 3074 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3075 | } |
| 3076 | |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 3077 | #include "translate_v10.c" |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 3078 | |
| 3079 | /* |
| 3080 | * Delay slots on QEMU/CRIS. |
| 3081 | * |
| 3082 | * If an exception hits on a delayslot, the core will let ERP (the Exception |
| 3083 | * Return Pointer) point to the branch (the previous) insn and set the lsb to |
| 3084 | * to give SW a hint that the exception actually hit on the dslot. |
| 3085 | * |
| 3086 | * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by |
| 3087 | * the core and any jmp to an odd addresses will mask off that lsb. It is |
| 3088 | * simply there to let sw know there was an exception on a dslot. |
| 3089 | * |
| 3090 | * When the software returns from an exception, the branch will re-execute. |
| 3091 | * On QEMU care needs to be taken when a branch+delayslot sequence is broken |
| 3092 | * and the branch and delayslot dont share pages. |
| 3093 | * |
| 3094 | * The TB contaning the branch insn will set up env->btarget and evaluate |
| 3095 | * env->btaken. When the translation loop exits we will note that the branch |
| 3096 | * sequence is broken and let env->dslot be the size of the branch insn (those |
| 3097 | * vary in length). |
| 3098 | * |
| 3099 | * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb |
| 3100 | * set). It will also expect to have env->dslot setup with the size of the |
| 3101 | * delay slot so that env->pc - env->dslot point to the branch insn. This TB |
| 3102 | * will execute the dslot and take the branch, either to btarget or just one |
| 3103 | * insn ahead. |
| 3104 | * |
| 3105 | * When exceptions occur, we check for env->dslot in do_interrupt to detect |
| 3106 | * broken branch sequences and setup $erp accordingly (i.e let it point to the |
| 3107 | * branch and set lsb). Then env->dslot gets cleared so that the exception |
| 3108 | * handler can enter. When returning from exceptions (jump $erp) the lsb gets |
| 3109 | * masked off and we will reexecute the branch insn. |
| 3110 | * |
| 3111 | */ |
| 3112 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3113 | /* generate intermediate code for basic block 'tb'. */ |
Andreas Färber | 6f47ec5 | 2013-07-02 19:30:14 +0200 | [diff] [blame] | 3114 | static inline void |
Andreas Färber | 7fd2592 | 2013-06-21 22:04:49 +0200 | [diff] [blame] | 3115 | gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb, |
| 3116 | bool search_pc) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3117 | { |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 3118 | CPUState *cs = CPU(cpu); |
Andreas Färber | 7fd2592 | 2013-06-21 22:04:49 +0200 | [diff] [blame] | 3119 | CPUCRISState *env = &cpu->env; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3120 | uint16_t *gen_opc_end; |
| 3121 | uint32_t pc_start; |
| 3122 | unsigned int insn_len; |
| 3123 | int j, lj; |
| 3124 | struct DisasContext ctx; |
| 3125 | struct DisasContext *dc = &ctx; |
| 3126 | uint32_t next_page_start; |
| 3127 | target_ulong npc; |
| 3128 | int num_insns; |
| 3129 | int max_insns; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3130 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3131 | if (env->pregs[PR_VR] == 32) { |
| 3132 | dc->decoder = crisv32_decoder; |
| 3133 | dc->clear_locked_irq = 0; |
| 3134 | } else { |
| 3135 | dc->decoder = crisv10_decoder; |
| 3136 | dc->clear_locked_irq = 1; |
| 3137 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 3138 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3139 | /* Odd PC indicates that branch is rexecuting due to exception in the |
| 3140 | * delayslot, like in real hw. |
| 3141 | */ |
| 3142 | pc_start = tb->pc & ~1; |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 3143 | dc->cpu = cpu; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3144 | dc->tb = tb; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3145 | |
Evgeny Voevodin | 92414b3 | 2012-11-12 13:27:47 +0400 | [diff] [blame] | 3146 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3147 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3148 | dc->is_jmp = DISAS_NEXT; |
| 3149 | dc->ppc = pc_start; |
| 3150 | dc->pc = pc_start; |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 3151 | dc->singlestep_enabled = cs->singlestep_enabled; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3152 | dc->flags_uptodate = 1; |
| 3153 | dc->flagx_known = 1; |
| 3154 | dc->flags_x = tb->flags & X_FLAG; |
| 3155 | dc->cc_x_uptodate = 0; |
| 3156 | dc->cc_mask = 0; |
| 3157 | dc->update_cc = 0; |
| 3158 | dc->clear_prefix = 0; |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 3159 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3160 | cris_update_cc_op(dc, CC_OP_FLAGS, 4); |
| 3161 | dc->cc_size_uptodate = -1; |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 3162 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3163 | /* Decode TB flags. */ |
| 3164 | dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \ |
| 3165 | | X_FLAG | PFIX_FLAG); |
| 3166 | dc->delayed_branch = !!(tb->flags & 7); |
| 3167 | if (dc->delayed_branch) { |
| 3168 | dc->jmp = JMP_INDIRECT; |
| 3169 | } else { |
| 3170 | dc->jmp = JMP_NOJMP; |
| 3171 | } |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 3172 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3173 | dc->cpustate_changed = 0; |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 3174 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3175 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
| 3176 | qemu_log( |
| 3177 | "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n" |
| 3178 | "pid=%x usp=%x\n" |
| 3179 | "%x.%x.%x.%x\n" |
| 3180 | "%x.%x.%x.%x\n" |
| 3181 | "%x.%x.%x.%x\n" |
| 3182 | "%x.%x.%x.%x\n", |
| 3183 | search_pc, dc->pc, dc->ppc, |
| 3184 | (uint64_t)tb->flags, |
| 3185 | env->btarget, (unsigned)tb->flags & 7, |
| 3186 | env->pregs[PR_CCS], |
| 3187 | env->pregs[PR_PID], env->pregs[PR_USP], |
| 3188 | env->regs[0], env->regs[1], env->regs[2], env->regs[3], |
| 3189 | env->regs[4], env->regs[5], env->regs[6], env->regs[7], |
| 3190 | env->regs[8], env->regs[9], |
| 3191 | env->regs[10], env->regs[11], |
| 3192 | env->regs[12], env->regs[13], |
| 3193 | env->regs[14], env->regs[15]); |
| 3194 | qemu_log("--------------\n"); |
| 3195 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
| 3196 | } |
edgar_igl | 3157a0a | 2008-03-15 20:45:05 +0000 | [diff] [blame] | 3197 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3198 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
| 3199 | lj = -1; |
| 3200 | num_insns = 0; |
| 3201 | max_insns = tb->cflags & CF_COUNT_MASK; |
| 3202 | if (max_insns == 0) { |
| 3203 | max_insns = CF_COUNT_MASK; |
| 3204 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3205 | |
Peter Maydell | 806f352 | 2013-02-22 18:10:05 +0000 | [diff] [blame] | 3206 | gen_tb_start(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3207 | do { |
| 3208 | check_breakpoint(env, dc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3209 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3210 | if (search_pc) { |
Evgeny Voevodin | 92414b3 | 2012-11-12 13:27:47 +0400 | [diff] [blame] | 3211 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3212 | if (lj < j) { |
| 3213 | lj++; |
| 3214 | while (lj < j) { |
Evgeny Voevodin | ab1103d | 2012-11-21 11:43:06 +0400 | [diff] [blame] | 3215 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3216 | } |
| 3217 | } |
| 3218 | if (dc->delayed_branch == 1) { |
Evgeny Voevodin | 25983ca | 2012-11-21 11:43:04 +0400 | [diff] [blame] | 3219 | tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3220 | } else { |
Evgeny Voevodin | 25983ca | 2012-11-21 11:43:04 +0400 | [diff] [blame] | 3221 | tcg_ctx.gen_opc_pc[lj] = dc->pc; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3222 | } |
Evgeny Voevodin | ab1103d | 2012-11-21 11:43:06 +0400 | [diff] [blame] | 3223 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
Evgeny Voevodin | c9c99c2 | 2012-11-21 11:43:05 +0400 | [diff] [blame] | 3224 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3225 | } |
edgar_igl | cf1d97f | 2008-05-13 10:59:14 +0000 | [diff] [blame] | 3226 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3227 | /* Pretty disas. */ |
| 3228 | LOG_DIS("%8.8x:\t", dc->pc); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3229 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3230 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { |
| 3231 | gen_io_start(); |
| 3232 | } |
| 3233 | dc->clear_x = 1; |
edgar_igl | 28de16d | 2008-09-22 20:51:28 +0000 | [diff] [blame] | 3234 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3235 | insn_len = dc->decoder(env, dc); |
| 3236 | dc->ppc = dc->pc; |
| 3237 | dc->pc += insn_len; |
| 3238 | if (dc->clear_x) { |
| 3239 | cris_clear_x_flag(dc); |
| 3240 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3241 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3242 | num_insns++; |
| 3243 | /* Check for delayed branches here. If we do it before |
| 3244 | actually generating any host code, the simulator will just |
| 3245 | loop doing nothing for on this program location. */ |
| 3246 | if (dc->delayed_branch) { |
| 3247 | dc->delayed_branch--; |
| 3248 | if (dc->delayed_branch == 0) { |
| 3249 | if (tb->flags & 7) { |
| 3250 | t_gen_mov_env_TN(dslot, tcg_const_tl(0)); |
| 3251 | } |
| 3252 | if (dc->cpustate_changed || !dc->flagx_known |
| 3253 | || (dc->flags_x != (tb->flags & X_FLAG))) { |
| 3254 | cris_store_direct_jmp(dc); |
| 3255 | } |
Edgar E. Iglesias | 5cabc5c | 2011-01-10 23:24:36 +0100 | [diff] [blame] | 3256 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3257 | if (dc->clear_locked_irq) { |
| 3258 | dc->clear_locked_irq = 0; |
| 3259 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); |
| 3260 | } |
Edgar E. Iglesias | 5cabc5c | 2011-01-10 23:24:36 +0100 | [diff] [blame] | 3261 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3262 | if (dc->jmp == JMP_DIRECT_CC) { |
| 3263 | int l1; |
Edgar E. Iglesias | cb752a6 | 2011-01-07 16:18:13 +0100 | [diff] [blame] | 3264 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3265 | l1 = gen_new_label(); |
| 3266 | cris_evaluate_flags(dc); |
Edgar E. Iglesias | cb752a6 | 2011-01-07 16:18:13 +0100 | [diff] [blame] | 3267 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3268 | /* Conditional jmp. */ |
| 3269 | tcg_gen_brcondi_tl(TCG_COND_EQ, |
| 3270 | env_btaken, 0, l1); |
| 3271 | gen_goto_tb(dc, 1, dc->jmp_pc); |
| 3272 | gen_set_label(l1); |
| 3273 | gen_goto_tb(dc, 0, dc->pc); |
| 3274 | dc->is_jmp = DISAS_TB_JUMP; |
| 3275 | dc->jmp = JMP_NOJMP; |
| 3276 | } else if (dc->jmp == JMP_DIRECT) { |
| 3277 | cris_evaluate_flags(dc); |
| 3278 | gen_goto_tb(dc, 0, dc->jmp_pc); |
| 3279 | dc->is_jmp = DISAS_TB_JUMP; |
| 3280 | dc->jmp = JMP_NOJMP; |
| 3281 | } else { |
| 3282 | t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc)); |
| 3283 | dc->is_jmp = DISAS_JUMP; |
| 3284 | } |
| 3285 | break; |
| 3286 | } |
| 3287 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3288 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3289 | /* If we are rexecuting a branch due to exceptions on |
| 3290 | delay slots dont break. */ |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 3291 | if (!(tb->pc & 1) && cs->singlestep_enabled) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3292 | break; |
| 3293 | } |
| 3294 | } while (!dc->is_jmp && !dc->cpustate_changed |
Evgeny Voevodin | efd7f48 | 2012-11-12 13:27:45 +0400 | [diff] [blame] | 3295 | && tcg_ctx.gen_opc_ptr < gen_opc_end |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3296 | && !singlestep |
| 3297 | && (dc->pc < next_page_start) |
| 3298 | && num_insns < max_insns); |
edgar_igl | b41f7df | 2008-05-02 22:16:17 +0000 | [diff] [blame] | 3299 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3300 | if (dc->clear_locked_irq) { |
| 3301 | t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); |
| 3302 | } |
Edgar E. Iglesias | 40e9edd | 2010-02-15 12:18:57 +0100 | [diff] [blame] | 3303 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3304 | npc = dc->pc; |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 3305 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 3306 | if (tb->cflags & CF_LAST_IO) |
| 3307 | gen_io_end(); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3308 | /* Force an update if the per-tb cpu state has changed. */ |
| 3309 | if (dc->is_jmp == DISAS_NEXT |
| 3310 | && (dc->cpustate_changed || !dc->flagx_known |
| 3311 | || (dc->flags_x != (tb->flags & X_FLAG)))) { |
| 3312 | dc->is_jmp = DISAS_UPDATE; |
| 3313 | tcg_gen_movi_tl(env_pc, npc); |
| 3314 | } |
| 3315 | /* Broken branch+delayslot sequence. */ |
| 3316 | if (dc->delayed_branch == 1) { |
| 3317 | /* Set env->dslot to the size of the branch insn. */ |
| 3318 | t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc)); |
| 3319 | cris_store_direct_jmp(dc); |
| 3320 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3321 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3322 | cris_evaluate_flags(dc); |
edgar_igl | 2a44f7f | 2008-06-06 11:23:28 +0000 | [diff] [blame] | 3323 | |
Andreas Färber | ed2803d | 2013-06-21 20:20:45 +0200 | [diff] [blame] | 3324 | if (unlikely(cs->singlestep_enabled)) { |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3325 | if (dc->is_jmp == DISAS_NEXT) { |
| 3326 | tcg_gen_movi_tl(env_pc, npc); |
| 3327 | } |
| 3328 | t_gen_raise_exception(EXCP_DEBUG); |
| 3329 | } else { |
| 3330 | switch (dc->is_jmp) { |
| 3331 | case DISAS_NEXT: |
| 3332 | gen_goto_tb(dc, 1, npc); |
| 3333 | break; |
| 3334 | default: |
| 3335 | case DISAS_JUMP: |
| 3336 | case DISAS_UPDATE: |
| 3337 | /* indicate that the hash table must be used |
| 3338 | to find the next TB */ |
| 3339 | tcg_gen_exit_tb(0); |
| 3340 | break; |
| 3341 | case DISAS_SWI: |
| 3342 | case DISAS_TB_JUMP: |
| 3343 | /* nothing more to generate */ |
| 3344 | break; |
| 3345 | } |
| 3346 | } |
Peter Maydell | 806f352 | 2013-02-22 18:10:05 +0000 | [diff] [blame] | 3347 | gen_tb_end(tb, num_insns); |
Evgeny Voevodin | efd7f48 | 2012-11-12 13:27:45 +0400 | [diff] [blame] | 3348 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3349 | if (search_pc) { |
Evgeny Voevodin | 92414b3 | 2012-11-12 13:27:47 +0400 | [diff] [blame] | 3350 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3351 | lj++; |
| 3352 | while (lj <= j) { |
Evgeny Voevodin | ab1103d | 2012-11-21 11:43:06 +0400 | [diff] [blame] | 3353 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3354 | } |
| 3355 | } else { |
| 3356 | tb->size = dc->pc - pc_start; |
| 3357 | tb->icount = num_insns; |
| 3358 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3359 | |
| 3360 | #ifdef DEBUG_DISAS |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 3361 | #if !DISAS_CRIS |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3362 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
| 3363 | log_target_disas(env, pc_start, dc->pc - pc_start, |
Andreas Färber | 0dd106c | 2013-09-03 18:42:27 +0200 | [diff] [blame] | 3364 | env->pregs[PR_VR]); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3365 | qemu_log("\nisize=%d osize=%td\n", |
Evgeny Voevodin | 92414b3 | 2012-11-12 13:27:47 +0400 | [diff] [blame] | 3366 | dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf); |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3367 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3368 | #endif |
edgar_igl | a1aebcb | 2008-10-07 22:48:41 +0000 | [diff] [blame] | 3369 | #endif |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3370 | } |
| 3371 | |
Andreas Färber | a1170bf | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 3372 | void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3373 | { |
Andreas Färber | 7fd2592 | 2013-06-21 22:04:49 +0200 | [diff] [blame] | 3374 | gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3375 | } |
| 3376 | |
Andreas Färber | a1170bf | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 3377 | void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3378 | { |
Andreas Färber | 7fd2592 | 2013-06-21 22:04:49 +0200 | [diff] [blame] | 3379 | gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3380 | } |
| 3381 | |
Andreas Färber | 878096e | 2013-05-27 01:33:50 +0200 | [diff] [blame] | 3382 | void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
| 3383 | int flags) |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3384 | { |
Andreas Färber | 878096e | 2013-05-27 01:33:50 +0200 | [diff] [blame] | 3385 | CRISCPU *cpu = CRIS_CPU(cs); |
| 3386 | CPUCRISState *env = &cpu->env; |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3387 | int i; |
| 3388 | uint32_t srs; |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3389 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3390 | if (!env || !f) { |
| 3391 | return; |
| 3392 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3393 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3394 | cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n" |
| 3395 | "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n", |
| 3396 | env->pc, env->pregs[PR_CCS], env->btaken, env->btarget, |
| 3397 | env->cc_op, |
| 3398 | env->cc_src, env->cc_dest, env->cc_result, env->cc_mask); |
edgar_igl | 30abcfc | 2008-05-27 21:10:56 +0000 | [diff] [blame] | 3399 | |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3400 | |
Evgeny Voevodin | 7b5eff4 | 2012-11-12 13:27:43 +0400 | [diff] [blame] | 3401 | for (i = 0; i < 16; i++) { |
| 3402 | cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]); |
| 3403 | if ((i + 1) % 4 == 0) { |
| 3404 | cpu_fprintf(f, "\n"); |
| 3405 | } |
| 3406 | } |
| 3407 | cpu_fprintf(f, "\nspecial regs:\n"); |
| 3408 | for (i = 0; i < 16; i++) { |
| 3409 | cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]); |
| 3410 | if ((i + 1) % 4 == 0) { |
| 3411 | cpu_fprintf(f, "\n"); |
| 3412 | } |
| 3413 | } |
| 3414 | srs = env->pregs[PR_SRS]; |
| 3415 | cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs); |
| 3416 | if (srs < ARRAY_SIZE(env->sregs)) { |
| 3417 | for (i = 0; i < 16; i++) { |
| 3418 | cpu_fprintf(f, "s%2.2d=%8.8x ", |
| 3419 | i, env->sregs[srs][i]); |
| 3420 | if ((i + 1) % 4 == 0) { |
| 3421 | cpu_fprintf(f, "\n"); |
| 3422 | } |
| 3423 | } |
| 3424 | } |
| 3425 | cpu_fprintf(f, "\n\n"); |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3426 | |
| 3427 | } |
| 3428 | |
Andreas Färber | d1a94fe | 2013-01-19 23:55:42 +0100 | [diff] [blame] | 3429 | void cris_initialize_tcg(void) |
| 3430 | { |
| 3431 | int i; |
edgar_igl | 05ba7d5 | 2008-03-14 01:11:25 +0000 | [diff] [blame] | 3432 | |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3433 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
| 3434 | cc_x = tcg_global_mem_new(TCG_AREG0, |
| 3435 | offsetof(CPUCRISState, cc_x), "cc_x"); |
| 3436 | cc_src = tcg_global_mem_new(TCG_AREG0, |
| 3437 | offsetof(CPUCRISState, cc_src), "cc_src"); |
| 3438 | cc_dest = tcg_global_mem_new(TCG_AREG0, |
| 3439 | offsetof(CPUCRISState, cc_dest), |
| 3440 | "cc_dest"); |
| 3441 | cc_result = tcg_global_mem_new(TCG_AREG0, |
| 3442 | offsetof(CPUCRISState, cc_result), |
| 3443 | "cc_result"); |
| 3444 | cc_op = tcg_global_mem_new(TCG_AREG0, |
| 3445 | offsetof(CPUCRISState, cc_op), "cc_op"); |
| 3446 | cc_size = tcg_global_mem_new(TCG_AREG0, |
| 3447 | offsetof(CPUCRISState, cc_size), |
| 3448 | "cc_size"); |
| 3449 | cc_mask = tcg_global_mem_new(TCG_AREG0, |
| 3450 | offsetof(CPUCRISState, cc_mask), |
| 3451 | "cc_mask"); |
edgar_igl | a825e70 | 2008-03-16 16:51:58 +0000 | [diff] [blame] | 3452 | |
Andreas Färber | dd10ce6 | 2012-05-05 11:45:32 +0200 | [diff] [blame] | 3453 | env_pc = tcg_global_mem_new(TCG_AREG0, |
| 3454 | offsetof(CPUCRISState, pc), |
| 3455 | "pc"); |
| 3456 | env_btarget = tcg_global_mem_new(TCG_AREG0, |
| 3457 | offsetof(CPUCRISState, btarget), |
| 3458 | "btarget"); |
| 3459 | env_btaken = tcg_global_mem_new(TCG_AREG0, |
| 3460 | offsetof(CPUCRISState, btaken), |
| 3461 | "btaken"); |
| 3462 | for (i = 0; i < 16; i++) { |
| 3463 | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
| 3464 | offsetof(CPUCRISState, regs[i]), |
| 3465 | regnames[i]); |
| 3466 | } |
| 3467 | for (i = 0; i < 16; i++) { |
| 3468 | cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, |
| 3469 | offsetof(CPUCRISState, pregs[i]), |
| 3470 | pregnames[i]); |
| 3471 | } |
ths | 8170028 | 2007-10-08 12:49:08 +0000 | [diff] [blame] | 3472 | } |
| 3473 | |
Andreas Färber | a1170bf | 2012-03-14 01:38:21 +0100 | [diff] [blame] | 3474 | void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 3475 | { |
Evgeny Voevodin | 25983ca | 2012-11-21 11:43:04 +0400 | [diff] [blame] | 3476 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 3477 | } |