blob: 01ea5f160b6e29dda5c0ce7f1f3c26c99edd53e0 [file] [log] [blame]
Michael Rolnikf1c671f2020-01-26 19:51:34 +01001/*
2 * QEMU AVR CPU
3 *
4 * Copyright (c) 2016-2020 Michael Rolnik
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
Markus Armbruster52581c72022-05-06 15:49:08 +020021#ifndef TARGET_AVR_CPU_QOM_H
22#define TARGET_AVR_CPU_QOM_H
Michael Rolnikf1c671f2020-01-26 19:51:34 +010023
24#include "hw/core/cpu.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040025#include "qom/object.h"
Michael Rolnikf1c671f2020-01-26 19:51:34 +010026
27#define TYPE_AVR_CPU "avr-cpu"
28
Philippe Mathieu-Daudé9295b1a2022-02-14 17:08:40 +010029OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
Michael Rolnikf1c671f2020-01-26 19:51:34 +010030
31/**
32 * AVRCPUClass:
33 * @parent_realize: The parent class' realize handler.
Peter Maydell60578762022-11-24 11:50:06 +000034 * @parent_phases: The parent class' reset phase handlers.
Michael Rolnikf1c671f2020-01-26 19:51:34 +010035 *
36 * A AVR CPU model.
37 */
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040038struct AVRCPUClass {
Michael Rolnikf1c671f2020-01-26 19:51:34 +010039 /*< private >*/
40 CPUClass parent_class;
41 /*< public >*/
42 DeviceRealize parent_realize;
Peter Maydell60578762022-11-24 11:50:06 +000043 ResettablePhases parent_phases;
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040044};
Michael Rolnikf1c671f2020-01-26 19:51:34 +010045
Michael Rolnikf1c671f2020-01-26 19:51:34 +010046
Markus Armbruster52581c72022-05-06 15:49:08 +020047#endif /* TARGET_AVR_CPU_QOM_H */