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Bin Menga8fb0a52020-09-01 09:39:00 +08001/*
2 * Microchip PolarFire SoC MMUART emulation
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 or
12 * (at your option) version 3 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include "qemu/osdep.h"
24#include "qemu/log.h"
25#include "chardev/char.h"
Bin Menga8fb0a52020-09-01 09:39:00 +080026#include "hw/char/mchp_pfsoc_mmuart.h"
27
Philippe Mathieu-Daudé24ce7622021-09-25 15:34:06 +020028#define REGS_OFFSET 0x20
29
Bin Menga8fb0a52020-09-01 09:39:00 +080030static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
31{
32 MchpPfSoCMMUartState *s = opaque;
33
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020034 addr >>= 2;
35 if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
Bin Menga8fb0a52020-09-01 09:39:00 +080036 qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020037 __func__, addr << 2);
Bin Menga8fb0a52020-09-01 09:39:00 +080038 return 0;
39 }
40
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020041 return s->reg[addr];
Bin Menga8fb0a52020-09-01 09:39:00 +080042}
43
44static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
45 uint64_t value, unsigned size)
46{
47 MchpPfSoCMMUartState *s = opaque;
48 uint32_t val32 = (uint32_t)value;
49
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020050 addr >>= 2;
51 if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
Bin Menga8fb0a52020-09-01 09:39:00 +080052 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020053 " v=0x%x\n", __func__, addr << 2, val32);
Bin Menga8fb0a52020-09-01 09:39:00 +080054 return;
55 }
56
Philippe Mathieu-Daudé284a66a2021-09-25 15:34:05 +020057 s->reg[addr] = val32;
Bin Menga8fb0a52020-09-01 09:39:00 +080058}
59
60static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
61 .read = mchp_pfsoc_mmuart_read,
62 .write = mchp_pfsoc_mmuart_write,
63 .endianness = DEVICE_LITTLE_ENDIAN,
64 .impl = {
65 .min_access_size = 4,
66 .max_access_size = 4,
67 },
68};
69
70MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
71 hwaddr base, qemu_irq irq, Chardev *chr)
72{
73 MchpPfSoCMMUartState *s;
74
75 s = g_new0(MchpPfSoCMMUartState, 1);
76
Philippe Mathieu-Daudé24ce7622021-09-25 15:34:06 +020077 memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
78
Bin Menga8fb0a52020-09-01 09:39:00 +080079 memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
Philippe Mathieu-Daudé24ce7622021-09-25 15:34:06 +020080 "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
81 memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
Bin Menga8fb0a52020-09-01 09:39:00 +080082
83 s->base = base;
84 s->irq = irq;
85
Philippe Mathieu-Daudé24ce7622021-09-25 15:34:06 +020086 s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
Bin Menga8fb0a52020-09-01 09:39:00 +080087 DEVICE_LITTLE_ENDIAN);
88
Philippe Mathieu-Daudé24ce7622021-09-25 15:34:06 +020089 memory_region_add_subregion(sysmem, base, &s->container);
Bin Menga8fb0a52020-09-01 09:39:00 +080090
91 return s;
92}