Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU ARM CPU -- internal functions and types |
| 3 | * |
| 4 | * Copyright (c) 2014 Linaro Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | * |
| 20 | * This header defines functions, types, etc which need to be shared |
Thomas Huth | fcf5ef2 | 2016-10-11 08:56:52 +0200 | [diff] [blame] | 21 | * between different source files within target/arm/ but which are |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 22 | * private to it and not required by the rest of QEMU. |
| 23 | */ |
| 24 | |
| 25 | #ifndef TARGET_ARM_INTERNALS_H |
| 26 | #define TARGET_ARM_INTERNALS_H |
| 27 | |
Michael Davidsaver | abc24d8 | 2017-01-27 15:20:21 +0000 | [diff] [blame] | 28 | #include "hw/registerfields.h" |
Richard Henderson | 28f3250 | 2021-04-16 11:31:02 -0700 | [diff] [blame] | 29 | #include "tcg/tcg-gvec-desc.h" |
Richard Henderson | 1fe2785 | 2021-02-12 10:48:56 -0800 | [diff] [blame] | 30 | #include "syndrome.h" |
Michael Davidsaver | abc24d8 | 2017-01-27 15:20:21 +0000 | [diff] [blame] | 31 | |
Soren Brinkmann | 99a99c1 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 32 | /* register banks for CPU modes */ |
| 33 | #define BANK_USRSYS 0 |
| 34 | #define BANK_SVC 1 |
| 35 | #define BANK_ABT 2 |
| 36 | #define BANK_UND 3 |
| 37 | #define BANK_IRQ 4 |
| 38 | #define BANK_FIQ 5 |
| 39 | #define BANK_HYP 6 |
| 40 | #define BANK_MON 7 |
| 41 | |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 42 | static inline bool excp_is_internal(int excp) |
| 43 | { |
| 44 | /* Return true if this exception number represents a QEMU-internal |
| 45 | * exception that will not be passed to the guest. |
| 46 | */ |
| 47 | return excp == EXCP_INTERRUPT |
| 48 | || excp == EXCP_HLT |
| 49 | || excp == EXCP_DEBUG |
| 50 | || excp == EXCP_HALTED |
| 51 | || excp == EXCP_EXCEPTION_EXIT |
| 52 | || excp == EXCP_KERNEL_TRAP |
Emilio G. Cota | 05188cc | 2016-06-27 15:02:16 -0400 | [diff] [blame] | 53 | || excp == EXCP_SEMIHOST; |
Peter Maydell | d4a2dc6 | 2014-04-15 19:18:38 +0100 | [diff] [blame] | 54 | } |
| 55 | |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 56 | /* Scale factor for generic timers, ie number of ns per tick. |
| 57 | * This gives a 62.5MHz timer. |
| 58 | */ |
| 59 | #define GTIMER_SCALE 16 |
| 60 | |
Michael Davidsaver | abc24d8 | 2017-01-27 15:20:21 +0000 | [diff] [blame] | 61 | /* Bit definitions for the v7M CONTROL register */ |
| 62 | FIELD(V7M_CONTROL, NPRIV, 0, 1) |
| 63 | FIELD(V7M_CONTROL, SPSEL, 1, 1) |
| 64 | FIELD(V7M_CONTROL, FPCA, 2, 1) |
Peter Maydell | 3e3fa23 | 2017-10-09 14:48:33 +0100 | [diff] [blame] | 65 | FIELD(V7M_CONTROL, SFPA, 3, 1) |
Michael Davidsaver | abc24d8 | 2017-01-27 15:20:21 +0000 | [diff] [blame] | 66 | |
Peter Maydell | 4d1e7a4 | 2017-09-14 18:43:17 +0100 | [diff] [blame] | 67 | /* Bit definitions for v7M exception return payload */ |
| 68 | FIELD(V7M_EXCRET, ES, 0, 1) |
| 69 | FIELD(V7M_EXCRET, RES0, 1, 1) |
| 70 | FIELD(V7M_EXCRET, SPSEL, 2, 1) |
| 71 | FIELD(V7M_EXCRET, MODE, 3, 1) |
| 72 | FIELD(V7M_EXCRET, FTYPE, 4, 1) |
| 73 | FIELD(V7M_EXCRET, DCRS, 5, 1) |
| 74 | FIELD(V7M_EXCRET, S, 6, 1) |
| 75 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ |
| 76 | |
Peter Maydell | d02a869 | 2017-10-09 14:48:34 +0100 | [diff] [blame] | 77 | /* Minimum value which is a magic number for exception return */ |
| 78 | #define EXC_RETURN_MIN_MAGIC 0xff000000 |
| 79 | /* Minimum number which is a magic number for function or exception return |
| 80 | * when using v8M security extension |
| 81 | */ |
| 82 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe |
| 83 | |
Richard Henderson | 8b7a5bb | 2022-04-26 22:19:26 -0700 | [diff] [blame] | 84 | /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ |
| 85 | FIELD(DBGWCR, E, 0, 1) |
| 86 | FIELD(DBGWCR, PAC, 1, 2) |
| 87 | FIELD(DBGWCR, LSC, 3, 2) |
| 88 | FIELD(DBGWCR, BAS, 5, 8) |
| 89 | FIELD(DBGWCR, HMC, 13, 1) |
| 90 | FIELD(DBGWCR, SSC, 14, 2) |
| 91 | FIELD(DBGWCR, LBN, 16, 4) |
| 92 | FIELD(DBGWCR, WT, 20, 1) |
| 93 | FIELD(DBGWCR, MASK, 24, 5) |
| 94 | FIELD(DBGWCR, SSCE, 29, 1) |
| 95 | |
Peter Maydell | 35337cc | 2017-10-06 16:46:49 +0100 | [diff] [blame] | 96 | /* We use a few fake FSR values for internal purposes in M profile. |
| 97 | * M profile cores don't have A/R format FSRs, but currently our |
| 98 | * get_phys_addr() code assumes A/R profile and reports failures via |
| 99 | * an A/R format FSR value. We then translate that into the proper |
| 100 | * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). |
| 101 | * Mostly the FSR values we use for this are those defined for v7PMSA, |
| 102 | * since we share some of that codepath. A few kinds of fault are |
| 103 | * only for M profile and have no A/R equivalent, though, so we have |
| 104 | * to pick a value from the reserved range (which we never otherwise |
| 105 | * generate) to use for these. |
| 106 | * These values will never be visible to the guest. |
| 107 | */ |
| 108 | #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ |
| 109 | #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ |
| 110 | |
Peter Maydell | 597610e | 2018-10-08 14:55:04 +0100 | [diff] [blame] | 111 | /** |
| 112 | * raise_exception: Raise the specified exception. |
| 113 | * Raise a guest exception with the specified value, syndrome register |
| 114 | * and target exception level. This should be called from helper functions, |
| 115 | * and never returns because we will longjump back up to the CPU main loop. |
| 116 | */ |
Marc-André Lureau | 8905770 | 2022-04-20 17:26:02 +0400 | [diff] [blame] | 117 | G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, |
| 118 | uint32_t syndrome, uint32_t target_el); |
Peter Maydell | 597610e | 2018-10-08 14:55:04 +0100 | [diff] [blame] | 119 | |
Edgar E. Iglesias | 2a923c4 | 2014-05-27 17:09:52 +0100 | [diff] [blame] | 120 | /* |
Richard Henderson | 7469f6c | 2019-01-21 10:23:11 +0000 | [diff] [blame] | 121 | * Similarly, but also use unwinding to restore cpu state. |
| 122 | */ |
Marc-André Lureau | 8905770 | 2022-04-20 17:26:02 +0400 | [diff] [blame] | 123 | G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, |
Richard Henderson | 7469f6c | 2019-01-21 10:23:11 +0000 | [diff] [blame] | 124 | uint32_t syndrome, uint32_t target_el, |
| 125 | uintptr_t ra); |
| 126 | |
| 127 | /* |
Edgar E. Iglesias | 2a923c4 | 2014-05-27 17:09:52 +0100 | [diff] [blame] | 128 | * For AArch64, map a given EL to an index in the banked_spsr array. |
Peter Maydell | 7847f9e | 2015-04-01 17:57:29 +0100 | [diff] [blame] | 129 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
| 130 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally |
| 131 | * mandated mapping between each other. |
Edgar E. Iglesias | 2a923c4 | 2014-05-27 17:09:52 +0100 | [diff] [blame] | 132 | */ |
| 133 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) |
| 134 | { |
| 135 | static const unsigned int map[4] = { |
Soren Brinkmann | 99a99c1 | 2015-11-03 13:49:41 +0000 | [diff] [blame] | 136 | [1] = BANK_SVC, /* EL1. */ |
| 137 | [2] = BANK_HYP, /* EL2. */ |
| 138 | [3] = BANK_MON, /* EL3. */ |
Edgar E. Iglesias | 2a923c4 | 2014-05-27 17:09:52 +0100 | [diff] [blame] | 139 | }; |
| 140 | assert(el >= 1 && el <= 3); |
| 141 | return map[el]; |
| 142 | } |
| 143 | |
Peter Maydell | c766568 | 2016-02-18 14:16:16 +0000 | [diff] [blame] | 144 | /* Map CPU modes onto saved register banks. */ |
| 145 | static inline int bank_number(int mode) |
| 146 | { |
| 147 | switch (mode) { |
| 148 | case ARM_CPU_MODE_USR: |
| 149 | case ARM_CPU_MODE_SYS: |
| 150 | return BANK_USRSYS; |
| 151 | case ARM_CPU_MODE_SVC: |
| 152 | return BANK_SVC; |
| 153 | case ARM_CPU_MODE_ABT: |
| 154 | return BANK_ABT; |
| 155 | case ARM_CPU_MODE_UND: |
| 156 | return BANK_UND; |
| 157 | case ARM_CPU_MODE_IRQ: |
| 158 | return BANK_IRQ; |
| 159 | case ARM_CPU_MODE_FIQ: |
| 160 | return BANK_FIQ; |
| 161 | case ARM_CPU_MODE_HYP: |
| 162 | return BANK_HYP; |
| 163 | case ARM_CPU_MODE_MON: |
| 164 | return BANK_MON; |
| 165 | } |
| 166 | g_assert_not_reached(); |
| 167 | } |
| 168 | |
Peter Maydell | 593cfa2 | 2018-11-13 10:47:59 +0000 | [diff] [blame] | 169 | /** |
| 170 | * r14_bank_number: Map CPU mode onto register bank for r14 |
| 171 | * |
| 172 | * Given an AArch32 CPU mode, return the index into the saved register |
| 173 | * banks to use for the R14 (LR) in that mode. This is the same as |
| 174 | * bank_number(), except for the special case of Hyp mode, where |
| 175 | * R14 is shared with USR and SYS, unlike its R13 and SPSR. |
| 176 | * This should be used as the index into env->banked_r14[], and |
| 177 | * bank_number() used for the index into env->banked_r13[] and |
| 178 | * env->banked_spsr[]. |
| 179 | */ |
| 180 | static inline int r14_bank_number(int mode) |
| 181 | { |
| 182 | return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); |
| 183 | } |
| 184 | |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 185 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
| 186 | void arm_translate_init(void); |
| 187 | |
Claudio Fontana | 7827168 | 2021-02-04 17:39:23 +0100 | [diff] [blame] | 188 | #ifdef CONFIG_TCG |
Richard Henderson | 8349d2a | 2021-02-13 13:03:12 +0000 | [diff] [blame] | 189 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); |
Claudio Fontana | 7827168 | 2021-02-04 17:39:23 +0100 | [diff] [blame] | 190 | #endif /* CONFIG_TCG */ |
| 191 | |
Richard Henderson | ce44058 | 2021-07-23 10:33:43 -1000 | [diff] [blame] | 192 | /** |
| 193 | * aarch64_sve_zcr_get_valid_len: |
| 194 | * @cpu: cpu context |
| 195 | * @start_len: maximum len to consider |
| 196 | * |
| 197 | * Return the maximum supported sve vector length <= @start_len. |
| 198 | * Note that both @start_len and the return value are in units |
| 199 | * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. |
| 200 | */ |
| 201 | uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); |
Claudio Fontana | 7827168 | 2021-02-04 17:39:23 +0100 | [diff] [blame] | 202 | |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 203 | enum arm_fprounding { |
| 204 | FPROUNDING_TIEEVEN, |
| 205 | FPROUNDING_POSINF, |
| 206 | FPROUNDING_NEGINF, |
| 207 | FPROUNDING_ZERO, |
| 208 | FPROUNDING_TIEAWAY, |
| 209 | FPROUNDING_ODD |
| 210 | }; |
| 211 | |
| 212 | int arm_rmode_to_sf(int rmode); |
| 213 | |
Edgar E. Iglesias | 9208b96 | 2014-08-04 14:41:54 +0100 | [diff] [blame] | 214 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
| 215 | { |
| 216 | if (env->pstate & PSTATE_SP) { |
| 217 | env->sp_el[el] = env->xregs[31]; |
| 218 | } else { |
| 219 | env->sp_el[0] = env->xregs[31]; |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | static inline void aarch64_restore_sp(CPUARMState *env, int el) |
| 224 | { |
| 225 | if (env->pstate & PSTATE_SP) { |
| 226 | env->xregs[31] = env->sp_el[el]; |
| 227 | } else { |
| 228 | env->xregs[31] = env->sp_el[0]; |
| 229 | } |
| 230 | } |
| 231 | |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 232 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
| 233 | { |
Greg Bellows | dcbff19 | 2014-10-24 12:19:14 +0100 | [diff] [blame] | 234 | unsigned int cur_el = arm_current_el(env); |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 235 | /* Update PSTATE SPSel bit; this requires us to update the |
| 236 | * working stack pointer in xregs[31]. |
| 237 | */ |
| 238 | if (!((imm ^ env->pstate) & PSTATE_SP)) { |
| 239 | return; |
| 240 | } |
Edgar E. Iglesias | 9208b96 | 2014-08-04 14:41:54 +0100 | [diff] [blame] | 241 | aarch64_save_sp(env, cur_el); |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 242 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
| 243 | |
Edgar E. Iglesias | 61d4b21 | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 244 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
| 245 | * at translation time. |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 246 | */ |
Edgar E. Iglesias | 61d4b21 | 2014-05-27 17:09:54 +0100 | [diff] [blame] | 247 | assert(cur_el >= 1 && cur_el <= 3); |
Edgar E. Iglesias | 9208b96 | 2014-08-04 14:41:54 +0100 | [diff] [blame] | 248 | aarch64_restore_sp(env, cur_el); |
Peter Maydell | f502cfc | 2014-04-15 19:18:43 +0100 | [diff] [blame] | 249 | } |
| 250 | |
Edgar E. Iglesias | 1853d5a | 2015-10-26 14:02:00 +0100 | [diff] [blame] | 251 | /* |
| 252 | * arm_pamax |
| 253 | * @cpu: ARMCPU |
| 254 | * |
| 255 | * Returns the implementation defined bit-width of physical addresses. |
| 256 | * The ARMv8 reference manuals refer to this as PAMax(). |
| 257 | */ |
Richard Henderson | 71a7725 | 2022-03-01 11:59:44 -1000 | [diff] [blame] | 258 | unsigned int arm_pamax(ARMCPU *cpu); |
Edgar E. Iglesias | 1853d5a | 2015-10-26 14:02:00 +0100 | [diff] [blame] | 259 | |
Peter Maydell | 73c5211 | 2014-09-12 14:06:49 +0100 | [diff] [blame] | 260 | /* Return true if extended addresses are enabled. |
| 261 | * This is always the case if our translation regime is 64 bit, |
| 262 | * but depends on TTBCR.EAE for 32 bit. |
| 263 | */ |
| 264 | static inline bool extended_addresses_enabled(CPUARMState *env) |
| 265 | { |
Fabian Aggeler | 11f136e | 2014-12-11 12:07:51 +0000 | [diff] [blame] | 266 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
| 267 | return arm_el_is_aa64(env, 1) || |
| 268 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); |
Peter Maydell | 73c5211 | 2014-09-12 14:06:49 +0100 | [diff] [blame] | 269 | } |
| 270 | |
Peter Maydell | 9ee98ce | 2014-09-12 14:06:49 +0100 | [diff] [blame] | 271 | /* Update a QEMU watchpoint based on the information the guest has set in the |
| 272 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. |
| 273 | */ |
| 274 | void hw_watchpoint_update(ARMCPU *cpu, int n); |
| 275 | /* Update the QEMU watchpoints for every guest watchpoint. This does a |
| 276 | * complete delete-and-reinstate of the QEMU watchpoint list and so is |
| 277 | * suitable for use after migration or on reset. |
| 278 | */ |
| 279 | void hw_watchpoint_update_all(ARMCPU *cpu); |
Peter Maydell | 46747d1 | 2014-09-29 18:48:46 +0100 | [diff] [blame] | 280 | /* Update a QEMU breakpoint based on the information the guest has set in the |
| 281 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. |
| 282 | */ |
| 283 | void hw_breakpoint_update(ARMCPU *cpu, int n); |
| 284 | /* Update the QEMU breakpoints for every guest breakpoint. This does a |
| 285 | * complete delete-and-reinstate of the QEMU breakpoint list and so is |
| 286 | * suitable for use after migration or on reset. |
| 287 | */ |
| 288 | void hw_breakpoint_update_all(ARMCPU *cpu); |
Peter Maydell | 9ee98ce | 2014-09-12 14:06:49 +0100 | [diff] [blame] | 289 | |
Richard Henderson | b00d86b | 2021-07-19 08:19:26 -1000 | [diff] [blame] | 290 | /* Callback function for checking if a breakpoint should trigger. */ |
| 291 | bool arm_debug_check_breakpoint(CPUState *cs); |
| 292 | |
Sergey Fedorov | 3826121 | 2016-02-11 11:17:32 +0000 | [diff] [blame] | 293 | /* Callback function for checking if a watchpoint should trigger. */ |
| 294 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); |
| 295 | |
Julian Brown | 4061200 | 2017-02-07 18:29:59 +0000 | [diff] [blame] | 296 | /* Adjust addresses (in BE32 mode) before testing against watchpoint |
| 297 | * addresses. |
| 298 | */ |
| 299 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); |
| 300 | |
Peter Maydell | 3ff6fc9 | 2014-09-12 14:06:49 +0100 | [diff] [blame] | 301 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
| 302 | void arm_debug_excp_handler(CPUState *cs); |
| 303 | |
Philippe Mathieu-Daudé | 21fbea8 | 2019-07-01 17:26:22 +0100 | [diff] [blame] | 304 | #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) |
Rob Herring | 9812860 | 2014-10-24 12:19:13 +0100 | [diff] [blame] | 305 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) |
| 306 | { |
| 307 | return false; |
| 308 | } |
Philippe Mathieu-Daudé | 21fbea8 | 2019-07-01 17:26:22 +0100 | [diff] [blame] | 309 | static inline void arm_handle_psci_call(ARMCPU *cpu) |
| 310 | { |
| 311 | g_assert_not_reached(); |
| 312 | } |
Rob Herring | 9812860 | 2014-10-24 12:19:13 +0100 | [diff] [blame] | 313 | #else |
| 314 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ |
| 315 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); |
| 316 | /* Actually handle a PSCI call */ |
| 317 | void arm_handle_psci_call(ARMCPU *cpu); |
| 318 | #endif |
| 319 | |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 320 | /** |
Peter Maydell | dc3c4c1 | 2017-09-14 18:43:16 +0100 | [diff] [blame] | 321 | * arm_clear_exclusive: clear the exclusive monitor |
| 322 | * @env: CPU env |
| 323 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. |
| 324 | */ |
| 325 | static inline void arm_clear_exclusive(CPUARMState *env) |
| 326 | { |
| 327 | env->exclusive_addr = -1; |
| 328 | } |
| 329 | |
| 330 | /** |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 331 | * ARMFaultType: type of an ARM MMU fault |
| 332 | * This corresponds to the v8A pseudocode's Fault enumeration, |
| 333 | * with extensions for QEMU internal conditions. |
| 334 | */ |
| 335 | typedef enum ARMFaultType { |
| 336 | ARMFault_None, |
| 337 | ARMFault_AccessFlag, |
| 338 | ARMFault_Alignment, |
| 339 | ARMFault_Background, |
| 340 | ARMFault_Domain, |
| 341 | ARMFault_Permission, |
| 342 | ARMFault_Translation, |
| 343 | ARMFault_AddressSize, |
| 344 | ARMFault_SyncExternal, |
| 345 | ARMFault_SyncExternalOnWalk, |
| 346 | ARMFault_SyncParity, |
| 347 | ARMFault_SyncParityOnWalk, |
| 348 | ARMFault_AsyncParity, |
| 349 | ARMFault_AsyncExternal, |
| 350 | ARMFault_Debug, |
| 351 | ARMFault_TLBConflict, |
| 352 | ARMFault_Lockdown, |
| 353 | ARMFault_Exclusive, |
| 354 | ARMFault_ICacheMaint, |
| 355 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ |
| 356 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ |
| 357 | } ARMFaultType; |
| 358 | |
| 359 | /** |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 360 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 361 | * @type: Type of fault |
| 362 | * @level: Table walk level (for translation, access flag and permission faults) |
| 363 | * @domain: Domain of the fault address (for non-LPAE CPUs only) |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 364 | * @s2addr: Address that caused a fault at stage 2 |
| 365 | * @stage2: True if we faulted at stage 2 |
| 366 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk |
RĂ©mi Denis-Courmont | 9861248 | 2021-01-12 12:45:07 +0200 | [diff] [blame] | 367 | * @s1ns: True if we faulted on a non-secure IPA while in secure state |
Peter Maydell | c528af7 | 2017-09-04 15:21:55 +0100 | [diff] [blame] | 368 | * @ea: True if we should set the EA (external abort type) bit in syndrome |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 369 | */ |
| 370 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; |
| 371 | struct ARMMMUFaultInfo { |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 372 | ARMFaultType type; |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 373 | target_ulong s2addr; |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 374 | int level; |
| 375 | int domain; |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 376 | bool stage2; |
| 377 | bool s1ptw; |
RĂ©mi Denis-Courmont | 9861248 | 2021-01-12 12:45:07 +0200 | [diff] [blame] | 378 | bool s1ns; |
Peter Maydell | c528af7 | 2017-09-04 15:21:55 +0100 | [diff] [blame] | 379 | bool ea; |
Edgar E. Iglesias | e14b5a2 | 2015-10-26 14:02:03 +0100 | [diff] [blame] | 380 | }; |
| 381 | |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 382 | /** |
| 383 | * arm_fi_to_sfsc: Convert fault info struct to short-format FSC |
| 384 | * Compare pseudocode EncodeSDFSC(), though unlike that function |
| 385 | * we set up a whole FSR-format code including domain field and |
| 386 | * putting the high bit of the FSC into bit 10. |
| 387 | */ |
| 388 | static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) |
| 389 | { |
| 390 | uint32_t fsc; |
| 391 | |
| 392 | switch (fi->type) { |
| 393 | case ARMFault_None: |
| 394 | return 0; |
| 395 | case ARMFault_AccessFlag: |
| 396 | fsc = fi->level == 1 ? 0x3 : 0x6; |
| 397 | break; |
| 398 | case ARMFault_Alignment: |
| 399 | fsc = 0x1; |
| 400 | break; |
| 401 | case ARMFault_Permission: |
| 402 | fsc = fi->level == 1 ? 0xd : 0xf; |
| 403 | break; |
| 404 | case ARMFault_Domain: |
| 405 | fsc = fi->level == 1 ? 0x9 : 0xb; |
| 406 | break; |
| 407 | case ARMFault_Translation: |
| 408 | fsc = fi->level == 1 ? 0x5 : 0x7; |
| 409 | break; |
| 410 | case ARMFault_SyncExternal: |
| 411 | fsc = 0x8 | (fi->ea << 12); |
| 412 | break; |
| 413 | case ARMFault_SyncExternalOnWalk: |
| 414 | fsc = fi->level == 1 ? 0xc : 0xe; |
| 415 | fsc |= (fi->ea << 12); |
| 416 | break; |
| 417 | case ARMFault_SyncParity: |
| 418 | fsc = 0x409; |
| 419 | break; |
| 420 | case ARMFault_SyncParityOnWalk: |
| 421 | fsc = fi->level == 1 ? 0x40c : 0x40e; |
| 422 | break; |
| 423 | case ARMFault_AsyncParity: |
| 424 | fsc = 0x408; |
| 425 | break; |
| 426 | case ARMFault_AsyncExternal: |
| 427 | fsc = 0x406 | (fi->ea << 12); |
| 428 | break; |
| 429 | case ARMFault_Debug: |
| 430 | fsc = 0x2; |
| 431 | break; |
| 432 | case ARMFault_TLBConflict: |
| 433 | fsc = 0x400; |
| 434 | break; |
| 435 | case ARMFault_Lockdown: |
| 436 | fsc = 0x404; |
| 437 | break; |
| 438 | case ARMFault_Exclusive: |
| 439 | fsc = 0x405; |
| 440 | break; |
| 441 | case ARMFault_ICacheMaint: |
| 442 | fsc = 0x4; |
| 443 | break; |
| 444 | case ARMFault_Background: |
| 445 | fsc = 0x0; |
| 446 | break; |
| 447 | case ARMFault_QEMU_NSCExec: |
| 448 | fsc = M_FAKE_FSR_NSC_EXEC; |
| 449 | break; |
| 450 | case ARMFault_QEMU_SFault: |
| 451 | fsc = M_FAKE_FSR_SFAULT; |
| 452 | break; |
| 453 | default: |
| 454 | /* Other faults can't occur in a context that requires a |
| 455 | * short-format status code. |
| 456 | */ |
| 457 | g_assert_not_reached(); |
| 458 | } |
| 459 | |
| 460 | fsc |= (fi->domain << 4); |
| 461 | return fsc; |
| 462 | } |
| 463 | |
| 464 | /** |
| 465 | * arm_fi_to_lfsc: Convert fault info struct to long-format FSC |
| 466 | * Compare pseudocode EncodeLDFSC(), though unlike that function |
| 467 | * we fill in also the LPAE bit 9 of a DFSR format. |
| 468 | */ |
| 469 | static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) |
| 470 | { |
| 471 | uint32_t fsc; |
| 472 | |
| 473 | switch (fi->type) { |
| 474 | case ARMFault_None: |
| 475 | return 0; |
| 476 | case ARMFault_AddressSize: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 477 | assert(fi->level >= -1 && fi->level <= 3); |
| 478 | if (fi->level < 0) { |
| 479 | fsc = 0b101001; |
| 480 | } else { |
| 481 | fsc = fi->level; |
| 482 | } |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 483 | break; |
| 484 | case ARMFault_AccessFlag: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 485 | assert(fi->level >= 0 && fi->level <= 3); |
| 486 | fsc = 0b001000 | fi->level; |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 487 | break; |
| 488 | case ARMFault_Permission: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 489 | assert(fi->level >= 0 && fi->level <= 3); |
| 490 | fsc = 0b001100 | fi->level; |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 491 | break; |
| 492 | case ARMFault_Translation: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 493 | assert(fi->level >= -1 && fi->level <= 3); |
| 494 | if (fi->level < 0) { |
| 495 | fsc = 0b101011; |
| 496 | } else { |
| 497 | fsc = 0b000100 | fi->level; |
| 498 | } |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 499 | break; |
| 500 | case ARMFault_SyncExternal: |
| 501 | fsc = 0x10 | (fi->ea << 12); |
| 502 | break; |
| 503 | case ARMFault_SyncExternalOnWalk: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 504 | assert(fi->level >= -1 && fi->level <= 3); |
| 505 | if (fi->level < 0) { |
| 506 | fsc = 0b010011; |
| 507 | } else { |
| 508 | fsc = 0b010100 | fi->level; |
| 509 | } |
| 510 | fsc |= fi->ea << 12; |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 511 | break; |
| 512 | case ARMFault_SyncParity: |
| 513 | fsc = 0x18; |
| 514 | break; |
| 515 | case ARMFault_SyncParityOnWalk: |
Richard Henderson | 13e481c | 2022-03-01 11:59:51 -1000 | [diff] [blame] | 516 | assert(fi->level >= -1 && fi->level <= 3); |
| 517 | if (fi->level < 0) { |
| 518 | fsc = 0b011011; |
| 519 | } else { |
| 520 | fsc = 0b011100 | fi->level; |
| 521 | } |
Peter Maydell | 1fa498f | 2017-12-13 17:59:24 +0000 | [diff] [blame] | 522 | break; |
| 523 | case ARMFault_AsyncParity: |
| 524 | fsc = 0x19; |
| 525 | break; |
| 526 | case ARMFault_AsyncExternal: |
| 527 | fsc = 0x11 | (fi->ea << 12); |
| 528 | break; |
| 529 | case ARMFault_Alignment: |
| 530 | fsc = 0x21; |
| 531 | break; |
| 532 | case ARMFault_Debug: |
| 533 | fsc = 0x22; |
| 534 | break; |
| 535 | case ARMFault_TLBConflict: |
| 536 | fsc = 0x30; |
| 537 | break; |
| 538 | case ARMFault_Lockdown: |
| 539 | fsc = 0x34; |
| 540 | break; |
| 541 | case ARMFault_Exclusive: |
| 542 | fsc = 0x35; |
| 543 | break; |
| 544 | default: |
| 545 | /* Other faults can't occur in a context that requires a |
| 546 | * long-format status code. |
| 547 | */ |
| 548 | g_assert_not_reached(); |
| 549 | } |
| 550 | |
| 551 | fsc |= 1 << 9; |
| 552 | return fsc; |
| 553 | } |
| 554 | |
Peter Maydell | 3b39d73 | 2018-01-16 13:28:11 +0000 | [diff] [blame] | 555 | static inline bool arm_extabort_type(MemTxResult result) |
| 556 | { |
| 557 | /* The EA bit in syndromes and fault status registers is an |
| 558 | * IMPDEF classification of external aborts. ARM implementations |
| 559 | * usually use this to indicate AXI bus Decode error (0) or |
| 560 | * Slave error (1); in QEMU we follow that. |
| 561 | */ |
| 562 | return result != MEMTX_DECODE_ERROR; |
| 563 | } |
| 564 | |
Richard Henderson | 9b12b6b | 2021-09-17 18:23:07 -0700 | [diff] [blame] | 565 | #ifdef CONFIG_USER_ONLY |
| 566 | void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, |
| 567 | MMUAccessType access_type, |
| 568 | bool maperr, uintptr_t ra); |
Richard Henderson | 39a099c | 2021-07-23 12:22:54 -1000 | [diff] [blame] | 569 | void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, |
| 570 | MMUAccessType access_type, uintptr_t ra); |
Richard Henderson | 9b12b6b | 2021-09-17 18:23:07 -0700 | [diff] [blame] | 571 | #else |
Richard Henderson | 7350d55 | 2019-04-02 15:12:58 +0700 | [diff] [blame] | 572 | bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 573 | MMUAccessType access_type, int mmu_idx, |
| 574 | bool probe, uintptr_t retaddr); |
Richard Henderson | 9b12b6b | 2021-09-17 18:23:07 -0700 | [diff] [blame] | 575 | #endif |
Richard Henderson | 7350d55 | 2019-04-02 15:12:58 +0700 | [diff] [blame] | 576 | |
Richard Henderson | b9f6033 | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 577 | static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) |
| 578 | { |
| 579 | return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; |
| 580 | } |
| 581 | |
| 582 | static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) |
| 583 | { |
| 584 | if (arm_feature(env, ARM_FEATURE_M)) { |
| 585 | return mmu_idx | ARM_MMU_IDX_M; |
| 586 | } else { |
| 587 | return mmu_idx | ARM_MMU_IDX_A; |
| 588 | } |
| 589 | } |
| 590 | |
Richard Henderson | 20dc67c | 2020-03-05 16:09:20 +0000 | [diff] [blame] | 591 | static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
| 592 | { |
| 593 | /* AArch64 is always a-profile. */ |
| 594 | return mmu_idx | ARM_MMU_IDX_A; |
| 595 | } |
| 596 | |
Richard Henderson | b9f6033 | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 597 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
| 598 | |
| 599 | /* |
| 600 | * Return the MMU index for a v7M CPU with all relevant information |
| 601 | * manually specified. |
| 602 | */ |
| 603 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
| 604 | bool secstate, bool priv, bool negpri); |
| 605 | |
| 606 | /* |
| 607 | * Return the MMU index for a v7M CPU in the specified security and |
| 608 | * privilege state. |
| 609 | */ |
| 610 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
| 611 | bool secstate, bool priv); |
| 612 | |
| 613 | /* Return the MMU index for a v7M CPU in the specified security state */ |
| 614 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); |
| 615 | |
Alvise Rigo | deb2db9 | 2016-01-15 11:37:42 +0100 | [diff] [blame] | 616 | /* Return true if the stage 1 translation regime is using LPAE format page |
| 617 | * tables */ |
| 618 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); |
Andrew Baumann | 3090147 | 2015-12-17 13:37:13 +0000 | [diff] [blame] | 619 | |
| 620 | /* Raise a data fault alignment exception for the specified virtual address */ |
Marc-André Lureau | 8905770 | 2022-04-20 17:26:02 +0400 | [diff] [blame] | 621 | G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
| 622 | MMUAccessType access_type, |
| 623 | int mmu_idx, uintptr_t retaddr); |
Andrew Baumann | 3090147 | 2015-12-17 13:37:13 +0000 | [diff] [blame] | 624 | |
Peter Maydell | c79c0a3 | 2017-09-07 13:54:55 +0100 | [diff] [blame] | 625 | /* arm_cpu_do_transaction_failed: handle a memory system error response |
| 626 | * (eg "no device/memory present at address") by raising an external abort |
| 627 | * exception |
| 628 | */ |
| 629 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 630 | vaddr addr, unsigned size, |
| 631 | MMUAccessType access_type, |
| 632 | int mmu_idx, MemTxAttrs attrs, |
| 633 | MemTxResult response, uintptr_t retaddr); |
| 634 | |
Aaron Lindsay | 0826748 | 2018-04-26 11:04:39 +0100 | [diff] [blame] | 635 | /* Call any registered EL change hooks */ |
Aaron Lindsay | b5c53d1 | 2018-04-26 11:04:39 +0100 | [diff] [blame] | 636 | static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) |
| 637 | { |
| 638 | ARMELChangeHook *hook, *next; |
| 639 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
| 640 | hook->hook(cpu, hook->opaque); |
| 641 | } |
| 642 | } |
Peter Maydell | bd7d00f | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 643 | static inline void arm_call_el_change_hook(ARMCPU *cpu) |
| 644 | { |
Aaron Lindsay | 0826748 | 2018-04-26 11:04:39 +0100 | [diff] [blame] | 645 | ARMELChangeHook *hook, *next; |
| 646 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
| 647 | hook->hook(cpu, hook->opaque); |
Peter Maydell | bd7d00f | 2016-06-17 15:23:46 +0100 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | |
Richard Henderson | 339370b | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 651 | /* Return true if this address translation regime has two ranges. */ |
| 652 | static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) |
| 653 | { |
| 654 | switch (mmu_idx) { |
| 655 | case ARMMMUIdx_Stage1_E0: |
| 656 | case ARMMMUIdx_Stage1_E1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 657 | case ARMMMUIdx_Stage1_E1_PAN: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 658 | case ARMMMUIdx_Stage1_SE0: |
| 659 | case ARMMMUIdx_Stage1_SE1: |
| 660 | case ARMMMUIdx_Stage1_SE1_PAN: |
Richard Henderson | 339370b | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 661 | case ARMMMUIdx_E10_0: |
| 662 | case ARMMMUIdx_E10_1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 663 | case ARMMMUIdx_E10_1_PAN: |
Richard Henderson | 339370b | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 664 | case ARMMMUIdx_E20_0: |
| 665 | case ARMMMUIdx_E20_2: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 666 | case ARMMMUIdx_E20_2_PAN: |
Richard Henderson | 339370b | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 667 | case ARMMMUIdx_SE10_0: |
| 668 | case ARMMMUIdx_SE10_1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 669 | case ARMMMUIdx_SE10_1_PAN: |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 670 | case ARMMMUIdx_SE20_0: |
| 671 | case ARMMMUIdx_SE20_2: |
| 672 | case ARMMMUIdx_SE20_2_PAN: |
Richard Henderson | 339370b | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 673 | return true; |
| 674 | default: |
| 675 | return false; |
| 676 | } |
| 677 | } |
| 678 | |
Peter Maydell | 61fcd69 | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 679 | /* Return true if this address translation regime is secure */ |
| 680 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 681 | { |
| 682 | switch (mmu_idx) { |
Richard Henderson | 01b98b6 | 2020-02-07 14:04:22 +0000 | [diff] [blame] | 683 | case ARMMMUIdx_E10_0: |
| 684 | case ARMMMUIdx_E10_1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 685 | case ARMMMUIdx_E10_1_PAN: |
Richard Henderson | b9f6033 | 2020-02-07 14:04:24 +0000 | [diff] [blame] | 686 | case ARMMMUIdx_E20_0: |
| 687 | case ARMMMUIdx_E20_2: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 688 | case ARMMMUIdx_E20_2_PAN: |
Richard Henderson | 2859d7b | 2020-02-07 14:04:22 +0000 | [diff] [blame] | 689 | case ARMMMUIdx_Stage1_E0: |
| 690 | case ARMMMUIdx_Stage1_E1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 691 | case ARMMMUIdx_Stage1_E1_PAN: |
Richard Henderson | e013b74 | 2020-02-07 14:04:23 +0000 | [diff] [blame] | 692 | case ARMMMUIdx_E2: |
Richard Henderson | 97fa935 | 2020-02-07 14:04:22 +0000 | [diff] [blame] | 693 | case ARMMMUIdx_Stage2: |
Peter Maydell | 6259371 | 2017-12-13 17:59:23 +0000 | [diff] [blame] | 694 | case ARMMMUIdx_MPrivNegPri: |
| 695 | case ARMMMUIdx_MUserNegPri: |
Peter Maydell | 61fcd69 | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 696 | case ARMMMUIdx_MPriv: |
Peter Maydell | 61fcd69 | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 697 | case ARMMMUIdx_MUser: |
| 698 | return false; |
Richard Henderson | 127b2b0 | 2020-02-07 14:04:23 +0000 | [diff] [blame] | 699 | case ARMMMUIdx_SE3: |
Richard Henderson | fba37ae | 2020-02-07 14:04:23 +0000 | [diff] [blame] | 700 | case ARMMMUIdx_SE10_0: |
| 701 | case ARMMMUIdx_SE10_1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 702 | case ARMMMUIdx_SE10_1_PAN: |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 703 | case ARMMMUIdx_SE20_0: |
| 704 | case ARMMMUIdx_SE20_2: |
| 705 | case ARMMMUIdx_SE20_2_PAN: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 706 | case ARMMMUIdx_Stage1_SE0: |
| 707 | case ARMMMUIdx_Stage1_SE1: |
| 708 | case ARMMMUIdx_Stage1_SE1_PAN: |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 709 | case ARMMMUIdx_SE2: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 710 | case ARMMMUIdx_Stage2_S: |
Peter Maydell | 6259371 | 2017-12-13 17:59:23 +0000 | [diff] [blame] | 711 | case ARMMMUIdx_MSPrivNegPri: |
| 712 | case ARMMMUIdx_MSUserNegPri: |
Peter Maydell | 61fcd69 | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 713 | case ARMMMUIdx_MSPriv: |
Peter Maydell | 61fcd69 | 2017-09-07 13:54:54 +0100 | [diff] [blame] | 714 | case ARMMMUIdx_MSUser: |
| 715 | return true; |
| 716 | default: |
| 717 | g_assert_not_reached(); |
| 718 | } |
| 719 | } |
| 720 | |
Richard Henderson | 81636b7 | 2020-02-08 12:58:09 +0000 | [diff] [blame] | 721 | static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 722 | { |
| 723 | switch (mmu_idx) { |
| 724 | case ARMMMUIdx_Stage1_E1_PAN: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 725 | case ARMMMUIdx_Stage1_SE1_PAN: |
Richard Henderson | 81636b7 | 2020-02-08 12:58:09 +0000 | [diff] [blame] | 726 | case ARMMMUIdx_E10_1_PAN: |
| 727 | case ARMMMUIdx_E20_2_PAN: |
| 728 | case ARMMMUIdx_SE10_1_PAN: |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 729 | case ARMMMUIdx_SE20_2_PAN: |
Richard Henderson | 81636b7 | 2020-02-08 12:58:09 +0000 | [diff] [blame] | 730 | return true; |
| 731 | default: |
| 732 | return false; |
| 733 | } |
| 734 | } |
| 735 | |
Richard Henderson | 9c7ab8f | 2020-06-25 20:31:19 -0700 | [diff] [blame] | 736 | /* Return the exception level which controls this address translation regime */ |
| 737 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 738 | { |
| 739 | switch (mmu_idx) { |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 740 | case ARMMMUIdx_SE20_0: |
| 741 | case ARMMMUIdx_SE20_2: |
| 742 | case ARMMMUIdx_SE20_2_PAN: |
Richard Henderson | 9c7ab8f | 2020-06-25 20:31:19 -0700 | [diff] [blame] | 743 | case ARMMMUIdx_E20_0: |
| 744 | case ARMMMUIdx_E20_2: |
| 745 | case ARMMMUIdx_E20_2_PAN: |
| 746 | case ARMMMUIdx_Stage2: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 747 | case ARMMMUIdx_Stage2_S: |
RĂ©mi Denis-Courmont | b6ad606 | 2021-01-12 12:45:00 +0200 | [diff] [blame] | 748 | case ARMMMUIdx_SE2: |
Richard Henderson | 9c7ab8f | 2020-06-25 20:31:19 -0700 | [diff] [blame] | 749 | case ARMMMUIdx_E2: |
| 750 | return 2; |
| 751 | case ARMMMUIdx_SE3: |
| 752 | return 3; |
| 753 | case ARMMMUIdx_SE10_0: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 754 | case ARMMMUIdx_Stage1_SE0: |
Richard Henderson | 9c7ab8f | 2020-06-25 20:31:19 -0700 | [diff] [blame] | 755 | return arm_el_is_aa64(env, 3) ? 1 : 3; |
| 756 | case ARMMMUIdx_SE10_1: |
| 757 | case ARMMMUIdx_SE10_1_PAN: |
| 758 | case ARMMMUIdx_Stage1_E0: |
| 759 | case ARMMMUIdx_Stage1_E1: |
| 760 | case ARMMMUIdx_Stage1_E1_PAN: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 761 | case ARMMMUIdx_Stage1_SE1: |
| 762 | case ARMMMUIdx_Stage1_SE1_PAN: |
Richard Henderson | 9c7ab8f | 2020-06-25 20:31:19 -0700 | [diff] [blame] | 763 | case ARMMMUIdx_E10_0: |
| 764 | case ARMMMUIdx_E10_1: |
| 765 | case ARMMMUIdx_E10_1_PAN: |
| 766 | case ARMMMUIdx_MPrivNegPri: |
| 767 | case ARMMMUIdx_MUserNegPri: |
| 768 | case ARMMMUIdx_MPriv: |
| 769 | case ARMMMUIdx_MUser: |
| 770 | case ARMMMUIdx_MSPrivNegPri: |
| 771 | case ARMMMUIdx_MSUserNegPri: |
| 772 | case ARMMMUIdx_MSPriv: |
| 773 | case ARMMMUIdx_MSUser: |
| 774 | return 1; |
| 775 | default: |
| 776 | g_assert_not_reached(); |
| 777 | } |
| 778 | } |
| 779 | |
Richard Henderson | 38659d3 | 2020-06-25 20:31:20 -0700 | [diff] [blame] | 780 | /* Return the TCR controlling this translation regime */ |
| 781 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 782 | { |
| 783 | if (mmu_idx == ARMMMUIdx_Stage2) { |
| 784 | return &env->cp15.vtcr_el2; |
| 785 | } |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 786 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
| 787 | /* |
| 788 | * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but |
| 789 | * those are not currently used by QEMU, so just return VSTCR_EL2. |
| 790 | */ |
| 791 | return &env->cp15.vstcr_el2; |
| 792 | } |
Richard Henderson | 38659d3 | 2020-06-25 20:31:20 -0700 | [diff] [blame] | 793 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; |
| 794 | } |
| 795 | |
Peter Maydell | 81621d9 | 2018-03-23 18:26:46 +0000 | [diff] [blame] | 796 | /* Return the FSR value for a debug exception (watchpoint, hardware |
| 797 | * breakpoint or BKPT insn) targeting the specified exception level. |
| 798 | */ |
| 799 | static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) |
| 800 | { |
| 801 | ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; |
| 802 | int target_el = arm_debug_target_el(env); |
| 803 | bool using_lpae = false; |
| 804 | |
| 805 | if (target_el == 2 || arm_el_is_aa64(env, target_el)) { |
| 806 | using_lpae = true; |
| 807 | } else { |
| 808 | if (arm_feature(env, ARM_FEATURE_LPAE) && |
| 809 | (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { |
| 810 | using_lpae = true; |
| 811 | } |
| 812 | } |
| 813 | |
| 814 | if (using_lpae) { |
| 815 | return arm_fi_to_lfsc(&fi); |
| 816 | } else { |
| 817 | return arm_fi_to_sfsc(&fi); |
| 818 | } |
| 819 | } |
| 820 | |
Peter Maydell | 88ce6c6 | 2020-02-14 17:51:05 +0000 | [diff] [blame] | 821 | /** |
| 822 | * arm_num_brps: Return number of implemented breakpoints. |
| 823 | * Note that the ID register BRPS field is "number of bps - 1", |
| 824 | * and we return the actual number of breakpoints. |
| 825 | */ |
| 826 | static inline int arm_num_brps(ARMCPU *cpu) |
| 827 | { |
| 828 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 829 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; |
| 830 | } else { |
Peter Maydell | 4426d36 | 2020-02-14 17:51:06 +0000 | [diff] [blame] | 831 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; |
Peter Maydell | 88ce6c6 | 2020-02-14 17:51:05 +0000 | [diff] [blame] | 832 | } |
| 833 | } |
| 834 | |
| 835 | /** |
| 836 | * arm_num_wrps: Return number of implemented watchpoints. |
| 837 | * Note that the ID register WRPS field is "number of wps - 1", |
| 838 | * and we return the actual number of watchpoints. |
| 839 | */ |
| 840 | static inline int arm_num_wrps(ARMCPU *cpu) |
| 841 | { |
| 842 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 843 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; |
| 844 | } else { |
Peter Maydell | 4426d36 | 2020-02-14 17:51:06 +0000 | [diff] [blame] | 845 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; |
Peter Maydell | 88ce6c6 | 2020-02-14 17:51:05 +0000 | [diff] [blame] | 846 | } |
| 847 | } |
| 848 | |
| 849 | /** |
| 850 | * arm_num_ctx_cmps: Return number of implemented context comparators. |
| 851 | * Note that the ID register CTX_CMPS field is "number of cmps - 1", |
| 852 | * and we return the actual number of comparators. |
| 853 | */ |
| 854 | static inline int arm_num_ctx_cmps(ARMCPU *cpu) |
| 855 | { |
| 856 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
| 857 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; |
| 858 | } else { |
Peter Maydell | 4426d36 | 2020-02-14 17:51:06 +0000 | [diff] [blame] | 859 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; |
Peter Maydell | 88ce6c6 | 2020-02-14 17:51:05 +0000 | [diff] [blame] | 860 | } |
| 861 | } |
| 862 | |
Peter Maydell | 5529bf1 | 2018-10-08 14:55:04 +0100 | [diff] [blame] | 863 | /** |
| 864 | * v7m_using_psp: Return true if using process stack pointer |
| 865 | * Return true if the CPU is currently using the process stack |
| 866 | * pointer, or false if it is using the main stack pointer. |
| 867 | */ |
| 868 | static inline bool v7m_using_psp(CPUARMState *env) |
| 869 | { |
| 870 | /* Handler mode always uses the main stack; for thread mode |
| 871 | * the CONTROL.SPSEL bit determines the answer. |
| 872 | * Note that in v7M it is not possible to be in Handler mode with |
| 873 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. |
| 874 | */ |
| 875 | return !arm_v7m_is_handler_mode(env) && |
| 876 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; |
| 877 | } |
| 878 | |
Peter Maydell | 5520318 | 2018-10-08 14:55:04 +0100 | [diff] [blame] | 879 | /** |
| 880 | * v7m_sp_limit: Return SP limit for current CPU state |
| 881 | * Return the SP limit value for the current CPU security state |
| 882 | * and stack pointer. |
| 883 | */ |
| 884 | static inline uint32_t v7m_sp_limit(CPUARMState *env) |
| 885 | { |
| 886 | if (v7m_using_psp(env)) { |
| 887 | return env->v7m.psplim[env->v7m.secure]; |
| 888 | } else { |
| 889 | return env->v7m.msplim[env->v7m.secure]; |
| 890 | } |
| 891 | } |
| 892 | |
Peter Maydell | 81e3728 | 2018-10-24 07:50:17 +0100 | [diff] [blame] | 893 | /** |
Philippe Mathieu-Daudé | 787a7e7 | 2019-07-01 17:26:22 +0100 | [diff] [blame] | 894 | * v7m_cpacr_pass: |
| 895 | * Return true if the v7M CPACR permits access to the FPU for the specified |
| 896 | * security state and privilege level. |
| 897 | */ |
| 898 | static inline bool v7m_cpacr_pass(CPUARMState *env, |
| 899 | bool is_secure, bool is_priv) |
| 900 | { |
| 901 | switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { |
| 902 | case 0: |
| 903 | case 2: /* UNPREDICTABLE: we treat like 0 */ |
| 904 | return false; |
| 905 | case 1: |
| 906 | return is_priv; |
| 907 | case 3: |
| 908 | return true; |
| 909 | default: |
| 910 | g_assert_not_reached(); |
| 911 | } |
| 912 | } |
| 913 | |
| 914 | /** |
Peter Maydell | 81e3728 | 2018-10-24 07:50:17 +0100 | [diff] [blame] | 915 | * aarch32_mode_name(): Return name of the AArch32 CPU mode |
| 916 | * @psr: Program Status Register indicating CPU mode |
| 917 | * |
| 918 | * Returns, for debug logging purposes, a printable representation |
| 919 | * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by |
| 920 | * the low bits of the specified PSR. |
| 921 | */ |
| 922 | static inline const char *aarch32_mode_name(uint32_t psr) |
| 923 | { |
| 924 | static const char cpu_mode_names[16][4] = { |
| 925 | "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", |
| 926 | "???", "???", "hyp", "und", "???", "???", "???", "sys" |
| 927 | }; |
| 928 | |
| 929 | return cpu_mode_names[psr & 0xf]; |
| 930 | } |
| 931 | |
Peter Maydell | 89430fc | 2018-11-13 10:47:59 +0000 | [diff] [blame] | 932 | /** |
| 933 | * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request |
| 934 | * |
| 935 | * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following |
| 936 | * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. |
| 937 | * Must be called with the iothread lock held. |
| 938 | */ |
| 939 | void arm_cpu_update_virq(ARMCPU *cpu); |
| 940 | |
| 941 | /** |
| 942 | * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request |
| 943 | * |
| 944 | * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following |
| 945 | * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. |
| 946 | * Must be called with the iothread lock held. |
| 947 | */ |
| 948 | void arm_cpu_update_vfiq(ARMCPU *cpu); |
| 949 | |
Richard Henderson | 50494a2 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 950 | /** |
Richard Henderson | 3c29632 | 2022-05-06 13:02:33 -0500 | [diff] [blame] | 951 | * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit |
| 952 | * |
| 953 | * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, |
| 954 | * following a change to the HCR_EL2.VSE bit. |
| 955 | */ |
| 956 | void arm_cpu_update_vserr(ARMCPU *cpu); |
| 957 | |
| 958 | /** |
Richard Henderson | 164690b | 2019-10-23 11:00:46 -0400 | [diff] [blame] | 959 | * arm_mmu_idx_el: |
| 960 | * @env: The cpu environment |
| 961 | * @el: The EL to use. |
| 962 | * |
| 963 | * Return the full ARMMMUIdx for the translation regime for EL. |
| 964 | */ |
| 965 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); |
| 966 | |
| 967 | /** |
Richard Henderson | 50494a2 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 968 | * arm_mmu_idx: |
| 969 | * @env: The cpu environment |
| 970 | * |
| 971 | * Return the full ARMMMUIdx for the current translation regime. |
| 972 | */ |
| 973 | ARMMMUIdx arm_mmu_idx(CPUARMState *env); |
| 974 | |
Richard Henderson | 64be86a | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 975 | /** |
| 976 | * arm_stage1_mmu_idx: |
| 977 | * @env: The cpu environment |
| 978 | * |
| 979 | * Return the ARMMMUIdx for the stage1 traversal for the current regime. |
| 980 | */ |
| 981 | #ifdef CONFIG_USER_ONLY |
| 982 | static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
| 983 | { |
Richard Henderson | 2859d7b | 2020-02-07 14:04:22 +0000 | [diff] [blame] | 984 | return ARMMMUIdx_Stage1_E0; |
Richard Henderson | 64be86a | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 985 | } |
| 986 | #else |
| 987 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); |
| 988 | #endif |
| 989 | |
Richard Henderson | fee7aa4 | 2020-02-08 12:57:57 +0000 | [diff] [blame] | 990 | /** |
| 991 | * arm_mmu_idx_is_stage1_of_2: |
| 992 | * @mmu_idx: The ARMMMUIdx to test |
| 993 | * |
| 994 | * Return true if @mmu_idx is a NOTLB mmu_idx that is the |
| 995 | * first stage of a two stage regime. |
| 996 | */ |
| 997 | static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) |
| 998 | { |
| 999 | switch (mmu_idx) { |
| 1000 | case ARMMMUIdx_Stage1_E0: |
| 1001 | case ARMMMUIdx_Stage1_E1: |
Richard Henderson | 452ef8c | 2020-02-08 12:57:58 +0000 | [diff] [blame] | 1002 | case ARMMMUIdx_Stage1_E1_PAN: |
RĂ©mi Denis-Courmont | b1a10c8 | 2021-01-12 12:45:06 +0200 | [diff] [blame] | 1003 | case ARMMMUIdx_Stage1_SE0: |
| 1004 | case ARMMMUIdx_Stage1_SE1: |
| 1005 | case ARMMMUIdx_Stage1_SE1_PAN: |
Richard Henderson | fee7aa4 | 2020-02-08 12:57:57 +0000 | [diff] [blame] | 1006 | return true; |
| 1007 | default: |
| 1008 | return false; |
| 1009 | } |
| 1010 | } |
| 1011 | |
Richard Henderson | 4f9584e | 2020-02-08 12:58:01 +0000 | [diff] [blame] | 1012 | static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, |
| 1013 | const ARMISARegisters *id) |
| 1014 | { |
Richard Henderson | f062d14 | 2020-02-08 12:58:02 +0000 | [diff] [blame] | 1015 | uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; |
Richard Henderson | 4f9584e | 2020-02-08 12:58:01 +0000 | [diff] [blame] | 1016 | |
| 1017 | if ((features >> ARM_FEATURE_V4T) & 1) { |
| 1018 | valid |= CPSR_T; |
| 1019 | } |
| 1020 | if ((features >> ARM_FEATURE_V5) & 1) { |
| 1021 | valid |= CPSR_Q; /* V5TE in reality*/ |
| 1022 | } |
| 1023 | if ((features >> ARM_FEATURE_V6) & 1) { |
| 1024 | valid |= CPSR_E | CPSR_GE; |
| 1025 | } |
| 1026 | if ((features >> ARM_FEATURE_THUMB2) & 1) { |
| 1027 | valid |= CPSR_IT; |
| 1028 | } |
Peter Maydell | 873b73c | 2020-02-14 17:50:56 +0000 | [diff] [blame] | 1029 | if (isar_feature_aa32_jazelle(id)) { |
Richard Henderson | f062d14 | 2020-02-08 12:58:02 +0000 | [diff] [blame] | 1030 | valid |= CPSR_J; |
| 1031 | } |
Richard Henderson | 220f508 | 2020-02-08 12:58:07 +0000 | [diff] [blame] | 1032 | if (isar_feature_aa32_pan(id)) { |
| 1033 | valid |= CPSR_PAN; |
| 1034 | } |
Rebecca Cran | dc8b185 | 2021-02-07 23:56:57 -0700 | [diff] [blame] | 1035 | if (isar_feature_aa32_dit(id)) { |
| 1036 | valid |= CPSR_DIT; |
| 1037 | } |
Rebecca Cran | f2f68a7 | 2021-02-16 15:45:41 -0700 | [diff] [blame] | 1038 | if (isar_feature_aa32_ssbs(id)) { |
| 1039 | valid |= CPSR_SSBS; |
| 1040 | } |
Richard Henderson | 4f9584e | 2020-02-08 12:58:01 +0000 | [diff] [blame] | 1041 | |
| 1042 | return valid; |
| 1043 | } |
| 1044 | |
Richard Henderson | 1408451 | 2020-02-08 12:58:06 +0000 | [diff] [blame] | 1045 | static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) |
| 1046 | { |
| 1047 | uint32_t valid; |
| 1048 | |
| 1049 | valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; |
| 1050 | if (isar_feature_aa64_bti(id)) { |
| 1051 | valid |= PSTATE_BTYPE; |
| 1052 | } |
Richard Henderson | 220f508 | 2020-02-08 12:58:07 +0000 | [diff] [blame] | 1053 | if (isar_feature_aa64_pan(id)) { |
| 1054 | valid |= PSTATE_PAN; |
| 1055 | } |
Richard Henderson | 9eeb7a1 | 2020-02-08 12:58:14 +0000 | [diff] [blame] | 1056 | if (isar_feature_aa64_uao(id)) { |
| 1057 | valid |= PSTATE_UAO; |
| 1058 | } |
Rebecca Cran | dc8b185 | 2021-02-07 23:56:57 -0700 | [diff] [blame] | 1059 | if (isar_feature_aa64_dit(id)) { |
| 1060 | valid |= PSTATE_DIT; |
| 1061 | } |
Rebecca Cran | f2f68a7 | 2021-02-16 15:45:41 -0700 | [diff] [blame] | 1062 | if (isar_feature_aa64_ssbs(id)) { |
| 1063 | valid |= PSTATE_SSBS; |
| 1064 | } |
Richard Henderson | 4b779ce | 2020-06-25 20:31:05 -0700 | [diff] [blame] | 1065 | if (isar_feature_aa64_mte(id)) { |
| 1066 | valid |= PSTATE_TCO; |
| 1067 | } |
Richard Henderson | 1408451 | 2020-02-08 12:58:06 +0000 | [diff] [blame] | 1068 | |
| 1069 | return valid; |
| 1070 | } |
| 1071 | |
Richard Henderson | ba97be9 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 1072 | /* |
| 1073 | * Parameters of a given virtual address, as extracted from the |
| 1074 | * translation control register (TCR) for a given regime. |
| 1075 | */ |
| 1076 | typedef struct ARMVAParameters { |
| 1077 | unsigned tsz : 8; |
Richard Henderson | f4ecc01 | 2022-03-01 11:59:47 -1000 | [diff] [blame] | 1078 | unsigned ps : 3; |
Richard Henderson | ef56c24 | 2022-03-01 11:59:56 -1000 | [diff] [blame] | 1079 | unsigned sh : 2; |
Richard Henderson | ba97be9 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 1080 | unsigned select : 1; |
| 1081 | bool tbi : 1; |
| 1082 | bool epd : 1; |
| 1083 | bool hpd : 1; |
| 1084 | bool using16k : 1; |
| 1085 | bool using64k : 1; |
Richard Henderson | ebf93ce | 2022-03-01 11:59:43 -1000 | [diff] [blame] | 1086 | bool tsz_oob : 1; /* tsz has been clamped to legal range */ |
Richard Henderson | ef56c24 | 2022-03-01 11:59:56 -1000 | [diff] [blame] | 1087 | bool ds : 1; |
Richard Henderson | ba97be9 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 1088 | } ARMVAParameters; |
| 1089 | |
Richard Henderson | bf0be43 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 1090 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
| 1091 | ARMMMUIdx mmu_idx, bool data); |
Richard Henderson | bf0be43 | 2019-01-21 10:23:12 +0000 | [diff] [blame] | 1092 | |
Richard Henderson | ff730e9 | 2019-03-01 12:04:55 -0800 | [diff] [blame] | 1093 | static inline int exception_target_el(CPUARMState *env) |
| 1094 | { |
| 1095 | int target_el = MAX(1, arm_current_el(env)); |
| 1096 | |
| 1097 | /* |
| 1098 | * No such thing as secure EL1 if EL3 is aarch32, |
| 1099 | * so update the target EL to EL3 in this case. |
| 1100 | */ |
| 1101 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { |
| 1102 | target_el = 3; |
| 1103 | } |
| 1104 | |
| 1105 | return target_el; |
| 1106 | } |
| 1107 | |
Richard Henderson | 81ae05f | 2020-06-25 20:31:06 -0700 | [diff] [blame] | 1108 | /* Determine if allocation tags are available. */ |
| 1109 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, |
| 1110 | uint64_t sctlr) |
| 1111 | { |
| 1112 | if (el < 3 |
| 1113 | && arm_feature(env, ARM_FEATURE_EL3) |
| 1114 | && !(env->cp15.scr_el3 & SCR_ATA)) { |
| 1115 | return false; |
| 1116 | } |
Idan Horowitz | 0da067f | 2022-04-01 15:35:48 +0100 | [diff] [blame] | 1117 | if (el < 2 && arm_is_el2_enabled(env)) { |
Richard Henderson | 4301acd | 2020-10-08 11:21:55 -0500 | [diff] [blame] | 1118 | uint64_t hcr = arm_hcr_el2_eff(env); |
| 1119 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { |
| 1120 | return false; |
| 1121 | } |
Richard Henderson | 81ae05f | 2020-06-25 20:31:06 -0700 | [diff] [blame] | 1122 | } |
| 1123 | sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); |
| 1124 | return sctlr != 0; |
| 1125 | } |
| 1126 | |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1127 | #ifndef CONFIG_USER_ONLY |
| 1128 | |
Philippe Mathieu-Daudé | 787a7e7 | 2019-07-01 17:26:22 +0100 | [diff] [blame] | 1129 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
| 1130 | typedef struct V8M_SAttributes { |
| 1131 | bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ |
| 1132 | bool ns; |
| 1133 | bool nsc; |
| 1134 | uint8_t sregion; |
| 1135 | bool srvalid; |
| 1136 | uint8_t iregion; |
| 1137 | bool irvalid; |
| 1138 | } V8M_SAttributes; |
| 1139 | |
| 1140 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
| 1141 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
| 1142 | V8M_SAttributes *sattrs); |
| 1143 | |
| 1144 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
| 1145 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
| 1146 | hwaddr *phys_ptr, MemTxAttrs *txattrs, |
| 1147 | int *prot, bool *is_subpage, |
| 1148 | ARMMMUFaultInfo *fi, uint32_t *mregion); |
| 1149 | |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1150 | /* Cacheability and shareability attributes for a memory access */ |
| 1151 | typedef struct ARMCacheAttrs { |
Peter Maydell | 9f225e6 | 2022-05-05 19:39:47 +0100 | [diff] [blame] | 1152 | /* |
| 1153 | * If is_s2_format is true, attrs is the S2 descriptor bits [5:2] |
| 1154 | * Otherwise, attrs is the same as the MAIR_EL1 8-bit format |
| 1155 | */ |
| 1156 | unsigned int attrs:8; |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1157 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ |
Peter Maydell | 9f225e6 | 2022-05-05 19:39:47 +0100 | [diff] [blame] | 1158 | bool is_s2_format:1; |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1159 | } ARMCacheAttrs; |
| 1160 | |
| 1161 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
| 1162 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
| 1163 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
| 1164 | target_ulong *page_size, |
Richard Henderson | 7e98e21 | 2020-06-25 20:31:39 -0700 | [diff] [blame] | 1165 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
| 1166 | __attribute__((nonnull)); |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1167 | |
Peter Maydell | fc6177a | 2022-01-22 18:24:31 +0000 | [diff] [blame] | 1168 | void arm_log_exception(CPUState *cs); |
Philippe Mathieu-Daudé | b59f479 | 2019-07-01 17:26:22 +0100 | [diff] [blame] | 1169 | |
Philippe Mathieu-Daudé | ebae861 | 2019-07-01 17:26:20 +0100 | [diff] [blame] | 1170 | #endif /* !CONFIG_USER_ONLY */ |
| 1171 | |
Richard Henderson | 4b779ce | 2020-06-25 20:31:05 -0700 | [diff] [blame] | 1172 | /* |
| 1173 | * The log2 of the words in the tag block, for GMID_EL1.BS. |
| 1174 | * The is the maximum, 256 bytes, which manipulates 64-bits of tags. |
| 1175 | */ |
| 1176 | #define GMID_EL1_BS 6 |
| 1177 | |
Richard Henderson | efbc78a | 2020-06-25 20:31:09 -0700 | [diff] [blame] | 1178 | /* We associate one allocation tag per 16 bytes, the minimum. */ |
| 1179 | #define LOG2_TAG_GRANULE 4 |
| 1180 | #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) |
| 1181 | |
Richard Henderson | 206adac | 2020-06-25 20:31:31 -0700 | [diff] [blame] | 1182 | /* |
Richard Henderson | b64ee45 | 2021-01-12 20:26:47 -1000 | [diff] [blame] | 1183 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use |
| 1184 | * the same simd_desc() encoding due to restrictions on size. |
| 1185 | * Use these instead. |
| 1186 | */ |
| 1187 | FIELD(PREDDESC, OPRSZ, 0, 6) |
| 1188 | FIELD(PREDDESC, ESZ, 6, 2) |
| 1189 | FIELD(PREDDESC, DATA, 8, 24) |
| 1190 | |
| 1191 | /* |
Richard Henderson | 206adac | 2020-06-25 20:31:31 -0700 | [diff] [blame] | 1192 | * The SVE simd_data field, for memory ops, contains either |
| 1193 | * rd (5 bits) or a shift count (2 bits). |
| 1194 | */ |
| 1195 | #define SVE_MTEDESC_SHIFT 5 |
| 1196 | |
Richard Henderson | 0a405be | 2020-06-25 20:31:21 -0700 | [diff] [blame] | 1197 | /* Bits within a descriptor passed to the helper_mte_check* functions. */ |
| 1198 | FIELD(MTEDESC, MIDX, 0, 4) |
| 1199 | FIELD(MTEDESC, TBI, 4, 2) |
| 1200 | FIELD(MTEDESC, TCMA, 6, 2) |
| 1201 | FIELD(MTEDESC, WRITE, 8, 1) |
Richard Henderson | 28f3250 | 2021-04-16 11:31:02 -0700 | [diff] [blame] | 1202 | FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ |
Richard Henderson | 0a405be | 2020-06-25 20:31:21 -0700 | [diff] [blame] | 1203 | |
Richard Henderson | d304d28 | 2021-04-16 11:31:04 -0700 | [diff] [blame] | 1204 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
Richard Henderson | bd47b61 | 2021-04-16 11:31:03 -0700 | [diff] [blame] | 1205 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
Richard Henderson | 2e34ff4 | 2020-06-25 20:31:23 -0700 | [diff] [blame] | 1206 | |
Richard Henderson | efbc78a | 2020-06-25 20:31:09 -0700 | [diff] [blame] | 1207 | static inline int allocation_tag_from_addr(uint64_t ptr) |
| 1208 | { |
| 1209 | return extract64(ptr, 56, 4); |
| 1210 | } |
| 1211 | |
Richard Henderson | da54941 | 2020-06-25 20:31:07 -0700 | [diff] [blame] | 1212 | static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) |
| 1213 | { |
| 1214 | return deposit64(ptr, 56, 4, rtag); |
| 1215 | } |
| 1216 | |
Richard Henderson | 2e34ff4 | 2020-06-25 20:31:23 -0700 | [diff] [blame] | 1217 | /* Return true if tbi bits mean that the access is checked. */ |
| 1218 | static inline bool tbi_check(uint32_t desc, int bit55) |
| 1219 | { |
| 1220 | return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; |
| 1221 | } |
| 1222 | |
| 1223 | /* Return true if tcma bits mean that the access is unchecked. */ |
| 1224 | static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) |
| 1225 | { |
| 1226 | /* |
| 1227 | * We had extracted bit55 and ptr_tag for other reasons, so fold |
| 1228 | * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. |
| 1229 | */ |
| 1230 | bool match = ((ptr_tag + bit55) & 0xf) == 0; |
| 1231 | bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; |
| 1232 | return tcma && match; |
| 1233 | } |
| 1234 | |
| 1235 | /* |
| 1236 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is |
| 1237 | * for the tag to be present in the FAR_ELx register. But for user-only |
| 1238 | * mode, we do not have a TLB with which to implement this, so we must |
| 1239 | * remove the top byte. |
| 1240 | */ |
| 1241 | static inline uint64_t useronly_clean_ptr(uint64_t ptr) |
| 1242 | { |
Richard Henderson | 2e34ff4 | 2020-06-25 20:31:23 -0700 | [diff] [blame] | 1243 | #ifdef CONFIG_USER_ONLY |
Richard Henderson | 16c8497 | 2021-02-12 10:48:53 -0800 | [diff] [blame] | 1244 | /* TBI0 is known to be enabled, while TBI1 is disabled. */ |
| 1245 | ptr &= sextract64(ptr, 0, 56); |
Richard Henderson | 2e34ff4 | 2020-06-25 20:31:23 -0700 | [diff] [blame] | 1246 | #endif |
| 1247 | return ptr; |
| 1248 | } |
| 1249 | |
| 1250 | static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) |
| 1251 | { |
| 1252 | #ifdef CONFIG_USER_ONLY |
| 1253 | int64_t clean_ptr = sextract64(ptr, 0, 56); |
| 1254 | if (tbi_check(desc, clean_ptr < 0)) { |
| 1255 | ptr = clean_ptr; |
| 1256 | } |
| 1257 | #endif |
| 1258 | return ptr; |
| 1259 | } |
| 1260 | |
Peter Maydell | 507b6a5 | 2021-06-17 13:15:45 +0100 | [diff] [blame] | 1261 | /* Values for M-profile PSR.ECI for MVE insns */ |
| 1262 | enum MVEECIState { |
| 1263 | ECI_NONE = 0, /* No completed beats */ |
| 1264 | ECI_A0 = 1, /* Completed: A0 */ |
| 1265 | ECI_A0A1 = 2, /* Completed: A0, A1 */ |
| 1266 | /* 3 is reserved */ |
| 1267 | ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ |
| 1268 | ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ |
| 1269 | /* All other values reserved */ |
| 1270 | }; |
| 1271 | |
Alexander Graf | 0130895 | 2021-09-16 17:53:55 +0200 | [diff] [blame] | 1272 | /* Definitions for the PMU registers */ |
| 1273 | #define PMCRN_MASK 0xf800 |
| 1274 | #define PMCRN_SHIFT 11 |
| 1275 | #define PMCRLC 0x40 |
| 1276 | #define PMCRDP 0x20 |
| 1277 | #define PMCRX 0x10 |
| 1278 | #define PMCRD 0x8 |
| 1279 | #define PMCRC 0x4 |
| 1280 | #define PMCRP 0x2 |
| 1281 | #define PMCRE 0x1 |
| 1282 | /* |
| 1283 | * Mask of PMCR bits writeable by guest (not including WO bits like C, P, |
| 1284 | * which can be written as 1 to trigger behaviour but which stay RAZ). |
| 1285 | */ |
| 1286 | #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) |
| 1287 | |
| 1288 | #define PMXEVTYPER_P 0x80000000 |
| 1289 | #define PMXEVTYPER_U 0x40000000 |
| 1290 | #define PMXEVTYPER_NSK 0x20000000 |
| 1291 | #define PMXEVTYPER_NSU 0x10000000 |
| 1292 | #define PMXEVTYPER_NSH 0x08000000 |
| 1293 | #define PMXEVTYPER_M 0x04000000 |
| 1294 | #define PMXEVTYPER_MT 0x02000000 |
| 1295 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff |
| 1296 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ |
| 1297 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ |
| 1298 | PMXEVTYPER_M | PMXEVTYPER_MT | \ |
| 1299 | PMXEVTYPER_EVTCOUNT) |
| 1300 | |
| 1301 | #define PMCCFILTR 0xf8000000 |
| 1302 | #define PMCCFILTR_M PMXEVTYPER_M |
| 1303 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) |
| 1304 | |
| 1305 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
| 1306 | { |
Peter Maydell | 24526bb | 2022-05-13 13:28:52 +0100 | [diff] [blame^] | 1307 | ARMCPU *cpu = env_archcpu(env); |
| 1308 | |
| 1309 | return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; |
Alexander Graf | 0130895 | 2021-09-16 17:53:55 +0200 | [diff] [blame] | 1310 | } |
| 1311 | |
| 1312 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ |
| 1313 | static inline uint64_t pmu_counter_mask(CPUARMState *env) |
| 1314 | { |
| 1315 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); |
| 1316 | } |
| 1317 | |
Peter Maydell | 89f4f20 | 2021-09-21 17:28:59 +0100 | [diff] [blame] | 1318 | #ifdef TARGET_AARCH64 |
| 1319 | int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); |
| 1320 | int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); |
| 1321 | int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); |
| 1322 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); |
| 1323 | #endif |
| 1324 | |
Richard Henderson | 7c1aaf9 | 2022-05-06 13:02:23 -0500 | [diff] [blame] | 1325 | #ifdef CONFIG_USER_ONLY |
| 1326 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
| 1327 | #else |
| 1328 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); |
| 1329 | #endif |
| 1330 | |
Richard Henderson | b6f8b35 | 2022-05-06 13:02:26 -0500 | [diff] [blame] | 1331 | void aa32_max_features(ARMCPU *cpu); |
| 1332 | |
Peter Maydell | ccd3808 | 2014-04-15 19:18:37 +0100 | [diff] [blame] | 1333 | #endif |